16-Channel DAS with 16-Bit, Bipolar Input,

Dual Simultaneous Sampling ADC

Data Sheet AD7616
FEATURES APPLICATIONS
16-channel, dual, simultaneously sampled inputs Power line monitoring
Independently selectable channel input ranges Protective relays
True bipolar: ±10 V, ±5 V, ±2.5 V Multiphase motor control
Single 5 V analog supply and 2.3 V to 3.6 V VDRIVE supply Instrumentation and control systems
Fully integrated data acquisition solution Data acquisition systems (DASs)
Analog input clamp protection GENERAL DESCRIPTION
Input buffer with 1 MΩ analog input impedance
The AD7616 is a 16-bit, DAS that supports dual simultaneous
First-order antialiasing analog filter
sampling of 16 channels. The AD7616 operates from a single 5 V
On-chip accurate reference and reference buffer
supply and can accommodate ±10 V, ±5 V, and ±2.5 V true bipolar
Dual 16-bit successive approximation register (SAR) ADC
input signals while sampling at throughput rates up to 1 MSPS
Throughput rate: 2 × 1 MSPS
Oversampling capability with digital filter
per channel pair with 90.5 dB SNR. Higher SNR performance can
Flexible sequencer with burst mode
be achieved with the on-chip oversampling mode (92 dB for an
Flexible parallel/serial interface oversampling ratio (OSR) of 2).
SPI/QSPI/MICROWIRE/DSP compatible The input clamp protection circuitry can tolerate voltages up to
Optional cyclic redundancy check (CRC) error checking ±21 V. The AD7616 has 1 MΩ analog input impedance, regardless
Hardware/software configuration of sampling frequency. The single-supply operation, on-chip
Performance filtering, and high input impedance eliminate the need for
92 dB SNR at 500 kSPS (2× oversampling) driver op amps and external bipolar supplies.
90.5 dB SNR at 1 MSPS The device contains analog input clamp protection, a dual, 16-bit
−103 dB THD
charge redistribution SAR analog-to-digital converter (ADC), a
±1 LSB INL (typical), ±0.99 LSB DNL (maximum)
flexible digital filter, a 2.5 V reference and reference buffer, and
8 kV ESD rating on analog input channels
high speed serial and parallel interfaces.
On-chip self detect function
80-lead LQFP package The AD7616 is serial peripheral interface (SPI)/QSPI™/DSP/
MICROWIRE compatible
FUNCTIONAL BLOCK DIAGRAM
VCC REFCAP REFINOUT REFSEL REGCAP REGCAPD VDRIVE

1MΩ RFB
V0A CLAMP 2.5V 1.8V 1.8V
REF ALDO DLDO
V0AGND FIRST-
CLAMP RFB ORDER LPF
1MΩ
9:1
MUX
1MΩ RFB SERIAL SDOx/SDI
V7A CLAMP
FIRST- 16-BIT
V7AGND CLAMP SAR OSR PARALLEL/ SER/PAR
RFB ORDER LPF
1MΩ DIGITAL
SERIAL
SER1W
INTERFACE
1MΩ RFB FILTER
V0B CLAMP 16-BIT
SAR PARALLEL DB15 TO DB0
V0BGND CLAMP FIRST-
RFB ORDER LPF
1MΩ
OS2 TO OS0
9:1
1MΩ RFB MUX
V7B CLAMP RESET
V7BGND CLAMP FIRST- FLEXIBLE BURST
RFB ORDER LPF
1MΩ SEQUENCER SEQEN
CONTROL HW_RNGSEL0, HW_RNGSEL1
INPUTS
CHSEL2 TO CHSEL0
AD7616 VCC 2:1 CLK OSC
MUX BUSY
ALDO
CONVST

AGND DGND
NOTES
13591-001

1. MULTIFUNCTION PINS, SUCH AS DB15/OS2, ARE REFERRED TO BY A SINGLE FUNCTION OF THE PIN,
FOR EXAMPLE, DB15, WHEN ONLY THAT FUNCTION IS RELEVANT. REFER TO THE PIN CONFIGURATION
AND FUNCTION DESCRIPTIONS SECTION FOR MORE INFORMATION.
Figure 1.
Rev. 0 Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD7616 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Software Mode ............................................................................ 29
Applications ....................................................................................... 1 Reset Functionality..................................................................... 29
General Description ......................................................................... 1 Pin Function Overview ............................................................. 30
Functional Block Diagram .............................................................. 1 Digital Interface .............................................................................. 31
Revision History ............................................................................... 2 Channel Selection....................................................................... 31
Specifications..................................................................................... 3 Parallel Interface ......................................................................... 32
Timing Specifications .................................................................. 6 Serial Interface ............................................................................ 33
Parallel Mode Timing Specifications ......................................... 8 Sequencer......................................................................................... 35
Serial Mode Timing Specifications ............................................ 9 Hardware Mode Sequencer ....................................................... 35
Absolute Maximum Ratings .......................................................... 10 Software Mode Sequencer ......................................................... 35
Thermal Resistance .................................................................... 10 Burst Sequencer .......................................................................... 36
ESD Caution ................................................................................ 10 Diagnostics ...................................................................................... 38
Pin Configuration and Function Descriptions ........................... 11 Diagnostic Channels .................................................................. 38
Typical Performance Characteristics ........................................... 15 Interface Self Test ....................................................................... 38
Terminology .................................................................................... 21 CRC .............................................................................................. 38
Theory of Operation ...................................................................... 23 Register Summary .......................................................................... 40
Converter Details........................................................................ 23 Addressing Registers .................................................................. 41
Analog Input ............................................................................... 23 Configuration Register .............................................................. 42
ADC Transfer Function ............................................................. 24 Channel Register ........................................................................ 43
Internal/External Reference ...................................................... 24 Input Range Registers ................................................................ 44
Shutdown Mode.......................................................................... 25 Input Range Register A1............................................................ 44
Digital Filter ................................................................................ 25 Input Range Register A2............................................................ 45
Applications Information .............................................................. 26 Input Range Register B1 ............................................................ 46
Functionality Overview ............................................................. 26 Input Range Register B2 ............................................................ 47
Device Configuration ..................................................................... 28 Sequencer Stack Registers ......................................................... 48
Operational Mode ...................................................................... 28 Status Register ............................................................................. 49
Internal/External Reference ...................................................... 28 Outline Dimensions ....................................................................... 50
Digital Interface .......................................................................... 28 Ordering Guide .......................................................................... 50
Hardware Mode .......................................................................... 28

REVISION HISTORY
10/2016—Revision 0: Initial Version

Rev. 0 | Page 2 of 50
Data Sheet AD7616

SPECIFICATIONS
VREF = 2.5 V external/internal, VCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 3.6 V, fSAMPLE = 1 MSPS, TA = −40°C to +125°C, unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE fIN = 1 kHz sine wave unless otherwise noted
Signal-to-Noise Ratio (SNR)1, 2 No oversampling, ±10 V range 89 90.5 dB
OSR = 2, ±10 V range,3 fSAMPLE = 500 kSPS 92 dB
OSR = 4, ±10 V range3 93 dB
No oversampling, ±5 V range 88 89.5 dB
No oversampling, ±2.5 V range 85.5 87 dB
Signal-to-Noise-and-Distortion (SINAD)1 No oversampling, ±10 V range 88.5 90 dB
No oversampling, ±5 V range 87.5 89 dB
No oversampling, ±2.5 V range 85 87 dB
Dynamic Range No oversampling, ±10 V range 92 dB
No oversampling, ±5 V range 90.5 dB
No oversampling, ±2.5 V range 88 dB
Total Harmonic Distortion (THD)1 No oversampling, ±10 V range −103 −93.5 dB
No oversampling, ±5 V range −100 dB
No oversampling, ±2.5 V range −97 dB
Peak Harmonic or Spurious Noise1 −103 dB
Intermodulation Distortion (IMD)1 fa = 1 kHz, fb = 1.1 kHz
Second-Order Terms −105 dB
Third-Order Terms −113 dB
Channel to Channel Isolation1 fIN on unselected channels up to 5 kHz −106 dB
ANALOG INPUT FILTER
Full Power Bandwidth −3 dB, ±10 V range 39 kHz
−3 dB, ±5 V/2.5 V range 33 kHz
−0.1 dB 5.5 kHz
Phase Delay3 ±10 V range 4.4 6 μs
±5 V range 5 μs
±2.5 V range 4.9 μs
Phase Delay Drift3 ±10 V range ±0.55 5 ns/°C
Phase Delay Matching (Dual Simultaneous ±10 V range 4.4 100 ns
Pair)3
±5 V range 4.7 ns
±2.5 V range 4.1 ns
DC ACCURACY
Resolution No missing codes 16 Bits
Differential Nonlinearity (DNL)1 ±0.5 ±0.99 LSB4
Integral Nonlinearity (INL)1 ±1 ±2 LSB
Total Unadjusted Error (TUE) ±10 V range ±6 LSB
±5 V range ±8 LSB
±2.5 V range ±10 LSB
Positive Full-Scale Error5
External reference ±10 V range ±5 ±32 LSB
±5 V range ±4 LSB
±2.5 V range ±2 LSB
Internal reference
±10 V range ±5 LSB

Rev. 0 | Page 3 of 50
AD7616 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
Positive Full-Scale (PFS) Error Drift3 External reference ±2 ±5 ppm/°C
Internal reference ±3 ±10 ppm/°C
Positive Full-Scale Error Matching1 ±10 V range 3 11 LSB
±5 V range 4 LSB
±2.5 V range 8 LSB
Bipolar Zero Code Error1 ±10 V range ±0.8 ±8 LSB
±5 V range ±1 ±10 LSB
±2.5 V range ±3 ±15 LSB
Bipolar Zero Code Error Drift3 ±10 V range ±1.3 ±20.4 μV/°C
±5 V range ±0.9 μV/°C
±2.5 V range ±0.5 μV/°C
Bipolar Zero Code Error Matching ±10 V range ±2 ±10 LSB
±5 V range ±3 LSB
±2.5 V range ±3 LSB
Negative Full-Scale (NFS) Error1, 5 External reference
±10 V range ±4 ±32 LSB
±5 V range ±3 LSB
±2.5 V range ±6 LSB
Internal reference
±10 V range ±3 LSB
Negative Full-Scale Error Drift3 External reference ±2 ±5 ppm/°C
Internal reference ±4 ppm/°C
Negative Full-Scale Error Matching1 ±10 V range 4 12 LSB
±5 V range 4 LSB
±2.5 V range 8 LSB
ANALOG INPUT
Input Voltage Ranges Software/hardware selectable ±10 V
Software/hardware selectable ±5 V
Software/hardware selectable ±2.5 V
Analog Input Current ±10 V range, see Figure 34 ±10.5 μA
±5 V range, see Figure 34 ±6.5 μA
±2.5 V range, see Figure 34 ±4 μA
Input Capacitance6 10 pF
Input Impedance See the Analog Input section 0.85 1 MΩ
Input Impedance Drift3 25 ppm/°C
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range See the ADC Transfer Function section 2.495 2.5 2.505 V
DC Leakage Current ±1 μA
Input Capacitance6 REFSEL = 1 7.5 pF
Reference Output Voltage REFINOUT 2.495 2.505 V
Reference Temperature Coefficient3 ±2 ±15 ppm/°C
LOGIC INPUTS
Input Voltage
High (VINH) VDRIVE = 2.7 V to 3.6 V 2 V
VDRIVE = 2.3 V to 2.7 V 1.7 V
Low (VINL) VDRIVE = 2.7 V to 3.6 V 0.8 V
VDRIVE = 2.3 V to 2.7 V 0.7 V
Input Current (IIN) ±1 μA
Input Capacitance (CIN)6 5 pF

Rev. 0 | Page 4 of 50
Data Sheet AD7616
Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC OUTPUTS
Output Voltage
High (VOH) ISOURCE = 100 μA VDRIVE − 0.2 V
Low (VOL) ISINK = 100 μA 0.4 V
Floating State Leakage Current ±0.005 ±1 μA
Floating State Output Capacitance6 5 pF
Output Coding Twos complement
CONVERSION RATE
Conversion Time Per channel pair 0.5 μs
Acquisition Time Per channel pair 0.5 μs
Throughput Rate Per channel pair 1 MSPS
POWER REQUIREMENTS
VCC 4.75 5.25 V
VDRIVE 2.3 3.6 V
IVCC
Normal Mode
Static 37 57 mA
Operational fSAMPLE = 1 MSPS 42 65 mA
Shutdown Mode 28 μA
IDRIVE Digital inputs = 0 V or VDRIVE
Normal Mode
Static 0.3 0.75 mA
Operational fSAMPLE = 1 MSPS 7 8 mA
Shutdown Mode 50 μA
Power Dissipation
Normal Mode
Static 185 300 mW
Operational fSAMPLE = 1 MSPS 230 350 mW
Shutdown Mode 0.75 mW
1
See the Terminology section.
2
The user can achieve 93 dB SNR by enabling oversampling. The values are valid for manual mode. In burst mode, values degrade by ~1 dB.
3
Not production tested. Sample tested during initial release to ensure compliance.
4
LSB means least significant bit. With a ±2.5 V input range, 1 LSB = 76.293 μV. With a ±5 V input range, 1 LSB = 152.58 μV. With a ±10 V input range, 1 LSB = 305.175 μV.
5
Positive and negative full-scale error for the internal reference excludes reference errors.
6
Supported by simulation data.

Rev. 0 | Page 5 of 50
AD7616 Data Sheet
TIMING SPECIFICATIONS
Universal Timing Specifications
VCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 3.6 V, VREF = 2.5 V external reference/internal reference, TA = −40°C to +125°C, unless otherwise noted.
Interface timing tested using a load capacitance of 30 pF, dependent on VDRIVE and load capacitance for serial interface (see Table 14).

Table 2.
Parameter1 Min Typ Max Unit Description
tCYCLE 1 µs Minimum time between consecutive CONVST rising edges (excluding burst and
oversampling modes)
tCONV_LOW 50 ns CONVST low pulse width
tCONV_HIGH 50 ns CONVST high pulse width
tBUSY_DELAY 32 ns CONVST high to BUSY high (manual mode)
tCS_SETUP 20 ns BUSY falling edge to CS falling edge setup time
tCH_SETUP 50 ns Channel select setup time in hardware mode for CHSELx
tCH_HOLD 20 ns Channel select hold time in hardware mode for CHSELx
tCONV 475 520 ns Conversion time for the selected channel pair
tACQ 480 ns Acquisition time for the selected channel pair
tQUIET 50 ns CS rising edge to next CONVST rising edge
tRESET_LOW
Partial Reset 40 500 ns Partial RESET low pulse width
Full Reset 1.2 µs Full RESET low pulse width
tDEVICE_SETUP
Partial Reset 50 ns Time between partial RESET high and CONVST rising edge
Full Reset 15 ms Time between full RESET high and CONVST rising edge
tWRITE
Partial Reset 50 ns Time between partial RESET high and CS for write operation
Full Reset 240 µs Time between full RESET high and CS for write operation
tRESET_WAIT 1 ms Time between stable VCC/VDRIVE and release of RESET (see Figure 50)
tRESET_SETUP Time prior to release of RESET that queried hardware inputs must be stable for (see Figure 50)
Partial Reset 10 ns
Full Reset 0.05 ms
tRESET_HOLD Time after release of RESET that queried hardware inputs must be stable for (see Figure 50)
Partial Reset 10 ns
Full Reset 0.24 ms
1
Not production tested. Sample tested during initial release to ensure compliance.

tCYCLE

tCONV_LOW t CONV_HIGH

tBUSY_DELAY tQUIET

CONVST

BUSY

t CONV t ACQ

t CS_SETUP

CS

t CH_SETUP t CH_HOLD
13591-102

HARDWARE CHSEL0 TO CHx y

MODE ONLY CHSEL2

Figure 2. Universal Timing Diagram Across All Interfaces

Rev. 0 | Page 6 of 50
Data Sheet AD7616
tRESET_WAIT

tDEVICE_SETUP

VCC
VDRIVE

RESET

tRESET_LOW

CONVST

BUSY

tWRITE

CS

tRESET_SETUP

tRESET_HOLD
REFSEL
SER/PAR, SER1W
ALL MODES
HW_RNGSEL0,
HW_RNGSEL1 MODE RANGE SETTING IN HW MODE

CRCEN, BURST
SEQEN, OS0 TO OS2

HARDWARE
MODE ONLY CHSEL0 TO CHSEL2 CHx CHy CHz

13591-103
ADC INTERNAL ACTION ACQx CONVx ACQy CONVy

Figure 3. Reset Timing

Rev. 0 | Page 7 of 50
AD7616 Data Sheet
Parallel Mode Timing Specifications
Table 3.
Parameter Min Typ Max Unit Description
tRD_SETUP 10 ns CS falling edge to RD falling edge setup time
tRD_HOLD 10 ns RD rising edge to CS rising edge hold time
tRD_HIGH 10 ns RD high pulse width
tRD_LOW 30 ns RD low pulse width
tDOUT_SETUP 30 ns Data access time after falling edge of RD
tDOUT_3STATE 11 ns CS rising edge to DBx high impedance
tWR_SETUP 10 ns CS to WR setup time
tWR_HIGH 20 ns WR high pulse width
tWR_LOW 30 ns WR low pulse width
tWR_HOLD 10 ns WR hold time
tDIN_SETUP 30 ns Configuration data to WR setup time
tDIN_HOLD 10 ns Configuration data to WR hold time
tCONF_SETTLE 20 ns Configuration data settle time, WR rising edge to CONVST rising edge

CONVST

BUSY

tRD_HIGH tRD_HOLD

tDOUT_3STATE

CS

RD

DB15 TO DB0 CONV A CONV B

tRD_SETUP tRD_LOW
13591-033
tDOUT_SETUP

Figure 4. Parallel Read Timing Diagram

tWR_SETUP tCONF_SETTLE

CONVST

CS

tWR_HIGH tWR_HOLD

WR

tDIN_HOLD tWR_LOW

DB0 TO
DB15 WRITE REG 1 WRITE REG 2
13591-105

tDIN_SETUP

Figure 5. Parallel Write Timing Diagram

Rev. 0 | Page 8 of 50
Data Sheet AD7616
Serial Mode Timing Specifications
Table 4.
Parameter Min Typ Max Unit Description
fSCLK1 40/50 MHz SCLK frequency
tSCLK 1/fSCLK Minimum SCLK period
tSCLK_SETUP1 10.5 ns CS to SCLK falling edge setup time, VDRIVE above 3 V
13.5 ns CS to SCLK falling edge setup time, VDRIVE above 2.3 V
tSCLK_HOLD 10 ns SCLK to CS rising edge hold time
tSCLK_LOW 8 ns SCLK low pulse width
tSCLK_HIGH 9 ns SCLK high pulse width
tDOUT_SETUP1 9 ns Data out access time after SCLK rising edge, VDRIVE above 3 V
11 ns Data out access time after SCLK rising edge, VDRIVE above 2.3 V
tDOUT_HOLD 4 ns Data out hold time after SCLK rising edge
tDIN_SETUP 10 ns Data in setup time before SCLK falling edge
tDIN_HOLD 8 ns Data in hold time after SCLK falling edge
tDOUT_3STATE 10 ns CS rising edge to SDOx high impedance
1
Dependent on VDRIVE and load capacitance (see Table 14).

CONVST

BUSY

t SCLK_SETUP t DOUT_SETUP t DOUT_HOLD

t SCLK t SCLK_HIGH

t SCLK_LOW t SCLK_HOLD

CS

SCLK 1 2 3 14 15 16

SDOA DB15 DB14 DB13 DB2 DB1 DB0

SDOB DB15 DB14 DB13 DB2 DB1 DB0

SDI DB15 DB14 DB13 DB2 DB1 DB0

13591-106
t DIN_SETUP t DIN_HOLD t DOUT_3STATE

Figure 6. Serial Timing Diagram

Rev. 0 | Page 9 of 50
AD7616 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. THERMAL RESISTANCE
Table 5. Thermal performance is directly linked to printed circuit board
Parameter Rating (PCB) design and operating environment. Close attention to
PCB thermal design is required.
VCC to AGND −0.3 V to +7 V
VDRIVE to AGND −0.3 V to VCC + 0.3 V θJA is the natural convection junction to ambient thermal
Analog Input Voltage to AGND1 ±21 V resistance measured in a one cubic foot sealed enclosure. θJC is
Digital Input Voltage to AGND −0.3 V to VDRIVE + 0.3 V the junction to case thermal resistance.
Digital Output Voltage to AGND −0.3 V to VDRIVE + 0.3 V
Table 6. Thermal Resistance
REFINOUT to AGND −0.3 V to VCC + 0.3 V
Package Type θJA θJC Unit
Input Current to Any Pin Except
Supplies1 ±10 mA ST-80-21 41 7.5 °C/W
Operating Temperature Range −40°C to +125°C 1
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
Storage Temperature Range −65°C to +150°C test board. See JEDEC JESD51.
Junction Temperature 150°C
Soldering Reflow
Pb/Sn Temperature (10 sec to 30 sec) 240 (+0)°C ESD CAUTION
Pb-Free Temperature 260 (+0)°C
ESD
All Pins Except Analog Inputs 2 kV
Analog Input Pins Only 8 kV
1
Transient currents of up to 100 mA do not cause silicon controlled rectifier
(SCR) latch-up.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. 0 | Page 10 of 50
Data Sheet AD7616

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

WR/BURST
SCLK/RD
REGGND
REGCAP

CONVST
V3BGND

V2BGND

V1BGND

V0BGND

CHSEL2
CHSEL1
CHSEL0
AGND

BUSY
V3B

V2B

V1B

V0B

VCC

CS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

V4BGND 1 60 DB15/OS2
V4B 2 59 DB14/OS1
V5BGND 3 58 DB13/OS0
V5B 4 57 DB12/SDOA
AGND 5 56 DB11/SDOB
VCC 6 55 DB10/SDI
V6B 7 54 DB9
V6BGND 8 AD7616 53 DB8
V7B 9 TOP VIEW 52 REGCAPD
(Not to Scale)
V7BGND 10 51 REGGNDD
V7AGND 11 50 DGND
V7A 12 49 VDRIVE
V6AGND 13 48 DB7
V6A 14 47 DB6
VCC 15 46 DB5/CRCEN
AGND 16 45 DB4/SER1W
V5A 17 44 DB3
V5AGND 18 43 DB2
V4A 19 42 DB1
V4AGND 20 41 DB0

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
REFGND

REFINOUTGND

SEQEN
REFSEL
RESET
REFINOUT
VCC
V3AGND
V3A
V2AGND
V2A
V1AGND
V1A
V0AGND
V0A
AGND

HW_RNGSEL1
HW_RNGSEL0
SER/PAR
REFCAP

ANALOG INPUT DIGITAL INPUT

DECOUPLING CAP PIN REFERENCE INPUT/OUTPUT

13591-005
POWER SUPPLY DIGITAL INPUT/OUTPUT
GROUND PIN DIGITAL OUTPUT

Figure 7. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Type1 Mnemonic2 Description
1 AI GND V4BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V4B.
2 AI V4B Analog Input for Channel 4, ADC B.
3 AI GND V5BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V5B.
4 AI V5B Analog Input for Channel 5, ADC B.
5, 16, 29, 72 P AGND Analog Supply Ground Pins.
6, 15, 30, 71 P VCC Analog Supply Voltage, 4.7 V to 5.25 V. This supply voltage is applied to the internal front-end
amplifiers and to the ADC core. Decouple these pins to AGND using 0.1 µF and 10 µF
capacitors in parallel.
7 AI V6B Analog Input for Channel 6, ADC B.
8 AI GND V6BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V6B.
9 AI V7B Analog Input for Channel 7, ADC B.
10 AI GND V7BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V7B.
11 AI GND V7AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V7A.
12 AI V7A Analog Input for Channel 7, ADC A.
13 AI GND V6AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V6A.
14 AI V6A Analog Input for Channel 6, ADC A.
17 AI V5A Analog Input V5A.
18 AI GND V5AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V5A.
19 AI V4A Analog Input V4A.
20 AI GND V4AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V4A.
Rev. 0 | Page 11 of 50
AD7616 Data Sheet
Pin No. Type1 Mnemonic2 Description
21 AI GND V3AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V3A.
22 AI V3A Analog Input for Channel 3, ADC A.
23 AI GND V2AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V2A.
24 AI V2A Analog Input for Channel 2, ADC A.
25 AI GND V1AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V1A.
26 AI V1A Analog Input for Channel 1, ADC A.
27 AI GND V0AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V0A.
28 AI V0A Analog Input for Channel 0, ADC A.
31 CAP REFCAP Reference Buffer Output Force/Sense Pin. Decouple this pin to AGND using a low effective
series resistance (ESR), 10 µF, X5R ceramic capacitor, as close to the REFCAP pin as possible.
The voltage on this pin is typically 4.096 V.
32 CAP REFGND Reference Ground pin. Connect this pin to AGND.
33 REF REFINOUT Reference Input/Reference Output. The on-chip reference of 2.5 V is available on this pin for
external use when the REFSEL pin is set to logic high. Alternatively, the internal reference can
be disabled by setting the REFSEL pin to logic low, and an external reference of 2.5 V can be
applied to this input. Decoupling is required on this pin for both the internal and external
reference options. Connect a 100 nF, X8R capacitor between the REFINOUT and REFINOUTGND
pins, as close to the REFINOUT pin as possible. If using an external reference, connect a 10 kΩ
series resistor to this pin to band limit the reference signal.
34 CAP REFINOUTGND Reference Input, Reference Output Ground Pin.
35 DI REFSEL Internal/External Reference Selection Input. REFSEL is a logic input. If this pin is set to logic
high, the internal reference is selected and enabled. If this pin is set to logic low, the internal
reference is disabled and an external reference voltage must be applied to the REFINOUT pin.
The signal state is latched on the release of a full reset, and requires an additional full reset to
reconfigure.
36 DI RESET Reset Input. Full and partial reset options are available. The type of reset is determined by the
length of the RESET pulse. Keeping RESET low places the device into shutdown mode. See the
Reset Functionality section for further details.
37 DI SEQEN Channel Sequencer Enable Input (Hardware Mode Only). When SEQEN is tied low, the
sequencer is disabled.
When SEQEN is high, the sequencer is enabled (with restricted functionality in hardware
mode). See the Sequencer section for further details. The signal state is latched on the release
of a full reset, and requires an additional full reset to reconfigure.
In software mode, this pin must be connected to DGND.
38, 39 DI HW_RNGSEL1, Hardware/Software Mode Selection, Hardware Mode Range Select Inputs. Hardware/software
HW_RNGSEL0 mode selection is latched at full reset. Range selection in hardware mode is not latched.
HW_RNGSELx = 00: software mode; the AD7616 is configured via the software registers.
HW_RNGSELx = 01: hardware mode; analog input range is ±2.5 V.
HW_RNGSELx = 10: hardware mode; analog input range is ±5 V.
HW_RNGSELx = 11: hardware mode; analog input range is ±10 V.
40 DI SER/PAR Serial/Parallel Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel
interface is selected. If this pin is tied to logic high, the serial interface is selected. The signal
state is latched on the release of a full reset, and requires an additional full reset to reconfigure.
41, 42, 43, DO/DI DB0, DB1, DB2, Parallel Output/Input Data Bit 0 to Data Bit 3. In parallel mode, these pins are output/input
44 DB3 parallel data bits, DB7 to DB0. Refer to the Parallel Interface section for further details. In serial
mode, these pins must be tied to DGND.
45 DO/DI DB4/SER1W Parallel Output/Input Data Bit 4/Serial Output Selection. In parallel mode, this pin acts as a
three-state parallel digital output/input pin. Refer to the Parallel Interface section for further
details.
In serial mode, this pin determines whether the serial output operates over SDOA and SDOB
or just SDOA. When SER1W is low, the serial output operates over SDOA only. When SER1W is
high, the serial output operates over both SDOA and SDOB. The signal state is latched on the
release of a full reset, and requires an additional full reset to reconfigure.

Rev. 0 | Page 12 of 50
Data Sheet AD7616
Pin No. Type1 Mnemonic2 Description
46 DO/DI DB5/CRCEN Parallel Output/Input Data Bit 5/CRC Enable Input. In parallel mode, this pin acts as a three-
state parallel digital input/output. While in serial mode, this pin acts as a CRC enable input.
The CRCEN signal state is latched on the release of a full reset, and requires an additional full
reset to reconfigure. Refer to the Digital Interface section for further details.
In serial mode, when CRCEN is low, there is no CRC word following the conversion results;
when CRCEN is high, an extra CRC word follows the last conversion word configured by
CHSELx. See the CRC section for further details.
In software mode, this pin must be connected to DGND.
47, 48 DO/DI DB6, DB7 Parallel Output/Input Data Bit 6 and Data Bit 7. When SER/PAR = 0, these pins act as three-
state parallel digital input/outputs. Refer to the Parallel Interface section for further details. In
serial mode, when SER/PAR = 1 these pins must be tied to DGND.
49 P VDRIVE Logic Power Supply Input. The voltage (2.3 V to 3.6 V) supplied at this pin determines the
operating voltage of the interface. This pin is nominally at the same supply as the supply of
the host interface. Decouple this pin with 0.1 µF and 10 µF capacitors in parallel.
50 P DGND Digital Ground. This pin is the ground reference point for all digital circuitry on the AD7616.
The DGND pin must connect to the DGND plane of a system.
51 CAP REGGNDD Ground for the Digital Low Dropout (LDO) Regulator Connected to REGCAPD (Pin 52).
52 CAP REGCAPD Decoupling Capacitor Pin for Voltage Output from Internal Digital Regulator. Decouple this
output pin separately to REGGNDD using a 10 μF capacitor. The voltage at this pin is 1.89 V typical.
53, 54 DO/DI DB8, DB9 Parallel Output/Input Data Bit 9 and Data Bit 8. When SER/PAR = 0, these pins act as three-
state parallel digital input/outputs. Refer to the Parallel Interface section for further details.
In serial mode, when SER/PAR = 1, these pins must be tied to DGND.
55 DO/DI DB10/SDI Parallel Output/Input Data Bit DB10/Serial Data Input. When SER/PAR = 0, this pin acts as a
three-state parallel digital input/output. Refer to the Parallel Interface section for further
details. In hardware serial mode, tie this pin to DGND.
In serial mode, when SER/PAR = 1, this pin acts as the data input of the SPI interface.
56 DO/DI DB11/SDOB Parallel Output/Input Data Bit 11/Serial Data Output B. When SER/PAR = 0, this pin acts as a
three-state parallel digital input/output. Refer to the Parallel Interface section for further
details.
In serial mode, when SER/PAR = 1, this pin functions as SDOB and outputs serial conversion data.
57 DO/DI DB12/SDOA Parallel Output/Input Data Bit 12/Serial Data Output A. When SER/PAR = 0, this pin acts as a
three-state parallel digital input/output. Refer to the Parallel Interface section for further
details.
In serial mode, when SER/PAR = 1, this pin functions as SDOA and outputs serial conversion data.
58, 59, 60 DO/DI DB13/OS0, Parallel Output/Input Data Bit 13, Data Bit 14, and Data Bit 15/Oversampling Ratio Selection.
DB14/OS1, When SER/PAR = 0, these pins act as three-state parallel digital input/outputs. Refer to the
DB15/OS2 Parallel Interface section for further details.
In serial hardware mode, these pins control the oversampling settings. The signal state is
latched on the release of a full reset, and requires an additional full reset to reconfigure. See the
Digital Filter section for further details.
In software serial mode, these pins must be connected to DGND.
61 DI WR/BURST Write/Burst Mode Enable.
In software parallel mode, this pin acts as WR for a parallel interface.
In hardware parallel or serial mode, this pin enables BURST mode. The signal state is latched on
the release of a full reset, and requires an additional full reset to reconfigure. Refer to the Burst
Sequencer section for further information.
In software serial mode, connect this pin to DGND.
62 DI SCLK/RD Serial Clock Input/Parallel Data Read Control Input. In serial mode, this pin acts as the serial
clock input for data transfers. The CS falling edge takes the SDOA and SDOB data output lines
out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK
clocks all subsequent data bits onto the SDOA and SDOB serial data outputs.
When both CS and RD are logic low in parallel mode, the output bus is enabled.
63 DI CS Chip Select. This active low logic input frames the data transfer.
In parallel mode, when both CS and RD are logic low, the DBx output bus is enabled and the
conversion result is output on the parallel data bus lines.
In serial mode, CS frames the serial read transfer and clocks out the MSB of the serial output data.

Rev. 0 | Page 13 of 50
AD7616 Data Sheet
Pin No. Type1 Mnemonic2 Description
64, 65, 66 DI CHSEL0, CHSEL1, Channel Selection Input 0 to Input 2. In hardware mode, these inputs select the input
CHSEL2 channels for the next conversion in Channel Group A and Channel Group B. For example,
CHSELx = 0x000 selects V0A and V0B for the next conversion; CHSELx = 0x001 selects V1A and
V1B for the next conversion.
In software mode, these pins must be connected to DGND.
67 DO BUSY Busy Output. This pin transitions to a logic high after a CONVST rising edge and indicates that
the conversion process has started. The BUSY output remains high until the conversion
process for the current selected channels is complete. The falling edge of BUSY signals that
the conversion data is being latched into the output data registers and is available to read.
Data must be read after BUSY returns to low. Rising edges on CONVST have no effect while
the BUSY signal is high.
68 DI CONVST Conversion Start Input for Channel Group A and Channel Group B. This logic input initiates
conversions on the analog input channels.
A conversion is initiated when CONVST transitions from low to high for the selected analog
input pair. When burst mode and oversampling mode are disabled, every CONVST transition
from low to high converts one channel pair. In sequencer mode, when burst mode or
oversampling is enabled, a single CONVST transition from low to high is necessary to perform
the required number of conversions.
69 CAP REGGND Internal Analog Regulator Ground. This pin must connect to the AGND plane of a system.
70 CAP REGCAP Decoupling Capacitor Pin for Voltage Output from Internal Analog Regulator. Decouple this
output pin separately to REGGND using a 10 μF capacitor. The voltage at this pin is 1.87 V
typical.
73 AI V0B Analog Input for Channel 0, ADC B.
74 AI GND V0BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V0B.
75 AI V1B Analog Input for Channel 1, ADC B.
76 AI GND V1BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V1B.
77 AI V2B Analog Input for Channel 2, ADC B.
78 AI GND V2BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V2B.
79 AI V3B Analog Input for Channel 3, ADC B.
80 AI GND V3BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V3B.
1
AI is analog input, GND is ground, P is power supply, REF is reference input/output, DI is digital input, DO is digital output, and CAP is decoupling capacitor pin.
2
Note that throughout this data sheet, multifunction pins, such as SER/PAR, are referred to either by the entire pin name or by a single function of the pin, for example,
SER, when only that function is relevant.

Rev. 0 | Page 14 of 50
Data Sheet AD7616

TYPICAL PERFORMANCE CHARACTERISTICS

VREF = 2.5 V internal, VCC = 5 V, VDRIVE = 3.3 V, fSAMPLE = 1 MSPS, fIN = 1 kHz TA = 25°C, unless otherwise noted.
0 100
SNR = 90.44dB ±10V RANGE
SINAD = 90.25dB 98 ±5V RANGE
–20 THD = –103.41dB ±2.5V RANGE
N SAMPLES = 65536
96
–40
94
MAGNITUDE (dB)

–60
92

SNR (dB)
–80 90

88
–100
86
–120
84
–140
82

–160 80
13591-208

13591-211
0 20 40 60 80 100 –40 –25 –10 5 20 35 50 65 80 95 110 125
FREQUENCY (kHz) TEMPERATURE (°C)

Figure 8. Fast Fourier Transform (FFT), ±10 V Range Figure 11. SNR vs. Temperature

0 100
SNR = 89.59dB ±10V RANGE
SINAD = 89.39dB 98 ±5V RANGE
–20 THD = –102.36dB ±2.5V RANGE
N SAMPLES = 65536
96
–40
94
MAGNITUDE (dB)

–60 92
SINAD (dB)

–80 90

88
–100
86
–120
84
–140
82

–160 80

13591-212
13591-209

0 20 40 60 80 100 –40 –25 –10 5 20 35 50 65 80 95 110 125

FREQUENCY (kHz) TEMPERATURE (°C)

Figure 9. FFT, ±5 V Range Figure 12. SINAD vs. Temperature

0 –60
SNR = 90.6dB ±10V RANGE
SINAD = 90.65dB ±5V RANGE
–20 THD = –107.4dB ±2.5V RANGE
N SAMPLES = 65536 –70

–40
–80
MAGNITUDE (dB)

–60
THD (dB)

–80 –90

–100
–100

–120
–110
–140
RSOURCE MATCHED ON Vx AND VxGND INPUTS
–160 –120
13591-213
13591-210

0 10 20 30 40 50 –40 –25 –10 5 20 35 50 65 80 95 110 125

FREQUENCY (kHz) TEMPERATURE (°C)

Figure 10. FFT Burst Mode, ±10 V Range Figure 13. THD vs. Temperature

Rev. 0 | Page 15 of 50
AD7616 Data Sheet
2.0 2.0

1.5 1.5

1.0 1.0

DNL ERROR (LSB)

INL ERROR (LSB)

0.5 0.5

0 0

–0.5 –0.5

–1.0 –1.0

–1.5 –1.5

–2.0 –2.0

13591-214

13591-217
0 10000 20000 30000 40000 50000 60000 0 10000 20000 30000 40000 50000 60000
CODE CODE

Figure 14. Typical INL Error, ±10 V Range Figure 17. Typical DNL Error, ±5 V Range

2.0 35000
32731 ±10V RANGE
Vxx AND VxxGND
1.5 SHORTED TOGETHER
30000 65536 SAMPLES
26334
1.0
25000
NUMBER OF HITS
INL ERROR (LSB)

0.5
20000
0
15000
–0.5

10000
–1.0

5000 4140
–1.5
2297
29 5
–2.0 0

13591-218
13591-215

0 10000 20000 30000 40000 50000 60000 32766 32767 32768 32769 32770 32771
CODE CODE

Figure 15. Typical INL Error, ±5 V Range Figure 18. DC Histogram of Codes at Code Center, ±10 V Range

2.0 35000
±5V RANGE
Vxx AND VxxGND 31138
1.5 SHORTED TOGETHER
30000 65536 SAMPLES

1.0 24343
25000
NUMBER OF HITS
DNL ERROR (LSB)

0.5
20000
0
15000
–0.5
10000
–1.0 6841

5000
–1.5 3021
36 157
–2.0 0
13591-219
13591-216

0 10000 20000 30000 40000 50000 60000 32764 32765 32766 32767 32768 32769

CODE CODE

Figure 16. Typical DNL Error, ±10 V Range Figure 19. DC Histogram of Codes at Code Center, ±5 V Range

Rev. 0 | Page 16 of 50
Data Sheet AD7616
30000 0.009
27621 ±2.5V RANGE
Vxx and VxxGND
SHORTED TOGETHER 0.008
25000 65536 SAMPLES
0.007

PFS/NFS ERROR (%FS)

NUMBER OF HITS

20000 0.006
18123

0.005
15000
13596
0.004
NFS ±10V RANGE
10000 0.003 NFS ±5V RANGE
NFS ±2.5V RANGE
PFS ±10V RANGE
0.002 PFS ±5V RANGE
5000 3836
PFS ±2.5V RANGE
2022 0.001
1 85 249 2 1
0 0

13591-220

13591-223
32757 32758 32759 32760 32761 32762 32763 32764 32765 32768 0 20 40 60 80 100
CODE SOURCE RESISTANCE (kΩ)

Figure 20. DC Histogram of Codes at Code Center, ±2.5 V Range Figure 23. PFS/NFS Error vs. Source Resistance

30 10
±10V RANGE PFS ±10V RANGE
±5V RANGE 9 NFS ±10V RANGE
±2.5V RANGE

NFS/PFS ERROR MATCHING (LSB)

20
8

7
NFS ERROR (LSB)

10
6

0 5

4
–10
3

2
–20
1

–30 0

13591-224
13591-221

–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 21. NFS Error vs. Temperature Figure 24. NFS/PFS Error Matching vs. Temperature

30 10
±10V RANGE ±10V RANGE
±5V RANGE 8 ±5V RANGE
±2.5V RANGE ±2.5V RANGE
BIPOLAR ZERO CODE ERROR (LSB)

20
6

4
PFS ERROR (LSB)

10
2

0 0

-2
–10
-4

-6
–20
-8

–30 -10
13591-225
13591-222

–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 22. PFS Error vs. Temperature Figure 25. Bipolar Zero Code Error vs. Temperature

Rev. 0 | Page 17 of 50
AD7616 Data Sheet
8 98
DC INPUT ±10V RANGE
BIPOLAR ZERO ERROR MATCHING (LSB)

7 96

94
6

92
5

SNR (dB)
90
4
88
3
86
NO OS
2 OSR × 2
84
OSR × 4
1 ±10V RANGE OSR × 8
82 OSR × 16
±5V RANGE
±2.5V RANGE OSR × 32
0 80

13591-229
13591-226
–40 –25 –10 5 20 35 50 65 80 95 110 125 100 1k 10k 100k
TEMPERATURE (°C) INPUT FREQUENCY (Hz)

Figure 26. Bipolar Zero Error Matching vs. Temperature Figure 29. SNR vs. Input Frequency for Different Oversampling Rates,
±10 V Range

–40 98
±10V RANGE ±5V RANGE
RSOURCE MATCHED ON Vxx AND VxxGND INPUTS 96
–50
0Ω
50Ω 94
100Ω
–60 1.2kΩ
5.6kΩ 92
10kΩ
23.7kΩ
SNR (dB)

–70 90
47.3kΩ
THD (dB)

105kΩ
–80 88

86
–90 NO OS
84 OSR × 2
OSR × 4
–100 OSR × 8
82 OSR × 16
OSR × 32
–110 80

13591-230
13591-227

1k 10k 100k 100 1k 10k 100k

INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz)

Figure 27. THD vs. Input Frequency for Various Source Impedances, Figure 30. SNR vs. Input Frequency for Different Oversampling Rates,
±10 V Range ±5 V Range

–40 –50
±5V RANGE ±10V RANGE
RSOURCE MATCHED ON Vxx AND VxxGND INPUTS –60 ±5V RANGE
CHANNEL TO CHANNEL ISOLATION (dB)

–50 ±2.5V RANGE

0Ω –70
50Ω
–60 100Ω
1.2kΩ –80
5.6kΩ
–70 10kΩ –90
23.7kΩ
47.3kΩ
THD (dB)

–80 105kΩ –100

–110
–90
–120
–100
–130
–110 –140

–120 –150
13591-231
13591-228

1k 10k 100k 0 5000 10000 15000 20000 25000 30000

INPUT FREQUENCY (Hz) INTERFERER FREQUENCY (Hz)

Figure 28. THD vs. Input Frequency for Various Source Figure 31. Channel to Channel Isolation
Impedances, ±5 V Range

Rev. 0 | Page 18 of 50
Data Sheet AD7616
12 130
±10V RANGE
±5V RANGE
120 ±2.5V RANGE
10
110
PHASE DELAY (µs)

8 100

PSRR (dB)
90
6
80

4 70

±10V RANGE 60
2 ±5V RANGE
±2.5V RANGE
50
100mV p-p SINE WAVE
APPLIED TO VCC SUPPLY
0 40

13591-236
13591-232
–40 –25 –10 5 20 35 50 65 80 95 110 125 0.1 1 10 100 1000
TEMPERATURE (°C) RIPPLE FREQUENCY (kHz)

Figure 32. Phase Delay vs. Temperature Figure 35. PSRR vs. Ripple Frequency

2.510 0
4.75V ±10V RANGE
5V ±5V RANGE
5.25V ±2.5V RANGE
INTERNAL REFERENCE VOLTAGE (V)

–20
2.505

–40

CMRR (dB)
2.500 –60

–80
2.495

–100

2.490 –120
13591-234

13591-237
–40 –25 –10 5 20 35 50 65 80 95 110 125 10 100 1k 10k 100k 1M 10M
TEMPERATURE (°C) RIPPLE FREQUENCY (Hz)
Figure 33. Internal Reference Voltage vs. Temperature for Various Figure 36. CMRR vs. Ripple Frequency
Supply Voltages
15 100

90
STATIC/DYNAMIC IVCC CURRENT (mA)

10
ANALOG INPUT CURRENT (µA)

80
+10V INPUT
70
5
+5V INPUT
60

0 +2.5V INPUT 50
DYNAMIC
–2.5V INPUT 40
STATIC
–5
–5V INPUT 30

20
–10
–10V INPUT
10

–15 0
13591-235

13591-238

–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 34. Analog Input Current vs. Temperature for Various Supply Voltages Figure 37. Static/Dynamic IVCC Current vs. Temperature

Rev. 0 | Page 19 of 50
AD7616 Data Sheet
5.0 47

4.5 46
DYNAMIC VDRIVE CURRENT (mA)

4.0
45
3.5

IVCC CURRENT (mA)

44
3.0
43
2.5
42
2.0
41
1.5
40
1.0

0.5 39

0 38

13591-241
13591-239
–40 –25 –10 5 20 35 50 65 80 95 110 125 100 200 300 400 500 600 700 800 900 1000
TEMPERATURE (°C) SAMPLING FREQUENCY (kSPS)

Figure 38. Dynamic VDRIVE Current vs. Temperature Figure 40. IVCC Current vs. Sampling Frequency

0.7

0.6
STATIC VDRIVE CURRENT (mA)

0.5

0.4

0.3

0.2

0.1

0
13591-240

–40 –25 –10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 39. Static VDRIVE Current vs. Temperature

Rev. 0 | Page 20 of 50
Data Sheet AD7616

TERMINOLOGY
Integral Nonlinearity (INL) The ratio is dependent on the number of quantization levels in
INL is the maximum deviation from a straight line passing the digitization process: the greater the number of levels, the
through the endpoints of the ADC transfer function. The smaller the quantization noise. The theoretical SNR for an ideal
endpoints of the transfer function are zero scale, at ½ LSB below N-bit converter with a sine wave input is given by
the first code transition; and full scale, at ½ LSB above the last code Signal-to-Noise Ratio = (6.02N + 1.76) dB
transition.
Therefore, for a 16-bit converter, the SNR is 98 dB.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal 1 Total Harmonic Distortion (THD)
LSB change between any two adjacent codes in the ADC. THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
Bipolar Zero Code Error expressed in decibels (dB).
Bipolar zero code error is the deviation of the midscale
transition (all 1s to all 0s) from the ideal, which is 0 V − ½ LSB. Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
Bipolar Zero Code Error Matching ADC output spectrum (up to fS/2, excluding dc) to the rms value
Bipolar zero code error matching is the absolute difference in of the fundamental. Normally, the value of this specification is
bipolar zero code error between any two input channels. determined by the largest harmonic in the spectrum, but for
Positive Full-Scale (PFS) Error ADCs where the harmonics are buried in the noise floor, it is
Positive full-scale error is the deviation of the actual last code determined by a noise peak.
transition from the ideal last code transition (10 V − 1½ LSB Intermodulation Distortion
(9.99954), 5 V − 1½ LSB (4.99977) and 2.5 V − 1½ LSB With inputs consisting of sine waves at two frequencies, fa and fb,
(2.49989)) after bipolar zero code error is adjusted out. The any active device with nonlinearities creates distortion products
positive full-scale error includes the contribution from the at the sum and difference frequencies of mfa ± nfb, where m,
internal reference buffer. n = 0, 1, 2, 3. Intermodulation distortion terms are those for
Positive Full-Scale Error Matching which neither m nor n is equal to 0. For example, the second-
Positive full-scale error matching is the absolute difference in order terms include (fa + fb) and (fa − fb), and the third-order
positive full-scale error between any two input channels. terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
Negative Full-Scale (NFS) Error The calculation of the intermodulation distortion is per the
Negative full-scale error is the deviation of the first code THD specification, where it is the ratio of the rms sum of the
transition from the ideal first code transition (−10 V + ½ LSB individual distortion products to the rms amplitude of the sum
(−9.99985), −5 V + ½ LSB (−4.99992) and −2.5 V + ½ LSB of the fundamentals expressed in decibels (dB).
(−2.49996)) after the bipolar zero code error is adjusted out. Power Supply Rejection Ratio (PSRR)
The negative full-scale error includes the contribution from the Variations in power supply affect the full-scale transition but
internal reference buffer. not the linearity of the converter. Power supply rejection is the
Negative Full-Scale Error Matching maximum change in full-scale transition point due to a change
Negative full-scale error matching is the absolute difference in in power supply voltage from the nominal value. The PSRR is
negative full-scale error between any two input channels. defined as the ratio of the power in the ADC output at full-scale
Signal-to-Noise-and-Distortion Ratio (SINAD) frequency, f, to the power of a 100 mV p-p sine wave applied to
SINAD is the measured ratio of signal to noise and distortion at the VCC supply of the ADC of frequency, fS.
the output of the ADC. The signal is the rms value of the sine PSRR (dB) = 10log(Pf/PfS)
wave, and noise is the rms sum of all nonfundamental signals where:
up to half the sampling frequency (fS/2), including harmonics, Pf is equal to the power at frequency, f, in the ADC output.
but excluding dc. PfS is equal to the power at frequency, fS, coupled onto the VCC
Signal-to-Noise Ratio (SNR) supply.
SNR is the measured ratio of signal to noise at the output of the
ADC. The signal is the rms amplitude of the fundamental. Noise is
the sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc.

Rev. 0 | Page 21 of 50
AD7616 Data Sheet
AC Common-Mode Rejection Ratio (AC CMRR) Phase Delay
AC CMRR is defined as the ratio of the power in the ADC Phase delay is a measure of the absolute time delay between
output at frequency, f, to the power of a sine wave applied to the when an input is sampled by the converter and when the result
common-mode voltage of Vxx and VxxGND at frequency, fS. associated with that sample is available to be read back from the
AC CMRR (dB) = 10log(Pf/PfS) ADC, including delay induced by the analog front end of the
device.
where:
Pf is the power at frequency, f, in the ADC output. Phase Delay Drift
PfS is the power at frequency, fS, in the ADC output. Phase delay drift is the change in group delay per unit
temperature across the entire operating temperature of the
Channel to Channel Isolation device.
Channel to channel isolation is a measure of the level of crosstalk
between all input channels. It is measured by applying a full-scale Phase Delay Matching
sine wave signal, up to 160 kHz, to all unselected input channels Phase delay matching is the maximum phase delay seen
and then determining the degree to which the signal attenuates between any simultaneously sampled pair.
in the selected channel with a 1 kHz sine wave signal applied.

Rev. 0 | Page 22 of 50
Data Sheet AD7616

THEORY OF OPERATION
CONVERTER DETAILS In hardware mode, a logic change on these pins has an immediate
The AD7616 is a data acquisition system that employs a high effect on the analog input range; however, there is typically a
speed, low power, charge redistribution, SAR analog-to-digital settling time of approximately 120 µs in addition to the normal
converter (ADC), and allows dual simultaneous sampling of acquisition time requirement. The recommended practice is to
16 analog input channels. The analog inputs on the AD7616 can hardwire the range select pins according to the desired input
accept true bipolar input signals. Analog input range options range for the system signals.
include ±10 V, ±5 V, and ±2.5 V. The AD7616 operates from a Analog Input Impedance
single 5 V supply.
The analog input impedance of the AD7616 is 1 MΩ, a fixed
The AD7616 contains input clamp protection, input signal input impedance that does not vary with the AD7616 sampling
scaling amplifiers, a first-order antialiasing filter, an on-chip frequency. This high analog input impedance eliminates the need
reference, a reference buffer, a dual high speed ADC, a digital for a driver amplifier in front of the AD7616, allowing direct
filter, a flexible sequencer, and high speed parallel and serial connection to the source or sensor.
interfaces.
Analog Input Clamp Protection
The AD7616 can be operated in hardware or software mode by
Figure 41 shows the analog input circuitry of the AD7616. Each
controlling the HW_RNGSELx pins. In hardware mode, the
analog input of the AD7616 contains clamp protection circuitry.
AD7616 is configured by pin control. In software mode, the
Despite single 5 V supply operation, this analog input clamp
AD7616 is configured by the control registers accessed via the
protection allows an input overvoltage of between −20 V and
serial or parallel interface.
+20 V.
ANALOG INPUT RFB

Analog Input Channel Selection 1MΩ

Vxx CLAMP
The AD7616 contains dual, simultaneous sampling, 16-bit 1MΩ
VxxGND CLAMP
ADCs. Each ADC has eight analog input channels for a total of

13591-006
FIRST-
ORDER
16 analog inputs. Additionally, the AD7616 has on-chip diagnostic RFB LPF
channels to monitor the VCC supply and an on-chip adjustable Figure 41. Analog Input Circuitry
low dropout regulator. Channels can be selected for conversion
by control of the CHSELx pins in hardware mode or via the Figure 42 shows the input clamp current vs. source voltage
channel register control in software mode. Software mode is characteristic of the clamp circuit. For source voltages between
required to sample the diagnostic channels. Channels can be −20 V and +20 V, no current flows in the clamp circuit. For input
selected dynamically or the AD7616 has an on-chip sequencer to voltages that are greater than +20 V and less than −20 V, the
allow the channels for conversion to be preprogrammed. In hard- AD7616 clamp circuitry turns on.
ware mode, simultaneous sampling is limited to the corresponding 0.25
POWERED OFF
A and B channel, that is, Channel V0A is always sampled with 0.20 POWERED ON

Channel V0B. In software mode, it is possible to select any A 0.15

INPUT CLAMP CURRENT (mA)

channel with any B channel for simultaneous sampling. 0.10

Analog Input Ranges 0.05

The AD7616 can handle true bipolar, single-ended input 0

voltages. The logic levels on the range select pins, HW_RNGSEL0 –0.05
and HW_RNGSEL1, determine the analog input range of all
–0.10
analog input channels. If both range select pins are tied to a
–0.15
logic low, the analog input range is determined in software mode
via the input range registers (see the Register Summary section –0.20

for more details). In software mode, it is possible to configure –0.25

13591-243

–30 –20 –10 0 10 20 30

an individual analog input range per channel. SOURCE VOLTAGE (V)

Table 8. Analog Input Range Selection Figure 42. Input Protection Clamp Profile, Input Clamp Current vs. Source Voltage

Analog Input Range HW_RNGSEL1 HW_RNGSEL0 Place a series resistor on the analog input channels to limit the
Configured via the Input 0 0 current to ±10 mA for input voltages greater than +20 V and less
Range Registers than −20 V. In an application where there is a series resistance
±2.5 V 0 1 on an analog input channel, VxA or VxB, a corresponding
±5 V 1 0 resistance is required on the analog input ground channel,
±10 V 1 1 VxAGND or VxBGND (see Figure 43). If there is no correspond-
Rev. 0 | Page 23 of 50
AD7616 Data Sheet
ing resistor on the VxAGND or VxBGND channel, an offset ADC TRANSFER FUNCTION
error occurs on that channel. Use the input overvoltage clamp The output coding of the AD7616 is twos complement. The
protection circuitry to protect the AD7616 against transient designed code transitions occur midway between successive
overvoltage events. It is not recommended to leave the AD7616 integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is
in a condition where the clamp protection circuitry is active in full-scale range ÷ 65,536 for the AD7616. The ideal transfer
normal or power-down conditions for extended periods. characteristics for the AD7616 are shown in Figure 46. The LSB
AD7616
RFB size is dependent on the analog input range selected.
ANALOG R 1MΩ VIN 2.5V
Vxx ±10V CODE = × 32,768 ×
INPUT CLAMP 10V REFINOUT
SIGNAL
R C 1MΩ VIN 2.5V
CLAMP ±5V CODE = × 32,768 ×
VxxGND 5V REFINOUT
VIN 2.5V

13591-008
±2.5V CODE = × 32,768 ×
RFB 2.5V REFINOUT
011...111
011...110
Figure 43. Input Resistance Matching on the Analog Input

ADC CODE
+FS – (–FS)
Analog Input Antialiasing Filter 000...001 LSB =
000...000 2N*
111...111
An analog antialiasing filter (a first-order Butterworth) is also
provided on the AD7616. Figure 44 and Figure 45 show the 100...010
frequency and phase response, respectively, of the analog 100...001
100...000
antialiasing filter. The typical corner frequency in the ±10 V –FS + 1/2LSB 0V – 1/2LSB +FS – 3/2LSB
ANALOG INPUT
range is 39 kHz, and 33 kHz in the ±5 V range.
5 +FS MIDSCALE –FS LSB
±10V RANGE ±10V RANGE +10V 0V –10V 305µV
±5V RANGE ±5V RANGE +5V 0V –5V 152µV
±2.5V RANGE
0

13591-009
±2.5V RANGE +2.5V 0V –2.5V 76µV
*WHERE N IS THE NUMBER OF BITS OF THE CONVERTER
–5
Figure 46. Transfer Characteristics
ATTENUATION (dB)

–10 INTERNAL/EXTERNAL REFERENCE

–15
The AD7616 can operate with either an internal or external
reference. The device contains an on-chip 2.5 V band gap refer-
–20 ence. The REFINOUT pin allows access to the 2.5 V reference
that generates the on-chip 4.096 V reference internally, or it
–25
allows an external reference of 2.5 V to be applied to the AD7616.
An externally applied reference of 2.5 V is also amplified to 4.096 V
–30
13591-244

100 1k 10k 100k using the internal buffer. This 4.096 V buffered reference is the
INPUT FREQUENCY (Hz) reference used by the SAR ADC.
Figure 44. Analog Antialiasing Filter Frequency Response
The REFSEL pin is a logic input pin that allows the user to select
6
between the internal reference and an external reference. If this
±10V RANGE
±5V RANGE pin is set to logic high, the internal reference is selected and
5 ±2.5V RANGE
enabled. If this pin is set to logic low, the internal reference is
disabled and an external reference voltage must be applied
4
to the REFINOUT pin.
PHASE (µs)

3 The internal reference buffer is always enabled. After a full reset,

the AD7616 operates in the reference mode selected by the
2 REFSEL pin. Decoupling is required on the REFINOUT pin for
both the internal and external reference options. A 100 nF, X8R
1 ceramic capacitor is required on the REFINOUT pin to
REFINOUTGND.
0 The AD7616 contains a reference buffer configured to amplify
100
13591-246

1k 10k 100k
INPUT FREQUENCY (Hz)
the reference voltage to ~4.096 V. A 10 μF, X5R ceramic capacitor
Figure 45. Analog Antialiasing Filter Phase Response is required between REFCAP and REFGND. The reference voltage
available at the REFINOUT pin is 2.5 V. When the AD7616 is
configured in external reference mode, the REFINOUT pin is a
high input impedance pin.

Rev. 0 | Page 24 of 50
Data Sheet AD7616
If the internal reference is to be applied elsewhere within the Table 9 provides the oversampling bit decoding to select the
system, it must first be buffered externally. different oversample rates. In addition to the oversampling
function, the output result is decimated to 16-bit resolution.
REFINOUT
BUF
REFCAP If the OSx pins/OS bits are set to select an OS ratio of eight, the
REFSEL next CONVST rising edge takes the first sample for the selected
10µF channel, and the remaining seven samples for that channel are
2.5V
100nF
REF taken with an internally generated sampling signal. These
samples are then averaged to yield an improvement in SNR
REFINOUTGND

13591-010
REFINOUTGND
performance. As the OS ratio increases, the −3 dB frequency is
reduced, and the allowed sampling frequency is also reduced.
Figure 47. Reference Circuitry The conversion time extends as the oversampling rate is increased,
SHUTDOWN MODE and the BUSY signal scales with oversampling rates. Acquisition
and conversion time increase linearly with oversampling ratio.
The AD7616 enters shutdown mode by keeping the RESET pin
low for greater than 1.2 µs. When the RESET pin is set from low If oversampling is enabled with the sequencer or in burst mode,
to high, the device exits shutdown mode and enters normal the extra samples are gathered for a given channel before the
mode. sequencer moves on to the next channel.
When the AD7616 is placed in shutdown mode, the current Table 9 shows the typical SNR performance of the device for
consumption is typically 78 µA and the power-up time to each permissible oversampling ratio. The input tone used was a
perform a write to the device is approximately 240 µs. Power-up 100 Hz sine wave for the three input ranges of the device. A plot
time to perform a conversion is 15 ms. In shutdown mode, all of SNR vs. OSR is shown in Figure 48.
circuitry is powered down and all registers are cleared and reset 97

to their default values. 96

DIGITAL FILTER 95

94
The AD7616 contains an optional digital first-order sinc filter
for use in applications where slower throughput rates are in use 93
SNR (dB)

or where higher SNR or dynamic range is desirable. 92

The OSR of the digital filter is controlled in hardware using the 91

oversampling pins, OS2 to OS0 (OSx), or in software via the OS 90

bits within the configuration register. In software mode, over- 89
±2.5V RANGE
±5V RANGE
sampling is enabled for all channels after the OS bits are set in 88
±10V RANGE

the configuration register. In hardware mode, the OSx signals at fIN = 100Hz
87
the time a full reset is released determine the OSR to be used.

13591-011
0 20 40 60 80 100 120
OSR

Figure 48. Typical SNR vs. OSR for all Analog Input Ranges

Table 9. Oversampling Bit Decoding

Typical SNR (dB) −3 dB Bandwidth (kHz)
OSx Pins/OS Bits OSR ±2.5 V Range ±5 V Range ±10 V Range All Ranges
000 No oversampling 87.5 89.7 90.8 37
001 2 88.1 90.6 91.8 36.5
010 4 89 91.6 92.9 35
011 8 89.9 92.6 93.9 30.5
100 16 91 93.6 94.9 22
101 32 92.6 94.8 95.8 13.2
110 64 93.9 95.5 96.2 7.2
111 128 94.4 95.4 95.9 3.6

Rev. 0 | Page 25 of 50
AD7616 Data Sheet

APPLICATIONS INFORMATION
FUNCTIONALITY OVERVIEW REGCAP and REGCAPGND pins. The digital LDO (DLDO)
The AD7616 has two main modes of operation: hardware mode typically supplies 1.89 V. Decouple the DLDO with a 10 µF
and software mode. Additionally, the communications interface capacitor between the REGCAPD and REGCAPDGND pins.
for hardware or software mode can be serial or parallel. Depending The AD7616 is robust to power supply sequencing. The recom-
on the mode of operation and interface chosen, certain functional- mended sequence is to power up VDRIVE first, followed by VCC.
ity may not be available. Full functionality is available in both Hold RESET low until both supplies are stabilized.
software serial and software parallel mode with restricted
TYPICAL CONNECTIONS
functionality in hardware serial mode and hardware parallel
mode. Table 10 shows the functionality available in the different Figure 49 shows the typical connections required for correct
modes of operation. operation of the AD7616. Decouple the VCC and VDRIVE supplies
as shown in Figure 49. Place the smaller, 0.1 µF capacitor as
POWER SUPPLIES close to the supply pin as possible, with the larger 10 µF bulk
The AD7616 has two independent power supplies, VCC and capacitor in parallel. Decouple the reference and LDO
VDRIVE, that supply the analog circuitry and digital interface, regulators as shown in Figure 49 and as described in Table 7.
respectively. Decouple both the VCC supply and the VDRIVE The analog input pins require a matched resistance, R, on both
supply with a 10 µF capacitor in parallel with a 100 nF capacitor. the VxA and VxAGND (similarly, VxB and VxBGND) inputs
Additionally, these supplies are regulated by two internal LDO to avoid a gain error on the analog input channels caused by an
regulators. The analog LDO (ALDO) typically supplies 1.87 V. impedance mismatch.
Decouple the ALDO with a 10 µF capacitor between the
Table 10. Functionality Matrix
Operation Mode1
Software Mode, HW_RNGSELx = 00 Hardware Mode, HW_RNGSELx ≠ 00
Functionality Serial, SER/PAR = 1 Parallel, SER/PAR = 0 Serial, SER/PAR = 1 Parallel, SER/PAR = 0
Internal/External Reference Yes Yes Yes Yes
Selectable Analog Input Ranges
Individual Channel Configuration Yes Yes No No
Common Channel Configuration No No Yes Yes
Sequential Sequencer Yes Yes Yes Yes
Fully Configurable Sequencer Yes Yes No No
Burst Mode Yes Yes Yes Yes
On-Chip Oversampling Yes Yes Yes No
CRC Yes Yes Yes No
Diagnostic Channel Conversion Yes Yes No No
Hardware Reset Yes Yes Yes Yes
Serial 1-Wire Mode Yes No Yes No
Serial 2-Wire Mode Yes No Yes No
Register Access Yes Yes No No
1
Yes means available; no means not available.

Rev. 0 | Page 26 of 50
Data Sheet AD7616
5V 2.5V/3.3V

10µF 0.1µF 0.1µF 10µF

VCC VDRIVE

REGCAP REGCAPD
ALDO DLDO

10µF AD7616 10µF

REGGND REGGNDD

VxA
R C PGA MUX ADC
VxAGND
R
VxB
R C MUX ADC
PGA
VxBGND
R
REFINOUT
REFCAP
BUF
0.1µF 10µF
x8R x5R
2.5V
REF

13591-300
REFINOUTGND REFGND

Figure 49. Typical External Connections

Rev. 0 | Page 27 of 50
AD7616 Data Sheet

DEVICE CONFIGURATION
OPERATIONAL MODE to high configures the interface. If the SER/PAR signal is set to 0,
The mode of operation, hardware mode or software mode, is the parallel interface is enabled. If the SER/PAR signal is set to 1,
configured when the AD7616 is released from full reset. The the serial interface is selected. Additionally, if the serial interface
logic level of the HW_RNGSELx pins when the RESET pin is selected, the SER1W signal is monitored when the RESET pin is
transitions from low to high determines the operational mode. The released to determine if serial 1-wire or 2-wire mode is selected.
HW_RNGSELx pins are dual function. If HW_RNGSELx = 0b00, After the interface is configured, changes to the logic level of the
the AD7616 enters software mode. Any other combination of SER/PAR signal or the SER1W signal (when the serial interface is
the HW_RNGSELx configures the AD7616 to hardware mode and enabled) are ignored. A full reset via the RESET pin is required
the analog input range is configured as per Table 8. After software to exit the operation mode and set up an alternative mode.
mode is configured, the logic level of the HW_RNGSELx signals is HARDWARE MODE
ignored. After an operational mode is configured, a full reset via
If hardware mode is selected, the available functionality is
the RESET pin is required to exit the operational mode and to set
restricted and all functionality is configured via pin control.
up an alternative mode. If hardware mode is selected, all further
The logic level of the following signals is checked after a full
device configuration is via pin control. Access to the on-chip
reset to configure the functionality of the AD7616: CRC,
registers is prohibited in hardware mode. In software mode, the
BURST, SEQEN, and OSx. Table 11 provides a summary of the
interface and reference configuration must be configured via
signals that are latched by the device on the release of a full
pin control but all further device configuration is via register
reset, depending on the mode of operation chosen. After the
access only.
device is configured, a full reset via the RESET pin is required to
INTERNAL/EXTERNAL REFERENCE exit the configuration and set up an alternative configuration.
The internal reference is enabled or disabled when the AD7616 Functionality availability is restricted depending on the interface
is released from a full reset. The logic level of the REFSEL signal type selected. See Table 10 for a full list of the functionality
when the RESET pin transitions from low to high configures the available in hardware parallel or serial mode.
reference. After the reference is configured, changes to the logic The CHSELx pins are queried at reset to determine the initial
level of the REFSEL signal are ignored. If the REFSEL signal is analog input channel pair to acquire for conversion or to configure
set to 1, the internal reference is enabled. If REFSEL is set to the initial settings for the sequencer. The channel pair selected
Logic 0, the internal reference is disabled and an external for conversion or the hardware sequencer can be reconfigured
reference must be supplied to the REFINOUT pin for correct during normal operation by setting and maintaining the
operation of the AD7616. A full reset via the RESET pin is required CHSELx signal level before the CONVST rising edge until the
to exit the operational mode and set up an alternative mode. BUSY falling edge.
Connect a 100 nF capacitor between the REFINOUT and The HW_RNGSELx signals control the analog input range for
REFINOUTGND pins. If using an external reference, place a all 16 analog input channels. A logic change on these pins has an
10 kΩ band limiting resistor in series between the reference and immediate effect on the analog input range; however, the typical
the REFINOUT pin of the AD7616. settling time is approximately 120 µs, in addition to the normal
DIGITAL INTERFACE acquisition time requirement. The recommended practice is to
hardwire the range select pins according to the desired input
The digital interface selection, parallel or serial, is configured
range for the system signals.
when the AD7616 is released from a full reset. The logic level of
the SER/PAR signal when the RESET pin transitions from low Access to the on-chip registers is prohibited in hardware mode.

Rev. 0 | Page 28 of 50
Data Sheet AD7616
Table 11. Summary of Latched Hardware Signals1
Latched at Full Reset Read at Reset Read During Busy Edge Driven
HW SW HW SW HW SW
Signal HW Mode SW Mode Mode Mode Mode Mode Mode Mode
REFSEL Yes Yes
SEQEN Yes No
HW_RNGSELx (Range Change) Yes Yes Yes No
HW_RNGSELx (Hardware (HW) or Software Yes Yes
(SW) Mode)
SER/PAR Yes Yes
CRCEN Yes No
OSx Yes No
BURST Yes No
CHSELx Yes No Yes No
SER1W Yes Yes
1
Blank cells in Table 11 mean not applicable.

SOFTWARE MODE A full reset returns the device to its default power-on state. The
If software mode is selected and the reference and interface type following features are configured when the AD7616 is released
is configured, all other configuration settings in the AD7616 are from full reset:
controlled via the on-chip registers. All functionality of the • Hardware mode or software mode
AD7616 is available when software mode is selected. Table 11 • Internal/external reference
provides a summary of the signals that are latched by the device on • Interface type
the release of a full reset, depending on the mode of operation
chosen. On power-up, the RESET signal can be released as soon as both
the VCC and VDRIVE supplies are stable. The logic level of the
RESET FUNCTIONALITY HW_RNGSELx, REFSEL, SER/PAR and DB4/SER1W pins when
The AD7616 has two reset modes: full or partial. The reset the RESET pin is released after a full reset determines the
mode selected is dependent on the length of the reset low pulse. configuration.
A partial reset requires the RESET pin to be held low between
If hardware mode is selected, the functionality determined by
40 ns and 500 ns. After 50 ns from release of RESET, the device
the CRC, BURSTEN, SEQEN, and OSx signals is also latched
is fully functional and a conversion can be initiated. A full reset
when the RESET pin transitions from low to high in full reset
requires the RESET pin to be held low for a minimum of 1.2 µs.
mode. After the functionality is configured, changes to these
After 15 ms from release of RESET, the devices is completely signals are ignored. In hardware mode, the analog input range
reconfigured and a conversion can be initiated. (HW_RNGSELx signals) can be configured during either a full
A partial reset reinitializes the following modules: or partial reset or during normal operation, but hardware/software
mode selection requires a full reset to reconfigure while this
• Sequencer
setting is latched.
• Digital filter
• SPI In hardware mode, the CHSELx and HW_RNGSELx pins are
• Both SAR ADCs queried at release from both a full and a partial reset to perform
the following actions:
The current conversion result is discarded on completion of a
• Determine the initial analog input channel pair to acquire
partial reset. The partial reset does not affect the register values
for conversion.
programmed in software mode or the latches that store the user
configuration in both hardware and software modes. A dummy • Configure the initial settings for the sequencer.
conversion is required in software mode after a partial reset. • Select the analog input voltage range.

Rev. 0 | Page 29 of 50
AD7616 Data Sheet
The CHSELx and HW_RNGSELx signals are not latched. The PIN FUNCTION OVERVIEW
channel pair selected for conversion, or the hardware sequencer, There are several dual function pins on the AD7616. Their
can be reconfigured during normal operation by setting and functionality is dependent on the mode of operation selected by
maintaining the CHSELx signal level before the CONVST rising the HW_RNGSELx pins. Table 12 outlines the pin functionality
edge, and ensuring the signal level remains constant until after in the different modes of operation and interface modes.
BUSY transitions low again. See the Channel Selection section
for further details.
In software mode, all additional functionality is configured by
controlling the on-chip registers.

tRESET_WAIT
tDEVICE_SETUP
VCC
VDRIVE

RESET

CONVST

BUSY

tRESET_SETUP
tRESET_HOLD
REFSEL
SER/PAR, SER1W
ALL MODES
HW_RNGSEL0,
HW_RNGSEL1 MODE RANGE SETTING IN HW MODE

CRCEN, BURST
SEQEN, OS0 TO OS2
HARDWARE
MODE ONLY CHSEL0 TO CHSEL2 CHx y z

13591-012
ACTION ACQx CONV x ACQy CONVy

Figure 50. AD7616 Configuration at Reset

Table 12. Pin Functionality Overview

Operation Mode
Software, HW_RNGSELx = 00 Hardware, HW_RNGSELx ≠ 00
Pins Serial, SER/PAR = 1 Parallel, SER/PAR = 0 Serial, SER/PAR = 1 Parallel, SER/PAR = 0
CHSELx No function, connect to No function, connect CHSELx CHSELx
DGND to DGND
SCLK/RD SCLK RD SCLK RD
WR/BURST Connect to DGND WR BURST BURST
DB15/OS0 to Connect to DGND DB15 to DB13 OSx DB15 to DB13
DB13/OS2
DB12/SDOA SDOA DB12 SDOA DB12
DB11/SDOB SDOB, leave floating for DB11 SDOB DB11
serial 1-wire mode
DB10/SDI SDI DB10 Connect to DGND DB10
DB9 to DB6, DB3 Connect to DGND DB9 to DB6, DB3 to Connect to DGND DB9 to DB6, DB3 to DB0
to DB0 DB0
DB5/CRCEN Connect to DGND DB5 CRCEN DB5
DB4/SER1W SER1W DB4 SER1W DB4
HW_RNGSELx HW_RNGSELx, connect to HW_RNGSELx, connect HW_RNGSELx, configure HW_RNGSELx, configure
DGND to DGND analog input range analog input range
SEQEN No function, connect to No function, connect SEQEN SEQEN
DGND to DGND
REFSEL REFSEL REFSEL REFSEL REFSEL

Rev. 0 | Page 30 of 50
Data Sheet AD7616

DIGITAL INTERFACE
CHANNEL SELECTION Software Mode
Hardware Mode In software mode, the channels for conversion are selected by
The logic level of the CHSELx signals determine the channel control of the channel register. On power-up or after a reset, the
pair for conversion; see Table 13 for signal decoding information. default channels selected for conversion are Channel V0A and
The CHSELx signals at the time that either full or partial reset is Channel V0B.
released determine the initial channel pair to sample. After a reset, Table 13. CHSELx Pin Decoding
the logic levels of the CHSELx signals are examined during the
Channel Selection Input Pin Analog Input Channels for
BUSY high period to set the channel pair for the next conversion.
CHSEL0 CHSEL1 CHSEL2 Conversion
The CHSELx signal level must be set before CONVST goes from
0 0 0 V0A, V0B
low to high and be maintained until BUSY goes from high to
0 0 1 V1A, V1B
low to indicate a conversion is complete. See Figure 51 for
0 1 0 V2A, V2B
further details.
0 1 1 V3A, V3B
1 0 0 V4A, V4B
1 0 1 V5A, V5B
1 1 0 V6A, V6B
1 1 1 V7A, V7B

RESET

CONVST

BUSY

CHSEL2
TO CHx CHy CHz CH...
CHSEL0

DATA BUS A/Bx A/By A/Bz

13591-013
INITIAL SETUP
CONFIGURE POINT CONFIGURE POINT CONFIGURE POINT
Figure 51. Hardware Mode Channel Conversion Setting
RESET

CONVST

BUSY

CS

SDI WRITE CHx WRITE CHy WRITE CHz WRITE CH...

SDOA,
13591-014

DO NOT CARE A/B0 A/Bx A/By

SDOB
CHx CONVERSION START

Figure 52. Software Serial Mode Channel Conversion Setting

RESET

CONVST

BUSY

CS

WR

RD

DB0 TO B0 CHy Ay By CH...

13591-153

CH x A0 Ax Bx CHz
DB15
CHx CONVERSION START

Figure 53. Software Parallel Mode Channel Conversion Setting

Rev. 0 | Page 31 of 50
AD7616 Data Sheet
goes low clocks out the conversion result from Channel AX. The
PARALLEL INTERFACE
next RD falling edge updates the bus with the Channel BX
The parallel interface reads the conversion results, and config- conversion result.
ures and reads back the on-chip registers. Data can be read from
Writing Register Data
the AD7616 via the parallel data bus with standard CS, RD,
and WR signals. To read the data over the parallel bus, tie the In software mode, all the read/write registers in the AD7616 can
SER/PAR pin low. be written to over the parallel interface. A register write
command is performed by a single 16-bit parallel access via the
Reading Conversion Results parallel bus (DB15 to DB0), CS, and WR signals. Provide data
The CONVST signal initiates the conversion process. A low to written to the AD7616 on the DB15 to DB0 inputs, with DB0
high transition on the CONVST signal initiates a conversion of being the LSB of the data-word. The format for a write
the selected inputs. The BUSY signal goes high to indicate a command is shown in Figure 54. Bit D15 must be set to 1 to
conversion is in progress. When the BUSY signal transitions select a write command. Bits[D14:D9] contain the register
from high to low to indicate that a conversion is complete, it is address. The subsequent nine bits (Bits[D8:D0]) contain the
possible to read back conversion results on the parallel interface. data to be written to the selected register. See the Register
Data can be read from the AD7616 via the parallel data bus with Summary section for the complete list of register addresses.
standard CS and RD signals. The CS and RD input signals are Data is latched into the device on the rising edge of WR.
internally gated to enable the conversion result onto the data CS

bus. The data lines, DB15 to DB0, leave their high impedance
WR
state when both CS and RD are logic low.

13591-020
DB15
The rising edge of the CS input signal three-states the bus, and TO WRITE REG 1 WRITE REG 2
DB0
the falling edge of the CS input signal takes the bus out of the Figure 54. Parallel Interface Register Write
high impedance state. CS is the control signal that enables the
data lines; it is the function that allows multiple AD7616 Reading Register Data
devices to share the same parallel data bus. All the registers in the device can be read over the parallel interface.
A register read is performed by first writing the address of the
The number of required read operations depends on the device
register to be read to the AD7616. The format for a register read
configuration. A minimum of two reads are required to read the
command is shown in Figure 56. Bit D15 must be set to 0 to
conversion result for the simultaneously sampled A and B
select a read command. Bits[D14:D9] contain the register address.
channels. If additional functions such as CRC, status, and burst
The subsequent nine bits (Bits[D8:D0]) are ignored. The read
mode are enabled, the number of required readbacks increases
accordingly. command is latched into the AD7616 on the rising edge of WR.
This latch transfers the relevant register data to the output
The RD pin reads data from the output conversion results register. register. The register data can then be read on the DB15 to DB0
Applying a sequence of RD pulses to the RD pin of the AD7616 pins by using a standard read command. See Figure 56 for
clocks the conversion results out from each channel onto the additional information.
parallel bus, DB15 to DB0. The first RD falling edge after BUSY

CONVST

BUSY

CS

RD
13591-016

DB15 TO DB0 CONV A CONV B

Figure 55. Parallel Interface Conversion Readback

CS

WR

RD
13591-023

DB15 TO DB0 READ REG 1 DATA REG 1 READ REG 2 DATA REG 2

Figure 56. Parallel Interface Register Read

Rev. 0 | Page 32 of 50
Data Sheet AD7616
SERIAL INTERFACE onto the serial data outputs, SDOA and SDOB. Figure 57 shows
a read of two simultaneous conversion results using two SDOx
To interface to the AD7616 over the SPI, the SER/PAR pin must
lines on the AD7616. If the status register is appended to the
be tied high. The CS and SCLK signals transfer data from the
conversion results or operating in sequencer burst mode where
AD7616. The AD7616 has two serial data output pins, SDOA
multiples of 16 SCLK transfers access data from the AD7616,
and SDOB. Data is read back from the AD7616 using serial
hold CS low to frame the entire data. Data can also be clocked
1-wire or serial 2-wire mode.
out using just one SDOx line, in which case SDOA must be used
In serial 2-wire mode for the AD7616, conversion results from to access all conversion data. For the AD7616 to access both
Channel V0A to Channel V7A appear on SDOA, and conversion Channel VxA and Channel VxB conversion results on one
results from Channel V0B to Channel V7B appear on SDOB. SDOx line, a total of 32 SCLK cycles is required. Frame these
In serial 1-wire mode, conversion results from Channel V0B 32 SCLK cycles using one CS signal, or individually frame each
to Channel V7B are interlaced with conversion results from group of 16 SCLK cycles using the CS signal. The disadvantage
Channel V0A to Channel V7A. To achieve the maximum of using just one SDOx line is that the throughput rate is reduced.
throughput, it is required to use 2-wire mode.
Leave the unused SDOB line unconnected in serial 1-wire
To read back data over both SDOA and SDOB, the SER1W pin mode. If using SDOA as a single serial data output line, the
must be tied high. If data is to be read back over SDOA only, the channel results are output in the following order: VxA and VxB.
SER1W pin must be tied low. Serial 1-wire or 2-wire mode is Figure 58 shows a 1-wire, serial readback operation.
configured when the AD7616 is released from full reset.
The speed at which the data can be read back in serial interface
Reading Conversion Results mode is dependent on SPI frequency, VDRIVE supply, and the
The CONVST signal initiates the conversion process. A low to capacitance of the load on the SDO line, CLOAD. Table 14 shows a
high transition on the CONVST signal initiates a conversion of summary of the maximum speed achievable for various conditions.
the selected inputs. The BUSY signal goes high to indicate a
Table 14. SPI Frequency vs. Load Capacitance and VDRIVE
conversion is in progress. When the BUSY signal transitions
from high to low to indicate that a conversion is complete, it is VDRIVE (V) CLOAD (pF) SPI Frequency (MHz)
possible to read back conversion results on the serial interface. 2.3 to 3 20 40
3 to 3.6 30 50
The CS falling edge takes the data output lines, SDOA and SDOB,
out of three-state and clocks out the MSB of the conversion
result. The rising edge of SCLK clocks all subsequent data bits

CONVST

BUSY

CS

SCLK 1 2 3 14 15 16

SDOA DB15 DB14 DB13 DB2 DB1 DB0

CHANNEL VAx RESULT

13591-017

SDOB DB15 DB14 DB13 DB2 DB1 DB0

CHANNEL VBx RESULT

Figure 57. Serial Interface, 2-Wire Mode

CONVST

BUSY

CS

SCLK 1 2 15 16 17 18 31 32
13591-018

SDOA DB15 DB14 DB1 DB0 DB15 DB14 DB1 DB0

CHANNEL VAx RESULT CHANNEL VBx RESULT
Figure 58. Serial Interface, 1-Wire Mode

Rev. 0 | Page 33 of 50
AD7616 Data Sheet
Writing Register Data Reading Register Data
All the read/write registers in the AD7616 can be written to All the registers in the device can be read over the serial
over the serial interface. A register write command is performed interface. A register read is performed by issuing a register read
by a single 16-bit SPI access. The format for a write command is command followed by an additional SPI command that can be
shown in Table 15. Bit D15 must be set to 1 to select a write either a valid command or no operation (NOP). The format for
command. Bits[D14:D9] contain the register address. The a read command is shown in Table 16. Bit D15 must be set to 0
subsequent nine bits (Bits[D8:D0]) contain the data to be to select a read command. Bits[D14:D9] contain the register
written to the selected register. Figure 59 shows a typical serial address. The subsequent nine bits (Bits[D8:D0]) are ignored.
write command. See the Register Summary section for the complete list of register
addresses. Figure 60 shows a typical serial read command.
CONVST

CS

SDI WRITE REG 1 WRITE REG 2 WRITE REG 3

13591-021
SDOA, SDOB CONV RESULT INVALID INVALID

Figure 59. Serial Interface Register Write

CONVST

CS

SDI READ REG 1 READ REG 2 READ REG 3

13591-024
SDOA CONV RESULT REG 1 DATA REG 2 DATA

Figure 60. Serial Interface Register Read

Table 15. Write Command Message Configuration

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W/R REGADDR[5:0] Data[8:0]
1 Register address Data to write

Table 16. Read Command Message Configuration

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W/R REGADDR[5:0] Data[8:0]
0 Register address Do not care

Rev. 0 | Page 34 of 50
Data Sheet AD7616

SEQUENCER
The AD7616 features a highly configurable on-chip sequencer. When the sequencer is enabled, the logic levels of the CHSELx pins
The functionality and configuration of the sequencer is determine the channels selected for conversion in the sequence.
dependent on the mode of operation of the AD7616. The CHSELx pins at the time RESET is released determine the
In hardware mode, the sequencer is sequential only. The initial settings for the channels to convert in the sequence. To
sequencer always starts converting at Channel V0A and reconfigure the channels selected for conversion thereafter, set
Channel V0B and converts each subsequent channel up to the the CHSELx pins to the required setting for the duration of the
configured end channel. final BUSY pulse before the current conversion sequence is
complete. See Figure 61 for further details.
In software mode, the sequencer has additional functionality
and configurability. The sequencer stack has 32 uniquely Table 18. CHSELx Pin Decoding Sequencer
configurable sequence steps, allowing any channel order to be Channel Selection Input Pin Analog Input Channels for
programmed. Additionally, any Channel VxA input can be CHSEL0 CHSEL1 CHSEL2 Sequential Conversion
paired with any Channel VxB input or diagnostic channel. 0 0 0 V0x only
The sequencer can be operated with or without the burst 0 0 1 V0x to V1x
function enabled. With the burst function enabled, only one 0 1 0 V0x to V2x
CONVST pulse is required to convert every channel in a 0 1 1 V0x to V3x
sequence. With burst mode disabled, one CONVST pulse is 1 0 0 V0x to V4x
required for every conversion step in the sequence. See the 1 0 1 V0x to V5x
Burst Sequencer section for additional details on operating in 1 1 0 V0x to V6x
burst mode. 1 1 1 V0x to V7x
HARDWARE MODE SEQUENCER SOFTWARE MODE SEQUENCER
In hardware mode, the sequencer is controlled by the SEQEN pin In software mode, the AD7616 contains a 32-layer fully
and the CHSELx pins. The sequencer is enabled or disabled configurable sequencer stack. Control of the sequencer is
when the AD7616 is released from full reset. The logic level of achieved by programming the configuration register and
the SEQEN pin when the RESET pin is released determines sequencer stack registers via the parallel or serial interface.
whether the sequencer is enabled or disabled (see Table 17 for Each stack step can be individually programmed to pair any
settings). After the RESET pin is released, the function is fixed input from Channel VxA to any input from Channel VxB, or
and a full reset via the RESET pin is required to exit the any diagnostic channel can be selected for conversion. The
function and set up an alternative configuration. sequencer depth can be set to any length from 1 to 32 layers.
The sequencer depth is controlled via the SSRENx bit. Set the
Table 17. Hardware Mode Sequencer Configuration SSRENx bit in the sequencer stack register corresponding to the
SEQEN Interface Mode last step required. The channels to convert are selected by
0 Sequencer disabled programming the ASELx and BSELx bits in each sequence stack
1 Sequencer enabled register for the depth required.
The sequencer is activated by setting the SEQEN bit in the
configuration register to 1.

RESET

SEQEN

CONVST

BUSY

CHSEL2 TO CHSEL0 CHx CHy CHz

13591-025

DATA A/B0 A/Bx-1 A/Bx A/B0 A/By-1 A/By A/B0

INITIAL SETUP CONFIGURE POINT CONFIGURE POINT

Figure 61. Hardware Mode Sequencer Configuration

Rev. 0 | Page 35 of 50
AD7616 Data Sheet
To configure and enable the sequencer, it is recommended to The conversion results are presented on the data bus (parallel or
complete the following procedure (see Figure 62): serial) in the same order as the programmed sequence.
1. Configure the analog input range for the required analog The throughput rate of the AD7616 is limited in burst mode
input channels. and dependent on the length of the sequence. Each channel pair
2. Program the sequencer stack registers to select the requires an acquisition, conversion, and readback time. The
channels for the sequence. time taken to complete a sequence with number of channel
3. Set the SSRENx bit in the last required sequence step. pairs, N, is estimated by
4. Set the SEQEN bit in the configuration register. tBURST = (tCONV + 25 ns) + (N – 1)(tACQ + tCONV) + N(tRB)
5. Provide a dummy CONVST pulse.
6. Cycle through CONVST pulses and conversion reads to step where:
through each element of the sequencer stack. tCONV is the typical conversion time.
tACQ is typical acquisition time.
The sequence automatically restarts from the first element in tRB is the time required to read back the conversion results in
the sequencer stack with the next CONVST pulse. either serial 1-wire, serial 2-wire, or parallel mode.
Following a partial reset, the sequencer pointer is repositioned Hardware Mode Burst
to the first layer of the stack, but the register programmed
Burst mode is enabled in hardware mode by setting the BURST pin
values remain unchanged.
to 1. The SEQEN pin must also be set to 1 to enable the sequencer.
BURST SEQUENCER In hardware mode, the burst sequencer is controlled by the BURST,
Burst mode avoids generating a CONVST pulse for each step in SEQEN, and CHSELx pins. The burst sequencer is enabled or
a sequence of conversions. One CONVST pulse converts every disabled when the AD7616 is released from full reset. The logic
step in the sequence. level of the SEQEN pin and the BURST pin when the RESET pin
The burst sequencer is an additional feature that works in is released determines whether the burst sequencer is enabled
conjunction with the sequencer. If the burst function is enabled, or disabled. After the RESET pin is released, the function is
one CONVST pulse initiates a conversion of all the channels fixed and a full reset via the RESET pin is required to exit the
configured in the sequencer. The burst function avoids generating function and set up an alternative configuration.
a CONVST pulse for each step in a sequence of conversions, as When the burst sequencer is enabled, the logic levels of the
is the case when the burst function is disabled. CHSELx pins determine the channels selected for conversion in the
Configuration of the burst function varies depending on the burst sequence. The CHSELx pins at the time RESET is released
mode of operation: hardware or software mode. See the Hardware determines the initial settings for the channels to convert in the
Mode Burst section and the Software Mode Burst section for burst sequence. To reconfigure the channels selected for conver-
specific details on configuring the burst function in the each sion after a reset, set the CHSELx pins to the required setting
mode. for the duration of the next BUSY pulse (see Figure 63 for
When configured, the burst sequence is initiated at the rising further details).
edge of CONVST. The BUSY pin goes high to indicate that a Software Mode Burst
conversion is in progress. The BUSY pin remain highs until all In software mode, the burst function is enabled by setting the
conversions in the sequence are complete. The conversion BURST bit in the configuration register to 1. This action must
results are available for readback after the BUSY pin goes low. be performed when setting the SEQEN bit in the configuration
The number of data reads required to read all the data in the burst register as outlined in the steps described in the Software Mode
sequence is dependent on the length of the sequence configured. Sequencer section to configure the sequencer (see Figure 64 for
additional information).
RESET

CONVST

BUSY

REGISTER
SETUP

DATA A/B0 S0 S1 Sn – 1 Sn S0
13591-026

INITIAL SETUP SEQUENCE START SEQUENCE START

DUMMY CONVERSION

Figure 62. Software Mode Sequencer Configuration

Rev. 0 | Page 36 of 50
Data Sheet AD7616
RESET

SEQEN

BURST

CONVST

BUSY

CHSEL2
TO CHx CHy CHz CHz CHz
CHSEL0

A/B0 A/Bx–1 A/Bx A/B0 A/By–1 A/By A/B0 A/Bz–1 A/Bz

13591-027
DATA

INITIAL SETUP CONFIGURE POINT CONFIGURE POINT CONFIGURE POINT

Figure 63. BURST Sequencer, Hardware Mode

RESET

CONVST

BUSY

REGISTER
SETUP

A/B0 S0 S1 Sn–1 Sn S0 S1 Sn–1 Sn

13591-028
DATA

DUMMY CONVERSION
Figure 64. BURST Sequencer, Software Mode

Rev. 0 | Page 37 of 50
AD7616 Data Sheet

DIAGNOSTICS
DIAGNOSTIC CHANNELS
–7200

–7400
In addition to the 16 analog inputs, VxA and VxB, the AD7616
can also convert the following diagnostic channels: VCC and the –7600

EXPECTED OUTPUT (Codes)

analog ALDO voltage. The diagnostic channels are selected for –7800
conversion by programming the channel register (see the Channel
Register section) to the corresponding channel identifier. Diagnos- –8000

tic channels can also be added to the sequencer stack in software –8200
mode, but only provide an accurate reading at throughput rates
–8400
<250 kSPS. See Figure 65 for a plot of the deviation from
expected value vs. sampling frequency that can be expected –8600

when using the diagnostic channels. –8800

The expected output for each channel is governed by the –9000

13591-030
following transfer functions: 1.75 1.80 1.85 1.90 1.95
ALDO (V)

VCC Code =
((4 × VCC ) – VREF ) × 32,768 Figure 67. ALDO Diagnostic Transfer Function
5 × VREF
INTERFACE SELF TEST
LDO Code =
((10 × VALDO ) – (7 × VREF )) × 32,768 It is possible to test the integrity of the digital interface by
10 × VREF selecting the communication self test channel in the channel
750 register (see the Channel Register section).
DEVIATION FROM EXPECTED VALUE (Codes)

Selecting the communication self test for conversion forces the

500
conversion result register to a known fixed output. When
conversion code is read, Code 0xAAAA is output as the
250
conversion code of ADC A, and Code 0x5555 is output as the
conversion code of ADC B.
0 VCC ERROR

ALDO ERROR
CRC
–250 The AD7616 has a cyclic redundancy check (CRC) checksum
mode to improve interface robustness by detecting errors in
–500
data. The CRC feature is available in both software (serial and
parallel) mode and hardware (serial only) mode. The CRC
–750
feature is not available in hardware parallel mode. The CRC
13591-035

0 100 200 300 400 500 600

SAMPLING FREQUENCY (kSPS) result is contained within the status register. Enabling the CRC
Figure 65. Deviation from Expected Value vs. Sampling Frequency feature enables the status register and vice versa.
29000 In hardware mode, the CRCEN pin controls the CRC feature.
The CRC feature is enabled or disabled when the AD7616 is
28000
released from full reset. The logic level of the CRCEN pin when
EXPECTED OUTPUT (Codes)

27000 the RESET pin is released determines whether the CRC feature is
enabled or disabled. Set the CRCEN pin to 1 to enable the CRC
26000 feature. After the RESET pin is released, the function is fixed
and a full reset via the RESET pin is required to exit the
25000
function and set up an alternative configuration. See the Reset
24500 Functionality section for additional information. After being
enabled, the CRC result is appended to the conversion result and
23000
consists of a 16-bit word, where the first eight bits contain the
channel ID of the last channel pair converted and the last eight
22000
bits are the CRC result. The result is accessed via an extra read
13591-029

4.50 4.75 5.00 5.25 5.50

VCC (V)
command, as shown in Figure 68.
Figure 66. VCC Diagnostic Transfer Function In software mode, the CRC function is enabled by setting either
the CRCEN bit or the STATUSEN bit in the configuration
register to 1 (see the section).

Rev. 0 | Page 38 of 50
Data Sheet AD7616
If the CRC function is enabled, a CRC is calculated on the crc_out[3] = data[14] ^ data[13] ^ data[11]
conversion results for Channel VxA and Channel VxB. The ^ data[9] ^ data[7] ^ data[3] ^ data[2] ^
data[1] ^ crc[1] ^ crc[3] ^ crc[5] ^ crc[6];
CRC is calculated and transferred on the serial or parallel
interface after the conversion results are transmitted, depending crc_out[4] = data[15] ^ data[14] ^ data[12]
^ data[10] ^ data[8] ^ data[4] ^ data[3] ^
on the configuration of the device. The Hamming distance
data[2] ^ crc[0] ^ crc[2] ^ crc[4] ^ crc[6]
varies relative to the number of bits in the conversion result. For ^ crc[7];
conversions with ≤119 bits, the Hamming distance is 4. For
crc_out[5] = data[15] ^ data[13] ^ data[11]
>119 bits, the Hamming distance is 1, that is, 1-bit errors are ^ data[9] ^ data[5] ^ data[4] ^ data[3] ^
always detected. crc[1] ^ crc[3] ^ crc[5] ^ crc[7];
The following is a pseudocode description of how the CRC is crc_out[6] = data[14] ^ data[12] ^ data[10]
implemented in the AD7616: ^ data[6] ^ data[5] ^ data[4] ^ crc[2] ^
crc[4] ^ crc[6];
crc = 8’b0;
crc_out[7] = data[15] ^ data[13] ^ data[11]
i = 0; ^ data[7] ^ data[6] ^ data[5] ^ crc[3] ^
x = number of conversion channel pairs; crc[5] ^ crc[7];
for (i=0, i<x, i++) begin The initial CRC word used by the AD7616 is an 8-bit word
crc1 = crc_out(An,Crc); equal to zero. The XOR operation described in the preceding
crc = crc_out(Bn,Crc1); code is executed to calculate each bit of the CRC word for the
conversion result, AN. This CRC word (crc1) is then used as the
i = i +1;
starting point for calculating the CRC word (crc) for the
end conversion result, BN. The process repeats cyclically for each
where the function crc_out(data, crc) is channel pair converted.
crc_out[0] = data[14] ^ data[12] ^ data[8] ^ Depending on the mode of operation of the AD7616, the status
data[7] ^ data[6] ^ data[0] ^ crc[0] ^ register value is appended to the conversion data and read out
crc[4] ^ crc[6];
via an extra read command over the serial or parallel interface.
crc_out[1] = data[15] ^ data[14] ^ data[13] The user can then repeat the XOR calculation described in the
^ data[12] ^ data[9] ^ data[6] ^ data[1] ^
data[0] ^ crc[1] ^ crc[4] ^ crc[5] ^ crc[6] preceding code for the received conversion results to check
^ crc[7]; whether both CRC words match. See Figure 68 or a description
crc_out[2] = data[15] ^ data[13] ^ data[12]
of how the CRC word is appended to the data for each mode of
^ data[10] ^ data[8] ^ data[6] ^ data[2] ^ operation.
data[1] ^ data[0] ^ crc[0] ^ crc[2] ^ crc[4]
^ crc[5] ^ crc[7];

CONVST

BUSY

PARALLEL/SERIAL (1-WIRE), Ax Bx CRCAB(x)

SEQUENCER/MANUAL MODE DATA

PARALLEL/SERIAL (1-WIRE), Ax Bx Az Bz CRC AB(x:z)

BURST DATA

SDOA Ax CRCAB(x)
SERIAL (2-WIRE),
SEQUENCER/MANUAL MODE
SDOB Bx CRCAB(x)

SDOA Ax Az CRCAB(x:z)
SERIAL (2-WIRE),
BURST
13591-032

SDOB Bx Bz CRCAB(x:z)

Figure 68. CRC Readback for All Modes

Rev. 0 | Page 39 of 50
AD7616 Data Sheet

REGISTER SUMMARY
The AD7616 has six read/write registers used for configuring the device in software mode and an additional 32 sequencer stack registers
for programming the flexible on-chip sequencer and a read only status register. Table 19 shows an overview of the read/write registers
available on the AD7616. The status register is an additional read only register than contains information on the channel pair previously
converted and the CRC result.

Table 19. Register Summary1

Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x02 Configuration [15:8] Addressing Reserved 0x0000 R/W
register
[7:0] SDEF BURSTEN SEQEN OS STATUSEN CRCEN
0x03 Channel [15:8] Addressing Reserved 0x0000 R/W
register
[7:0] CHB CHA
0x04 Input Range [15:8] Addressing Reserved 0x00FF R/W
Register A1
[7:0] V3A V2A V1A V0A
0x05 Input Range [15:8] Addressing Reserved 0x00FF R/W
Register A2
[7:0] V7A V6A V5A V4A
0x06 Input Range [15:8] Addressing Reserved 0x00FF R/W
Register B1
[7:0] V3B V2B VB1 V0B
0x07 Input Range [15:8] Addressing Reserved 0x00FF R/W
Register B2
[7:0] V7B V6B VB5 V4B
0x20 Sequencer [15:8] Addressing SSRENx 0x00002 R/W
to Stack
[7:0] BSELx ASELx
0x3F Registers[0:31]
N/A Status register [15:8] A[3:0] B[3:0] N/A R
[7:0] CRC[7:0]
1
N/A means not applicable.
2
After a full or partial rest is issued, the sequencer stack register is reinitialized to cycle through Channel V0A and Channel V0B to Channel V7A and Channel V7B. The
remaining 24 layers of the stack are reinitialized to 0x0.

Rev. 0 | Page 40 of 50
Data Sheet AD7616
ADDRESSING REGISTERS
The seven MSBs written to the device are decoded to determine which register is addressed. The seven MSBs consist of the register
address (REGADDR), Bits[5:0], and the read/write bit. The register address bits determine which on-chip register is selected. The
read/write bit determines if the remaining nine bits of data on the DB10/SDI lines are loaded into the addressed register. If the read/write
bit is 1, the bits load into the register addressed by the register select bits. If the read/write bit is 0, the command is seen as a read request.
The addressed register data is available to be read during the next read operation.

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 to D0
W/R REGADDR[5] REGADDR[4] REGADDR[3] REGADDR[2] REGADDR[1] REGADDR[0] DATA[8:0]

Table 20.
Bit s Mnemonic Description
D15 W/R If a 1 is written to this bit, Bits[D8:D0] of this register are written to the register specified by REGADDR[5:0].
Alternatively, if a 0 is written, the next operation is a read from the designated register.
D14 REGADDR[5] If a 1 is written to this bit, the contents of REGADDR[4:0] specifies the 32 sequencer stack registers.
Alternatively, if a 0 is written to this bit, a register is selected as defined by REGADDR[4:0].
[D13:D9] REGADDR[4:0] When W/R =1, the contents of REGADDR[4:0] determine register for selection as follows:
00001: reserved.
00010: selects the configuration register.
00011: selects the channel register.
00100: selects Input Range Register A1.
00101: selects Input Range Register A2.
00110: selects Input Range Register B1.
00111: selects Input Range Register B2.
01000: selects the status register
When W/R = 0, and REGADDR[4:0] contains 00000, the conversion codes are read.
[D8:D0] DATA[8:0] These bits are written into the corresponding register specified by Bits REGADDR[5:0]. See the following
sections for detailed descriptions of each register.

Rev. 0 | Page 41 of 50
AD7616 Data Sheet
CONFIGURATION REGISTER
The configuration register is used in software mode to configure many of the main functions of the ADC, including the sequencer, burst
mode, oversampling, and CRC options.
Address: 0x02, Reset: 0x0000, Name: Configuration Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[15:9] Addressing (R/W) [0] CRCEN (R/W)

CRC Enable
[8] RESERVED
[1] STATUSEN (R/W)
[7] SDEF (R) Status Register Output Enable
Self-Detector Error flag
[4:2] OS (R/W)
[6] BURSTEN (R/W) OS ratio sam ples per channel
Burst Mode enable 000: OS1.
001: OS2.
010: OS4.
011: OS8.
100: OS16.
101: OS32.
110: OS64.
111: OS128.
[5] SEQEN (R/W)
Channel Sequencer Enable

Table 21. Bit Descriptions for the Configuration Register

Bits Bit Name Settings Description Reset1 Access
[15:9] Addressing 0 Bits[15:9] define the address of the relevant register. See the Addressing Registers 0x0 RW
section for further details.
8 RESERVED Reserved. 0x0 R/W
7 SDEF Self detector error flag. N/A R
0 Test passed. The AD7616 has configured itself successfully after power-up.
1 Test failed. An issue was detected during device configuration. A reset is required.
6 BURSTEN Burst mode enable. 0x0 RW
0 Burst mode is disabled. Each channel pair to be converted requires a CNVST pulse.
1 A single CNVST pulse converts every channel pair programmed in the 32-layer
sequencer stack registers up to and including the layer defined by the SSRENx bit. See
the Software Mode Sequencer section and the Software Mode Burst section for
further details.
5 SEQEN Channel sequencer enable. 0x0 RW
0 The channel sequencer is disabled.
1 The channel sequencer is enabled.
[4:2] OS Oversampling (OS) ratio, samples per channel. 0x0 RW
000 Oversampling disabled.
001 Oversampling enabled, OSR = 2.
010 Oversampling enabled, OSR = 4.
011 Oversampling enabled, OSR = 8.
100 Oversampling enabled, OSR = 16.
101 Oversampling enabled, OSR = 32.
110 Oversampling enabled, OSR = 64.
111 Oversampling enabled, OSR = 128.
1 STATUSEN Status register output enable. 0x0 RW
0 The status register is not read out when reading the conversion result.
1 The status register is read out at the end of all the conversion words (including the
self test channel if enabled in sequencer mode) if all the selected channels are read
out. The CRC result is included in the last eight bits.
0 CRCEN CRC enable. The STATUSEN and CRCEN bits have identical functionality. 0x0 RW
1
N/A means not applicable.

Rev. 0 | Page 42 of 50
Data Sheet AD7616
CHANNEL REGISTER
Address: 0x03, Reset: 0x0000, Name: Channel Register
In software manual mode, the channel register selects the input channel or self test channel for the next conversion.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[15:9] Addressing (R/W) [3:0] CHA (R/W)

Channel Selection bits for ADC A
[8] RESERVED Channels
0: V0A.
1: V1A.
10: V2A.
...
1010: Reserved.
1011: 0XAAAA.
1100: Reserved.
[7:4] CHB (R/W)
Channel Selection bits for ADC B
Channels
0: V0B.
1: V1B.
10: V2B.
...
1010: Reserved.
1011: 0x5555.
1100: Reserved.

Table 22. Bit Descriptions for the Channel Register

Bits Bit Name Settings Description Reset Access
[15:9] Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers 0x0 R/W
section for further details.
8 RESERVED Reserved. 0x0 R/W
[7:4] CHB Channel selection bits for ADC B channels.
0000 V0A/V0B.
0001 V1A/V1B.
0010 V2A/V2B.
0011 V3A/V3B.
0100 V4A/V4B.
0101 V5A/V5B.
0110 V6A/V6B.
0111 V7A/V7B.
1000 VCC.
1001 ALDO.
1010 Reserved.
1011 Set the dedicated bits for digital interface communication self test function. When
conversion codes are read, Code 0xAAAA is read out as the conversion code of
Channel A, and Code 0x5555 is output as the conversion code of Channel B.
1100 Reserved.
[3:0] CHA Channel selection bits for ADC A Channels. Settings are the same as for ADC B. 0x0 R/W

Rev. 0 | Page 43 of 50
AD7616 Data Sheet
INPUT RANGE REGISTERS
Input Range Register A1 and Input Range Register A2 select from one of the three possible input ranges (±10 V, ±5 V, or ±2.5 V) for
analog input Channel V0A to Channel V7A. Input Range Register B1 and Input Range Register B2 select from one of the three possible
input ranges (±10 V, ±5 V, or ±2.5 V) for analog input Channel V0B to Channel V7B.
INPUT RANGE REGISTER A1
Address: 0x04, Reset: 0x00FF, Name: Input Range Register A1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

[15:9] Addressing (R/W) [1:0] V0A (R/W)

VA0 Voltage Range Selection
[8] RESERVED 0: V0A+/-10V.
[7:6] V3A (R/W) 1: V0A+/-2.5V.
VA3 Voltage Range Selection 10: V0A+/-5V.
0: V3A+/-10V. 11: V0A+/-10V.
1: V3A+/-2.5V. [3:2] V1A (R/W)
10: V3A+/-5V. VA1 Voltage Range Selection
11: V3A+/-10V. 0: V1A+/-10V.
1: V1A+/-2.5V.
10: V1A+/-5V.
11: V1A+/-10V.
[5:4] V2A (R/W)
VA2 Voltage Range Selection
10: V2A+/-5V.
1: V2A+/-2.5V.
11: V2A+/-10V.
0: V2A+/-10V.

Table 23. Bit Descriptions for Input Range Register A1

Bits Bit Name Settings Description Reset Access
[15:9] Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers 0x0 R/W
section for further details.
8 RESERVED Reserved. 0x0 R/W
[7:6] V3A V3A voltage range selection. 0x3 R/W
00 V3A ± 10 V.
01 V3A ± 2.5 V.
10 V3A ± 5 V.
11 V3A ± 10 V.
[5:4] V2A V2A voltage range selection. 0x3 R/W
00 V2A ± 10 V.
01 V2A ± 2.5 V.
10 V2A ± 5 V.
11 V2A ± 10 V.
[3:2] V1A V1A voltage range selection. 0x3 R/W
00 V1A ± 10 V.
01 V1A ± 2.5 V.
10 V1A ± 5 V.
11 V1A ± 10 V.
[1:0] V0A V0A voltage range selection. 0x3 R/W
00 V0A ± 10 V.
01 V0A ± 2.5 V.
10 V0A ± 5 V.
11 V0A ± 10 V.

Rev. 0 | Page 44 of 50
Data Sheet AD7616
INPUT RANGE REGISTER A2
Address: 0x05, Reset: 0x00FF, Name: Input Range Register A2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

[15:9] Addressing (R/W) [1:0] V4A (R/W)

Reserved VA4 Voltage Range Selection
0: V4A+/-10V.
[8] RESERVED 1: V4A+/-2.5V.
[7:6] V7A (R/W) 10: V4A+/-5V.
VA7 Voltage Range Selection 11: V4A+/-10V.
0: V7A+/-10V. [3:2] V5A (R/W)
1: V7A+/-2.5V. VA5 Voltage Range Selection
10: V7A+/-5V. 0: V5A+/-10V.
11: V7A+/-10V. 1: V5A+/-2.5V.
10: V5A+/-5V.
11: V5A+/-10V.
[5:4] V6A (R/W)
VA6 Voltage Range Selection
0: V6A+/-10V.
1: V6A+/-2.5V.
10: V6A+/-5V.
11: V6A+/-10V.

Table 24. Bit Descriptions for Input Range Register A2

Bits Bit Name Settings Description Reset Access
[15:9] Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers 0x0 R/W
section for further details.
8 RESERVED Reserved. 0x0 R/W
[7:6] V7A V7A voltage range selection. 0x3 R/W
00 V7A ± 10 V.
01 V7A ± 2.5 V.
10 V7A ± 5 V.
11 V7A ± 10 V.
[5:4] V6A V6A voltage range selection. 0x3 R/W
00 V6A ± 10 V.
01 V6A ± 2.5 V.
10 V6A ± 5 V.
11 V6A ± 10 V.
[3:2] V5A V5A voltage range selection. 0x3 R/W
00 V5A ± 10 V.
01 V5A ± 2.5 V.
10 V5A ± 5 V.
11 V5A ± 10 V.
[1:0] V4A V4A voltage range selection. 0x3 R/W
00 V4A ± 10 V.
01 V4A ± 2.5 V.
10 V4A ± 5 V.
11 V4A ± 10 V.

Rev. 0 | Page 45 of 50
AD7616 Data Sheet
INPUT RANGE REGISTER B1
Address: 0x06, Reset: 0x00FF, Name: Input Range Register B1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

[15:9] Addressing (R/W) [1:0] V0B (R/W)

VB0 Voltage Range Selection
[8] RESERVED 0: V0B+/-10V.
[7:6] V3B (R/W) 1: V0B+/-2.5V.
VB3 Voltage Range Selection 10: V0B+/-5V.
10: V3B+/-5V. 11: V0B+/-10V.
1: V3B+/-2.5V. [3:2] V1B (R/W)
11: V3B+/-10V. VB1 Voltage Range Selection
0: V3B+/-10V. 0: V1B+/-10V.
1: V1B+/-2.5V.
10: V1B+/-5V.
11: V1B+/-10V.
[5:4] V2B (R/W)
VB2 Voltage Range Selection
0: V2B+/-10V.
1: V2B+/-2.5V.
10: V2B+/-5V.
11: V2B+/-10V.

Table 25. Bit Descriptions for Input Range Register B1

Bits Bit Name Settings Description Reset Access
[15:9] Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers 0x0 R/W
section for further details.
8 RESERVED Reserved. 0x0 R/W
[7:6] V3B V3B voltage range selection. 0x3 R/W
00 V3B ± 10 V.
01 V3B ± 2.5 V.
10 V3B ± 5 V.
11 V3B ± 10 V.
[5:4] V2B V2B voltage range selection. 0x3 R/W
00 V2B ± 10 V.
01 V2B ± 2.5 V.
10 V2B ± 5 V.
11 V2B ± 10 V.
[3:2] VB1 VB1 voltage range selection. 0x3 R/W
00 VB1 ± 10 V.
01 VB1 ± 2.5 V.
10 VB1 ± 5 V.
11 VB1 ± 10 V.
[1:0] V0B V0B voltage range selection. 0x3 R/W
00 V0B ± 10 V.
01 V0B ± 2.5 V.
10 V0B ± 5 V.
11 V0B ± 10 V.

Rev. 0 | Page 46 of 50
Data Sheet AD7616
INPUT RANGE REGISTER B2
Address: 0x07, Reset: 0x00FF, Name: Input Range Register B2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

[15:9] Addressing (R/W) [1:0] V4B (R/W)

VB4 Voltage Range Selection
[8] RESERVED 0: V4B+/-10V.
[7:6] V7B (R/W) 1: V4B+/-2.5V.
VB7 Voltage Range Selection 10: V4B+/-5V.
0: V7B+/-10V. 11: V4B+/-10V.
1: V7B+/-2.5V. [3:2] V5B (R/W)
10: V7B+/-5V. VB5 Voltage Range Selection
11: V7B+/-10V. 0: V5B+/-10V.
1: V5B+/-2.5V.
10: V5B+/-5V.
11: V5B+/-10V.
[5:4] V6B (R/W)
VB6 Voltage Range Selection
0: V6B+/-10V.
1: V6B+/-2.5V.
10: V6B+/-5V.
11: V6B+/-10V.

Table 26. Bit Descriptions for Input Range Register B2

Bits Bit Name Settings Description Reset Access
[15:9] Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers 0x0 R/W
section for further details.
8 RESERVED Reserved. 0x0 R/W
[7:6] V7B V7B voltage range selection. 0x3 R/W
00 V7B ± 10 V.
01 V7B ± 2.5 V.
10 V7B ± 5 V.
11 V7B ± 10 V.
[5:4] V6B V6B voltage range selection. 0x3 R/W
00 V6B ± 10 V.
01 V6B ± 2.5 V.
10 V6B ± 5 V.
11 V6B ± 10 V.
[3:2] V5B V5B voltage range selection. 0x3 R/W
00 V5B ± 10 V.
01 V5B ± 2.5 V.
10 V5B ± 5 V.
11 V5B ± 10 V.
[1:0] V4B V4B voltage range selection. 0x3 R/W
00 V4B ± 10 V.
01 V4B ± 2.5 V.
10 V4B ± 5 V.
11 V4B ± 10 V.

Rev. 0 | Page 47 of 50
AD7616 Data Sheet
SEQUENCER STACK REGISTERS
Although the channel register defines the next channel for conversion (be it a diagnostic channel or pair of analog input channels), to
sample numerous analog input channels, the 32 sequencer stack registers offer a convenient solution. Within the communication register,
when the REGADDR5 bit is set to Logic 1, the contents of REGADDR[4:0] specifies 1 of the 32 sequencer stack registers. Within each
sequencer stack register, the user can define a pair of analog inputs to sample simultaneously.
The structure of the sequence forms a stack, in which each row represents two channels to convert simultaneously. The sequence begins
with Sequencer Stack Register 1 and cycles through to Sequencer Stack Register 32. If Bit D8 (the enable bit, SSRENx) within a sequencer
stack register is set to 1, the sequence ends with the pair of analog inputs defined by that register, then returns to the first sequencer stack
register, and resumes the cycle again. By default, the sequencer stack registers are programmed to cycle through Channel V0A and
Channel V0B to Channel V7A and Channel V7B. After a full or partial reset is issued, the sequencer stack register reinitializes to cycle
through Channel V0A and Channel V0B to Channel V7A and Channel V7B.
Address: 0x20 to 0x3F, Reset: 0x0000, Name: Sequencer Stack Registers[0:31]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[15:9] Addressing (R/W) [3:0] ASELx (R/W)

Channel Selection bits for Set-A Channels
[8] SSRENx (R/W)
Defines final layer of stack [7:4] BSELx (R/W)
Channel Selection bits for Set-B Channels

Table 27. Bit Descriptions for Sequencer Stack Registers[0:31]

Bits Bit Name Settings Description Reset Access
[15:9] Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers 0x0 R/W
section for further details.
8 SSREN[0:31] Setting this bit to 0 instructs the ADC to move to the next layer of the sequencer 0x0 R/W
stack after converting the present channel pair. Setting this bit to 1 defines that
layer of the sequencer stack as the final layer in the sequence. Thereafter, the
sequencer loops back to the first layer of the stack.
[7:4] BSEL[0:31] Channel selection bits for ADC B channels. 0x01 R/W
0000 V0B.
0001 V1B.
0010 V2B.
0011 V3B.
0100 V4B.
0101 V5B.
0110 V6B.
0111 V7B.
1000 VCC.
1001 ALDO.
1010 Reserved.
1011 Set the dedicated bits for digital interface communication self test function. When
the conversion codes is read, Code 0xAAAA is read out as the conversion code of
Channel A, and Code 0x5555 is output as the conversion code of Channel B.
1100 Reserved.
[3:0] ASEL[0:31] Channel selection bits for ADC A channels. Settings are the same as for ADC B. 0x01 R/W
1
After a full or partial reset is issued, the sequencer stack register is reinitialized to cycle through Channel V0A and Channel V0B to Channel V7A and Channel V7B. The
remaining 24 layers of the stack are reinitialized to 0x0.

Rev. 0 | Page 48 of 50
Data Sheet AD7616
STATUS REGISTER
The status register is a 16-bit read only register. If the STATUSEN bit or the CRCEN bit is set to Logic 1 in the configuration register, the
status register is read out at the end of all conversion words for the selected channels, including the self test channel if enabled in
sequencer mode. Consult the CRC section and Figure 68.
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A[3:0] B[3:0] CRC[7:0]

Table 28. Bit Descriptions for Status Register

Bit Bit Name Settings Description Reset1 Access
[D15:D12] A[3:0] Channel index for previous conversion result on Channel A. N/A R
[D11:D8] B[3:0] Channel index for previous conversion result on Channel B. N/A R
[D7:D0] CRC[7:0] CRC calculation for the previous conversion result(s). Refer to the CRC section N/A R
for further details.
1
N/A means not applicable.

Rev. 0 | Page 49 of 50
AD7616 Data Sheet

OUTLINE DIMENSIONS
16.20
0.75 16.00 SQ
1.60 15.80
0.60 MAX
0.45 80 61
1 60

PIN 1

14.20
TOP VIEW
(PINS DOWN) 14.00 SQ
13.80
1.45
0.20
1.40
0.09
1.35
7°
3.5°
0.15 0° 20 41
SEATING 21 40
0.05 0.10
PLANE COPLANARITY
VIEW A 0.65 0.38
BSC 0.32
VIEW A LEAD PITCH
ROTATED 90° CCW 0.22

051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BEC

Figure 69. 80-Lead Low Profile Quad Flat Package [LQFP]

(ST-80-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7616BSTZ −40°C to +125°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-2
AD7616BSTZ-RL −40°C to +125°C 80-Lead Low Profile Quad Flat Package [LQFP], 13” Reel ST-80-2
EVAL-AD7616SDZ Evaluation Board
1
Z = RoHS Compliant Part.

©2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D13591-0-10/16(0)

Rev. 0 | Page 50 of 50