STM32MP133A STM32MP133D

Arm® Cortex®-A7 up to 1 GHz, 2×ETH, 2×CAN FD, 2×ADC,

24 timers, audio
Datasheet - production data

Features TFBGA
LFBGA

Includes ST state-of-the-art patented

technology LFBGA289 (14 × 14mm) TFBGA289 (9 × 9 mm)
Pitch 0.8 mm TFBGA320 (11 × 11 mm)
min pitch 0.5 mm
Core
• DDR retention in Standby mode
• 32-bit Arm® Cortex®-A7
• Controls for PMIC companion chip
– L1 32-Kbyte I / 32-Kbyte D
– 128-Kbyte unified level 2 cache Clock management
– Arm® NEON™ and Arm® TrustZone®
• Internal oscillators: 64 MHz HSI oscillator,
Memories 4 MHz CSI oscillator, 32 kHz LSI oscillator
• External oscillators: 8-48 MHz HSE oscillator,
• External DDR memory up to 1 Gbyte
32.768 kHz LSE oscillator
– up to LPDDR2/LPDDR3-1066 16-bit
• 4 × PLLs with fractional mode
– up to DDR3/DDR3L-1066 16-bit
• 168 Kbytes of internal SRAM: 128 Kbytes of General-purpose input/outputs
AXI SYSRAM + 32 Kbytes of AHB SRAM and
8 Kbytes of SRAM in Backup domain • Up to 135 secure I/O ports with interrupt
capability
• Dual Quad-SPI memory interface
• Up to 6 wakeup
• Flexible external memory controller with up to
16-bit data bus: parallel interface to connect Interconnect matrix
external ICs and SLC NAND memories with up
to 8-bit ECC • 2 bus matrices
– 64-bit Arm® AMBA® AXI interconnect,
Security/safety up to 266 MHz
• TrustZone® peripherals, 12 x tamper pins – 32-bit Arm® AMBA® AHB interconnect,
including 5 x active tampers up to 209 MHz

• Temperature, voltage, frequency and 4 DMA controllers to unload the CPU

32 kHz monitoring
• 56 physical channels in total
Reset and power management • 1 x high-speed general-purpose master direct
• 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) memory access controller (MDMA)

• POR, PDR, PVD and BOR • 3 × dual-port DMAs with FIFO and request
router capabilities for optimal peripheral
• On-chip LDOs (USB 1.8 V, 1.1 V) management
• Backup regulator (~0.9 V)
• Internal temperature sensors
• Low-power modes: Sleep, Stop, LPLV-Stop,
LPLV-Stop2 and Standby

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This is information on a product in full production. www.st.com
 STM32MP133A/D

Up to 29 communication peripherals • HASH (SHA-1, SHA-224, SHA-256, SHA-384,

SHA-512, SHA-3), HMAC
• 5 × I2C FM+ (1 Mbit/s, SMBus/PMBus™)
• 1 x true random number generator (6 triple
• 4 x UART + 4 x USART (12.5 Mbit/s,
oscillators)
ISO7816 interface, LIN, IrDA, SPI)
• 1 x CRC calculation unit
• 5 × SPI (50 Mbit/s, including 4 with full-duplex
I2S audio class accuracy via internal audio PLL
Debug mode
or external clock)(+2 QUADSPI + 4 with
USART) • Arm® CoreSight™ trace and debug: SWD and
• 2 × SAI (stereo audio: I2S, PDM, SPDIF Tx) JTAG interfaces usable as GPIOs
• 4-Kbyte embedded trace buffer
• SPDIF Rx with 4 inputs
• 2 × SDMMC up to 8 bits (SD/e•MMC™/SDIO) 3072-bit fuses including 96-bit unique ID,
• 2 × CAN controllers supporting CAN FD up to 1280 bits available for user
protocol
• 2 × USB 2.0 high-speed Host All packages are ECOPACK2 compliant
– or 1 × USB 2.0 high-speed Host
+ 1 × USB 2.0 high-speed OTG
simultaneously
• 2 x Ethernet MAC/GMAC
– IEEE 1588v2 hardware, MII/RMII/RGMII

6 analog peripherals
• 2 × ADCs with 12-bit max. resolution up to
5 Msps
• 1 x temperature sensor
• 1 x digital filter for sigma-delta modulator
(DFSDM) with 4 channels and 2 filters
• Internal or external ADC reference VREF+

Up to 24 timers and 2 watchdogs

• 2 × 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input
• 2 × 16-bit advanced timers
• 10 × 16-bit general-purpose timers (including
2 basic timers without PWM)
• 5 × 16-bit low-power timers
• Secure RTC with sub-second accuracy and
hardware calendar
• 4 Cortex®-A7 system timers (secure,
non-secure, virtual, hypervisor)
• 2 × independent watchdogs

Hardware acceleration
• ECDSA verification with SCA

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STM32MP133A/D Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Arm Cortex-A7 subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.1 External SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL) . . . . . . . . . . . . 21
3.4 TrustZone address space controller for DDR (TZC) . . . . . . . . . . . . . . . . 22
3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.8.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.9 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10 TrustZone protection controller (ETZPC) . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.12 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 30
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 30
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.16 Dual Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . 31
3.17 Analog-to-digital converters (ADC1, ADC2) . . . . . . . . . . . . . . . . . . . . . . . 31
3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.19 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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Contents STM32MP133A/D

3.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.21 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.22 Digital filter for sigma-delta modulator (DFSDM) . . . . . . . . . . . . . . . . . . . 33
3.23 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24 Hash processor (HASH1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.25 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.26 Boot and security and OTP control (BSEC) . . . . . . . . . . . . . . . . . . . . . . . 35
3.27 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.27.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.27.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13,
TIM14, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.27.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.27.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 38
3.27.5 Independent watchdogs (IWDG1, IWDG2) . . . . . . . . . . . . . . . . . . . . . . 38
3.27.6 Generic timers (Cortex-A7 CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28 System timer generation (STGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.30 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.31 Inter-integrated circuit interfaces (I2C1, I2C2, I2C3, I2C4, I2C5) . . . . . . . 40
3.32 Universal synchronous asynchronous receiver transmitter
(USART1, USART2, USART3, USART6 and UART4, UART5,
UART7, UART8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.33 Serial peripheral interfaces (SPI1, SPI2, SPI3, SPI4, SPI5)
– inter- integrated sound interfaces (I2S1, I2S2, I2S3, I2S4) . . . . . . . . . . 42
3.34 Serial audio interfaces (SAI1, SAI2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.35 SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.36 Secure digital input/output MultiMediaCard interfaces
(SDMMC1, SDMMC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.37 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 44
3.38 Universal serial bus high-speed host (USBH) . . . . . . . . . . . . . . . . . . . . . 45
3.39 USB on-the-go high-speed (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.40 Gigabit Ethernet MAC interfaces (ETH1, ETH2) . . . . . . . . . . . . . . . . . . . 46
3.41 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4 Pinout, pin description and alternate functions . . . . . . . . . . . . . . . . . . 48

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5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 103
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 105
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.5 Embedded regulators characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.9 External clock source security characteristics . . . . . . . . . . . . . . . . . . . 125
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 132
6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 137
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.3.19 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.3.20 QUADSPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.3.21 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.22 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.23 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 177
6.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

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6.3.25 DTS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

6.3.26 VBAT ADC monitoring characteristics and charging characteristics . . 180
6.3.27 VDDCORE, VDDCPU, VDDQ_DDR monitoring characteristics . . . . . 180
6.3.28 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.3.29 Compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.30 Digital filter for sigma-delta modulators (DFSDM) characteristics . . . . 181
6.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.3.32 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.3.33 USART (SPI mode) interface characteristics . . . . . . . . . . . . . . . . . . . . 199
6.3.34 USB High-Speed PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.35 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 201

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.1 LFBGA289 package information (B0ED) . . . . . . . . . . . . . . . . . . . . . . . . 204
7.2 TFBGA289 package information (B0EB) . . . . . . . . . . . . . . . . . . . . . . . . 206
7.3 TFBGA320 package information (B0EC) . . . . . . . . . . . . . . . . . . . . . . . . 209
7.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
7.4.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
7.5 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

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STM32MP133A/D List of tables

List of tables

Table 1. STM32MP133A/D features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3. System versus CPU power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5. USART/UART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 7. STM32MP133A/D ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 8. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 9. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 10. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 11. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 12. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 13. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 14. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 15. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 16. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 17. Embedded reference voltage calibration value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 18. REG1V1 embedded regulator (USB_PHY) characteristics . . . . . . . . . . . . . . . . . . . . . . . 109
Table 19. REG1V8 embedded regulator (USB_PHY) characteristics . . . . . . . . . . . . . . . . . . . . . . . 109
Table 20. Current consumption (IDDCORE) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 21. Current consumption (IDDCPU) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 22. Current consumption (IDD) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 23. Current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 24. Current consumption in LPLV-Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 25. Current consumption in LPLV-Stop2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 26. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 27. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 28. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 29. Wakeup time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 30. High-speed external user clock characteristics
(digital bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 31. High-speed external user clock characteristics
(analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 32. Low-speed external user clock characteristics
(analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 33. Low-speed external user clock characteristics (digital bypass) . . . . . . . . . . . . . . . . . . . . 122
Table 34. 8-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 35. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 36. High-speed external user clock security system (HSE CSS) . . . . . . . . . . . . . . . . . . . . . . 125
Table 37. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 38. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 39. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 40. PLL1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 41. PLL2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 42. PLL3, PLL4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 43. USB_PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 44. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 45. OTP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

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List of tables STM32MP133A/D

Table 46. DC specifications – DDR3 or DDR3L mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 47. DC specifications – LPDDR2 or LPDDR3 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 48. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 49. EMI characteristics for fHSE = 24 MHz and Fmpuss_ck = 650 MHz . . . . . . . . . . . . . . . . 137
Table 50. EMI characteristics for fHSE = 24 MHz and Fmpuss_ck = 1 GHz . . . . . . . . . . . . . . . . . . 137
Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 53. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 54. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 55. Output voltage characteristics for all I/Os except PC13, PC14, PC15, PI0 PI1, PI2, PI3 . 141
Table 56. Output voltage characteristics for PC13, PC14, PC15, PI0, PI1, PI2, PI3 . . . . . . . . . . . . 142
Table 57. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 58. Output timing characteristics (HSLV ON, _h IO structure) . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 59. Output timing characteristics (HSLV OFF, _vh IO structure) . . . . . . . . . . . . . . . . . . . . . . 146
Table 60. Output timing characteristics (HSLV ON, _vh IO structure) . . . . . . . . . . . . . . . . . . . . . . . 148
Table 61. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 151
Table 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 151
Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 152
Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 153
Table 66. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 67. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 154
Table 68. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 69. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 156
Table 70. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 71. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 72. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 73. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 74. Switching characteristics for NAND flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 75. Switching characteristics for NAND flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 76. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 77. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 78. Dynamics characteristics: Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 79. 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 80. Minimum sampling time vs RAIN (12-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 81. 12-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 82. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 83. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 84. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 85. DTS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 86. VBAT ADC monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 87. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 88. VDDCORE, VDDCPU, VDDQ_DDR monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 89. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 90. Compensation cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 91. DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 92. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 93. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 94. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 95. I2C FM+ pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 96. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 97. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

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STM32MP133A/D List of tables

Table 98. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 99. Dynamics characteristics: SD characteristics, VDD = 1.71 V to 3.6 V . . . . . . . . . . . . . . . 193
Table 100. Dynamics characteristics: e•MMC characteristics VDD = 1.71 V to 3.6 V . . . . . . . . . . . . 194
Table 101. Dynamics characteristics: Ethernet MAC timings for MDIO/SMA. . . . . . . . . . . . . . . . . . . 196
Table 102. Dynamics characteristics: Ethernet MAC timings for RMII . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 103. Dynamics characteristics: Ethernet MAC timings for MII . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 104. Dynamics characteristics: Ethernet MAC signals for RGMII . . . . . . . . . . . . . . . . . . . . . . 198
Table 105. USART (SPI mode) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 106. USB High-Speed PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 107. Dynamics characteristics: JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 108. Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 109. LFBGA289 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 110. LFBGA289 - Recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 111. TFBGA289 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 112. TFBGA289 - Recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 113. TFBGA320 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 114. TFBGA320 - Recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 115. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 116. STM32MP133A/D ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 117. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

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List of figures STM32MP133A/D

List of figures

Figure 1. STM32MP133A/D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 3. STM32MP133A/D bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5. STM32MP133A/D LFBGA289 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 6. STM32MP133A/D TFBGA289 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 7. STM32MP133A/D TFBGA320 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 12. VDDCORE / VDDCPU rise time from reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 13. VDDCORE / VDDCPU rise time from LPLV-Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 14. High-speed external clock source AC timing diagram (digital bypass) . . . . . . . . . . . . . . . 120
Figure 15. High-speed external clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . 121
Figure 16. Low-speed external clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . 122
Figure 17. AC timing diagram for low-speed external square clock source . . . . . . . . . . . . . . . . . . . . 122
Figure 18. Typical application with a 24 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 19. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 20. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 21. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 22. VIL/VIH for FT I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 150
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 152
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 29. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 32. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 33. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 34. QUADSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 35. QUADSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 36. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 37. Typical connection diagram using the ADC with FT/TT pins
featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 38. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 39. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 40. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 41. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 42. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 43. I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 44. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 45. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 46. SD high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 47. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

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Figure 48. SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 49. Ethernet MDIO/SMA timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 50. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 51. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 52. Ethernet RGMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 53. USART timing diagram in SPI master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 54. USART timing diagram in SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 55. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 56. SWD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 57. LFBGA289 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 58. LFBGA289 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 59. TFBGA289 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 60. TFBGA289 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 61. TFBGA320 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 62. TFBGA320 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

DS13876 Rev 6 11/218

11
Introduction STM32MP133A/D

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of
the STM32MP133A/D microprocessors.
This document should be read in conjunction with the STM32MP133 reference manual
(RM0475), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-A7, refer to the Cortex®-A7 Technical Reference
Manuals.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32MP131x/3x/5x device errata (ES0539), available on the
STMicroelectronics website www.st.com.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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2 Description

The STM32MP133A/D devices are based on the high-performance Arm® Cortex®-A7 32-bit
RISC core operating at up to 1 GHz. The Cortex®-A7 processor includes a 32-Kbyte L1
instruction cache, a 32-Kbyte L1 data cache and a 128-Kbyte level2 cache. The Cortex®-A7
processor is a very energy-efficient application processor designed to provide rich
performance in high-end wearables, and other low-power embedded and consumer
applications. It provides up to 20 % more single thread performance than the Cortex®-A5
and provides similar performance to the Cortex®-A9.
The Cortex®-A7 incorporates all features of the high-performance Cortex®-A15 and
Cortex®-A17 processors, including virtualization support in hardware, NEON™, and 128-bit
AMBA®4 AXI bus interface.
The STM32MP133A/D devices provide an external SDRAM interface supporting external
memories up to 8-Gbit density (1 Gbyte), 16-bit LPDDR2/LPDDR3 or DDR3/DDR3L
up to 533 MHz.
The STM32MP133A/D devices incorporate high-speed embedded memories with
168 Kbytes of internal SRAM (including 128 Kbytes of AXI SYSRAM, two banks of 8 Kbytes
and one bank of 16 Kbytes securable AHB SRAM, and 8 Kbytes of SRAM in Backup
domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB
buses, AHB buses, and a 64-bit multi-layer AXI interconnect supporting internal and
external memories access.

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Description STM32MP133A/D

All the devices offer two ADCs, a low-power secured RTC, ten general-purpose 16-bit
timers, two 32-bit timers, two PWM timers for motor control, five low-power timers, a
secured true random number generator (RNG). The devices support two digital filters for
external sigma-delta modulators (DFSDM). They also feature standard and advanced
communication interfaces.
• Standard peripherals:
– Five I2Cs
– Four USARTs and four UARTs
– Five SPIs, four I2Ss full-duplex master/slave. To achieve audio class accuracy, the
I2S peripherals can be clocked via a dedicated internal audio PLL or via an
external clock to allow synchronization.
– Two SAI serial audio interfaces (up to four audio channels each)
– One SPDIF Rx interface
– Two SDMMC interfaces
– A USB OTG high-speed controller
– A USB high-speed Host controller with two ports and two high-speed phys. The
second high-speed phy can be shared between the USB high-speed Host and the
USB OTG high-speed.
– Two FDCAN interfaces
– Two Gigabit Ethernet interfaces
• Advanced peripherals including:
– A flexible memory control (FMC) interface
– A Quad-SPI flash memory interface
Refer to Table 1: STM32MP133A/D features and peripheral counts for the specificity for
each package type.
A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32MP133A/D devices are proposed in three packages ranging from 289 to
320 balls, with pitch 0.5 mm to 0.8 mm.
These features make the STM32MP133A/D suitable for a wide range of consumer,
industrial, white goods and medical applications.
Figure 1 shows the general block diagram of the device family.

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Table 1. STM32MP133A/D features and peripheral counts

STM32MP133AAG
STM32MP133DAG
STM32MP133AAE
STM32MP133DAE

STM32MP133AAF
STM32MP133DAF

Miscellaneous
Features

LFBGA289 TFBGA289 TFBGA320

Body size (mm) 14x14 9x9 11x11

Pitch (mm) 0.8 0.5 0.5
Package Ball size (mm) 0.40 0.30 0.30 -
Thickness (mm) < 1.4 < 1.2 < 1.2
Ball count 289 289 320
CPU Cortex-A7 FPU Neon TrustZone
32-Kbyte L1 data cache
Caches size 32-Kbyte L1 instruction cache
-
128-Kbyte L2 unified coherent cache
STM32MP133A: 650 MHz
Frequency
STM32MP133D: 1 GHz
ROM 128 Kbytes (secure) -
System RAM 128 Kbytes (securable)

168 Kbytes
Embedded
Backup 8 Kbytes (securable, tamper protected)
SRAM
AHB SRAM 32 Kbytes
SDRAM Securable
LPDDR2/3 16-bit 533 MHz -
Up to 1 Gbyte, single rank
DDR3/3L 16-bit 533 MHz
Backup registers 128 bytes (32x32-bit, securable, tamper protected) -
Advanced 16 bits 2

General 16 bits 8 (6 securable)

purpose 32 bits 2
24 timers
Timers

Basic 16 bits 2
Low power 16 bits 5 (2 securable)
A7 timers 64 bits 4 (secure, non-secure, virtual, hypervisor)
RTC/AWU 1 (securable)

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Description STM32MP133A/D

Table 1. STM32MP133A/D features and peripheral counts (continued)

STM32MP133AAG
STM32MP133DAG
STM32MP133AAE
STM32MP133DAE

STM32MP133AAF
STM32MP133DAF

Miscellaneous
Features

LFBGA289 TFBGA289 TFBGA320

Watchdogs 2 (independent, independent secure) -

SPI 5 (2 securable)
Having I2S 4 -
I2C (with SMB/PMB support) 5 (3 securable)
Communication peripherals

USART (smartcard, SPI,

4 + 4 (including 2 securable USART), some can be a boot source Boot
IrDA, LIN) + UART (IrDA, LIN)
2 (up to 4 audio channels), with I2S master/slave,
SAI -
PCM input, SPDIF-TX
2 ports
EHCI/OHCI Host -
Embedded HSPHY with BCD
USB
OTG HS Embedded HS PHY with BCD (securable), can be a boot source Boot
Embedded PHYs 2 × HS shared between Host and OTG -
SPDIFRX 4 inputs -
FDCAN 2 (1 × TTCAN), clock calibration, 10 Kbyte shared buffer -
2 (8 + 8 bits) (securable), e•MMC or SD can be a boot source
SDMMC (SD, SDIO, e•MMC) Boot
2 optional independant power supplies for SD card interfaces
Boot
QUADSPI 1 (dual-quad) (securable), can be a boot source (1)

Parallel address/data 8/16-bit

4 × CS, up to 4 × 64 Mbyte -
FMC Parallel AD-mux 8/16-bit
NAND 8/16-bit Yes, 2× CS, SLC, BCH4/8, can be a boot source Boot
10/100M/Gigabit Ethernet 2 x (MII, RMI, RGMII) with PTP and EEE (securable) -
DMA 3 instances (1 secure), 33-channel MDMA -
SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3, HMAC
Hash -
(securable)
True random number generator True-RNG (securable) -
Fuses (one-time programmable) 3072 effective bits (secure, 1280 bits available for the user) -

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Table 1. STM32MP133A/D features and peripheral counts (continued)

STM32MP133AAG
STM32MP133DAG
STM32MP133AAE
STM32MP133DAE

STM32MP133AAF
STM32MP133DAF

Miscellaneous
Features

LFBGA289 TFBGA289 TFBGA320

GPIOs with interrupt (total count) 135(2)

Securable GPIOs All
-
Wakeup pins 6
Tamper pins (active tamper) 12 (5)
DFSDM 4 input channels with 2 filters -
Up to 12-bit synchronized ADC 2(3) (up to 5 Msps on 12-bit each) (securable)
ADC1: 19 channels including 1x internal, 18 channels available for
user including 8x differential -
(4)
12-bit ADC channels in total
ADC2: 18 channels including 6x internal, 12 channels available for
user including 6x differential
Internal ADC VREF 1.65 V, 1.8 V, 2.048 V, 2.5 V or VREF+ input
-
VREF+ input pin Yes
1. QUADSPI may boot either from dedicated GPIOs or using some FMC Nand8 boot GPIOs (PD4, PD1, PD5, PE9, PD11,
PD15 (see Table 7: STM32MP133A/D ball definitions).
2. This total GPIO count includes four JTAG GPIOs and three BOOT GPIOs with limited usage (may conflict with external
device connection during boundary scan or boot).
3. When both ADCs are used, the kernel clock should be the same for both ADCs and the embedded ADC prescalers cannot
be used.
4. In addition, there are also internal channels:
- ADC1 internal channel: VREFINT
- ADC2 internal channels: temperature, internal voltage reference, VDDCORE, VDDCPU, VDDQ_DDR, VBAT / 4.

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Description STM32MP133A/D

Figure 1. STM32MP133A/D block diagram

@VDDA
IC supplies
HSI HSE (XTAL) 2

CSI LSI PLL1/2/3/4

@VDDCPU

+ SCU T
GIC T
T RCC 5
Cortex-A7 CPU

L2$L2$

T
650/1000 MHz + T PWR 9

128KB
MMU + FPU + NEONT
Debug timestamp

async
128 bits generator TSGEN

256KB
32K D$
T EXTI 16ext 176

T DAP T
32K I$ (JTAG/SWD) USBO

FIFO

PHY
(OTG HS)
2
CNT (timer) T SYSRAM 128KB

T
T
ETM T 12b ADC1 18
ROM 128KB T

T
12b ADC2 18

AXIM: Arm 64-bit AXI interconnect (266 MHz)

T

@VBAT
BKPSRAM 8KB T GPIOA 16b 16
T
RNG T GPIOB 16b 16
T
HASH T GPIOC 16b 16
T
38
2 x ETH MAC
(R)(G)MII
FIFO
10/100/1000(no GMII) T
T GPIOD 16b 16

T
16b PHY

DDRCTRL GPIOE 16b 16

async

T
TZC
58
LPDDR2/3, DDR3/3L
CRC T GPIOF 16b 16
DDRPHYC T DLYBSD1
T (SDMMC1 DLY control) T GPIOG 16b 16
DLY

13 8b QUADSPI (dual) T T DLYBSD2

(SDMMC2 DLY control) T GPIOH 16b 15
37 16b FMC T T DLYBQS
(QUADSPI DLY control) T GPIOI 16b 8
FIFO
DLY

14 8b SDMMC1 T T
PKA
FIFO

MLAHB: Arm 32-bit multi-AHB bus matrix (209 MHz)

DLY

14 8b SDMMC2 T
T MDMA
FIFO

32 channels
TT

2 USBH AHB2APB
FIFO
PHY

2 (2xHS Host)
AXIMC

FIFO
PLLUSB USART1 Smartcard
IrDA 5
T

FIFO
Smartcard
USART2 IrDA 5
T

FIFO
async SPI4/I2S4 5
T

FIFO
SPI5
FIFO

4
8KB

17 16b Trace port

AHB2APB T

Filter
T I2C3/SMBUS 3
ETZPC T

Filter
T I2C4/SMBUS 3
@VBAT

IWDG1
APB5 (100MHz)

APB6 T

Filter
SRAM1 16KB T
I2C5/SMBUS 3
BSEC T
T
TIM12 2
@VDDA

16b
OTP Fuses SRAM2 8KB T
T
TIM13 16b 1
2 RTC / AWU T SRAM3 8KB T T
TIM14 16b 1
12 TAMP / Backup regs T T
TIM15 16b 4
LSE (32kHz XTAL)
@VBAT

2 T
TIM16 16b 3
T
System timing STGENC T
generation STGENR TIM17 16b 3

USBPHYC TIM2 32b 5

APB4

(USB 2 x PHY control)

TIM3 5
@VBAT

16b
IWDG2
AHB2APB TIM4 16b 5

TIM5 32b 5
DMA1
FIFO

8 streams
T TIM6 16b
@VDDA

1 VREFBUF DMAMUX1
T TIM7 16b
4 16b LPTIM2 DMA2
FIFO

8 streams
LPTIM3
T LPTIM1 16b 4
APB3 (100 MHz)

1 16b

DMAMUX2
APB1 (100 MHz)

1 16b LPTIM4
FIFO

Smartcard
DMA3 USART3 5
FIFO

IrDA
1 16b LPTIM5 8 streams
T
FIFO

UART4 4
PMB
FIFO

UART5 4
BOOT (process monitor)
3 pins SYSCFG T 2x2
FIFO

DTS Matrix UART7 4

8 8b HDP (digital temp. sensor)
FIFO

UART8 4

Voltage regulators
@VDDA

TIM1/PWM
Filter

10 16b AHB2APB I2C1/SMBUS 3

TIM8/PWM Supply supervision
Filter

10 16b I2C2/SMBUS 3
FIFO

13 SAI1
FIFO

AHB2APB SPI2/I2S2 5
AXI AXI master
APB2 (100 MHz)

64 bits 64bits
FIFO

FIFO

13 SAI2 32 bits AHB 32 bits AHB master SPI3/I2S3 5

9 4ch DFSDM 32 bits APB
FIFO

Smartcard
USART6 IrDA 5
Buffer 10KB CCU T TrustZone security protection
4 FDCAN1
FIFO

4
SPI1/I2S1 5
FDCAN2 APB2 (100 MHz)

MSv67508V3

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3 Functional overview

3.1 Arm Cortex-A7 subsystem

3.1.1 Features
• ARMv7-A architecture
• 32-Kbyte L1 instruction cache
• 32-Kbyte L1 data cache
• 128-Kbyte level2 cache
• Arm + Thumb®-2 instruction set
• Arm TrustZone security technology
• Arm NEON advanced SIMD
• DSP and SIMD extensions
• VFPv4 floating-point
• Hardware virtualization support
• Embedded trace module (ETM)
• Integrated generic interrupt controller (GIC) with 160 shared peripheral interrupts
• Integrated generic timer (CNT)

3.1.2 Overview
The Cortex-A7 processor is a very energy-efficient applications processor designed to
provide rich performance in high-end wearables, and other low-power embedded and
consumer applications. It provides up to 20 % more single thread performance than the
Cortex-A5 and provides similar performance than the Cortex-A9.
The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and Cortex-
A17 processors, including virtualization support in hardware, NEON, and 128-bit
AMBA 4 AXI bus interface.
The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5
processor. It also benefits from an integrated L2 cache designed for low-power, with lower
transaction latencies and improved OS support for cache maintenance. On top of this, there
is improved branch prediction and improved memory system performance, with 64-bit load-
store path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry, up from 128 entry
for Cortex-A9 and Cortex-A5), increasing performance for large workloads such as web
browsing.

Thumb-2 technology
Delivers the peak performance of traditional Arm code while also providing up to a 30 %
reduction in memory requirement for instructions storage.

TrustZone technology
Ensures reliable implementation of security applications ranging from digital rights
management to electronic payment. Broad support from technology and industry partners.

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Functional overview STM32MP133A/D

NEON
NEON technology can accelerate multimedia and signal processing algorithms such as
video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image
processing, telephony, and sound synthesis. The Cortex-A7 provides an engine that offers
both the performance and functionality of the Cortex-A7 floating-point unit (FPU) and an
implementation of the NEON advanced SIMD instruction set for further acceleration of
media and signal processing functions. The NEON extends the Cortex-A7 processor FPU to
provide a quad-MAC and additional 64-bit and 128-bit register set supporting a rich set of
SIMD operations over 8-, 16- and 32-bit integer and 32-bit floating-point data quantities.

Hardware virtualization
Highly efficient hardware support for data management and arbitration, whereby multiple
software environments and their applications are able to simultaneously access the system
capabilities. This enables the realization of devices that are robust, with virtual environments
that are well isolated from each other.

Optimized L1 caches
Performance and power optimized L1 caches combine minimal access latency techniques
to maximize performance and minimize power consumption.

Integrated L2 cache controller

Provides low-latency and high-bandwidth access to cached memory in high-frequency, or to
reduce the power consumption associated with off-chip memory access.

Cortex-A7 floating-point unit (FPU)

The FPU provides high-performance single and double precision floating-point instructions
compatible with the Arm VFPv4 architecture that is software compatible with previous
generations of Arm floating-point coprocessor.

Snoop control unit (SCU)

The SCU is responsible for managing the interconnect, arbitration, communication, cache to
cache and system memory transfers, cache coherence and other capabilities for the
processor.
This system coherence also reduces software complexity involved in maintaining software
coherence within each OS driver.

Generic interrupt controller (GIC)

Implementing the standardized and architected interrupt controller, the GIC provides a rich
and flexible approach to inter-processor communication and the routing and prioritization of
system interrupts.
Supporting up to 192 independent interrupts, under software control, hardware prioritized,
and routed between the operating system and TrustZone software management layer.
This routing flexibility and the support for virtualization of interrupts into the operating
system, provides one of the key features required to enhance the capabilities of a solution
utilizing a hypervisor.

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3.2 Memories

3.2.1 External SDRAM

The STM32MP133A/D devices embed a controller for external SDRAM that supports the
following:
• LPDDR2 or LPDDR3, 16-bit data, up to 1 Gbyte, up to 533 MHz clock
• DDR3 or DDR3L, 16-bit data, up to 1 Gbyte, up to 533 MHz clock

3.2.2 Embedded SRAM

All devices feature:
• SYSRAM: 128 Kbytes (with programmable size secure zone)
• AHB SRAM: 32 Kbytes (securable)
• BKPSRAM (backup SRAM): 8 Kbytes
The content of this area is protected against possible unwanted write accesses, and
can be retained in Standby or VBAT mode.
BKPSRAM can be defined (in ETZPC) as accessible by secure software only.

3.3 DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL)

DDRCTRL combined with DDRPHYC provides a complete memory interface solution for
DDR memory subsystem.
• One 64-bit AMBA 4 AXI ports interface (XPI)
• AXI clock asynchronous to the controller
• Supported standards:
– JEDEC DDR3 SDRAM specification, JESD79-3E for DDR3/3L with
16-bit interface
– JEDEC LPDDR2 SDRAM specification, JESD209-2E for LPDDR2 with
16-bit interface
– JEDEC LPDDR3 SDRAM specification, JESD209-3B for LPDDR3 with
16-bit interface
• Advanced scheduler and SDRAM command generator
• Programmable full data width (16-bit) or half data width (8-bit)
• Advanced QoS support with three traffic class on read and two traffic classes on write
• Options to avoid starvation of lower priority traffic
• Guaranteed coherency for write-after-read (WAR) and read-after-write (RAW) on
AXI ports
• Programmable support for burst length options (4, 8, 16)
• Write combine to allow multiple writes to the same address to be combined into a
single write
• Single rank configuration
• Support of automatic SDRAM power-down entry and exit caused by lack of transaction
arrival for programmable time

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Functional overview STM32MP133A/D

• Support of automatic clock stop (LPDDR2/3) entry and exit caused by lack of
transaction arrival
• Support of automatic low-power mode operation caused by lack of transaction arrival
for programmable time via hardware low-power interface
• Programmable paging policy
• Support of automatic or under software control self-refresh entry and exit
• Support of deep power-down entry and exit under software control (LPDDR2 and
LPDDR3)
• Support of explicit SDRAM mode register updates under software control
• Flexible address mapper logic to allow application specific mapping of row, column,
bank bits
• User-selectable refresh control options
• DDRPERFM associated block to help for performance monitoring and tuning
DDRCTRL and DDRPHYC can be defined (in ETZPC) as accessible by secure software
only.

3.4 TrustZone address space controller for DDR (TZC)

TZC is used to filter read/write accesses to DDR controller according to TrustZone rights
and according to non-secure master (NSAID) on up to nine programmable regions:
• Configuration supported by trusted software only
• One filter unit
• Nine regions:
– Region 0 is always enabled and covers the whole address range.
– Regions 1 to 8 have programmable base-/end-address and can be assigned to
any one or both filters.
• Secure and non-secure access permissions programmed per region
• Non-secure accesses filtered according to NSAID
• Regions controlled by same filter must not overlap
• Fail modes with error and/or interrupt
• Acceptance capability = 256
• Gate keeper logic to enable and disable of each filter
• Speculative accesses

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3.5 Boot modes

At startup, the boot source used by the internal boot ROM is selected by the BOOT pin and
OTP bytes.

Table 2. Boot modes

BOOT2 BOOT1 BOOT0 Initial boot mode Comments

Wait incoming connection on:

0 0 0 UART and USB(1) – USART3/6 and UART4/5/7/8 on default pins
– USB high-speed device on OTG_HS_DP/DM pins(2)
0 0 1 Serial NOR flash(3) Serial NOR flash on QUADSPI(5)
0 1 0 e•MMC(3) e•MMC on SDMMC2 (default)(5)(6)
0 1 1 NAND flash(3) SLC NAND flash on FMC
Development boot (no
1 0 0 Used to get debug access without boot from flash memory(4)
flash memory boot)
1 0 1 SD card(3) SD card on SDMMC1 (default)(5)(6)
Wait incoming connection on:
1 1 0 UART and USB(1)(3) – USART3/6 and UART4/5/7/8 on default pins
– USB high-speed device on OTG_HS_DP/DM pins(2)
1 1 1 Serial NAND flash(3) Serial NAND flash on QUADSPI(5)
1. Can be disabled by OTP settings.
2. USB requires HSE clock/crystal (see AN5474 for supported frequencies with and without OTP settings).
3. Boot source can be changed by OTP settings (for example initial boot on SD card, then e•MMC with OTP settings).
4. Cortex®-A7 core in infinite loop toggling PA13.
5. Default pins can be altered by OTP.
6. Alternatively, another SDMMC interface than this default can be selected by OTP.

Although low level boot is done using internal clocks, ST supplied software packages as
well as major external interfaces such as DDR, USB (but not limited to) require a crystal or
an external oscillator to be connected on HSE pins.
See RM0475 “STM32MP13xx advanced Arm®-based 32-bit MPUs” or AN5474 "Getting
started with STM32MP13xx lines hardware development" for constraints and
recommendations regarding HSE pins connection and supported frequencies.

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Functional overview STM32MP133A/D

3.6 Power supply management

3.6.1 Power supply scheme

• VDD is the main supply for I/Os and internal part kept powered during Standby mode.
Useful voltage range is 1.71 V to 3.6 V (1.8 V, 2.5 V, 3.0 V or 3.3 V typ.)
– VDD_PLL and VDD_ANA must be star-connected to VDD.
• VDDCPU is the Cortex-A7 CPU dedicated voltage supply, whose value depends on the
desired CPU frequency. 1.22 V to 1.38 V in run mode. VDD must be present before
VDDCPU.
• VDDCORE is the main digital voltage and is usually shutdown during Standby mode.
Voltage range is 1.21 V to 1.29 V in run mode. VDD must be present before VDDCORE.
• The VBAT pin can be connected to the external battery (1.6 V < VBAT < 3.6 V). If no
external battery is used, this pin must be connected to VDD.
• VDDA is the analog (ADC/VREF), supply voltage (1.62 V to 3.6 V). Using the internal
VREF+ requires VDDA equal to or higher than VREF+ + 0.3 V.
• The VDDA1V8_REG pin is the output of the internal regulator, connected internally to
USB PHY and USB PLL. The internal VDDA1V8_REG regulator is enabled by default and
can be controlled by software. It is always shut down during Standby mode.
The specific BYPASS_REG1V8 pin must never be left floating. It must be connected
either to VSS or to VDD to activate or deactivate the voltage regulator. When
VDD = 1.8 V, BYPASS_REG1V8 should be set.
• VDDA1V1_REG pin is the output of the internal regulator, connected internally to
USB PHY. The internal VDDA1V1_REG regulator is enabled by default and can be
controlled by software. It is always shut down during Standby mode.
• VDD3V3_USBHS is the USB high-speed supply. Voltage range is 3.07 V to 3.6 V.
Caution: VDD3V3_USBHS must not be present unless VDDA1V8_REG is present, otherwise permanent
damage may occur on the STM32MP133A/D. This must be ensured by PMIC ranking order
or with external component in case of discrete component power supply implementation.
• VDDSD1 and VDDSD2 are respectively SDMMC1 and SDMMC2 SD card power supplies
to support ultra-high-speed mode.
• VDDQ_DDR is the DDR IO supply.
– 1.425 V to 1.575 V for interfacing DDR3 memories (1.5 V typ.)
– 1.283 V to 1.45 V for interfacing DDR3L memories (1.35 V typ.)
– 1.14 V to 1.3 V for interfacing LPDDR2 or LPDDR3 memories (1.2 V typ.)
During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDCORE, VDDCPU, VDDSD1, VDDSD2,
VDDA, VDDA1V8_REG, VDDA1V1_REG, VDD3V3_USBHS, VDDQ_DDR) must remain below VDD
+ 300 mV.
• When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the STM32MP133A/D remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power- down
transient phase.

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Figure 2. Power-up/down sequence

V

3.6
VDDX(1)

VDD

VPOR
VPDR

0.3

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V2

1. VDDX refers to any power supply among VDDCORE, VDDCPU, VDDSD1, VDDSD2, VDDA, VDDA1V8_REG,
VDDA1V1_REG, VDD3V3_USBHS, VDDQ_DDR.

3.6.2 Power supply supervisor

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
• Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in reset mode when VDD is below this threshold,
• Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
• Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.
• Power-on reset VDDCORE (POR_VDDCORE)
The POR_VDDCORE supervisor monitors VDDCORE power supply and compares it to
a fixed threshold. The VDDCORE domain remains in reset mode when VDDCORE is
below this threshold.
• Power-down reset VDDCORE (PDR_VDDCORE)
The PDR_VDDCORE supervisor monitors VDDCORE power supply. A VDDCORE domain
reset is generated when VDDCORE drops below a fixed threshold.
• Power-on-reset VDDCPU (POR_VDDCPU)
The POR_VDDCPU supervisor monitors VDDCPU power supply and compares it to a
fixed threshold. The VDDCPU domain remains in reset mode when VDDCORE is below
this threshold.
Note: The PDR_ON pin is reserved for STMicroelectronics production tests and must always be
connected to VDD in an application.

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3.7 Low-power strategy

There are several ways to reduce power consumption on STM32MP133A/D:
• Decrease dynamic power consumption by slowing down the CPU clocks and/or the
bus matrix clocks and/or controlling individual peripheral clocks.
• Save power consumption when the CPU is IDLE, by selecting among the available low-
power modes according to the user application needs. This allows the best
compromise between short startup time, low-power consumption, as well as available
wakeup sources, to be achieved.
• Use the DVFS (dynamic voltage and frequency scaling) operating points that directly
controls the CPU clock frequency as well as the VDDCPU output supply.
The operating modes allow the control of the clock distribution to the different system parts
and the power of the system. The system operation mode is driven by the MPU sub-system.
The MPU sub-system low-power modes are listed below:
• CSleep: The CPU clocks are stopped and the peripheral(s) clock operates as
previously set in the RCC (reset and clock controller).
• CStop: The CPU peripheral(s) clocks are stopped.
• CStandby: VDDCPU OFF
CSleep and CStop low-power modes are entered by the CPU when executing the WFI (wait
for interrupt) or WFE (wait for event) instructions.
The system operating modes available are the followings:
• Run (system at its full performance, VDDCORE, VDDCPU and clocks ON)
• Stop (clocks OFF)
• LP-Stop (clocks OFF)
• LPLV-Stop (clocks OFF, VDDCORE and VDDCPU supply level may be lowered)
• LPLV-Stop2 (VDDCPU OFF, VDDCORE lowered, and clocks OFF)
• Standby (VDDCPU, VDDCORE, and clocks OFF)

Table 3. System versus CPU power mode

System power mode CPU

Run mode CRun or CSleep

Stop mode
LP-Stop mode
CStop or CStandby
LPLV-Stop mode
LPLV-Stop2 mode
Standby mode CStandby

3.8 Reset and clock controller (RCC)

The clock and reset controller manages the generation of all the clocks, as well as the clock
gating, and the control of the system and peripheral resets.RCC provides a high flexibility in
the choice of clock sources and allows application of clock ratios to improve the power
consumption. In addition, on some communication peripherals that are capable to work with

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two different clock domains (either a bus interface clock or a kernel peripheral clock), the
system frequency can be changed without modifying the baudrate.

3.8.1 Clock management

The devices embed four internal oscillators, two oscillators with external crystal or
resonator, three internal oscillators with fast startup time and four PLLs.
The RCC receives the following clock source inputs:
• Internal oscillators:
– 64 MHz HSI clock (1 % accuracy)
– 4 MHz CSI clock
– 32 kHz LSI clock
• External oscillators:
– 8-48 MHz HSE clock
– 32.768 kHz LSE clock
The RCC provides four PLLs:
• PLL1 dedicated to the CPU clocking
• PLL2 providing:
– clocks for the AXI-SS (including APB4, APB5, AHB5 and AHB6 bridges)
– clocks for the DDR interface
• PLL3 providing:
– clocks for the multi-Layer AHB and peripheral bus matrix (including the APB1,
APB2, APB3, APB6, AHB1, AHB2, and AHB4)
– kernel clocks for peripherals
• PLL4 dedicated to the generation of the kernel clocks for various peripherals
The system starts on the HSI clock. The user application can then select the clock
configuration.

3.8.2 System reset sources

The power-on reset initializes all registers except for the debug, a part of the RCC, a part of
the RTC and power controller status registers, as well as the Backup power domain.
An application reset is generated from one of the following sources:
• a reset from NRST pad
• a reset from POR and PDR signal (generally called power-on reset)
• a reset from BOR (generally called brownout)
• a reset from the independent watchdog 1
• a reset from the independent watchdog 2
• a software system reset from the Cortex-A7 (CPU)
• a failure on HSE, when the clock security system feature is activated
A system reset is generated from one of the following sources:
• an application reset
• a reset from POR_VDDCORE signal
• an exit from Standby mode to Run mode

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A MPU processor reset is generated from one of the following sources:

• a system reset
• every time the MPU exits CStandby
• a software MPU reset from the Cortex-A7 (CPU)

3.9 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (with or without pull-up or pull-down) or as
peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
All GPIO pins can be individually set as secure, which means that software accesses to
these GPIOs and associated peripherals defined as secure are restricted to secure software
running on the CPU.

3.10 TrustZone protection controller (ETZPC)

ETZPC is used to configure TrustZone security of bus masters and slaves with
programmable-security attributes (securable resources). For instance:
• On-chip SYSRAM secure region size can be programmed.
• AHB and APB peripherals can be made secure or non-secure.
• AHB SRAM can be made secure or non-secure.
Note: By default, SYSRAM, AHB SRAMs and securable peripherals are set to secure access only,
so, not accessible by non-secure masters such as DMA1/DMA2.

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3.11 Bus-interconnect matrix

The devices feature an AXI bus matrix, one main AHB bus matrix and bus bridges that allow
bus masters to be interconnected with bus slaves (see the figure below, the dots represent
the enabled master/slave connections).

Figure 3. STM32MP133A/D bus matrix

From MLAHB
interconnect

SDMMC1

SDMMC2

MDMA
USBH

ETH1

ETH2
DBG

CPU
128-bit

M9 M0 M1 M2 M3 M11 M4 M5 M6 M7

S0 DDRCTRL 533 MHz

S1
AHB bridge to AHB6

S2
To MLAHB interconnect

S3
FMC/NAND
AXIM

S4
QUADSPI

S5
SYSRAM 128 KB

S6
ROM 128 KB

S7
AHB bridge to AHB5

S8
APB bridge to APB5

S9
APB bridge to DBG APB

Default
slave

AXIMC

NIC-400 AXI 64 bits 266 MHz - 10 masters / 10 slaves AXI 64 synchronous master port
AXI 64 synchronous slave port
AXI 64 asynchronous master port
AXI 64 asynchronous slave port
interconnect
From AXIM

AHB 32 synchronous master port

USBO
DMA1

DMA2

DMA3

AHB 32 synchronous slave port

AHB 32 asynchronous master port
AHB 32 asynchronous slave port

M0 M1 M2 M3 M4 M5 M6 M7

S0
Bridge to AHB2

S1
SRAM1
MLAHB

S2
SRAM2

S3
SRAM3

S4 To AXIM interconnect

S5
Bridge to AHB4

Interconnect AHB 32 bits 209 MHz - 8 masters / 6 slaves

MSv67511V2

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3.12 DMA controllers

The devices feature the following DMA modules to unload CPU activity:
• a master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, that is in charge of all types of memory
transfers (peripheral-to-memory, memory-to-memory, memory-to-peripheral), without
any CPU action. It features a master AXI interface.
The MDMA is able to interface with the other DMA controllers to extend the standard
DMA capabilities, or can manage peripheral DMA requests directly.
Each of the 32 channels can perform block transfers, repeated block transfers and
linked list transfers.
The MDMA can be set to make secure transfers to secured memories.
• three DMA controllers (not secure DMA1 and DMA2, plus secure DMA3)
Each controller has a dual-port AHB, for a total of 16 non-secure and eight secure DMA
channels to perform FIFO-based block transfers.
Two DMAMUX units multiplex and route the DMA peripheral requests to the three DMA
controllers, with high flexibility, maximizing the number of DMA requests that run
concurrently, as well as generating DMA requests from peripheral output triggers or DMA
events.
DMAMUX1 maps DMA requests from non-secure peripherals to DMA1 and DMA2
channels. DMAMUX2 maps DMA requests from secure peripherals to DMA3 channels.

3.13 Extended interrupt and event controller (EXTI)

The extended interrupt and event controller (EXTI) manages the CPU and system wakeup
through configurable and direct event inputs. EXTI provides wakeup requests to the power
control, and generates an interrupt request to the GIC, and events to the CPU event input.
The EXTI wakeup requests allow the system to be woken up from Stop mode, and the CPU
to be woken up from CStop and CStandby modes.
The interrupt request and event request generation can also be used in Run mode.
The EXTI also includes the EXTI IOport selection.
Each interrupt or event can be set as secure in order to restrict access to secure software
only.

3.14 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps computing a signature
of the software during runtime, to be compared with a reference signature generated at
link-time and stored at a given memory location.

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3.15 Flexible memory controller (FMC)

The FMC controller main features are the following:
• Interface with static-memory mapped devices including:
– NOR flash memory
– Static or pseudo-static random access memory (SRAM, PSRAM)
– NAND flash memory with 4-bit/8-bit BCH hardware ECC
• 8-,16-bit data bus width
• Independent chip-select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
The FMC configuration registers can be made secure.

3.16 Dual Quad-SPI memory interface (QUADSPI)

The QUADSPI is a specialized communication interface targeting single, dual or quad SPI
flash memories. It can operate in any of the three following modes:
• Indirect mode: all the operations are performed using the QUADSPI registers.
• Status-polling mode: the external flash memory status register is periodically read and
an interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external flash memory is mapped to the address space
and is seen by the system as if it was an internal memory.
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
Quad-SPI flash memories are accessed simultaneously.
QUADSPI is coupled with a delay block (DLYBQS) allowing the support of external data
frequency above 100 MHz.
The QUADSPI configuration registers can be secure, as well as its delay block.

3.17 Analog-to-digital converters (ADC1, ADC2)

The devices embed two analog-to-digital converters, whose resolution can be configured to
12-, 10-, 8- or 6-bit. Each ADC shares up to 18 external channels, performing conversions in
the single-shot or scan mode. In scan mode, the automatic conversion is performed on a
selected group of analog inputs.
Both ADCs have securable bus interfaces.
Each ADC can be served by a DMA controller, thus allowing the automatic transfer of ADC
converted values to a destination location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
In order to synchronize A/D conversion and timers, the ADCs can be triggered by any of
TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, LPTIM1, LPTIM2 and LPTIM3 timers.

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3.18 Temperature sensor

The devices embed a temperature sensor that generates a voltage (VTS) that varies linearly
with the temperature. This temperature sensor is internally connected to ADC2_INP12 and
can measure the device ambient temperature ranging from –40 to +125 °C with a precision
of ±2 %.
The temperature sensor has a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the OTP area, that is
accessible in read-only mode.

3.19 Digital temperature sensor (DTS)

The devices embed a frequency output temperature sensor. DTS counts the frequency
based on the LSE or PCLK to provide the temperature information.
Following functions are supported:
• interrupt generation by temperature threshold
• wakeup signal generation by temperature threshold

3.20 VBAT operation

The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
In order to optimize battery duration, this power domain is supplied by VDD when available
or by the voltage applied on VBAT pin (when VDD supply is not present). VBAT power is
switched when the PDR detects that VDD has dropped below the PDR level.
The voltage on the VBAT pin can be provided by an external battery, a supercapacitor or
directly by VDD. In the later case, VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
Note: None of these events (external interrupts, TAMP event, or RTC alarm/events) are able to
directly restore the VDD supply and force the device out of the VBAT operation. Nevertheless,
TAMP events and RTC alarm/events can be used to generate a signal to an external
circuitry (typically a PMIC) that can restore the VDD supply.

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3.21 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer that can be used as voltage reference for the
ADCs, and also as voltage reference for external components through the VREF+ pin.
VREFBUF can be secure.
The internal VREFBUF supports four voltages:
• 1.65 V
• 1.8 V
• 2.048 V
• 2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
VREFBUF is off.

Figure 4. Voltage reference buffer

VREFINT +
VREF+

VSSA
MSv64430V2

3.22 Digital filter for sigma-delta modulator (DFSDM)

The devices embed one DFSDM with support for two digital filters modules and four
external input serial channels (transceivers) or alternately four internal parallel inputs.
The DFSDM interfaces external Σ∆ modulators to the device and performs digital filtering of
the received data streams. Σ∆ modulators are used to convert analog signals into
digital-serial streams that constitute the inputs of the DFSDM.
The DFSDM can also interface PDM (pulse-density modulation) microphones and perform
the PDM to PCM conversion and filtering (hardware accelerated). The DFSDM features
optional parallel data stream inputs from the ADCs or from the device memory (through
DMA/CPU transfers into DFSDM).
The DFSDM transceivers support several serial-interface formats (to support various
Σ∆ modulators). DFSDM digital filter modules perform digital processing according
user-defined filter parameters with up to 24-bit final ADC resolution.

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The DFSDM peripheral supports:

• Four multiplexed input digital serial channels:
– configurable SPI interface to connect various Σ∆ modulators
– configurable Manchester coded 1-wire interface
– PDM (pulse-density modulation) microphone input
– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
– clock output for Σ∆ modulators (0 to 20 MHz)
• Alternative inputs from four internal digital parallel channels (up to 16-bit input
resolution):
– internal sources: ADC data or memory data streams (DMA)
• Two digital filter modules with adjustable digital signal processing:
– Sincx filter: filter order/type (1 to 5), oversampling ratio (1 to 1024)
– integrator: oversampling ratio (1 to 256)
• Up to 24-bit output data resolution, signed output data format
• Automatic data offset correction (offset stored in register by user)
• Continuous or single conversion
• Start-of-conversion triggered by:
– software trigger
– internal timers
– external events
– start-of-conversion synchronously with first digital filter module (DFSDM)
• Analog watchdog featuring:
– low-value and high-value data threshold registers
– dedicated configurable Sincx digital filter (order = 1 to 3,
oversampling ratio = 1 to 32)
– input from final output data or from selected input digital serial channels
– continuous monitoring independently from standard conversion
• Short-circuit detector to detect saturated analog input values (bottom and top range):
– up to 8-bit counter to detect 1 to 256 consecutive 0’s or 1’s on serial data stream
– monitoring continuously each input serial channel
• Break signal generation on analog watchdog event or on short-circuit detector event
• Extremes detector:
– storage of minimum and maximum values of final conversion data
– refreshed by software
• DMA capability to read the final conversion data
• Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
• “Regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority

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3.23 True random number generator (RNG)

The devices embed one RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.
The RNG can be defined (in ETZPC) as accessible by secure software only.

3.24 Hash processor (HASH1)

The devices embed one processor that supports the advanced algorithms usually required
to ensure authentication, data integrity and non-repudiation when exchanging messages
with a peer.
Universal HASH main features:
• SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3 (secure HASH algorithms)
• HMAC
The accelerator supports DMA request generation.
HASH can be defined (in ETZPC) as accessible by secure software only.

3.25 Public key accelerator (PKA)

The PKA is intended for ECDSA signature generation and verification.
For a given operation, all needed computations are performed within the accelerator: no
further hardware/software elaboration is needed to process inputs or outputs.

3.26 Boot and security and OTP control (BSEC)

The BSEC (boot and security and OTP control) is intended to control an OTP (one-time
programmable) fuse box, used for embedded non-volatile storage for device configuration
and security parameters. Some part of BSEC must be configured as accessible by secure
software only.

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3.27 Timers and watchdogs

The devices include two advanced-control timers, ten general-purpose timers (out of which
seven are secured), two basic timers, five low-power timers, two watchdogs, and four
system timers in each Cortex-A7.
All timer counters can be frozen in debug mode.
The table below compares the features of the advanced-control, general-purpose, basic and
low-power timers.

Table 4. Timer feature comparison

Max Max
Counter DMA Capture/ Comple-
Timer Counter Prescaler interface timer
Timer resolu- request compare mentary
type type factor clock clock
tion generation channels output
(MHz) (MHz)(1)

Up, Any integer

Advanced TIM1,
16-bit down, between 1 Yes 6 4 104.5 209
-control TIM8
up/down and 65536
Up, Any integer
TIM2
32-bit down, between 1 Yes 4 No 104.5 209
TIM5
up/down and 65536
Up, Any integer
TIM3
16-bit down, between 1 Yes 4 No 104.5 209
TIM4
up/down and 65536
Any integer
TIM12(2) 16-bit Up between 1 No 2 No 104.5 209
General and 65536
purpose Any integer
TIM13(2)
16-bit Up between 1 No 1 No 104.5 209
TIM14(2)
and 65536
Any integer
TIM15(2) 16-bit Up between 1 Yes 2 1 104.5 209
and 65536
Any integer
TIM16(2)
16-bit Up between 1 Yes 1 1 104.5 209
TIM17(2)
and 65536
Any integer
TIM6,
Basic 16-bit Up between 1 Yes 0 No 104.5 209
TIM7
and 65536
LPTIM1,
LPTIM2(2), 1, 2, 4, 8,
Low-
LPTIM3(2), 16-bit Up 16, 32, 64, No 1(3) No 104.5 104.5
power
LPTIM4, 128
LPTIM5
1. The maximum timer clock is up to 209 MHz depending on TIMGxPRE bit in the RCC.
2. Securable timer.
3. No capture channel on LPTIM.

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3.27.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their four independent channels can be used for:
• input capture
• output compare
• PWM generation (edge- or center-aligned modes)
• one-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
timers. If configured as 16-bit PWM generators, they have full modulation
capability (0-100 %).
The advanced-control timer can work together with the general-purpose timers via the timer
link feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.

3.27.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13,

TIM14, TIM15, TIM16, TIM17)
There are ten synchronizable general-purpose timers embedded in the STM32MP133A/D
devices (see Table 4 for differences).
• TIM2, TIM3, TIM4, TIM5
TIM 2 and TIM5 are based on a 32-bit auto-reload up/down counter and a 16-bit
prescaler, while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature four independent channels for input capture/output
compare, PWM or one-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
These general-purpose timers can work together, or with the other general-purpose
timers and the advanced-control timers TIM1 and TIM8, via the timer link feature for
synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from one to four hall-effect sensors.
• TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
Each of these timers can be defined (in ETZPC) as accessible by secure software only.

3.27.3 Basic timers (TIM6 and TIM7)

These timers are mainly used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.

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3.27.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)

Each low-power timer has an independent clock and runs also in Stop mode if it is clocked
by LSE, LSI or an external clock. An LPTIMx is able to wake up the device from Stop mode.
These low-power timers support the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/one-shot mode
• Selectable software/hardware input trigger
• Selectable clock source:
– internal clock source: LSE, LSI, HSI or APB clock
– external clock source over LPTIM input (working even with no internal clock
source running, used by the pulse counter application)
• Programmable digital glitch filter
• Encoder mode
LPTIM2 and LPTIM3 can be defined (in ETZPC) as accessible by secure software only.

3.27.5 Independent watchdogs (IWDG1, IWDG2)

An independent watchdog is based on a 12-bit downcounter and a 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently
from the main clock, it can operate in Stop and Standby modes. IWDG can be used as a
watchdog to reset the device when a problem occurs. It is hardware- or software-
configurable through the option bytes.
IWDG1 can be defined (in ETZPC) as accessible by secure software only.

3.27.6 Generic timers (Cortex-A7 CNT)

Cortex-A7 generic timers embedded inside Cortex-A7 are fed by value from system timing
generation (STGEN).
The Cortex-A7 processor provides the following timers:
• physical timer for use in secure and non-secure modes
The registers for the physical timer are banked to provide secure and non-secure
copies.
• virtual timer for use in non-secure modes
• physical timer for use in hypervisor mode
Generic timers are not memory mapped peripherals and are then accessible only by
specific Cortex-A7 coprocessor instructions (cp15).

3.28 System timer generation (STGEN)

The system timing generation (STGEN) generates a time-count value that provides a
consistent view of time for all Cortex-A7 generic timers.

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The system timing generation has the following key features:

• 64-bit wide to avoid roll-over issues
• Start from zero or a programmable value
• Control APB interface (STGENC) that enables the timer to be saved and restored
across powerdown events
• Read-only APB interface (STGENR) that enables the timer value to be read by non-
secure software and debug tools
• Timer value incrementing that can be stopped during system debug
STGENC can be defined (in ETZPC) as accessible by secure software only.

3.29 Real-time clock (RTC)

The RTC provides an automatic wakeup to manage all low-power modes.RTC is an
independent BCD timer/counter and provides a time-of-day clock/calendar with
programmable alarm interrupts.
The RTC includes also a periodic programmable wakeup flag with interrupt capability.
Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day
of week), date (day of month), month, and year, expressed in binary coded decimal format
(BCD). The sub-seconds value is also available in binary format.
Binary mode is supported to ease software driver management.
Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed.
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
A digital calibration feature is available to compensate for any deviation in crystal oscillator
accuracy.
After Backup domain reset, all RTC registers are protected against possible parasitic write
accesses and protected by secured access.
As long as the supply voltage remains in the operating range, the RTC never stops,
regardless of the device status (Run mode, low-power mode or under reset).
The RTC main features are the following:
• Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of
week), date (day of month), month, and year
• Daylight saving compensation programmable by software
• Programmable alarm with interrupt function. The alarm can be triggered by any
combination of the calendar fields.
• Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup
interrupt
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Accurate synchronization with an external clock using the sub-second shift feature
• Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a
calibration window of several seconds

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• Timestamp function for event saving

• Storage of SWKEY in RTC backup registers with direct bus access to SAE (not
readable by the CPU)
• Maskable interrupts/events:
– Alarm A
– Alarm B
– Wakeup interrupt
– Timestamp
• TrustZone support:
– RTC fully securable
– Alarm A, alarm B, wakeup timer and timestamp individual secure or non-secure
configuration
– RTC calibration done in secure on non-secure configuration

3.30 Tamper and backup registers (TAMP)

32 x 32-bit backup registers are retained in all low-power modes and also in VBAT mode.
They can be used to store sensitive data as their content is protected by a tamper detection
circuit.
Seven tamper input pins and five tamper output pins are available for anti-tamper detection.
The external tamper pins can be configured for edge detection, edge and level, level
detection with filtering, or active tamper that increases the security level by auto checking
that the tamper pins are not externally opened or shorted.
TAMP main features
• 32 backup registers (TAMP_BKPxR) implemented in the RTC domain that remains
powered-on by VBAT when the VDD power is switched off
• 12 tamper pins available (seven inputs and five outputs)
• Any tamper detection can generate a RTC timestamp event.
• Any tamper detection erases the backup registers.
• TrustZone support:
– Tamper secure or non-secure configuration
– Backup registers configuration in three configurable-size areas:
. one read/write secure area
. one write secure/read non-secure area
. one read/write non-secure area
• Monotonic counter

3.31 Inter-integrated circuit interfaces (I2C1, I2C2, I2C3, I2C4,

I2C5)
The devices embed five I2C interfaces.
The I2C bus interface handles communications between the STM32MP133A/D and the
serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

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The I2C peripheral supports:

• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBus™) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
I2C3, I2C4 and I2C5 can be defined (in ETZPC) as accessible by secure software only.

3.32 Universal synchronous asynchronous receiver transmitter

(USART1, USART2, USART3, USART6 and UART4, UART5,
UART7, UART8)
The devices have four embedded universal synchronous receiver transmitters (USART1,
USART2, USART3 and USART6) and four universal asynchronous receiver transmitters
(UART4, UART5, UART7 and UART8). Refer to the table below for a summary of USARTx
and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
13 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the STM32MP133A/D from Stop mode using baudrates up to 200 Kbaud.The
wakeup events from Stop mode are programmable and can be:
• start bit detection
• any received data frame
• a specific programmed data frame

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All USART interfaces can be served by the DMA controller.

Table 5. USART/UART features

USART modes/features(1) USART1/2/3/6 UART4/5/7/8

Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous SPI mode (master/slave) X -
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X X
LIN mode X X
Dual clock domain and wakeup from low power mode X X
Receiver timeout interrupt X X
Modbus communication X X
Auto baud rate detection X X
Driver Enable X X
USART data length 7, 8 and 9 bits
1. X = supported.

USART1 and USART2 can be defined (in ETZPC) as accessible by secure software only.

3.33 Serial peripheral interfaces (SPI1, SPI2, SPI3, SPI4, SPI5)

– inter- integrated sound interfaces (I2S1, I2S2, I2S3, I2S4)
The devices feature up to five SPIs (SPI2S1, SPI2S2, SPI2S3, SPI2S4, and SPI5) that
allow communication at up to 50 Mbit/s in master and slave modes, in half-duplex, full-
duplex and simplex modes. The 3-bit prescaler gives eight master mode frequencies and
the frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI
mode, hardware CRC calculation and multiply of 8-bit embedded Rx and Tx FIFOs with
DMA capability.
I2S1, I2S2, I2S3, and I2S4 are multiplexed with SPI1, SPI2, SPI3 and SPI4. They can be
operated in master or slave mode, in full-duplex and half-duplex communication modes, and
can be configured to operate with a 16- or 32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. All I2S interfaces
support multiply of 8-bit embedded Rx and Tx FIFOs with DMA capability.
SPI4 and SPI5 can be defined (in ETZPC) as accessible by secure software only.

3.34 Serial audio interfaces (SAI1, SAI2)

The devices embed two SAIs that allow the design of many stereo or mono audio protocols

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such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available
when the audio block is configured as a transmitter. To bring this level of flexibility and
reconfigurability, each SAI contains two independent audio sub-blocks. Each block has it
own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to eight microphones can be supported thanks to an embedded PDM
interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.

3.35 SPDIF receiver interface (SPDIFRX)

The SPDIFRX is designed to receive an S/PDIF flow compliant with IEC-60958 and
IEC-61937. These standards support simple stereo streams up to high sample rate, and
compressed multi-channel surround sound, such as those defined by Dolby or DTS
(up to 5.1).
The SPDIFRX main features are the following:
• Up to four inputs available
• Automatic symbol rate detection
• Maximum symbol rate: 12.288 MHz
• Stereo stream from 32 to 192 kHz supported
• Support of audio IEC-60958 and IEC-61937, consumer applications
• Parity bit management
• Communication using DMA for audio samples
• Communication using DMA for control and user channel information
• Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal is available, the SPDIFRX re-samples the incoming signal, decodes the
Manchester stream, and recognizes frames, sub-frames and blocks elements. The
SPDIFRX delivers to the CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, that toggles at the S/PDIF
sub-frame rate that is used to compute the exact sample rate for clock drift algorithms.

3.36 Secure digital input/output MultiMediaCard interfaces

(SDMMC1, SDMMC2)
Two secure digital input/output MultiMediaCard interfaces (SDMMC) provide an interface
between the AHB bus and SD memory cards, SDIO cards and MMC devices.
The SDMMC features include the following:
• Compliance with Embedded MultiMediaCard System Specification Version 5.1
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit

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(HS200 SDMMC_CK speed limited to maximum allowed I/O speed)(HS400 is not

supported)
• Full compatibility with previous versions of MultiMediaCards (backward compatibility)
• Full compliance with SD memory card specifications version 4.1
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported)
• Full compliance with SDIO card specification version 4.0
Card support for two different databus modes: 1-bit (default) and 4-bit
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported)
• Data transfer up to 208 Mbyte/s for the 8-bit mode
(depending maximum allowed I/O speed)
• Data and command output enable signals to control external bidirectional drivers
• Dedicated DMA controller embedded in the SDMMC host interface, allowing
high-speed transfers between the interface and the SRAM
• IDMA linked list support
• Dedicated power supplies, VDDSD1 and VDDSD2 for SDMMC1 and SDMMC2
respectively, removing the need for level-shifter insertion on the SD card interface in
UHS-I mode
Only some GPIOs for SDMMC1 and SDMMC2 are available on a dedicated VDDSD1 or
VDDSD2 supply pin. Those are part of the default boot GPIOs for SDMMC1 and SDMMC2
(SDMMC1: PC[12:8], PD[2], SDMMC2: PB[15,14,4,3], PE3, PG6). They can be identified in
the alternate function table by signals with a "_VSD1" or "_VSD2" suffix.
Each SDMMC is coupled with a delay block (DLYBSD) allowing support of an external data
frequency above 100 MHz.
Both SDMMC interfaces have securable configuration ports.

3.37 Controller area network (FDCAN1, FDCAN2)

The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs and transmit buffers (plus triggers for TTCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.

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3.38 Universal serial bus high-speed host (USBH)

The devices embed one USB high-speed host (up to 480 Mbit/s) with two physical ports.
USBH supports both low, full-speed (OHCI) as well as high-speed (EHCI) operations
independently on each port. It integrates two transceivers that can be used for either
low-speed (1.2 Mbit/s), full-speed (12 Mbit/s) or high-speed operation (480 Mbit/s). The
second high-speed transceiver is shared with OTG high-speed.
The USBH is compliant with the USB 2.0 specification. The USBH controllers require
dedicated clocks that are generated by a PLL inside the USB high-speed PHY.

3.39 USB on-the-go high-speed (OTG)

The devices embed one USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG supports both full-speed and high-speed operations. The transceiver for
high-speed operation (480 Mbit/s) is shared with the USB Host second port.
The USB OTG HS is compliant with the USB 2.0 specification and with the OTG 2.0
specification. It has software-configurable endpoint setting and supports suspend/resume.
The USB OTG controllers require a dedicated 48 MHz clock that is generated by a PLL
inside RCC or inside the USB high-speed PHY.
The USB OTG HS main features are listed below:
• Combined Rx and Tx FIFO size of 4 Kbyte with dynamic FIFO sizing
• SRP (session request protocol) and HNP (host negotiation protocol) support
• Eight bidirectional endpoints
• 16 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (link power management) support
• Battery charging specification revision 1.2 support
• HS OTG PHY support
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected.
The USB OTG configuration port can be secure.

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3.40 Gigabit Ethernet MAC interfaces (ETH1, ETH2)

The devices provide two IEEE-802.3-2002-compliant gigabit media access controllers
(GMAC) for Ethernet LAN communications through an industry-standard
medium-independent interface (MII), a reduced medium-independent interface (RMII), or a
reduced gigabit medium-independent interface (RGMII).
The devices require an external physical interface device (PHY) to connect to the physical
LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device port using 17 signals
for MII, 7 signals for RMII, or 13 signals for RGMII, and can be clocked using the 25 MHz
(MII, RMII, RGMII) or 125 MHz (RGMII) from the STM32MP133A/D or from the PHY.
The devices include the following features:
• Operation modes and PHY interfaces
– 10-, 100-, and 1000-Mbit/s data transfer rates
– Support of both full-duplex and half-duplex operations
– MII, RMII and RGMII PHY interfaces
• Processing control
– Multi-layer Packet filtering: MAC filtering on source (SA) and destination (DA)
address with perfect and hash filter, VLAN tag-based filtering with perfect and
hash filter, Layer 3 filtering on IP source (SA) or destination (DA) address, Layer 4
filtering on source (SP) or destination (DP) port
– Double VLAN processing: insertion of up to two VLAN tags in transmit path, tag
filtering in receive path
– IEEE 1588-2008/PTPv2 support
– Supports network statistics with RMON/MIB counters (RFC2819/RFC2665)
• Hardware offload processing
– Preamble and start-of-frame data (SFD) insertion or deletion
– Integrity checksum offload engine for IP header and TCP/UDP/ICMP payload:
transmit checksum calculation and insertion, receive checksum calculation and
comparison
– Automatic ARP request response with the device MAC address
– TCP segmentation: automatic split of large transmit TCP packet into multiple small
packets
• Low-power mode
– Energy efficient Ethernet (standard IEEE 802.3az-2010)
– Remote wakeup packet and AMD Magic Packet™ detection
Both ETH1 and ETH2 can be programmed as secure. When secure, transactions over the
AXI interface are secure, and the configuration registers can only be modified by secure
accesses.

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3.41 Debug infrastructure

The devices offer the following debug and trace features to support software development
and system integration:
• Breakpoint debugging
• Code execution tracing
• Software instrumentation
• JTAG debug port
• Serial-wire debug port
• Trigger input and output
• Trace port
• Arm CoreSight debug and trace components
The debug can be controlled via a JTAG/serial-wire debug access port, using industry
standard debugging tools.
A trace port allows data to be captured for logging and analysis.
A debug access to secure areas is enabled by the authentication signals in the BSEC.

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4 Pinout, pin description and alternate functions

Figure 5. STM32MP133A/D LFBGA289 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

A VSS PA9 PD10 PB7 PE7 PD5 PE8 PG4 PH9 PH13 PC7 PB9 PB14 PG6 PD2 PC9 VSS

B PD3 PF5 PD14 PE12 PE1 PE9 PH14 PE10 PF1 PF3 PC6 PB15 PB4 PC10 PC12 DDR_DQ4 DDR_DQ0

DDR_ DDR_
C PB6 PH12 PE14 PE13 PD8 PD12 PD15 VSS PG7 PB5 PB3 VDDSD1 PF0 PC11 DDR_DQ1
DQS0N DQS0P

DDR_
D PB8 PD6 VSS PE11 PD1 PE0 PG0 PE15 PB12 PB10 VDDSD2 VSS PE3 PC8 DDR_DQ5 DDR_DQ3
DQM0

VDDQ_ DDR_
E PG9 PD11 PA12 PD0 VSS PA15 PD4 PD9 PF2 PB13 PH10 DDR_DQ2 DDR_DQ6 DDR_DQ7 DDR_A5
DDR RESETN

VDDQ_
F PG10 PG5 PG8 PH2 PH8 VDDCPU VDD VDDCPU VDDCPU VDD VDD VSS DDR_A13 VSS DDR_A9 DDR_A2
DDR

VDDQ_
G PF9 PF6 PF10 PG15 PF8 VDD VSS VSS VSS VSS VSS DDR_BA2 DDR_A7 DDR_A3 DDR_A0 DDR_BA0
DDR

VDDQ_ DDR_
H PH11 PI3 PH7 PB2 PE4 VDDCPU VSS VDDCORE VDDCORE VDDCORE VSS DDR_WEN VSS DDR_ODT DDR_CSN
DDR RASN

VDDQ_ DDR_ DDR_ DDR_

J PD13 VBAT PI2 VSS_PLL VDD_PLL VDDCPU VSS VDDCORE VSS VDDCORE VSS VDDCORE DDR_A10
DDR CASN CLKP CLKN

PC15-
PC14- VDDQ_
K OSC32_ VSS PC13 PI1 VDD VSS VDDCORE VDDCORE VDDCORE VSS DDR_A11 DDR_CKE DDR_A1 DDR_A15 DDR_A12
OSC32_IN DDR
OUT

VDDQ_ DDR_
L PE2 PF4 PH6 PI0 PG3 VDD VSS VSS VSS VSS VSS DDR_ATO DDR_A8 DDR_BA1 DDR_A14
DDR DTO0

VDDQ_ DDR_ DDR_

M PF7 PA8 PG11 VDD_ANA VSS_ANA VDD VDD VDD VDD VDD VDD DDR_A4 VSS DDR_A6
DDR VREF DTO1

VSS_USB VDDA1V1_ VDDQ_ DDR_ DDR_

N PE6 PG1 PD7 VSS PB11 PF13 VSSA PA3 NJTRST PWR_LP DDR_DQ8 DDR_ZQ
HS REG DDR DQM1 DQ10

PH0- PH1- VDD3V3_ DDR_ DDR_

P PA13 PF14 PA2 VREF- VDDA PG13 PG14 VSS PI5-BOOT1 VSS_PLL2 PWR_ON DDR_DQ9
OSC_IN OSC_OUT USBHS DQ11 DQ13

PWR_CPU VDDA1V8_ DDR_ DDR_ DDR_

R PG2 PH3 PA1 VSS VREF+ PC5 VSS VDD PF15 PI6-BOOT2 VDD_PLL2 PH5
_ON REG DQ12 DQS1N DQS1P

BYPASS_ DDR_ DDR_

T PG12 PA11 PC0 PF12 PC3 PF11 PB1 PA6 PE5 PDR_ON USB_DP2 PA14 USB_DP1 PH4
REG1V8 DQ15 DQ14

USB_
U VSS PA7 PA0 PA5 PA4 PC4 PB0 PC1 PC2 NRST USB_DM2 USB_DM1 PI4-BOOT0 PA10 PI7 VSS
RREF

MSv65067V5

The above figure shows the package top view.

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Figure 6. STM32MP133A/D TFBGA289 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

A VSS PD4 PE9 PG0 PD15 PE15 PB12 PF1 PC7 PC6 PF0 PB14 VDDSD2 VDDSD1 DDR_DQ4 DDR_DQ0 VSS

DDR_ DDR_
B PE12 PD8 PE0 PD5 PD9 PH14 PF2 VSS PF3 PB13 PB3 PE3 PC12 VSS DDR_DQ1
DQS0N DQS0P

DDR_
C PE13 PD1 PE1 PE7 VSS VDD PE10 PG7 PG4 PB9 PH10 PC11 PC8 DDR_DQ2 DDR_DQ3 DDR_DQ5
DQM0

VDDQ_ DDR_
D PF5 PA9 PD10 VDDCPU PB7 VDDCPU PD12 VDDCPU PH9 VDD PB15 VDD VSS DDR_DQ7 DDR_DQ6
DDR RESETN

VDDQ_ VDDQ_
E PD0 PE14 VSS PE11 VDDCPU VSS PA15 VSS PH13 VSS PB4 VSS VSS VSS DDR_A13
DDR DDR

VDDCORE PD14 PE8 PB5 VDDCORE PC10 VDDCORE VDDQ_

F PH8 PA12 VDD VDDCPU VSS VSS DDR_A7 DDR_A5 DDR_A9
DDR

G PD11 PH2 PB6 PB8 PG9 PD3 PH12 PG15 PD6 PB10 PD2 PC9 DDR_A2 DDR_BA2 DDR_A3 DDR_A0 DDR_ODT

BYPASS_ VDDQ_
H PG5 PG10 PF8 VDDCPU VSS VDDCORE PH11 PI3 PF9 PG6 VDDCORE VSS DDR_BA0 DDR_CSN DDR_WEN
REG1V8 DDR

VDDA1V8_ DDR_ DDR_ DDR_

J VDD_PLL VSS_PLL PG8 PI2 VBAT PH6 PF7 PA8 PF12 VDD PA10 DDR_A10 VSS
REG VREF RASN CASN

VDDQ_ DDR_ DDR_

K PE4 PF10 PB2 VDD VSS VDDCORE PA13 PA1 PC4 NRST VSS_PLL2 VDDCORE VSS DDR_A15
DDR CLKP CLKN

L PF6 VSS PH7 VDD_ANA VSS_ANA PG12 PA0 PF11 PE5 PF15 VDD_PLL2 PH5 DDR_CKE DDR_A12 DDR_A1 DDR_A11 DDR_A14

PC15-
PC14- USB_ VDDQ_
M OSC32_ PC13 VDD VSS PB11 PA5 PB0 VDDCORE PI6-BOOT2 VDDCORE VSS DDR_A6 DDR_A8 DDR_BA1
OSC32_IN RREF DDR
OUT

VDDQ_ VDDQ_
N PD13 VSS PI0 PI1 PA11 VSS PA4 PB1 VSS VSS PI5-BOOT1 VSS VSS VSS DDR_ATO
DDR DDR

PH0- PH1- VDDQ_

P PF4 PG1 VSS VDD PC3 PC5 VDD VDD PI4-BOOT0 VDD VSS DDR_A4 DDR_ZQ DDR_DQ8
OSC_IN OSC_OUT DDR

PWR_ DDR_ DDR_ DDR_

R PG11 PE6 PD7 PA2 PA7 PC1 PA6 PG13 NJTRST PA14 VSS PWR_ON DDR_DQ9
CPU_ON DQM1 DQ12 DQ11

VSS_ DDR_ DDR_ DDR_ DDR_

T PE2 PH3 PF13 PC0 VSSA VREF- PA3 PG14 USB_DP2 VSS USB_DP1 PH4
USBHS DQ13 DQ14 DQS1P DQS1N

VDDA1V1_ VDD3V3_ DDR_ DDR_

U VSS PG3 PG2 PF14 VDDA VREF+ PDR_ON PC2 USB_DM2 USB_DM1 PI7 PWR_LP VSS
REG USBHS DQ15 DQ10

MSv67512V3

The above figure shows the package top view.

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Pinout, pin description and alternate functions STM32MP133A/D

Figure 7. STM32MP133A/D TFBGA320 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

A VSS PA9 PE13 PE12 PD12 PG0 PE15 PG7 PH13 PF3 PB9 PF0 PC10 PC12 PC9 VSS

DDR_ DDR_ DDR_

B PD0 PE11 PF5 PA15 PD8 PE0 PE9 PH14 PE8 PG4 PF1 VSS PB5 PC6 PB15 PB14 PE3 PC11
DQ4 DQ1 DQ0

VDD DDR_ DDR_

C PB6 PD3 PE14 PD14 PD1 PB7 PD4 PD5 PD9 PE10 PB12 PH9 PC7 PB3
SD2
PB4 PG6 PC8 PD2
DQS0P DQS0N

DDR_ DDR_ DDR_

D PB8 PD6 PH12 PD10 PE7 PF2 PB13 VSS
DQ2 DQ5 DQM0

VDD VDD VDDQ_ VDD DDR_ DDR_

E PH2 PH8 VSS VSS
CPU
PE1 PD15
CPU
VSS VDD PB10 PH10
DDR
VSS
SD1 DQ3 DQ6

DDR_ DDR_
F PF8 PG9 PD11 PA12 VSS VSS VSS
DQ7 A5
VSS

VDD VDD VDD VDD VDDQ_ VDDQ_ DDR_ DDR_ DDR_

G PF6 PG10 PG5
CPU CPU
VSS VDD
CPU CORE
VSS VDD VSS
DDR DDR A13 A2 A9

DDR_
DDR_ DDR_ DDR_
H PE4 PF10 PG15 PG8 VSS VSS RESET
N
BA2 A3 A0

VDD VDD DDR_ DDR_ DDR_ DDR_

J PH7 PD13 PB2 PF9 VDD VDD VSS
CORE
VSS VDD
CORE A7 BA0 CSN ODT

VSS_ VDD_ VDD VDD VDDQ_ VDDQ_ DDR_ DDR_

K PLL PLL
PH11
CPU CPU
VSS VSS VSS VSS VSS
DDR DDR WEN RASN
VSS

PC15-
VDD VDD VDD DDR_ DDR_ DDR_
L VBAT OSC32
_OUT
PI3 VSS
CORE CORE
VSS VSS
CORE
VSS VSS
A10 CASN CLKN

PC14-
VDDQ_ VDDQ_ DDR_ DDR_ DDR_
M VSS OSC32
_IN
PC13 VDD VSS VSS VSS VSS VSS VSS
DDR DDR A12 CLKP A15

VDD VDD VDD DDR_ DDR_ DDR_ DDR_

N PE2 PF4 PH6 PI2 VDD VDD
CORE
VSS VDD
CORE CORE A11 A14 CKE A1

DDR_ DDR_ DDR_ DDR_

P PA8 PF7 PI1 PI0 VSS VSS
DTO1 ATO A8 BA1

VDD VDD VDDQ_ VDDQ_ DDR_ DDR_ DDR_

R PG1 PG11 PH3 VDD VDD VSS VDD
CORE
VSS VDD
CORE
VSS
DDR DDR A4 ZQ A6

PH0- DDR_ DDR_ DDR_

T VSS PE6
OSC_IN
PA13 VSS VSS
VREF DQ10 DQ8
VSS

PH1-
VSS_ VDD VDD VDDQ_ PWR_ DDR_ DDR_
U OSC_
OUT
ANA
VSS VSS VDD VDDA VSSA PA6 VSS
CORE
VSS
CORE DDR
VSS
ON DQ13 DQ9

VDDA1
VDD_ NJ PWR_ DDR_ DDR_
V PD7
ANA
PG2 PA7 VREF-
TRST
V1_
REG
VSS
LP DQS1P DQS1N

PWR_ VDD VDDA1 BYPAS

USB_ DDR_ DDR_ DDR_
W PG3 PG12 CPU_
ON
PF13 PC0 PC3 VREF+ PB0 PA3 PE5 VDD
RREF
PA14 3V3_
USBHS
V8_
REG
VSS S_REG
1V8
PH5
DQ12 DQ11 DQM1

USB_ VSS_ PI6- USB_ PI4- VDD_ DDR_ DDR_

Y PA11 PF14 PA0 PA2 PA5 PF11 PC4 PB1 PC1 PG14 NRST PF15
DM2 USBHS BOOT2 DP1 BOOT0 PLL2
PH4
DQ15 DQ14

PDR_ USB_ PI5- USB_ VSS_

AA VSS PB11 PA1 PF12 PA4 PC5 PG13 PC2
ON DP2 BOOT1 DM1 PLL2
PA10 PI7 VSS

MSv65068V5

The above figure shows the package top view.

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Table 6. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified, the pin function during and after reset is the same as the actual pin
Pin name
name
S Supply pin
I Input only pin
Pin type O Output only pin
I/O Input/output pin
A Analog or special level pin
FT(U/D/PD) 5 V tolerant I/O (with fixed pull-up / pull-down / programmable pull-down)
DDR 1.5 V, 1.35 V or 1.2 V I/O for DDR3, DDR3L, LPDDR2/LPDDR3 interface
A Analog signal
RST Reset pin with weak pull-up resistor
Option for FT I/Os
I/O structure _f(1)
I2C FM+ option
_a(2) Analog option (supplied by VDDA for the analog part of the I/O)
_u(3) USB option (supplied by VDD3V3_USBxx for the USB part of the I/O)
(4)
_h High-speed output for 1.8V typ. VDD (for SPI, SDMMC, QUADSPI, TRACE)
Very-high-speed option for 1.8V typ. VDD (for ETH, SPI, SDMMC, QUADSPI,
_vh(5)
TRACE)
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 7 are: FT_f, FT_fh, FT_fvh
2. The related I/O structures in Table 7 are: FT_a, FT_ha, FT_vha
3. The related I/O structures in Table 7 are: FT_u
4. The related I/O structures in Table 7 are: FT_h, FT_fh, FT_fvh, FT_vh, FT_ha, FT_vha
5. The related I/O structures in Table 7 are: FT_vh, FT_vha, FT_fvh

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96
Pinout, pin description and alternate functions STM32MP133A/D

Table 7. STM32MP133A/D ball definitions

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

K10 F6 U14 VDDCORE S - - - -

TIM1_CH2, I2C3_SMBA,
DFSDM1_DATIN0,
A2 D2 A2 PA9 I/O FT_h - -
USART1_TX, UART4_TX,
FMC_NWAIT(boot)
A1 A1 T5 VSS S - - - -
M6 F3 U7 VDD S - - - -
TIM1_CH2,
USART2_CTS/USART2_NSS,
SAI1_D2,
SPI4_MOSI/I2S4_SDO,
D4 E4 B2 PE11 I/O FT_vh - -
SAI1_FS_A, USART6_CK,
ETH2_MII_TX_ER,
ETH1_MII_TX_ER,
FMC_D8(boot)/FMC_AD8
TRACED12, DFSDM1_CKIN0,
B2 D1 B3 PF5 I/O FT_h - -
I2C1_SMBA, FMC_A5
TIM2_CH1,
USART2_CTS/USART2_NSS,
B1 G6 C2 PD3 I/O FT_f - -
DFSDM1_CKOUT, I2C1_SDA,
SAI1_D3, FMC_CLK
TIM1_BKIN, SAI1_D4,
UART8_RTS/UART8_DE,
C3 E2 C3 PE14 I/O FT_h - QUADSPI_BK1_NCS, TAMP_IN6
QUADSPI_BK2_IO2,
FMC_D11(boot)/FMC_AD11
F6 D4 E7 VDDCPU S - - - -
SAI1_MCLK_A, SAI1_CK1,
E4 E1 B1 PD0 I/O FT - FDCAN1_RX, -
FMC_D2(boot)/FMC_AD2
USART2_TX, TIM5_CH3,
DFSDM1_CKIN1, I2C3_SCL,
SPI5_MOSI, SAI1_SCK_A,
C2 G7 D3 PH12 I/O FT_fh - -
QUADSPI_BK2_IO2,
SAI1_CK2, ETH1_MII_CRS,
FMC_A6
TRACED6, TIM16_CH1N,
TIM4_CH1, TIM8_CH1,
USART1_TX, SAI1_CK2,
C1 G3 C1 PB6 I/O FT_h - -
QUADSPI_BK1_NCS,
ETH2_MDIO, FMC_NE3,
HDP6

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STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

A17 A17 T17 VSS S - - - -

M7 - J13 VDD S - - - -
TIM16_CH1N, SAI1_D1,
D2 G9 D2 PD6 I/O FT - -
SAI1_SD_A, UART4_TX(boot)
TRACED9, TIM5_ETR,
F5 F1 E3 PH8 I/O FT_fh - USART2_RX, I2C3_SDA, -
FMC_A8, HDP2
TIM16_CH1, TIM4_CH3,
I2C1_SCL, I2C3_SCL,
D1 G4 D1 PB8 I/O FT_f - DFSDM1_DATIN1, -
UART4_RX, SAI1_D1,
FMC_D13(boot)/FMC_AD13
TIM1_ETR, SAI2_MCLK_A,
USART1_RTS/USART1_DE,
E3 F2 F4 PA12 I/O FT_h - ETH2_MII_RX_DV/ETH2_ -
RGMII_RX_CTL/ETH2_RMII_
CRS_DV, FMC_A7
F8 D6 E10 VDDCPU S - - - -
LPTIM1_IN2, UART7_TX,
QUADSPI_BK2_IO0(boot),
F4 G2 E2 PH2 I/O FT_h - ETH2_MII_CRS, -
ETH1_MII_CRS, FMC_NE4,
ETH2_RGMII_CLK125
C8 B8 T21 VSS S - - - -
LPTIM2_IN2, I2C4_SMBA,
USART3_CTS/USART3_NSS,
SPDIFRX_IN0,
E2 G1 F3 PD11 I/O FT_h - QUADSPI_BK1_IO2, -
ETH2_RGMII_CLK125,
FMC_CLE(boot)/FMC_A16,
UART7_RX
DBTRGO, I2C2_SDA,
USART6_RX, SPDIFRX_IN3,
E1 G5 F2 PG9 I/O FT_f - -
FDCAN1_RX, FMC_NE2,
FMC_NCE(boot)
TIM16_CH1N, TIM4_CH3,
TIM8_CH3, SAI1_SCK_B,
G5 H3 F1 PF8 I/O FT_h - WKUP1
USART6_TX, TIM13_CH1,
QUADSPI_BK1_IO0(boot)
M8 - M5 VDD S - - - -

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96
Pinout, pin description and alternate functions STM32MP133A/D

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

TIM2_CH1, TIM8_ETR,
SPI5_MISO, SAI1_MCLK_B,
USART3_RTS/USART3_DE,
F3 J3 H5 PG8 I/O FT_h - SPDIFRX_IN2, TAMP_IN4
QUADSPI_BK2_IO2,
QUADSPI_BK1_IO3,
FMC_NE2, ETH2_CLK
F9 D8 G5 VDDCPU S - - - -
TIM17_CH1, ETH2_MDC,
F2 H1 G3 PG5 I/O FT_h - -
FMC_A15
USART6_CTS/USART6_NSS,
UART7_CTS,
G4 G8 H4 PG15 I/O FT_h - -
QUADSPI_BK1_IO1,
ETH2_PHY_INTN
SPI5_SCK, SAI1_SD_B,
UART8_CTS, FDCAN1_TX,
F1 H2 G2 PG10 I/O FT_h - -
QUADSPI_BK2_IO1(boot),
FMC_NE3
D3 B14 U5 VSS S - - - -
TIM16_BKIN, SAI1_D3,
TIM8_BKIN, SPI5_NSS,
G3 K2 H3 PF10 I/O FT_h - USART6_RTS/USART6_DE, TAMP_IN1
UART7_RTS/UART7_DE,
QUADSPI_CLK(boot)
H8 F10 - VDDCORE S - - - -
TIM16_CH1, SPI5_NSS,
UART7_RX(boot),
QUADSPI_BK1_IO2,
G2 L1 G1 PF6 I/O FT_vh - -
ETH2_MII_TX_EN/ETH2_
RGMII_TX_CTL/ETH2_RMII_
TX_EN
D12 C5 U6 VSS S - - - -
M9 K4 N7 VDD S - - - -
TIM17_CH1N, TIM1_CH1,
DFSDM1_CKIN3, SAI1_D4,
UART7_CTS, UART8_RX,
G1 H9 J5 PF9 I/O FT_h - -
TIM14_CH1,
QUADSPI_BK1_IO1(boot),
QUADSPI_BK2_IO3, FMC_A9

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STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

SPI5_MISO, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N, I2S_CKIN,
SAI1_FS_A,
H5 K1 H2 PE4 I/O FT_h - -
UART7_RTS/UART7_DE,
UART8_TX,
QUADSPI_BK2_NCS,
FMC_NCE2, FMC_A25
H6 E5 G7 VDDCPU S - - - -
RTC_OUT2, SAI1_D1,
I2S_CKIN, SAI1_SD_A,
H4 K3 J3 PB2 I/O FT_h - UART4_RX, TAMP_IN7
QUADSPI_BK1_NCS(boot),
ETH2_MDIO, FMC_A6
E5 D13 U11 VSS S - - - -
SAI2_FS_B, I2C3_SDA,
SPI5_SCK,
QUADSPI_BK2_IO3,
H3 L3 J1 PH7 I/O FT_fh - -
ETH2_MII_TX_CLK,
ETH1_MII_TX_CLK,
QUADSPI_BK1_IO3
SPI5_NSS, TIM5_CH2,
SAI2_SD_A,
SPI2_NSS/I2S2_WS,
I2C4_SCL, USART6_RX,
H1 H7 K3 PH11 I/O FT_fh - -
QUADSPI_BK2_IO0,
ETH2_MII_RX_CLK/ETH2_
RGMII_RX_CLK/ETH2_RMII_
REF_CLK, FMC_A12
LPTIM2_ETR, TIM4_CH2,
TIM8_CH2, SAI1_CK1,
SAI1_MCLK_A, USART1_RX,
J1 N1 J2 PD13 I/O FT_h - -
QUADSPI_BK1_IO3,
QUADSPI_BK2_IO2,
FMC_A18
J5 J1 K2 VDD_PLL S - - - -
J4 J2 K1 VSS_PLL S - - - -

(1) SPDIFRX_IN3, TAMP_IN4/TAMP_

H2 H8 L4 PI3 I/O FT
ETH1_MII_RX_ER OUT5, WKUP2
RTC_OUT1/RTC_TS/
(1) RTC_LSCO,
K4 M3 M3 PC13 I/O FT -
TAMP_IN1/TAMP_
OUT2, WKUP3

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96
Pinout, pin description and alternate functions STM32MP133A/D

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

(1) TAMP_IN3/TAMP_
J3 J4 N5 PI2 I/O FT SPDIFRX_IN2
OUT4, WKUP5
RTC_OUT2/RTC_
(1) LSCO,
K5 N4 P4 PI1 I/O FT SPDIFRX_IN1
TAMP_IN2/TAMP_
OUT3, WKUP4
F13 L2 U13 VSS S - - - -
J2 J5 L2 VBAT S - - - -

(1) TAMP_IN8/TAMP_
L4 N3 P5 PI0 I/O FT SPDIFRX_IN0
OUT1
PC15- (1)
K2 M2 L3 I/O FT - OSC32_OUT
OSC32_OUT
F15 N2 U16 VSS S - - - -
PC14- (1)
K1 M1 M2 I/O FT - OSC32_IN
OSC32_IN
G7 E3 V16 VSS S - - - -
H9 K6 N15 VDDCORE S - - - -
M10 M4 N9 VDD S - - - -
G8 E6 W16 VSS S - - - -
USART2_RX,
ETH2_MII_RXD0/ETH2_
L2 P3 N2 PF4 I/O FT_h - -
RGMII_RXD0/ETH2_RMII_
RXD0, FMC_A4
MCO1, SAI2_MCLK_A,
TIM8_BKIN2, I2C4_SDA,
SPI5_MISO, SAI2_CK1,
USART1_CK,
M2 J8 P2 PA8 I/O FT_fh - -
SPI2_MOSI/I2S2_SDO,
OTG_HS_SOF,
ETH2_MII_RXD3/ETH2_
RGMII_RXD3, FMC_A21
TRACECLK, TIM2_ETR,
I2C4_SCL, SPI5_MOSI,
SAI1_FS_B,
USART6_RTS/USART6_DE,
L1 T1 N1 PE2 I/O FT_fh - -
SPDIFRX_IN1,
ETH2_MII_RXD1/ETH2_
RGMII_RXD1/ETH2_RMII_
RXD1, FMC_A23

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STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

TIM17_CH1,
UART7_TX(boot),
UART4_CTS,
M1 J7 P3 PF7 I/O FT_vh - ETH1_RGMII_CLK125, -
ETH2_MII_TXD0/ETH2_
RGMII_TXD0/ETH2_RMII_
TXD0, FMC_A18
SAI2_D3, I2S2_MCK,
USART3_TX, UART4_TX,
M3 R1 R2 PG11 I/O FT_vh - ETH2_MII_TXD1/ETH2_ -
RGMII_TXD1/ETH2_RMII_
TXD1, FMC_A24
TIM12_CH1, USART2_CK,
I2C5_SDA,
SPI2_SCK/I2S2_CK,
QUADSPI_BK1_IO2,
L3 J6 N3 PH6 I/O FT_fh - ETH1_PHY_INTN, -
ETH1_MII_RX_ER,
ETH2_MII_RXD2/ETH2_
RGMII_RXD2,
QUADSPI_BK1_NCS
LPTIM1_ETR, TIM4_ETR,
SAI2_FS_A, I2C2_SMBA,
SPI2_MISO/I2S2_SDI,
N2 P4 R1 PG1 I/O FT_vh - -
SAI2_D2, FDCAN2_TX,
ETH2_MII_TXD2/ETH2_
RGMII_TXD2, FMC_NBL0
M11 - N12 VDD S - - - -
MCO2, TIM1_BKIN2,
SAI2_SCK_B, TIM15_CH2,
I2C3_SMBA, SAI1_SCK_B,
N1 R2 T2 PE6 I/O FT_vh - -
UART4_RTS/UART4_DE,
ETH2_MII_TXD3/ETH2_
RGMII_TXD3, FMC_A22
P1 P1 T3 PH0-OSC_IN I/O FT - - OSC_IN
G9 U1 N11 VSS S - - - -
P2 P2 U2 PH1-OSC_OUT I/O FT - - OSC_OUT
I2C3_SCL, SPI5_MOSI,
QUADSPI_BK2_IO1,
R2 T2 R3 PH3 I/O FT_fh - ETH1_MII_COL, -
ETH2_MII_COL,
QUADSPI_BK1_IO0
M5 L5 U3 VSS_ANA S - - - -

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96
Pinout, pin description and alternate functions STM32MP133A/D

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

TIM8_BKIN2, I2C2_SDA,
SAI2_SD_B, FDCAN2_RX,
L5 U2 W1 PG3 I/O FT_fvh - -
ETH2_RGMII_GTX_CLK,
ETH1_MDIO, FMC_A13
M4 L4 V2 VDD_ANA S - - - -
MCO2, TIM8_BKIN,
R1 U3 V3 PG2 I/O FT - -
SAI2_MCLK_B, ETH1_MDC
LPTIM1_IN1, SAI2_SCK_A,
SAI2_CK2,
USART6_RTS/USART6_DE,
USART3_CTS,
T1 L6 W2 PG12 I/O FT - ETH2_PHY_INTN, -
ETH1_PHY_INTN,
ETH2_MII_RX_DV/ETH2_
RGMII_RX_CTL/ETH2_RMII_
CRS_DV
F7 P6 R5 VDD S - - - -
G10 E8 T1 VSS S - - - -
MCO1, USART2_CK,
I2C2_SCL, I2C3_SDA,
SPDIFRX_IN0,
ETH1_MII_RX_CLK/ETH1_
N3 R3 V1 PD7 I/O FT_fh - -
RGMII_RX_CLK/ETH1_RMII_
REF_CLK,
QUADSPI_BK1_IO2,
FMC_NE1
DBTRGO, DBTRGI, MCO1,
P3 K7 T4 PA13 I/O FT - BOOTFAILN
UART4_TX
R3 R4 W3 PWR_CPU_ON O FT - - -
TIM1_CH4, I2C5_SCL,
SPI2_NSS/I2S2_WS,
USART1_CTS/USART1_NSS,
T2 N5 Y1 PA11 I/O FT_f - ETH2_MII_RXD1/ETH2_ -
RGMII_RXD1/ETH2_RMII_
RXD1, ETH1_CLK,
ETH2_CLK
TIM2_CH4, LPTIM1_OUT,
I2C5_SMBA, USART3_RX,
N5 M6 AA2 PB11 I/O FT_vh - ETH1_MII_TX_EN/ETH1_ -
RGMII_TX_CTL/ETH1_RMII_
TX_EN

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STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

PF14(JTCK/SW (2)
P4 U4 Y2 I/O FT JTCK/SWCLK -
CLK)
TIM2_CH1, TIM5_CH1,
ADC1_INP7,
TIM8_ETR, TIM15_BKIN,
ADC1_INN3,
U3 L7 Y3 PA0 I/O FT_a - SAI1_SD_B, UART5_TX,
ADC2_INP7,
ETH1_MII_CRS,
ADC2_INN3
ETH2_MII_CRS
ADC1_INP11,
TIM2_ETR, SAI1_MCLK_B,
ADC1_INN10,
N6 T3 W4 PF13 I/O FT_a - DFSDM1_DATIN3,
ADC2_INP11,
USART2_TX, UART5_RX
ADC2_INN10
G11 E10 P7 VSS S - - - -
F10 - - VDD S - - - -
TIM2_CH2, TIM5_CH2,
LPTIM3_OUT, TIM15_CH1N,
DFSDM1_CKIN0,
ADC1_INP3,
R4 K8 AA3 PA1 I/O FT_a - USART2_RTS/USART2_DE,
ADC2_INP3
ETH1_MII_RX_CLK/ETH1_
RGMII_RX_CLK/ETH1_RMII_
REF_CLK
TIM2_CH3, TIM5_CH3,
ADC1_INP1,
P5 R5 Y4 PA2 I/O FT_a - LPTIM4_OUT, TIM15_CH1,
ADC2_INP1
USART2_TX, ETH1_MDIO
TIM2_CH1/TIM2_ETR,
USART2_CK, TIM8_CH1N,
SAI1_D1,
U4 M7 Y5 PA5 I/O FT_a - ADC1_INP2
SPI1_NSS/I2S1_WS,
SAI1_SD_A, ETH1_PPS_OUT,
ETH2_PPS_OUT
ADC1_INP0,
SAI1_SCK_A, SAI1_CK2,
ADC1_INN1,
I2S1_MCK,
T3 T4 W5 PC0 I/O FT_ha - ADC2_INP0,
SPI1_MOSI/I2S1_SDO,
ADC2_INN1,
USART1_TX
TAMP_IN3
SPI1_NSS/I2S1_WS,
SAI1_SD_A, UART4_TX, ADC1_INP6,
T4 J9 AA4 PF12 I/O FT_vha -
ETH1_MII_TX_ER, ADC1_INN2
ETH1_RGMII_CLK125
R6 U6 W7 VREF+ S - - - -
P7 U5 U8 VDDA S - - - -
P6 T6 V8 VREF- S - - - -

DS13876 Rev 6 59/218

96
Pinout, pin description and alternate functions STM32MP133A/D

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

N7 T5 U9 VSSA S - - - -
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N, SAI2_D1,
SPI1_SCK/I2S1_CK,
USART1_CTS/USART1_NSS,
U2 R6 V6 PA7 I/O FT_ha - ADC1_INP16
TIM14_CH1,
ETH1_MII_RX_DV/ETH1_
RGMII_RX_CTL/ETH1_RMII_
CRS_DV, SAI2_SD_A
ADC1_INP8,
USART2_TX, SAI1_D2,
ADC1_INN4,
T6 L8 Y6 PF11 I/O FT_a - DFSDM1_CKIN3, SAI1_FS_A,
ADC2_INP8,
ETH2_MII_RX_ER
ADC2_INN4
TIM5_ETR, USART2_CK,
SAI1_SCK_B,
SPI1_NSS/I2S1_WS,
U5 N7 AA6 PA4 I/O FT_a - DFSDM1_CKIN1, ADC1_INP14
ETH1_PPS_OUT,
ETH2_PPS_OUT,
SAI1_SCK_A
TIM3_ETR, DFSDM1_CKIN2,
SAI1_D3, I2S1_MCK,
UART5_RTS/UART5_DE,
ADC1_INP4,
U6 K9 Y7 PC4 I/O FT_a - SPDIFRX_IN2,
ADC2_INP4
ETH1_MII_RXD0/ETH1_
RGMII_RXD0/ETH1_RMII_
RXD0, SAI2_D3
F11 P9 - VDD S - - - -
H7 E12 P15 VSS S - - - -
SAI1_CK1, DFSDM1_CKOUT,
SPI1_MISO/I2S1_SDI,
ADC1_INP13,
SPI1_SCK/I2S1_CK,
T5 P7 W6 PC3 I/O FT_ha - ADC1_INN12,
UART5_CTS, SAI1_MCLK_A,
TAMP_IN5
ETH1_MII_TX_CLK,
ETH2_MII_TX_CLK
J8 M9 - VDDCORE S - - - -
DFSDM1_DATIN2, SAI2_D4,
I2S_CKIN, SAI1_D4,
USART2_CTS/USART2_NSS,
ADC1_INP10,
R7 P8 AA7 PC5 I/O FT_a - SPDIFRX_IN3,
ADC2_INP10
ETH1_MII_RXD1/ETH1_
RGMII_RXD1/ETH1_RMII_
RXD1

60/218 DS13876 Rev 6

STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

DBTRGI, TIM1_CH2N,
TIM3_CH3, TIM8_CH2N,
ADC1_INP9,
USART1_RX, I2S1_MCK,
ADC1_INN5,
U7 M8 W8 PB0 I/O FT_a - SAI2_FS_A, USART1_CK,
ADC2_INP9,
UART4_CTS, SAI2_D2,
ADC2_INN5
ETH1_MII_RXD2/ETH1_
RGMII_RXD2
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT, TIM15_CH2,
ADC1_INP12,
SPI1_MOSI/I2S1_SDO,
N8 T7 W9 PA3 I/O FT_ha - ADC1_INN11,
SAI1_FS_B, USART2_RX,
PVD_IN, WKUP6
ETH1_MII_COL,
ETH2_MII_COL
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
SPI1_SCK/I2S1_CK,
ADC1_INP5,
T7 N8 Y8 PB1 I/O FT_ha - DFSDM1_DATIN1,
ADC2_INP5
UART4_RX,
ETH1_MII_RXD3/ETH1_
RGMII_RXD3
DFSDM1_DATIN0, SAI1_D3,
ETH1_MII_RX_DV/ETH1_
U8 R7 Y9 PC1 I/O FT_vha - ADC2_INP2
RMII_CRS_DV,
ETH1_RGMII_GTX_CLK
H10 - R10 VDDCORE S - - - -
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SAI2_CK2,
ADC1_INP17,
SPI1_MISO/I2S1_SDI,
T8 R8 U10 PA6 I/O FT_ha - ADC1_INN16,
USART1_CK,
TAMP_IN2
UART4_RTS/UART4_DE,
TIM13_CH1, SAI2_SCK_A
H11 E14 R8 VSS S - - - -
G6 P10 - VDD S - - - -
J10 - R13 VDDCORE S - - - -
LPTIM1_OUT,
USART6_CTS/USART6_NSS,
ADC2_INP6,
P8 R9 AA9 PG13 I/O FT_vha - ETH1_MII_TXD0/ETH1_
ADC2_INN2
RGMII_TXD0/ETH1_RMII_
TXD0
SAI2_SCK_B, TIM8_CH3,
TIM15_CH1, UART4_RX,
T9 L9 W10 PE5 I/O FT_vh - -
ETH1_MII_TXD3/ETH1_
RGMII_TXD3, FMC_NE1

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96
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Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

LPTIM1_ETR, SAI2_D1,
USART6_TX, SAI2_SD_A,
P9 T8 Y10 PG14 I/O FT_vh - ETH1_MII_TXD1/ETH1_ -
RGMII_TXD1/ETH1_RMII_TX
D1
J13 - U12 VDDCORE S - - - -
SPI5_NSS,
SPI1_NSS/I2S1_WS,
SAI2_MCLK_A,
U9 U8 AA10 PC2 I/O FT_vha - USART1_RTS/USART1_DE, ADC1_INP15
SAI2_CK1,
ETH1_MII_TXD2/ETH1_
RGMII_TXD2
H14 E16 R11 VSS S - - - -
R9 J10 W11 VDD S - - - -
K8 - G11 VDDCORE S - - - -
N9 R10 V11 NJTRST I FTU - - -
U10 K10 Y11 NRST I/O RST - - -
T10 U7 AA12 PDR_ON I FT - - -
U12 M10 W12 USB_RREF A A - - -
VDD3V3_
P10 U11 W14 S - - - -
USBHS
USBH_HS_DP2
T11 T9 AA13 USB_DP2 A FT_u - -
(boot), OTG_HS_DP
USBH_HS_DM2
U11 U9 Y13 USB_DM2 A FT_u - -
(boot), OTG_HS_DM
N10 T11 Y14 VSS_USBHS S - - - -
PF15 (3)
R10 L10 Y12 I/O FT JTMS/SWDIO -
(JTMS/SWDIO)
DBTRGO, DBTRGI, MCO2,
T12 R11 W13 PA14 I/O FT - -
OTG_HS_SOF
PI6-BOOT2 (4)
R12 M11 Y15 I/O FT BOOT2 -
(BOOT2)
K6 - - VDD S - - - -
L6 - - VDD S - - - -
- - R7 VDD S - - - -

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STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

VDDA1V8_
R11 J11 W15 S - - - -
REG
J7 R12 R14 VSS S - - - -
VDDA1V1_
N11 U10 V14 S - - - -
REG
J9 T10 - VSS S - - - -
- - R9 VDD S - - - -
- - R12 VDD S - - - -
PI5-BOOT1 (4)
P12 N11 AA15 I/O FT BOOT1 -
(BOOT1)
PI4-BOOT0 (4)
U14 P11 Y17 I/O FT BOOT0 -
(BOOT0)
U13 U12 AA16 USB_DM1 A FT_u - - USBH_HS_DM1
T13 T12 Y16 USB_DP1 A FT_u - - USBH_HS_DP1
U15 J12 AA19 PA10 I/O FT_u - TIM1_CH3 OTG_HS_ID
U16 U13 AA20 PI7 I/O FT_u - - OTG_HS_VBUS
R13 L11 Y18 VDD_PLL2 S - - - -
P13 K11 AA18 VSS_PLL2 S - - - -
K9 F12 J11 VDDCORE S - - - -
BYPASS_REG
T14 H11 W17 I FT - - -
1V8
- F5 B12 VSS S - - - -
(3)
T15 T13 Y19 PH4(JTDI) I/O FT JTDI -
(3)
R14 L12 W18 PH5(JTDO) I/O FT JTDO -
N13 U14 V19 PWR_LP O FT - - -
P14 R13 U17 PWR_ON O FT - - PWR_ONLP
- F13 F17 VSS S - - - -
- P12 E12 VDD S - - - -
E12 K14 E15 VDDQ_DDR S - - - -
R15 R15 W19 DDR_DQ12 I/O DDR - - -
F12 M14 G15 VDDQ_DDR S - - - -
T16 U15 Y20 DDR_DQ15 I/O DDR - - -
- H5 A1 VSS S - - - -

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96
Pinout, pin description and alternate functions STM32MP133A/D

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

T17 T15 Y21 DDR_DQ14 I/O DDR - - -

- H13 A21 VSS S - - - -
P15 R16 W20 DDR_DQ11 I/O DDR - - -
G12 N13 G17 VDDQ_DDR S - - - -
N14 R14 W21 DDR_DQM1 O DDR - - -
H12 N15 K15 VDDQ_DDR S - - - -
R17 T16 V20 DDR_DQS1P I/O DDR - - -
- J16 AA1 VSS S - - - -
R16 T17 V21 DDR_DQS1N I/O DDR - - -
- K5 AA21 VSS S - - - -
- K13 G14 VSS S - - - -
M13 J13 T18 DDR_VREF A A - - -
- H6 J15 VDDCORE S - - - -
J12 P14 K17 VDDQ_DDR S - - - -
P16 T14 U19 DDR_DQ13 I/O DDR - - -
K12 - M15 VDDQ_DDR S - - - -
P17 R17 U20 DDR_DQ9 I/O DDR - - -
- M5 D16 VSS S - - - -
N15 U16 T19 DDR_DQ10 I/O DDR - - -
- M13 E5 VSS S - - - -
N16 P17 T20 DDR_DQ8 I/O DDR - - -
L12 - M17 VDDQ_DDR S - - - -
N17 P16 R20 DDR_ZQ A A - - -
M16 - P17 DDR_DTO1 O DDR - - -
M12 - R15 VDDQ_DDR S - - - -
M14 P15 R19 DDR_A4 O DDR - - -
L15 M16 P19 DDR_A8 O DDR - - -
M17 M15 R21 DDR_A6 O DDR - - -
- N6 E6 VSS S - - - -
L13 N17 P18 DDR_ATO A A - - -
- N9 E11 VSS S - - - -

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STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

L14 - - DDR_DTO0 O DDR - - -

N12 - R17 VDDQ_DDR S - - - -
L16 M17 P20 DDR_BA1 O DDR - - -
- - U15 VDDQ_DDR S - - - -
L17 L17 N19 DDR_A14 O DDR - - -
- N10 E16 VSS S - - - -
K13 L16 N17 DDR_A11 O DDR - - -
- N12 F5 VSS S - - - -
L8 N14 K11 VSS S - - - -
K14 L13 N20 DDR_CKE O DDR - - -
- H12 L7 VDDCORE S - - - -
K15 L15 N21 DDR_A1 O DDR - - -
K17 L14 M19 DDR_A12 O DDR - - -
K16 K15 M21 DDR_A15 O DDR - - -
- N16 F18 VSS S - - - -
J16 K16 M20 DDR_CLKP O DDR - - -
- P5 F21 VSS S - - - -
J17 K17 L20 DDR_CLKN O DDR - - -
- H14 - VDDQ_DDR S - - - -
J14 J15 L18 DDR_A10 O DDR - - -
- P13 G8 VSS S - - - -
H17 J14 K20 DDR_RASN O DDR - - -
J15 J17 L19 DDR_CASN O DDR - - -
H13 H17 K19 DDR_WEN O DDR - - -
- U17 G12 VSS S - - - -
P11 - L12 VSS S - - - -
- - H7 VSS S - - - -
- K12 L9 VDDCORE S - - - -
H16 H16 J20 DDR_CSN O DDR - - -
G17 H15 J19 DDR_BA0 O DDR - - -
J11 - H15 VSS S - - - -

DS13876 Rev 6 65/218

96
Pinout, pin description and alternate functions STM32MP133A/D

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

H15 G17 J21 DDR_ODT O DDR - - -

K3 - J10 VSS S - - - -
G16 G16 H20 DDR_A0 O DDR - - -
G15 G15 H19 DDR_A3 O DDR - - -
G14 F15 J17 DDR_A7 O DDR - - -
- D14 - VDDQ_DDR S - - - -
F17 G13 G20 DDR_A2 O DDR - - -
- E13 - VDDQ_DDR S - - - -
E16 F16 F20 DDR_A5 O DDR - - -
G13 G14 H18 DDR_BA2 O DDR - - -
F16 F17 G21 DDR_A9 O DDR - - -
K7 - J12 VSS S - - - -
F14 E17 G19 DDR_A13 O DDR - - -
K11 - K9 VSS S - - - -
E17 D15 H17 DDR_RESETN O DDR - - -
- E15 - VDDQ_DDR S - - - -
E15 D16 F19 DDR_DQ7 I/O DDR - - -
- F14 - VDDQ_DDR S - - - -
E14 D17 E20 DDR_DQ6 I/O DDR - - -
L7 - K10 VSS S - - - -
R5 - L15 VSS S - - - -
L9 - K12 VSS S - - - -
- M12 L13 VDDCORE S - - - -
D17 C16 E19 DDR_DQ3 I/O DDR - - -
D16 C17 D20 DDR_DQ5 I/O DDR - - -
C17 B17 C20 DDR_DQS0P I/O DDR - - -
L10 - K13 VSS S - - - -
C16 B16 C21 DDR_DQS0N I/O DDR - - -
L11 - K21 VSS S - - - -
D15 C15 D21 DDR_DQM0 O DDR - - -
E13 C14 D19 DDR_DQ2 I/O DDR - - -

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STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

C15 B15 B20 DDR_DQ1 I/O DDR - - -

M15 - L5 VSS S - - - -
B17 A16 B21 DDR_DQ0 I/O DDR - - -
N4 - L10 VSS S - - - -
B16 A15 B19 DDR_DQ4 I/O DDR - - -
TRACED1, TIM3_CH4,
(5) TIM8_CH4, USART3_RTS,
A16 G12 A20 PC9 I/O FT_h -
UART5_CTS, FDCAN1_TX,
SDMMC1_D1
C12 A14 E17 VDDSD1 S - - - -
R8 - L17 VSS S - - - -
TRACED0, TIM3_CH3,
TIM8_CH3,
SPI3_MISO/I2S3_SDI,
D14 C13 C18 PC8 I/O FT_h (5)
USART6_CK, USART3_CTS, -
SAI2_FS_B,
UART5_RTS/UART5_DE,
SDMMC1_D0(boot)
TRACED4, TIM3_ETR,
I2C1_SMBA,
(5)
A15 G11 C19 PD2 I/O FT_h SPI3_NSS/I2S3_WS, -
SAI2_D1, USART3_RX,
SDMMC1_CMD(boot)
TRACECLK, UART7_TX,
(5)
B15 B13 A19 PC12 I/O FT_h SAI2_SD_B, -
SDMMC1_CK(boot)
TRACED2, I2C1_SCL,
(5) SPI3_SCK/I2S3_CK,
B14 F11 A18 PC10 I/O FT_fh -
USART3_TX, SAI2_MCLK_B,
SDMMC1_D2
TRACED3, I2C1_SDA,
(5) SPI3_MOSI/I2S3_SDO,
C14 C12 B18 PC11 I/O FT_fh -
USART3_CK, UART5_RX,
SAI2_SCK_B, SDMMC1_D3
- - N10 VDDCORE S - - - -
TRACED3, TIM17_BKIN,
(6) TIM5_CH4, SAI2_D1,
A14 H10 C17 PG6 I/O FT_h -
USART1_RX, SAI2_SD_A,
SDMMC2_CMD(boot), HDP3

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96
Pinout, pin description and alternate functions STM32MP133A/D

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

TRACED11, SAI2_D4,
TIM15_BKIN,
(6) SPI4_MISO/I2S4_SDI,
D13 B12 B17 PE3 I/O FT_h -
USART3_RTS/USART3_DE,
FDCAN1_RX,
SDMMC2_CK(boot)
TRACED14, TIM16_BKIN,
TIM3_CH1, SAI2_CK2,
(6)
B13 E11 C16 PB4 I/O FT_h SPI4_SCK/I2S4_CK, -
USART3_CK, SDMMC2_D3,
SAI2_SCK_A
TRACED0, TIM1_CH2N,
TIM12_CH1, TIM8_CH2N,
(6)
A13 A12 B16 PB14 I/O FT_h USART1_TX, -
SDMMC2_D0(boot),
SDMMC1_D4
- - N13 VDDCORE S - - - -
D11 A13 C15 VDDSD2 S - - - -
U1 - M1 VSS S - - - -
TRACED2, TIM2_CH2,
SAI2_CK1,
(6) SPI4_NSS/I2S4_WS,
C11 B11 C14 PB3 I/O FT_h -
SDMMC1_D123DIR,
SDMMC2_D2, SAI2_MCLK_A,
UART7_RX
RTC_REFIN, TIM1_CH3N,
TIM12_CH2, TIM8_CH3N,
SAI2_D2,
(6) SPI4_MOSI/I2S4_SDO,
B12 D11 B15 PB15 I/O FT_h -
DFSDM1_CKIN2,
UART7_CTS,
SDMMC1_CKIN,
SDMMC2_D1, SAI2_FS_A
U17 - M7 VSS S - - - -
TRACED13,
DFSDM1_CKOUT,
C13 A11 A16 PF0 I/O FT_h - -
USART3_CK, SDMMC2_D4,
FMC_A0

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STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

TRACED0, TIM5_CH1,
SAI2_D3, DFSDM1_DATIN2,
I2S3_MCK,
E11 C11 E14 PH10 I/O FT_h - -
SPI2_MOSI/I2S2_SDO,
USART3_CTS/USART3_NSS,
SDMMC1_D4, HDP0
TRACED3, TIM4_CH4,
I2C4_SDA, FDCAN1_TX,
A12 C10 A15 PB9 I/O FT_fh - -
SDMMC2_D5, UART5_TX,
SDMMC1_CDIR(boot)
- D10 G9 VDD S - - - -
- - M9 VSS S - - - -
TRACECLK, TIM1_CH1N,
LPTIM2_OUT,
SPI2_NSS/I2S2_WS,
E10 B10 D14 PB13 I/O FT_fh - I2C4_SCL, -
SDMMC1_D123DIR,
FDCAN2_TX,
UART5_TX(boot)
TIM2_CH3, LPTIM2_IN1,
I2C5_SMBA,
D10 G10 E13 PB10 I/O FT_h - SPI4_NSS/I2S4_WS, -
SPI2_SCK/I2S2_CK,
USART3_TX(boot)
TRACED2, TIM3_CH1,
TIM8_CH1, DFSDM1_DATIN0,
I2S3_MCK,
USART6_TX(boot),
B11 A10 B14 PC6 I/O FT_h - -
SDMMC1_D6,
SDMMC2_D0DIR,
SDMMC2_D6, FMC_A19,
HDP2
TRACED4, TIM17_BKIN,
TIM3_CH2,
SPI2_MISO/I2S2_SDI,
C10 F9 B13 PB5 I/O FT_h - -
I2C4_SMBA, SDMMC1_CKIN,
FDCAN2_RX,
UART5_RX(boot)

DS13876 Rev 6 69/218

96
Pinout, pin description and alternate functions STM32MP133A/D

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

TRACED4, TIM3_CH2,
TIM8_CH2, I2S2_MCK,
USART6_RX(boot),
A11 A9 C13 PC7 I/O FT_h - USART3_CTS, -
SDMMC2_CDIR,
SDMMC2_D7, SDMMC1_D7,
HDP4
LPTIM2_IN2, I2C5_SDA,
B10 B9 A13 PF3 I/O FT_fh - SPI4_MISO/I2S4_SDI, -
SPI3_NSS/I2S3_WS, FMC_A3
TIM1_CH4, TIM12_CH2,
A9 D9 C12 PH9 I/O FT_h - SPI4_SCK/I2S4_CK, -
FMC_A20
- C6 G13 VDD S - - - -
- - M10 VSS S - - - -
TRACED7, I2C2_SDA,
B9 A8 B11 PF1 I/O FT_fh - SPI3_MOSI/I2S3_SDO, -
FMC_A1, HDP7
TRACED15, USART2_CK,
TIM8_CH1N, I2C5_SCL,
A10 E9 A12 PH13 I/O FT_fh - -
SPI3_SCK/I2S3_CK,
UART4_TX
TRACED8, TIM1_ETR,
C9 C8 A10 PG7 I/O FT_h - SPI3_MISO/I2S3_SDI, -
UART7_CTS, SDMMC2_CKIN
TRACED1, TIM1_BKIN2,
DFSDM1_CKIN3,
A8 C9 B10 PG4 I/O FT_h - USART3_RX, -
SDMMC2_D123DIR,
FMC_A14, HDP1
TRACED10, I2C2_SMBA,
DFSDM1_DATIN1,
D9 A7 C11 PB12 I/O FT_h - UART7_RTS/UART7_DE, -
USART3_RX(boot),
UART5_RX, SDMMC1_D5
TRACED1, I2C2_SCL,
DFSDM1_CKIN1,
E9 B7 D11 PF2 I/O FT_fh - USART6_CK, -
SDMMC2_D0DIR,
SDMMC1_D0DIR, FMC_A2
- - M11 VSS S - - - -
- - J7 VDD S - - - -

70/218 DS13876 Rev 6

STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

J6 F4 G10 VDDCPU S - - - -
TIM1_CH2N, UART7_RX,
B8 C7 C10 PE10 I/O FT - FDCAN1_TX, -
FMC_D7(boot)/FMC_AD7
- - M12 VSS S - - - -
TIM2_ETR, TIM1_BKIN,
USART2_CTS/USART2_NSS,
D8 A6 A9 PE15 I/O FT_fh - I2C4_SCL, -
FMC_D12(boot)/FMC_AD12,
HDP7
- H4 - VDDCPU S - - - -
DFSDM1_DATIN2, I2C3_SDA,
B7 B6 B8 PH14 I/O FT_fh - -
UART4_RX
TIM1_CH1N,
DFSDM1_CKIN2, I2C1_SDA,
A7 F8 B9 PE8 I/O FT_f - -
UART7_TX,
FMC_D5(boot)/FMC_AD5
USART2_RX, TIM4_CH4,
DFSDM1_DATIN2,
C7 A5 E9 PD15 I/O FT_h - -
QUADSPI_BK1_IO3,
FMC_D1(boot)/FMC_AD1
TRACECLK,
DFSDM1_DATIN3,
E8 B5 C9 PD9 I/O FT_h - -
SDMMC2_CDIR,
FMC_D14(boot)/FMC_AD14
- - M13 VSS S - - - -
D7 A4 A7 PG0 I/O FT_h - FDCAN2_TX, FMC_A10 -
QUADSPI_BK1_IO0,
A6 B4 C8 PD5 I/O FT_h - -
FMC_NWE(boot)
- - J9 VDD S - - - -
TIM1_CH1,
QUADSPI_BK1_IO1,
B6 A3 B7 PE9 I/O FT_h - -
FMC_D6(boot)/FMC_AD6,
HDP3
TIM1_ETR, LPTIM2_IN1,
A5 C4 D8 PE7 I/O FT_h - UART5_TX, -
FMC_D4(boot)/FMC_AD4
UART8_RX(boot),
D6 B3 B6 PE0 I/O FT_h - -
FDCAN2_RX, FMC_A11

DS13876 Rev 6 71/218

96
Pinout, pin description and alternate functions STM32MP133A/D

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

LPTIM1_IN1, TIM4_CH1,
I2C1_SCL,
C6 D7 A6 PD12 I/O FT_f - -
USART3_RTS/USART3_DE,
FMC_ALE(boot)/FMC_A17
USART2_RTS/USART2_DE,
SPI3_MISO/I2S3_SDI,
E7 A2 C7 PD4 I/O FT_h - DFSDM1_CKIN0, -
QUADSPI_CLK,
FMC_NOE(boot)
USART2_TX, I2S4_WS,
C5 B2 B5 PD8 I/O FT - USART3_TX, -
UART4_RX(boot)
LPTIM1_IN2,
B5 C3 E8 PE1 I/O FT_h - -
UART8_TX(boot), FMC_NBL1
TIM17_CH1N, TIM4_CH2,
A4 D5 C6 PB7 I/O FT_f - I2S4_CK, I2C4_SDA, -
FMC_NCE2, FMC_NL
TIM1_CH3N,
SPI4_SCK/I2S4_CK,
B4 B1 A4 PE12 I/O FT_h - UART8_RTS/UART8_DE, -
FMC_D9(boot)/FMC_AD9,
HDP4
- - K7 VDDCPU S - - - -
I2C5_SCL,
SPI4_MOSI/I2S4_SDO,
D5 C2 C5 PD1 I/O FT_fh - UART4_TX, -
QUADSPI_BK1_NCS,
FMC_D3(boot)/FMC_AD3
- - K5 VDDCPU S - - - -
RTC_REFIN, I2C5_SMBA,
SPI4_NSS/I2S4_WS,
A3 D3 D6 PD10 I/O FT_h - -
USART3_CK,
FMC_D15(boot)/FMC_AD15
TRACED5, TIM2_CH1,
I2S4_MCK,
E6 E7 B4 PA15 I/O FT_h - -
UART4_RTS/UART4_DE,
UART4_RX, FMC_A9, HDP5
TIM1_CH3, I2C5_SDA,
C4 C1 A3 PE13 I/O FT_fh - SPI4_MISO/I2S4_SDI, -
FMC_D10(boot)/FMC_AD10

72/218 DS13876 Rev 6

STM32MP133A/D Pinout, pin description and alternate functions

Table 7. STM32MP133A/D ball definitions (continued)

Pin Number Ball functions

I/O structure
Pin type
Pin name
LFBGA289

TFBGA289

TFBGA320

Notes
(function after
reset) Alternate functions Additional functions

TIM4_CH3, I2C3_SDA,
B3 F7 C4 PD14 I/O FT_fh - USART1_RX, UART8_CTS, -
FMC_D0(boot)/FMC_AD0
- D12 - VDD S - - - -
1. Power supply is VBAT.
2. During reset and when configured as alternate function for JTAG/SWD an internal pull-down is present.
3. During reset and when configured as alternate function for JTAG/SWD an internal pull-up is present.
4. During reset an internal pull-down is present.
5. Power supply is VDDSD1.
6. Power supply is VDDSD2.

DS13876 Rev 6 73/218

96
 Table 8. Alternate function AF0 to AF7
74/218

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

LPTIM1/RTC/ DFSDM1/ DFSDM1/ I2C1/3/SPI1/ DFSDM1/I2C4/

Port SAI1/2/SYS/
SPI5/SYS/ LPTIM2/3/4/5/ I2C1/2/3/4/5/ I2S1/SPI2/I2S2/ SAI1/2/SPI1/I2 UART4/7/
RTC/SYS TIM1/3/4/5/12/
TIM1/2/16/17/ SAI2/TIM8/ LPTIM2/SAI1/2/ SPI3/I2S3/SPI4/ S1/SPI2/I2S2/S USART1/2/3/6
USART2
USART2 USART2 TIM15/USART1 I2S4/SPI5 PI3/I2S3/SPI5

PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR TIM15_BKIN - SAI1_SD_B -

DFSDM1_ USART2_RTS/
PA1 - TIM2_CH2 TIM5_CH2 LPTIM3_OUT TIM15_CH1N -
CKIN0 USART2_DE
PA2 - TIM2_CH3 TIM5_CH3 LPTIM4_OUT TIM15_CH1 - - USART2_TX
SPI1_MOSI/
PA3 - TIM2_CH4 TIM5_CH4 LPTIM5_OUT TIM15_CH2 SAI1_FS_B USART2_RX
I2S1_SDO
SPI1_NSS/ DFSDM1_
PA4 - - TIM5_ETR USART2_CK SAI1_SCK_B -
I2S1_WS CKIN1
DS13876 Rev 6

TIM2_CH1/ SPI1_NSS/
PA5 - USART2_CK TIM8_CH1N SAI1_D1 SAI1_SD_A -
TIM2_ETR I2S1_WS
SPI1_MISO/
PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN SAI2_CK2 - USART1_CK
Port A I2S1_SDI
SPI1_SCK/ USART1_CTS/
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N SAI2_D1 -
I2S1_CK USART1_NSS
PA8 MCO1 - SAI2_MCLK_A TIM8_BKIN2 I2C4_SDA SPI5_MISO SAI2_CK1 USART1_CK
DFSDM1_
PA9 - TIM1_CH2 - - I2C3_SMBA - USART1_TX
DATIN0
PA10 - TIM1_CH3 - - - - - -
SPI2_NSS/ USART1_CTS/
PA11 - TIM1_CH4 - - I2C5_SCL -
I2S2_WS USART1_NSS

STM32MP133A/D
USART1_RTS/
PA12 - TIM1_ETR SAI2_MCLK_A - - - -
USART1_DE
PA13 DBTRGO DBTRGI MCO1 - - - - -
 Table 8. Alternate function AF0 to AF7 (continued)

STM32MP133A/D
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

LPTIM1/RTC/ DFSDM1/ DFSDM1/ I2C1/3/SPI1/ DFSDM1/I2C4/

Port SAI1/2/SYS/
SPI5/SYS/ LPTIM2/3/4/5/ I2C1/2/3/4/5/ I2S1/SPI2/I2S2/ SAI1/2/SPI1/I2 UART4/7/
RTC/SYS TIM1/3/4/5/12/
TIM1/2/16/17/ SAI2/TIM8/ LPTIM2/SAI1/2/ SPI3/I2S3/SPI4/ S1/SPI2/I2S2/S USART1/2/3/6
USART2
USART2 USART2 TIM15/USART1 I2S4/SPI5 PI3/I2S3/SPI5

PA14 DBTRGO DBTRGI MCO2 - - - - -

Port A UART4_RTS/
PA15 TRACED5 TIM2_CH1 - - - I2S4_MCK -
UART4_DE
PB0 DBTRGI TIM1_CH2N TIM3_CH3 TIM8_CH2N USART1_RX I2S1_MCK SAI2_FS_A USART1_CK
SPI1_SCK/ DFSDM1_
PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - UART4_RX
I2S1_CK DATIN1
PB2 - RTC_OUT2 SAI1_D1 - - I2S_CKIN SAI1_SD_A -
SPI4_NSS/
DS13876 Rev 6

PB3 TRACED2 TIM2_CH2 - - SAI2_CK1 - -

I2S4_WS
SPI4_SCK/
PB4 TRACED14 TIM16_BKIN TIM3_CH1 - SAI2_CK2 - USART3_CK
I2S4_CK

Pinout, pin description and alternate functions

SPI2_MISO/
PB5 TRACED4 TIM17_BKIN TIM3_CH2 - - I2C4_SMBA -
I2S2_SDI
Port B
PB6 TRACED6 TIM16_CH1N TIM4_CH1 TIM8_CH1 USART1_TX - SAI1_CK2 -
PB7 - TIM17_CH1N TIM4_CH2 - - I2S4_CK I2C4_SDA -
DFSDM1_
PB8 - TIM16_CH1 TIM4_CH3 - I2C1_SCL I2C3_SCL -
DATIN1
PB9 TRACED3 - TIM4_CH4 - - - I2C4_SDA -
SPI4_NSS/ SPI2_SCK/
PB10 - TIM2_CH3 - LPTIM2_IN1 I2C5_SMBA USART3_TX
I2S4_WS I2S2_CK
PB11 - TIM2_CH4 - LPTIM1_OUT I2C5_SMBA - - USART3_RX
DFSDM1_ UART7_RTS/
PB12 TRACED10 - - - I2C2_SMBA -
DATIN1 UART7_DE
75/218
 Table 8. Alternate function AF0 to AF7 (continued)
76/218

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

LPTIM1/RTC/ DFSDM1/ DFSDM1/ I2C1/3/SPI1/ DFSDM1/I2C4/

Port SAI1/2/SYS/
SPI5/SYS/ LPTIM2/3/4/5/ I2C1/2/3/4/5/ I2S1/SPI2/I2S2/ SAI1/2/SPI1/I2 UART4/7/
RTC/SYS TIM1/3/4/5/12/
TIM1/2/16/17/ SAI2/TIM8/ LPTIM2/SAI1/2/ SPI3/I2S3/SPI4/ S1/SPI2/I2S2/S USART1/2/3/6
USART2
USART2 USART2 TIM15/USART1 I2S4/SPI5 PI3/I2S3/SPI5

SPI2_NSS/
PB13 TRACECLK TIM1_CH1N - - LPTIM2_OUT I2C4_SCL -
I2S2_WS
Port B PB14 TRACED0 TIM1_CH2N TIM12_CH1 TIM8_CH2N USART1_TX - - -
SPI4_MOSI/ DFSDM1_
PB15 RTC_REFIN TIM1_CH3N TIM12_CH2 TIM8_CH3N SAI2_D2 UART7_CTS
I2S4_SDO CKIN2
SPI1_MOSI/
PC0 - - SAI1_SCK_A - SAI1_CK2 I2S1_MCK USART1_TX
I2S1_SDO
DFSDM1_
PC1 - - - - - SAI1_D3 -
DS13876 Rev 6

DATIN0
SPI1_NSS/ USART1_RTS/
PC2 - SPI5_NSS - - - SAI2_MCLK_A
I2S1_WS USART1_DE
DFSDM1_ SPI1_MISO/ SPI1_SCK/
PC3 - - SAI1_CK1 - -
CKOUT I2S1_SDI I2S1_CK
DFSDM1_
Port C PC4 - - TIM3_ETR SAI1_D3 I2S1_MCK - -
CKIN2
DFSDM1_ USART2_CTS/
PC5 - - - SAI2_D4 I2S_CKIN SAI1_D4
DATIN2 USART2_NSS
DFSDM1_
PC6 TRACED2 - TIM3_CH1 TIM8_CH1 I2S3_MCK - USART6_TX
DATIN0
PC7 TRACED4 - TIM3_CH2 TIM8_CH2 - - I2S2_MCK USART6_RX
SPI3_MISO/

STM32MP133A/D
PC8 TRACED0 - TIM3_CH3 TIM8_CH3 - - USART6_CK
I2S3_SDI
PC9 TRACED1 - TIM3_CH4 TIM8_CH4 - - - USART3_RTS
 Table 8. Alternate function AF0 to AF7 (continued)

STM32MP133A/D
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

LPTIM1/RTC/ DFSDM1/ DFSDM1/ I2C1/3/SPI1/ DFSDM1/I2C4/

Port SAI1/2/SYS/
SPI5/SYS/ LPTIM2/3/4/5/ I2C1/2/3/4/5/ I2S1/SPI2/I2S2/ SAI1/2/SPI1/I2 UART4/7/
RTC/SYS TIM1/3/4/5/12/
TIM1/2/16/17/ SAI2/TIM8/ LPTIM2/SAI1/2/ SPI3/I2S3/SPI4/ S1/SPI2/I2S2/S USART1/2/3/6
USART2
USART2 USART2 TIM15/USART1 I2S4/SPI5 PI3/I2S3/SPI5

SPI3_SCK/
PC10 TRACED2 - - - - I2C1_SCL USART3_TX
I2S3_CK
SPI3_MOSI/
PC11 TRACED3 - - - I2C1_SDA - USART3_CK
I2S3_SDO
Port C PC12 TRACECLK - - - - - - -
PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -
DS13876 Rev 6

PD0 - - SAI1_MCLK_A - - - SAI1_CK1 -

SPI4_MOSI/
PD1 - - - - I2C5_SCL - -

Pinout, pin description and alternate functions

I2S4_SDO
SPI3_NSS/
PD2 TRACED4 - TIM3_ETR - I2C1_SMBA SAI2_D1 USART3_RX
I2S3_WS
USART2_CTS/ DFSDM1_
PD3 - - TIM2_CH1 I2C1_SDA SAI1_D3 -
USART2_NSS CKOUT

Port D USART2_RTS/ SPI3_MISO/ DFSDM1_

PD4 - - - - -
USART2_DE I2S3_SDI CKIN0
PD5 - - - - - - - -
PD6 - TIM16_CH1N SAI1_D1 - - - SAI1_SD_A -
PD7 MCO1 - - USART2_CK I2C2_SCL I2C3_SDA - -
PD8 - - - USART2_TX - I2S4_WS - USART3_TX
DFSDM1_
PD9 TRACECLK - - - - - -
DATIN3
77/218
 Table 8. Alternate function AF0 to AF7 (continued)
78/218

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

LPTIM1/RTC/ DFSDM1/ DFSDM1/ I2C1/3/SPI1/ DFSDM1/I2C4/

Port SAI1/2/SYS/
SPI5/SYS/ LPTIM2/3/4/5/ I2C1/2/3/4/5/ I2S1/SPI2/I2S2/ SAI1/2/SPI1/I2 UART4/7/
RTC/SYS TIM1/3/4/5/12/
TIM1/2/16/17/ SAI2/TIM8/ LPTIM2/SAI1/2/ SPI3/I2S3/SPI4/ S1/SPI2/I2S2/S USART1/2/3/6
USART2
USART2 USART2 TIM15/USART1 I2S4/SPI5 PI3/I2S3/SPI5

SPI4_NSS/
PD10 RTC_REFIN - - - I2C5_SMBA - USART3_CK
I2S4_WS
USART3_CTS/
PD11 - - - LPTIM2_IN2 I2C4_SMBA - -
USART3_NSS
USART3_RTS/
Port D PD12 - LPTIM1_IN1 TIM4_CH1 - - I2C1_SCL -
USART3_DE
PD13 - LPTIM2_ETR TIM4_CH2 TIM8_CH2 SAI1_CK1 - SAI1_MCLK_A USART1_RX
PD14 - - TIM4_CH3 - I2C3_SDA - - USART1_RX
DS13876 Rev 6

DFSDM1_
PD15 - USART2_RX TIM4_CH4 - - - -
DATIN2
PE0 - - - - - - - -
PE1 - LPTIM1_IN2 - - - - - -
USART6_RTS/
PE2 TRACECLK TIM2_ETR - - I2C4_SCL SPI5_MOSI SAI1_FS_B
USART6_DE
SPI4_MISO/
PE3 TRACED11 - SAI2_D4 - TIM15_BKIN - -
I2S4_SDI
Port E DFSDM1_ UART7_RTS/U
PE4 - SPI5_MISO SAI1_D2 TIM15_CH1N I2S_CKIN SAI1_FS_A
DATIN3 ART7_DE
PE5 - - SAI2_SCK_B TIM8_CH3 TIM15_CH1 - - -
PE6 MCO2 TIM1_BKIN2 SAI2_SCK_B - TIM15_CH2 I2C3_SMBA SAI1_SCK_B -

STM32MP133A/D
PE7 - TIM1_ETR - - LPTIM2_IN1 - - -
DFSDM1_
PE8 - TIM1_CH1N - - I2C1_SDA - UART7_TX
CKIN2
 Table 8. Alternate function AF0 to AF7 (continued)

STM32MP133A/D
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

LPTIM1/RTC/ DFSDM1/ DFSDM1/ I2C1/3/SPI1/ DFSDM1/I2C4/

Port SAI1/2/SYS/
SPI5/SYS/ LPTIM2/3/4/5/ I2C1/2/3/4/5/ I2S1/SPI2/I2S2/ SAI1/2/SPI1/I2 UART4/7/
RTC/SYS TIM1/3/4/5/12/
TIM1/2/16/17/ SAI2/TIM8/ LPTIM2/SAI1/2/ SPI3/I2S3/SPI4/ S1/SPI2/I2S2/S USART1/2/3/6
USART2
USART2 USART2 TIM15/USART1 I2S4/SPI5 PI3/I2S3/SPI5

PE9 - TIM1_CH1 - - - - - -
PE10 - TIM1_CH2N - - - - - UART7_RX
USART2_CTS/ SPI4_MOSI/
PE11 - TIM1_CH2 - SAI1_D2 SAI1_FS_A USART6_CK
USART2_NSS I2S4_SDO
SPI4_SCK/
PE12 - TIM1_CH3N - - - - -
Port E I2S4_CK
SPI4_MISO/
PE13 - TIM1_CH3 - - I2C5_SDA - -
I2S4_SDI
DS13876 Rev 6

PE14 - TIM1_BKIN - - SAI1_D4 - - -

USART2_CTS/
PE15 - TIM2_ETR TIM1_BKIN - - I2C4_SCL -
USART2_NSS

Pinout, pin description and alternate functions

DFSDM1_
PF0 TRACED13 - - - - - USART3_CK
CKOUT
SPI3_MOSI/
PF1 TRACED7 - - - I2C2_SDA - -
I2S3_SDO
DFSDM1_
PF2 TRACED1 - - - I2C2_SCL - USART6_CK
CKIN1
Port F
SPI4_MISO/ SPI3_NSS/
PF3 - - - LPTIM2_IN2 I2C5_SDA -
I2S4_SDI I2S3_WS
PF4 - - - USART2_RX - - - -
DFSDM1_
PF5 TRACED12 - - - I2C1_SMBA - -
CKIN0
PF6 - TIM16_CH1 - - - SPI5_NSS - UART7_RX
79/218
 Table 8. Alternate function AF0 to AF7 (continued)
80/218

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

LPTIM1/RTC/ DFSDM1/ DFSDM1/ I2C1/3/SPI1/ DFSDM1/I2C4/

Port SAI1/2/SYS/
SPI5/SYS/ LPTIM2/3/4/5/ I2C1/2/3/4/5/ I2S1/SPI2/I2S2/ SAI1/2/SPI1/I2 UART4/7/
RTC/SYS TIM1/3/4/5/12/
TIM1/2/16/17/ SAI2/TIM8/ LPTIM2/SAI1/2/ SPI3/I2S3/SPI4/ S1/SPI2/I2S2/S USART1/2/3/6
USART2
USART2 USART2 TIM15/USART1 I2S4/SPI5 PI3/I2S3/SPI5

PF7 - TIM17_CH1 - - - - - UART7_TX

PF8 - TIM16_CH1N TIM4_CH3 TIM8_CH3 - - SAI1_SCK_B USART6_TX
DFSDM1_CKIN
PF9 - TIM17_CH1N TIM1_CH1 - - SAI1_D4 UART7_CTS
3
USART6_RTS/
PF10 - TIM16_BKIN SAI1_D3 TIM8_BKIN - SPI5_NSS -
USART6_DE
DFSDM1_
Port F PF11 - USART2_TX SAI1_D2 - - SAI1_FS_A -
CKIN3
DS13876 Rev 6

SPI1_NSS/
PF12 - - - - - SAI1_SD_A -
I2S1_WS
DFSDM1_
PF13 - TIM2_ETR SAI1_MCLK_B - - - USART2_TX
DATIN3
PF14 JTCK/SWCLK - - - - - - -
PF15 JTMS/SWDIO - - - - - - -
PG0 - - - - - - - -
SPI2_MISO/
PG1 - LPTIM1_ETR TIM4_ETR SAI2_FS_A I2C2_SMBA SAI2_D2 -
I2S2_SDI
PG2 - MCO2 - TIM8_BKIN - - - -
Port G PG3 - - - TIM8_BKIN2 I2C2_SDA - SAI2_SD_B -
DFSDM1_

STM32MP133A/D
PG4 TRACED1 TIM1_BKIN2 - - - - -
CKIN3
PG5 - TIM17_CH1 - - - - - -
PG6 TRACED3 TIM17_BKIN TIM5_CH4 SAI2_D1 USART1_RX - SAI2_SD_A -
 Table 8. Alternate function AF0 to AF7 (continued)

STM32MP133A/D
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

LPTIM1/RTC/ DFSDM1/ DFSDM1/ I2C1/3/SPI1/ DFSDM1/I2C4/

Port SAI1/2/SYS/
SPI5/SYS/ LPTIM2/3/4/5/ I2C1/2/3/4/5/ I2S1/SPI2/I2S2/ SAI1/2/SPI1/I2 UART4/7/
RTC/SYS TIM1/3/4/5/12/
TIM1/2/16/17/ SAI2/TIM8/ LPTIM2/SAI1/2/ SPI3/I2S3/SPI4/ S1/SPI2/I2S2/S USART1/2/3/6
USART2
USART2 USART2 TIM15/USART1 I2S4/SPI5 PI3/I2S3/SPI5

SPI3_MISO/
PG7 TRACED8 TIM1_ETR - - - - -
I2S3_SDI
PG8 - TIM2_CH1 - TIM8_ETR - SPI5_MISO SAI1_MCLK_B -
PG9 DBTRGO - - - I2C2_SDA - - USART6_RX
PG10 - - - - - SPI5_SCK SAI1_SD_B -
PG11 - - - - SAI2_D3 I2S2_MCK - USART3_TX
Port G
USART6_RTS/
PG12 - LPTIM1_IN1 - - SAI2_SCK_A - SAI2_CK2
USART6_DE
DS13876 Rev 6

USART6_CTS/
PG13 - LPTIM1_OUT - - - - -
USART6_NSS

Pinout, pin description and alternate functions

PG14 - LPTIM1_ETR - - - - SAI2_D1 USART6_TX
USART6_CTS/
PG15 - - - - - - -
USART6_NSS
PH0 - - - - - - - -
PH1 - - - - - - - -
PH2 - LPTIM1_IN2 - - - - - -
PH3 - - - - I2C3_SCL SPI5_MOSI - -
Port H PH4 JTDI - - - - - - -
PH5 JTDO - - - - - - -
SPI2_SCK/
PH6 - - TIM12_CH1 USART2_CK I2C5_SDA - -
I2S2_CK
PH7 - - SAI2_FS_B - - I2C3_SDA SPI5_SCK -
81/218
 Table 8. Alternate function AF0 to AF7 (continued)
82/218

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

LPTIM1/RTC/ DFSDM1/ DFSDM1/ I2C1/3/SPI1/ DFSDM1/I2C4/

Port SAI1/2/SYS/
SPI5/SYS/ LPTIM2/3/4/5/ I2C1/2/3/4/5/ I2S1/SPI2/I2S2/ SAI1/2/SPI1/I2 UART4/7/
RTC/SYS TIM1/3/4/5/12/
TIM1/2/16/17/ SAI2/TIM8/ LPTIM2/SAI1/2/ SPI3/I2S3/SPI4/ S1/SPI2/I2S2/S USART1/2/3/6
USART2
USART2 USART2 TIM15/USART1 I2S4/SPI5 PI3/I2S3/SPI5

PH8 TRACED9 - TIM5_ETR USART2_RX I2C3_SDA - - -

SPI4_SCK/
PH9 - TIM1_CH4 TIM12_CH2 - - - -
I2S4_CK
DFSDM1_ SPI2_MOSI/ USART3_CTS/
PH10 TRACED0 - TIM5_CH1 SAI2_D3 I2S3_MCK
DATIN2 I2S2_SDO USART3_NSS
SPI2_NSS/
PH11 - SPI5_NSS TIM5_CH2 SAI2_SD_A - I2C4_SCL USART6_RX
Port H I2S2_WS
DFSDM1_
PH12 - USART2_TX TIM5_CH3 I2C3_SCL SPI5_MOSI SAI1_SCK_A -
DS13876 Rev 6

CKIN1
SPI3_SCK/
PH13 TRACED15 - USART2_CK TIM8_CH1N I2C5_SCL - -
I2S3_CK
DFSDM1_
PH14 - - - I2C3_SDA - - -
DATIN2
PI0 - - - - - - - -
PI1 - - - - - - - -
PI2 - - - - - - - -
PI3 - - - - - - - -
Port I
PI4 BOOT0 - - - - - - -
PI5 BOOT1 - - - - - - -
PI6 BOOT2 - - - - - - -

STM32MP133A/D
PI7 - - - - - - - -
 Table 9. Alternate function AF8 to AF15

STM32MP133A/D
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

PA0 UART5_TX - - ETH1_MII_CRS ETH2_MII_CRS - - -

ETH1_MII_RX_
CLK/
ETH1_RGMII_
PA1 - - - - - - -
RX_CLK/
ETH1_RMII_
REF_CLK
PA2 - - - ETH1_MDIO - - - -
DS13876 Rev 6

PA3 - - - ETH1_MII_COL ETH2_MII_COL - - -

ETH1_PPS_ ETH2_PPS_
PA4 - - SAI1_SCK_A - - -
OUT OUT

Pinout, pin description and alternate functions

ETH1_PPS_ ETH2_PPS_
PA5 - - - - - -
OUT OUT
Port A
UART4_RTS/
PA6 TIM13_CH1 - - SAI2_SCK_A - - -
UART4_DE
ETH1_MII_RX_
DV/
ETH1_RGMII_
PA7 - TIM14_CH1 - SAI2_SD_A - - -
RX_CTL/
ETH1_RMII_
CRS_DV
ETH2_MII_
SPI2_MOSI/ RXD3/
PA8 - OTG_HS_SOF FMC_A21 - - -
I2S2_SDO ETH2_RGMII_
RXD3
PA9 UART4_TX - FMC_NWAIT - - - - -
83/218

PA10 - - - - - - - -
 Table 9. Alternate function AF8 to AF15 (continued)
84/218

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

ETH2_MII_
RXD1/
ETH2_RGMII_
PA11 - - ETH1_CLK - ETH2_CLK - -
RXD1/
ETH2_RMII_
RXD1
ETH2_MII_RX_
DV/
Port A
ETH2_RGMII_
DS13876 Rev 6

PA12 - - - FMC_A7 - - -
RX_CTL/
ETH2_RMII_
CRS_DV
PA13 UART4_TX - - - - - - -
PA14 - - OTG_HS_SOF - - - - -
PA15 UART4_RX - - - FMC_A9 - - HDP5
ETH1_MII_
RXD2/
PB0 UART4_CTS - SAI2_D2 - - - -
ETH1_RGMII_
RXD2
ETH1_MII_
RXD3/
Port B PB1 - - - - - - -
ETH1_RGMII_
RXD3

STM32MP133A/D
QUADSPI_
PB2 UART4_RX - ETH2_MDIO FMC_A6 - - -
BK1_NCS
SDMMC1_
PB3 - SDMMC2_D2 - SAI2_MCLK_A UART7_RX - -
D123DIR
 Table 9. Alternate function AF8 to AF15 (continued)

STM32MP133A/D
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

PB4 - - SDMMC2_D3 - SAI2_SCK_A - - -

SDMMC1_
PB5 FDCAN2_RX - UART5_RX - - - -
CKIN
QUADSPI_
PB6 - - ETH2_MDIO FMC_NE3 - - HDP6
BK1_NCS
PB7 - - FMC_NCE2 - FMC_NL - - -
FMC_D13/FMC
PB8 UART4_RX - SAI1_D1 - - - -
DS13876 Rev 6

_AD13
SDMMC1_
PB9 - FDCAN1_TX SDMMC2_D5 UART5_TX - - -
CDIR

Pinout, pin description and alternate functions

Port B
PB10 - - - - - - - -
ETH1_MII_TX_
EN/
ETH1_RGMII_
PB11 - - - - - - -
TX_CTL/
ETH1_RMII_TX
_EN
PB12 USART3_RX - - UART5_RX SDMMC1_D5 - - -
SDMMC1_
PB13 FDCAN2_TX - UART5_TX - - - -
D123DIR
PB14 - - SDMMC2_D0 SDMMC1_D4 - - - -
SDMMC1_
Port B PB15 - SDMMC2_D1 - SAI2_FS_A - - -
CKIN
85/218
 Table 9. Alternate function AF8 to AF15 (continued)
86/218

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

PC0 - - - - - - - -
ETH1_MII_RX_
DV/ ETH1_RGMII_
PC1 - - - - - -
ETH1_RMII_ GTX_CLK
CRS_DV
ETH1_MII_
TXD2/
PC2 - - SAI2_CK1 - - - -
ETH1_RGMII_
DS13876 Rev 6

TXD2
ETH1_MII_TX_ ETH2_MII_TX_
PC3 UART5_CTS - SAI1_MCLK_A - - -
CLK CLK
ETH1_MII_
Port C
RXD0/
UART5_RTS/ ETH1_RGMII_
PC4 SPDIFRX_IN2 - SAI2_D3 - - -
UART5_DE RXD0/
ETH1_RMII_
RXD0
ETH1_MII_
RXD1/
ETH1_RGMII_
PC5 - SPDIFRX_IN3 - - - - -
RXD1/
ETH1_RMII_
RXD1

STM32MP133A/D
SDMMC2_
PC6 SDMMC1_D6 SDMMC2_D6 - FMC_A19 - - HDP2
D0DIR
 Table 9. Alternate function AF8 to AF15 (continued)

STM32MP133A/D
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

SDMMC2_
PC7 USART3_CTS SDMMC2_D7 - SDMMC1_D7 - - HDP4
CDIR
UART5_RTS/
PC8 USART3_CTS - SAI2_FS_B SDMMC1_D0 - - -
UART5_DE
PC9 UART5_CTS FDCAN1_TX - - SDMMC1_D1 - - -
PC10 - - SAI2_MCLK_B - SDMMC1_D2 - - -
Port C
PC11 UART5_RX - SAI2_SCK_B - SDMMC1_D3 - - -
DS13876 Rev 6

PC12 UART7_TX - SAI2_SD_B - SDMMC1_CK - - -

PC13 - - - - - - - -

Pinout, pin description and alternate functions

PC14 - - - - - - - -
PC15 - - - - - - - -
FMC_D2/
PD0 - FDCAN1_RX - - - - -
FMC_AD2
Port D
QUADSPI_BK1 FMC_D3/
PD1 UART4_TX - - - - -
_NCS FMC_AD3
87/218
 Table 9. Alternate function AF8 to AF15 (continued)
88/218

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

PD2 - - - - SDMMC1_CMD - - -
PD3 - - - - FMC_CLK - - -
PD4 - QUADSPI_CLK - - FMC_NOE - - -
QUADSPI_BK1
PD5 - - - FMC_NWE - - -
_IO0
PD6 UART4_TX - - - - - - -
ETH1_MII_RX_
DS13876 Rev 6

CLK/
ETH1_RGMII_ QUADSPI_BK1
PD7 - SPDIFRX_IN0 FMC_NE1 - - -
RX_CLK/ _IO2
ETH1_RMII_
Port D REF_CLK
PD8 UART4_RX - - - - - - -
SDMMC2_ FMC_D14/
PD9 - - - - - -
CDIR FMC_AD14
FMC_D15/
PD10 - - - - - - -
FMC_AD15
QUADSPI_BK1 ETH2_RGMII_ FMC_CLE/FMC
PD11 SPDIFRX_IN0 - UART7_RX - -
_IO2 CLK125 _A16
FMC_ALE/FMC
PD12 - - - - - - -

STM32MP133A/D
_A17
QUADSPI_BK1 QUADSPI_BK2
PD13 - - FMC_A18 - - -
_IO3 _IO2
 Table 9. Alternate function AF8 to AF15 (continued)

STM32MP133A/D
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

FMC_D0/FMC_
PD14 UART8_CTS - - - - - -
AD0
Port D
QUADSPI_BK1 FMC_D1/FMC_
PD15 - - - - - -
_IO3 AD1
PE0 UART8_RX FDCAN2_RX - - FMC_A11 - - -
PE1 UART8_TX - - - FMC_NBL1 - - -
ETH2_MII_
DS13876 Rev 6

RXD1/
ETH2_RGMII_
PE2 - SPDIFRX_IN1 - FMC_A23 - - -
RXD1/
ETH2_RMII_

Pinout, pin description and alternate functions

RXD1
USART3_RTS/
PE3 FDCAN1_RX SDMMC2_CK - - - - -
USART3_DE

Port E QUADSPI_BK2
PE4 UART8_TX FMC_NCE2 - FMC_A25 - - -
_NCS
ETH1_MII_
TXD3/
PE5 UART4_RX - - FMC_NE1 - - -
ETH1_RGMII_
TXD3
ETH2_MII_
UART4_RTS/ TXD3/
PE6 - - FMC_A22 - - -
UART4_DE ETH2_RGMII_
TXD3
FMC_D4/
PE7 UART5_TX - - - - - -
FMC_AD4
89/218
 Table 9. Alternate function AF8 to AF15 (continued)
90/218

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

FMC_D5/
PE8 - - - - - - -
FMC_AD5
QUADSPI_BK1 FMC_D6/
PE9 - - - - - HDP3
_IO1 FMC_AD6
FMC_D7/
PE10 - FDCAN1_TX - - - - -
FMC_AD7
ETH2_MII_TX_ ETH1_MII_TX_ FMC_D8/
PE11 - - - - -
ER ER FMC_AD8
DS13876 Rev 6

Port E
UART8_RTS/ FMC_D9/
PE12 - - - - - HDP4
UART8_DE FMC_AD9
FMC_D10/
PE13 - - - - - - -
FMC_AD10
UART8_RTS/ QUADSPI_BK1 QUADSPI_BK2 FMC_D11/
PE14 - - - -
UART8_DE _NCS _IO2 FMC_AD11
FMC_D12/
PE15 - - - - - - HDP7
FMC_AD12
PF0 - - SDMMC2_D4 - FMC_A0 - - -
PF1 - - - - FMC_A1 - - HDP7
Port F SDMMC2_ SDMMC1_
PF2 - - FMC_A2 - - -
D0DIR D0DIR

STM32MP133A/D
PF3 - - - - FMC_A3 - - -
 Table 9. Alternate function AF8 to AF15 (continued)

STM32MP133A/D
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

ETH2_MII_
RXD0/
ETH2_RGMII_
PF4 - - - FMC_A4 - - -
RXD0/
ETH2_RMII_
RXD0
PF5 - - - - FMC_A5 - - -
ETH2_MII_TX_
DS13876 Rev 6

EN/
QUADSPI_BK1 ETH2_RGMII_
PF6 - - - - - -
_IO2 TX_CTL/
ETH2_RMII_TX

Pinout, pin description and alternate functions

_EN

Port F ETH2_MII_
TXD0/
ETH1_RGMII_ ETH2_RGMII_
PF7 UART4_CTS - FMC_A18 - - -
CLK125 TXD0/
ETH2_RMII_
TXD0
QUADSPI_BK1
PF8 - TIM13_CH1 - - - - -
_IO0
QUADSPI_BK1 QUADSPI_BK2
PF9 UART8_RX TIM14_CH1 FMC_A9 - - -
_IO1 _IO3
UART7_RTS/
PF10 QUADSPI_CLK - - - - - -
UART7_DE
ETH2_MII_RX_
PF11 - - - - - - -
ER
91/218
 Table 9. Alternate function AF8 to AF15 (continued)
92/218

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

ETH1_MII_TX_ ETH1_RGMII_
PF12 UART4_TX - - - - -
ER CLK125

Port F PF13 UART5_RX - - - - - - -

PF14 - - - - - - - -
PF15 - - - - - - - -
PG0 - FDCAN2_TX - - FMC_A10 - - -
ETH2_MII_TXD
DS13876 Rev 6

PG1 - FDCAN2_TX 2/ETH2_RGMII - FMC_NBL0 - - -

_TXD2
PG2 - - SAI2_MCLK_B ETH1_MDC - - - -
ETH2_RGMII_
PG3 - FDCAN2_RX ETH1_MDIO FMC_A13 - - -
GTX_CLK
Port G SDMMC2_
PG4 USART3_RX - - FMC_A14 - - HDP1
D123DIR
PG5 - - ETH2_MDC - FMC_A15 - - -
PG6 - - SDMMC2_CMD - - - - HDP3
SDMMC2_
PG7 UART7_CTS - - - - - -
CKIN
USART3_RTS/ QUADSPI_BK2 QUADSPI_BK1
PG8 SPDIFRX_IN2 FMC_NE2 ETH2_CLK - -

STM32MP133A/D
USART3_DE _IO2 _IO3
 Table 9. Alternate function AF8 to AF15 (continued)

STM32MP133A/D
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

PG9 SPDIFRX_IN3 FDCAN1_RX FMC_NE2 - FMC_NCE - - -

QUADSPI_BK2
PG10 UART8_CTS FDCAN1_TX - FMC_NE3 - - -
_IO1
ETH2_MII_
TXD1/
ETH2_RGMII_
PG11 UART4_TX - - FMC_A24 - - -
TXD1/
ETH2_RMII_
DS13876 Rev 6

TXD1
ETH2_MII_RX_
DV/
ETH2_PHY_ ETH1_PHY_ ETH2_RGMII_

Pinout, pin description and alternate functions

PG12 USART3_CTS - - - -
INTN INTN RX_CTL/
Port G ETH2_RMII_
CRS_DV
ETH1_MII_
TXD0/
ETH1_RGMII_
PG13 - - - - - - -
TXD0/
ETH1_RMII_
TXD0
ETH1_MII_
TXD1/
ETH1_RGMII_
PG14 - - SAI2_SD_A - - - -
TXD1/
ETH1_RMII_
TXD1
QUADSPI_BK1 ETH2_PHY_
93/218

Port G PG15 UART7_CTS - - - - -

_IO1 INTN
 Table 9. Alternate function AF8 to AF15 (continued)
94/218

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

PH0 - - - - - - - -
PH1 - - - - - - - -
QUADSPI_BK2 ETH2_RGMII_
PH2 UART7_TX ETH2_MII_CRS ETH1_MII_CRS FMC_NE4 - -
_IO0 CLK125
QUADSPI_BK2 QUADSPI_BK1
PH3 - ETH1_MII_COL - ETH2_MII_COL - -
_IO1 _IO0
PH4 - - - - - - - -
DS13876 Rev 6

PH5 - - - - - - - -
Port H
ETH2_MII_
QUADSPI_BK1 ETH1_PHY_IN ETH1_MII_RX_ RXD2/ QUADSPI_BK1
PH6 - - -
_IO2 TN ER ETH2_RGMII_ _NCS
RXD2
QUADSPI_BK2 ETH2_MII_TX_ ETH1_MII_TX_ QUADSPI_BK1
PH7 - - - -
_IO3 CLK CLK _IO3
PH8 - - - - FMC_A8 - - HDP2
PH9 - - - - FMC_A20 - - -
PH10 SDMMC1_D4 - - - - - - HDP0

STM32MP133A/D
 Table 9. Alternate function AF8 to AF15 (continued)

STM32MP133A/D
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SDMMC1/ FDCAN1/2/QU ETH1/2/FMC/

ETH1/2/
Port SPDIFRX/SPI2/ ADSPI/ OTG_HS/ ETH2/FMC/ ETH2/
QUADSPI/
I2S2/ SDMMC2/ QUADSPI/ SAI1/2/ QUADSPI/ HDP/SYS
SDMMC1/
UART4/5/7/8/ SPDIFRX/ SAI1/2/ SDMMC1 UART7
UART5
USART3 TIM13/14 SDMMC2

ETH2_MII_RX_
CLK/
QUADSPI_BK2 ETH2_RGMII_
PH11 - - FMC_A12 - - -
_IO0 RX_CLK/
ETH2_RMII_
Port H REF_CLK
QUADSPI_BK2
PH12 - SAI1_CK2 ETH1_MII_CRS FMC_A6 - - -
_IO2
DS13876 Rev 6

PH13 UART4_TX - - - - - - -
PH14 UART4_RX - - - - - - -
PI0 SPDIFRX_IN0 - - - - - - -

Pinout, pin description and alternate functions

PI1 SPDIFRX_IN1 - - - - - - -
PI2 SPDIFRX_IN2 - - - - - - -
ETH1_MII_RX_
PI3 SPDIFRX_IN3 - - - - - -
Port I ER
PI4 - - - - - - - -
PI5 - - - - - - - -
PI6 - - - - - - - -
PI7 - - - - - - - -
95/218
Memory mapping STM32MP133A/D

5 Memory mapping

Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.

96/218 DS13876 Rev 6

STM32MP133A/D Electrical characteristics

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V,
VDDCORE = 1.25 V, VDDCPU = 1.25 V. They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

Figure 8. Pin loading conditions Figure 9. Pin input voltage

Device pin Device pin

VIN
C = 50 pF

MSv47493V1 MSv47494V1

DS13876 Rev 6 97/218

203
Electrical characteristics STM32MP133A/D

6.1.6 Power supply scheme

Figure 10. Power supply scheme

VDDSD1
VDDSD2
3V3 USB VDDSD2
VDD3V3_USBHS Detector Detector

VDDA1V1_REG 1V1
Regulator VDDSD1
VDD
Detector
1V8
VDDA1V8_REG Regulator

PWR

vddsd1den
vddsd1rdy

vddsd2den
vddsd2rdy
reg18en
reg18rdy

usb33den
usb33rdy
reg11en
RCC
reg11rdy
rcc_pwr_sec
BYPASS_REG1V8
AHB
Register interface
nrst_por
PDR_ON vddcore_ok
vcore_rdy
vddcpu_ok vcpu_rdy
NRST
por_vsw
POR/PDR nrst_bor
BOR
hclk4
VDDCPU
VDDCORE Power pwrwake_mpu
VBAT management
thresholds
VDD Backup pwrwake_sys
domain TEMP mpu cstandby
VBAT thresholds
VBAT
charging MPU
(gic)

PWR_ON
PWR_CPU_ON PWR
control
PWR_LP

VSS sys_ds_exit sys_wakeup

mpu_ds_exit c1_wakeup
VDDA
VSSA WAKEUP
mpu_int_wkup

WKUP[6:1]
async_wkup[6:1] wakeup event
EXTI
pvdo wakeup event
PVD_IN PVD & AVD
avdo wakeup event

MSv65228V4

Caution: Each power supply pair (VDD/VSS, VDDSDx/VSS, VDDCORE/VSS, VDDCPU/VSS, VDDA/VSSA ...)
must be decoupled with filtering ceramic capacitors. These capacitors must be placed as
close as possible to, or below, the appropriate pins on the underside of the PCB to ensure

98/218 DS13876 Rev 6

STM32MP133A/D Electrical characteristics

good operation of the device. It is not recommended to remove filtering capacitors to reduce
PCB size or cost. This might cause incorrect operation of the device.

6.1.7 Current consumption measurement

Figure 11. Current consumption measurement scheme

IDD_CORE
VDDCORE

IDD_CPU
VDDCPU

IDD_VBAT
VBAT

IDD
VDD

VDD_ANA

VDD_PLL

MSv66294V2

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics,
Table 11: Current characteristics, and Table 12: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.

Table 10. Voltage characteristics (1)

Symbols Ratings Min Max Unit

External main supply voltage (including VDD,

VDDX - VSSX VDDSD1, VDDSD2, VDD_ANA, VDD_PLL, VDDA, -0.3 3.9 V
VDD3V3_USBHS, VBAT, VREF+)
VDDCORE -
External core supply voltage -0.3 1.5 V
VSS
VDDCPU -
External Cortex®-A7 CPU supply voltage -0.3 1.5 V
VSS
VDDA_DDR -
DDR IO supply voltage -0.3 1.98 V
VSS

DS13876 Rev 6 99/218

203
Electrical characteristics STM32MP133A/D

Table 10. Voltage characteristics (continued)(1)

Symbols Ratings Min Max Unit

VDDA1V8 -
1.8 V supply (VDDA1V8_REG) -0.3 3.9 V
VSS
(3)
Input voltage on FT_xxx pins V
Input voltage on TT_xx pins 3.9 V
VIN(2) VSS - 0.3
(4)
Input voltage on USB/OTG_HS_DP/DM pins V
Input voltage on any other pins 3.9 V
Variations between different VDDX power pins of
|∆VDDX| - 50 mV
the same domain
|VSSx-VSS| Variations between all the different ground pins - 50 mV
VREF+ - VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 V
1. All power (VDD, VDDSD1, VDDSD2, VDDA, VDD3V3_USBHS, VDDCORE, VDDCPU, VBAT) and ground (VSS, VSSA,
VSSX) pins must always be connected to the external/internal power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 53 for the maximum allowed injected current
values.
3. Min(6.0, VDD+3.9, VDDA+3.9, VDD3V3_USBHS+3.9, VBAT+3.9).
This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
To sustain a voltage higher than 3.9 V the internal pull-up/pull-down resistors must be disabled.
4. Min(5.25, VDD+3.9, VDD3V3_USBHS+3.9).

Table 11. Current characteristics(1)

Symbols Ratings Max Unit

ΣIVDD Total current into sum of all VDD power lines (source) 440
IVDD Maximum current into each VDD power pin (source) 100
IVSS Maximum current out of each VSS ground pin (sink) 100
IIO Output current sunk by any I/O and control pin 20
mA
Total output current sunk by sum of all I/Os and control pins(2) 140
ΣI(PIN)
Total output current sourced by sum of all I/Os and control pins(2) 140
IINJ(PIN)(3)(4) Injected current on FT_xxx, TT_xx, NRST pins -5/+0
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5) ±25
1. All power (VDD, VDDSD1, VDDSD2, VDDA, VDD3V3_USBHS) and ground (VSS, VSSA, VSSX) pins must always
be connected to the external/internal power supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 10: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).

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Table 12. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150

Maximum junction temperature (suffix 7) 105 °C
TJ
Maximum junction temperature (suffix 3) 125

6.3 Operating conditions

6.3.1 General operating conditions

Table 13. General operating conditions

Symbol Parameter Operating conditions Min. Typ Max. Unit

STM32MP133D 0 - 1000
Fmpuss_ck Cortex-A7 subsystem
STM32MP133A 0 - 650
Internal AXI, AHB5,
Faxiss_ck, Fhclk5,
AHB6 clock - 0 - 266.5
Fhclk6
frequency
Internal AHB clock
Fahb_ck - 0 - 209
frequency
Internal APB1 clock
Fpclk1 - 0 - 104.5
frequency
Internal APB2 clock MHz
Fpclk2 - 0 - 104.5
frequency
Internal APB3 clock
Fpclk3 - 0 - 104.5
frequency
Internal APB4 clock
Fpclk4 - 0 - 133
frequency
Internal APB5 clock
Fpclk5 - 0 - 133
frequency
Internal APB6 clock
Fpclk6 - 0 - 133
frequency
I/Os and embedded SYSCFG_HSLVENxR = 0 1.71(1)(2) - 3.6
regulators (REG1V1,
VDD V
REG1V8) supply SYSCFG_HSLVENxR ≠ 0 1.71 - 2.7
voltage

VDDSD1, VDDSD2 VDDSD1, VDDSD2, SYSCFG_HSLVENxR = 0 0(3) - 3.6 V

power section I/O’s
SYSCFG_HSLVENxR ≠ 0 0 - 2.7
System analog
VDD_ANA(4) - 1.71 - 3.6 V
supply voltage
VDD_PLL,
PLL supply voltage - 1.71 - 3.6 V
VDD_PLL2(5)

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Table 13. General operating conditions (continued)

Symbol Parameter Operating conditions Min. Typ Max. Unit
(6)
Run Overdrive mode
1.32 1.35 1.38
(Fmpuss_ck above 650 MHz)
Run mode(6)
1.21 1.25 1.38(7)
(Fmpuss_ck up to 650 MHz)

VDDCPU Cortex®-A7 CPU Run OppMin mode V

1.15 - 1.38(7)
(Fmpuss_ck = 64 MHz)
Stop, LP-Stop mode 1.15 1.25 1.38(7)(8)
LPLV-Stop mode on VDDCPU 0.85 0.9 1.38(7)(8)
LPLV-Stop2 mode 0 0 0
Run mode(6) 1.21 1.25 1.29
Stop, LP-Stop mode 1.15 1.25 1.29
Digital core domain
VDDCORE LPLV-Stop mode 0.85 0.90 1.29(9) V
supply voltage
LPLV-Stop2 mode 0.85 0.90 1.29(9)
Standby mode 0 0 0.75
ADC used with VREF < 2 V(10) 1.62 - 2.15
ADC used with VREF > 2 V(10) 2 - 3.6
VREFBUF with VREF = 1.65 V 1.95 - 3.6
Analog operating
VDDA VREFBUF with VREF = 1.8 V 2.1 - 3.6 V
voltage
VREFBUF with VREF = 2.048 V 2.35 - 3.6
VREFBUF with VREF = 2.5 V 2.8 - 3.6
ADC, VREF not used 0 - 3.6
Backup operating
VBAT - 1.6 - 3.6 V
voltage
USBH or USB OTG HS used 3.07 3.3 3.6
USB HS I/O supply
VDD3V3_USBHS(11) USBH and USB OTG HS not V
voltage 0 - 3.6
used
DDR3 memory 1.425 1.5 1.575
(12) DDR PHY supply
VDDQ_DDR DDR3L memory 1.283 1.35 1.45 V
voltage
LPDDR2 or LPDDR3 1.14 1.2 1.3
USB HS PHY voltage
supply with 1.8 V
VDDA1V8_REG BYPASS_REG1V8 = VDD 1.65 1.8 1.95 V
regulator in bypass
mode
TTxa I/O -0.3 - VDD+0.3
DDR I/O -0.3 - VDDQ_DDR
VIN I/O Input voltage V
USB HS I/O -1 - 5.25
All I/O except TTxa -0.3 - See(13)

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Table 13. General operating conditions (continued)

Symbol Parameter Operating conditions Min. Typ Max. Unit

Junction temperature Suffix 7 version -40 - 105

o
TJ C
range Suffix 3 version -40 - 125
1. Once nRST is released functionality is guaranteed down to VBOR falling edge max.
2. Min VDD is 2.25 V when REG1V8 is used BYPASS_REG1V8 = 0.
3. VDDSD1, VDDSD2 voltages should be above Max_Vpad - 3.6V. Where Max_Vpad is the maximum input voltage present on
device I/O’s.
4. Should be connected to same power supply voltage as VDD.
5. It is required to connect VDD_PLL and VDD_PLL2 to same power supply as VDD.
6. The min/typ/max values do not take into account any ripple. The values must be considered at the device power balls. It is
not possible to start the device in overdrive mode since at reset the bit MPU_RAM_LOWSPEED = 1.
7. The device is functional up to 1.38 V but using VDDCPU > 1.29 V does not guarantee life time according mission profile
“Cortex®-A7 @650 MHz, -40 °C < TJ < 125 °C”
Refer also to the application note AN5438 “STM32MP1 Series lifetime estimates” available from the ST website
www.st.com.
8. 1.38 V is the max allowed voltage, however LPLV-Stop mode is only relevant for VDDCPU up to 0.95 V.
9. 1.29 V is the max allowed voltage, however LPLV-Stop mode is only relevant for VDDCORE up to 0.95 V. In LPLV-Stop
mode, if VDDQ_DDR is not shutdown, to avoid overconsumption on VDDQ_DDR, the DDR memory must be put in
SelfRefresh and DDR PHY must be set in retention mode (setting bit DDRRETEN: DDR retention enable of PWR control
register 3 (PWR_CR3)).
10. VDDA should always be ≥ VREF.
11. For operation with voltage higher than Min (VDD, VDDA) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
12. Independent from any other supply.
13. Min(5.5, VDD+3.6, VDDA+3.6). This formula has to be applied on power supplies related to the IO structure described by the
pin definition table.

6.3.2 Operating conditions at power-up / power-down

Subject to general operating conditions.

Table 14. Operating conditions at power-up / power-down

Symbol Parameter Min Max Unit

VDD rise time rate 0 ∞

tVDD(1)
VDD fall time rate 20 ∞
VDDA rise time rate 0 ∞
tVDDA µs/V
VDDA fall time rate 10 ∞
VDD3V3_USBHS rise time rate 0 ∞
tVDD3V3_USBHS(2)
VDD3V3_USBHS fall time rate 10 ∞

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Table 14. Operating conditions at power-up / power-down (continued)

Symbol Parameter Min Max Unit

VDDCPU rise time rate (from reset

or LPLV-Stop2 mode to RUN - 2000
mode)
tVDDCPU
VDDCPU rise time rate (from LPLV-
- 1000(3)
Stop to RUN mode)
VDDCPU fall time rate 7.33 ∞
µs/V
VDDCORE rise time rate (from reset
- 2000
to RUN mode)
VDDCORE rise time rate (from
tVDDCORE
LPLV-Stop or LPLV-Stop2 mode to - 1000(3)
RUN mode)
VDDCORE fall time rate 7.33 ∞
1. VDD must be present before VDDCORE and VDDCPU.
2. VDDA1V8_REG must be present before VDD3V3_USBHS.
3. In case VDDCORE or VDDCPU rise time at exit of LPLV-Stop is larger than 1 ms/V, there is a risk
of unwanted reset due to VDDCORE or VDDCPU potentially not yet established after
tSEL_VDDCORETEMPO (cf.Table 14 and Figure 13). In such a case, the VDDCORE or VDDCPU
supply should not be decreased during LPLV-Stop mode.

Figure 12. VDDCORE / VDDCPU rise time from reset

average rise time rate should be less than
tVDDCORE (*) Max (from reset to Run mode)

VDDCORE (*) VDDCORE (*) should be above

V VDDCORE (*) Min when vddcore_ok is
enabled

VDDCORE (*) Min

VTH_VDDCORE (*) (rising edge)

tVDDCORE_TEMPO

pvdcore_out
Run mode

vddcore_ok

VDDCORE (*) Min = VTH_VDDCORE (*) Min (rising edge) + tVDDCORE_TEMPO Min / tVDDCORE (*) Max

(*) VDDCORE can be replaced by VDDCPU in formulas.

MSv66295V2

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Figure 13. VDDCORE / VDDCPU rise time from LPLV-Stop

average rise time rate should be less than

tVDDCORE (*) Max (from LPLV-Stop to Run mode)

VDDCORE (*) VDDCORE (*) should be above

V VDDCORE (*) Min at the end of
tSEL_VDDCORETEMPO

VDDCORE (*) Min

VTH_VDDCORE_1 (*)
(falling edge)

tSEL_VDDCORETEMPO

PWR_LP

LPLV-
Stop Wait Run mode
mode

VDDCORE (*) Min = VTH_VDDCORE_1 (*) Min (falling edge) + tSEL_VDDCORETEMPO Min / tVDDCORE (*) Max
(*) VDDCORE can be replaced by VDDCPU in formulas.
MSv66296V2

6.3.3 Embedded reset and power control block characteristics

The parameters given in Table 15 are derived from tests performed under ambient.
temperature and VDD supply voltage conditions summarized in Table 13: General operating
conditions.

Table 15. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

Reset delay after BOR0

tRSTTEMPO(1) - - 377 550 µs
released
Rising edge 1.62 1.67 1.71
VBOR0(1)(2) Brown-out reset threshold 0 V
Falling edge 1.58 1.63 1.67
Rising edge 2.055 2.1 2.145
VBOR1 Brown-out reset threshold 1 V
Falling edge 1.955 2 2.045
Rising edge 2.355 2.4 2.445
VBOR2 Brown-out reset threshold 2 V
Falling edge 2.255 2.3 2.345
Rising edge 2.655 2.7 2.745
VBOR3 Brown-out reset threshold 3 V
Falling edge 2.555 2.6 2.645

Programmable Voltage Rising edge 1.905 1.95 1.995

VPVD0 V
Detector threshold 0 Falling edge 1.805 1.85 1.895

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Table 15. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit

Programmable Voltage Rising edge 2.055 2.1 2.145

VPVD1 V
Detector threshold 1 Falling edge 1.955 2 2.045

Programmable Voltage Rising edge 2.205 2.25 2.295

VPVD2 V
Detector threshold 2 Falling edge 2.105 2.15 2.195

Programmable Voltage Rising edge 2.355 2.4 2.445

VPVD3 V
Detector threshold 3 Falling edge 2.255 2.3 2.345

Programmable Voltage Rising edge 2.505 2.55 2.595

VPVD4 V
Detector threshold 4 Falling edge 2.405 2.45 2.495

Programmable Voltage Rising edge 2.655 2.7 2.745

VPVD5 V
Detector threshold 5 Falling edge 2.555 2.6 2.645
Rising edge 2.805 2.85 2.895
Programmable Voltage
VPVD6 Falling edge in V
Detector threshold 6 2.705 2.75 2.795
RUN mode
Hysteresis in
Vhyst_BOR0 Hysteresis voltage of BOR0 - 40 - mV
RUN mode
Vhyst_BOR Hysteresis voltage of BOR Unless BOR0 - 100 - mV
Hysteresis voltage of BOR Hysteresis in
Vhyst_BOR_PVD - 100 - mV
(unless BOR0) and PVD(3) RUN mode
BOR (unless BOR0) and PVD
IDD_BOR_PVD(1)(4) - 0.246 - 0.626 µA
consumption from VDD

Analog voltage (VDDA) detector Rising edge 1.655 1.7 1.745

VAVM_0 V
threshold 0 Falling edge 1.555 1.6 1.645

Analog voltage (VDDA) detector Rising edge 2.055 2.1 2.145

VAVM_1 V
threshold 1 Falling edge 1.955 2 2.045

Analog voltage (VDDA) detector Rising edge 2.455 2.5 2.545

VAVM_2 V
threshold 2 Falling edge 2.355 2.4 2.445

Analog voltage (VDDA) detector Rising edge 2.755 2.8 2.845

VAVM_3 V
threshold 3 Falling edge 2.655 2.7 2.745
Hysteresis of analog voltage
Vhyst_VDDA - - 100 - mV
(VDDA) detector
Analog Voltage Monitoring
IVDD_AVM(1) - - - 0.248 µA
(VDDA) consumption on VDD
Analog Voltage Monitoring
IVDDA_AVM(1) Resistor bridge - 2.12 - µA
(VDDA) consumption on VDDA
Digital core domain supply Rising edge 0.95 0.995 1.04
VTH_VDDCORE(5) voltage (VDDCORE) detector V
threshold 0 (Run) Falling edge 0.91 0.955 1

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Table 15. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit

Digital core domain supply

VTH_VDDCORE_1
(6) voltage (VDDCORE) detector Falling edge 0.71 0.755 0.8 V
threshold 1 (LPLV_Stop)
Hysteresis of Digital core
Vhyst_VDDCORE domain supply voltage - - 40 - mV
(VDDCORE) detector
Delay on VTH_VDDCORE at
rising edge of VDDCORE to
tVDDCORE_TEMPO - 200 340 550 µs
ensure that VDDCORE is fully
established
Delay on VTH_VDDCORE_1 at
rising edge of VDDCORE to
tSEL_VDDCORETE
ensure that VDDCORE is fully - 234 380 700 µs
MPO established on exit of LPLV-
Stop mode
IVDD_VDDCOREVM VDDCORE Voltage Monitoring
(1) - 1.7 2.6 4.2 µA
consumption on VDD
Digital MPU domain supply Rising edge 0.95 0.995 1.04
VTH_VDDCPU(7) voltage (VDDCPU) detector V
threshold 0 (Run) Falling edge 0.91 0.955 1

Digital MPU domain supply

VTH_VDDCPU_1(8) voltage (VDDCPU) detector Falling edge 0.71 0.755 0.8 V
threshold 1 (LPLV_Stop)
Hysteresis of Digital MPU
Vhyst_VDDCPU domain supply voltage - - 40 - mV
(VDDCPU) detector
Delay on VTH_VDDCPU at rising
tVDDCPU_TEMPO edge of VDDCPU to ensure that - 200 340 550 µs
VDDCPU is fully established
Delay on VTH_VDDCPU_1 at
rising edge of VDDCPU to
tSEL_VDDCPUTEM
(9) ensure that VDDCPU is fully - 234 380 700 µs
PO established on exit of LPLV-
Stop mode
IVDD_VDDCPUVM(1 VDDCPU Voltage Monitoring
) - 2.2 3.5 5.2 µA
consumption on VDD
VDD3V3_USBHS Threshold
VTH_VDDUSB - - 1.21 - V
voltage
VTH_VDDSD1 VDDSD1 Threshold voltage - - 1.21 - V
VTH_VDDSD2 VDDSD2 Threshold voltage - - 1.21 - V
1. Specified by design, not tested in production.
2. VPOR (power-on reset Voltage threshold) = BOR0 rising edge value
VPDR (power-down reset Voltage threshold) = BOR0 falling edge value
3. No hysteresis when using PVD_IN pin.
4. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables.

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Electrical characteristics STM32MP133A/D

5. During the first rising edge of VDDCORE, the slope should be less than 2 ms/V to ensure VDDCORE is fully established before
the end of the tVDDCORE_TEMPO.
6. When exiting from LPLV-Stop mode to RUN mode the rising slope for VDDCORE should be less than 1 ms/V to ensure
VDDCORE is fully established before the end of the tVDDCORE_TEMPO.
7. During the first rising edge of VDDCORE, the slope should be less than 2 ms/V to ensure VDDCORE is fully established before
the end of the tVDDCORE_TEMPO.
8. When exiting from LPLV-Stop mode to RUN mode the rising slope for VDDCPU should be less than 1 ms/V to ensure
VDDCPU is fully established before the end of the tVDDCPU_TEMPO.
9. tSEL_VDDCPUTEMPO is identical to tSEL_VDDCORETEMPO since both VDDCORE and VDDCPU are following same supply voltage
increase on exit from LPLV-Stop mode.

6.3.4 Embedded reference voltage

The parameters given in Table 16, Table 17 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 13: General operating
conditions.

Table 16. Embedded reference voltage

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltages -40 °C < TJ < 125 °C 1.175 1.210 1.241 V
ADC sampling time when
tS_vrefint(1)(2) reading the internal reference - 4.3 - -
voltage
VBAT sampling time when
µs
tS_vbat(1) reading the internal VBAT - 9.8 - -
reference voltage
Start time of reference voltage
tstart_vrefint - 0.8 - 4.6
buffer when ADC is enable
Reference Buffer consumption
Irefbuf(2) VDDA = 3.3 V 9.1 13.6 27.7 µA
for ADC
Internal reference voltage
∆VREFINT(2) spread over the temperature -40 °C < TJ < 125 °C - 4.3 15 mV
range
Average temperature Average temperature
Tcoeff_VREFINT - 19 67 ppm/°C
coefficient coefficient
VDDcoeff Average Voltage coefficient 3.0 V < VDD < 3.6 V - 10 1370 ppm/V
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Specified by design, not tested in production.

Table 17. Embedded reference voltage calibration value

Symbol Parameter Memory address

VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = VREF+ = 3.3 V 0x5C00 5250[31:16](1)(2)
1. Mandatory to read in 32-bits word and do relevant mask and shift to isolate required bits.
2. These address is inside BSEC which should be enabled in RCC to allow access.

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6.3.5 Embedded regulators characteristics

The parameters given in Table 18, Table 19 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 13: General operating
conditions.

REG1V1 embedded regulator (USB_PHY)

Table 18. REG1V1 embedded regulator (USB_PHY) characteristics(1)

Symbol Parameter Condition Min Typ Max Unit

VDDA1V1_
Regulated output voltage - 1.045 1.1 1.155 V
REG

CL Load Capacitor - 1.1 2.2(2) 3.3 µF

esr Equivalent Serial Resistor of Cload - 0.1 25 600 mΩ
Iload Static load current(3) - 0 - 30 mA
Start-up time. from CL=2.2uF - 93 -
tSTART PWR_CR3.REG11EN = 1 to µs
PWR_CR3.REG11RDY = 1 CL=3.3uF - - 180

VDD Inrush Current to load external

IINRUSH - - 50 60 mA
capacitor at start
Regulator Enabled and Iload =
- 150 205
Regulator Current consumption on 0 mA
IVDD µA
VDD Regulator Enabled and Iload =
- 176 242
30 mA
1. Specified by design, not tested in production.
2. For better dynamic performances a 2.2 μF typical value external capacitor is recommended.
3. Load is for internal STM32MP133A/D analog blocks, no additional external load is accepted unless mentioned.

Table 19. REG1V8 embedded regulator (USB_PHY) characteristics(1)

Symbol Parameter Condition Min Typ Max Unit

VDD Regulator input voltage - 2.25 3.3 3.6 V

VDDA1V8_
Regulated output voltage after trimming 1.7 1.8 1.9 V
REG

CL Load Capacitor - 0.5 2.2(2) 3.3 µF

esr Equivalent Serial Resistor of Cload - 0.1 25 600 mΩ
Iload Static load current(3) - - - 70 mA
Start-up time. from CL=2.2uF - 81 -
tSTART PWR_CR3.REG11EN = 1 to µs
PWR_CR3.REG11RDY = 1 CL=3.3uF - - 150

VDD Inrush Current to load external

IINRUSH - - 80 100 mA
capacitor at start

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Electrical characteristics STM32MP133A/D

Table 19. REG1V8 embedded regulator (USB_PHY) characteristics(1) (continued)

Symbol Parameter Condition Min Typ Max Unit

Regulator Enabled and Iload =

- 130 181
Regulator Current consumption on 0 mA
IVDD µA
VDD Regulator Enabled and Iload =
- 170 231
70 mA
1. Specified by design, not tested in production.
2. For better dynamic performances a 2.2 μF typical value external capacitor is recommended.
3. Load is for internal STM32MP133A/D analog blocks, no additional external load is accepted unless mentioned.

6.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All the Run mode current consumption measurements given in this section are performed
with a CoreMark code unless otherwise specified.

Typical and maximum current consumption

The device is placed under the following conditions:
• All I/O pins are in analog input mode except when explicitly mentioned.
• All peripherals are disabled except when explicitly mentioned.
• The maximum values are obtained for VDD/VBAT = 3.6 V, VDDCORE = 1.29 V, and
VDDCPU = 1.29 V, and the typical values for VDD/VBAT = 3.3 V, VDDCORE = 1.25 V and
VDDCPU = 1.25 V unless otherwise specified.
The parameters given in Table 22 to Table 27 are derived from tests performed under
supply voltage conditions summarized in Table 13: General operating conditions.

110/218 DS13876 Rev 6

 Table 20. Current consumption (IDDCORE) in Run mode

STM32MP133A/D
Conditions Typ Max
Symbol Parameter Unit
MPU SS AXI clk Tj = Tj = Tj = Tj = Tj =
- Oscillator
mode (MHz) 25 °C 25 °C 85 °C 105 °C 125 °C

Supply
All peripherals
IDDCORE current in Run CRun AHB clock = 64 MHz(2) 266 115 143 213 267 340 mA
enabled(1)
mode
AHB clock = 200 MHz(3) 266 82 99 172 224 301
266 62 83.4 156 208 284
Supply
All peripherals
IDDCORE current in Run CRun 150 41 59.7 133 183 256 mA
disabled AHB clock = 64 MHz(4)
mode
64 30 47.6 121 171 244
24 24 41.1 115 168 237
1. Activity on peripherals and bus masters other than processors, could lead to additional power consumption above these values, largely dependent on the amount of
DS13876 Rev 6

initialized peripherals and their activity.

2. Peripheral clocks set at default values (see table “Peripheral clock distribution overview” in reference manual) with pll4_r_ck = pll4_q_ck = 50 MHz, pll4_p_ck = 125 Mhz,
pclk1/2/3 = 32 MHz, pclk4 = 132 MHz, pclk5 = 66 MHz, pclk6 = 64 MHz.
3. pclk1/2/3 = 100 MHz, pclk4 = 132 MHz, pclk5 = 66 MHz, pclk6 = 104.5 MHz.
4. pclk1/2/3 = 32 MHz, pclk4 = AXI clock/2, pclk5 = AXI clock/4, pclk6 = 64 MHz.

Electrical characteristics
111/218
 Table 21. Current consumption (IDDCPU) in Run mode
112/218

Electrical characteristics
Conditions Typ Max
Symbol Parameter Unit
MPU clk Tj = Tj = Tj = Tj = Tj =
MPU SS mode
(MHz) 25 °C 25 °C 85 °C 105 °C 125 °C

1000(1) 150 167 225 268 -

(1)
900 135 153 211 254 -
(1)
780 115 135 194 235 -
650 88.5 104 153 188 239
600 82 98 147 181 232
IDDCPU Supply current in Run mode CRun mA
400 56 69 119 153 203
300 43 54.7 105 139 188
150 30 40.9 91.5 125 174
DS13876 Rev 6

64 12 22.5 73.2 107 156

24 6.65 16.5 67.1 100.6 149
IDDCPU Supply current in Run mode OppMin CRun 64(2) 10.5 19.7 64.1 93.5 136 mA
(1)
900 20 32.9 93.8 133 -
780(1) 18 30.8 91.6 131 -

CSleep 650 13.5 23.9 74.3 108 156

(MPU in 600 13 23.1 73.5 107 156
IDDCPU Supply current in Run mode CSleep with mA
WFI (CLK 300 8.2 18.2 68.6 102.2 151
OFF)) 150 6.65 16.5 66.9 100.5 149
64 4.5 14.3 64.7 98.2 147
24 3.85 13.6 64.0 97.5 146

STM32MP133A/D
1. Typical value given with VDDCPU = 1.35 V, maximum values given with VDDCPU = 1.37 V.
2. Typical and maximum values given with VDDCPU = 1.15 V, VDDCORE = 1.25 V, VDD = 3.3 V.
 Table 22. Current consumption (IDD) in Run mode(1)

STM32MP133A/D
Conditions Typ Max
Symbol Parameter Unit
Tj = Tj = Tj = Tj = Tj =
MPU SS mode Oscillator
25 °C 25 °C 85 °C 105 °C 125 °C

HSE+HSI+LSI+CSI+
IDD Supply current in Run mode CRun 2.75 2.98 2.95 2.96 2.61(2) mA
PLL1,2,3,4
HSI+PLL1,2 1.95 2.1 2.1 2.1 2.1
IDD Supply current in Run mode CSleep HSE+HSI 0.56 0.64 0.65 0.67 0.70 mA
HSI 0.29 0.33 0.33 0.34 0.36
1. HSE = 24 MHz.
2. Value provided with PLL1 @648 MHz while other values on the same row are provided with PLL1 @1 GHz (not allowed at 125°C).

Table 23. Current consumption in Stop mode

DS13876 Rev 6

Conditions Typ Max

Symbol Parameter Unit
MPU SS Tj = Tj = Tj = Tj = Tj = Tj = Tj = Tj =
-
mode 25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C

IDD 10.0 13.0 17.5 28 15.1 22.4 37.4 74.0 µA

Supply current All peripherals
IDDCORE CStop 5.35 29 52.5 89.5 20.2 92.0 142 211
in Stop mode disabled mA
IDDCPU 3.45 19 34 58.5 12.6 60.2 92.4 137

Electrical characteristics
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 Table 24. Current consumption in LPLV-Stop mode
114/218

Electrical characteristics
Conditions Typ(1) Max(2)
Symbol Parameter Unit
MPU SS Tj = Tj = Tj = Tj = Tj = Tj = Tj = Tj =
-
mode 25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C

IDD 10.0 13.0 17.5 28 15.1 22.4 37.4 74.0 µA

Supply current
IDDCORE in LPLV-Stop All Peripheral disabled CStop 1.85 12.0 21.5 40.0 6.55 38.2 62.8 98.9
mode mA
IDDCPU 1.30 8.00 14.0 26.5 4.17 25.4 41.3 64.9
1. VDDCORE = 0.9 V, VDDCPU = 0.9 V.
2. VDDCORE = 0.95 VVDDCPU = 0.95 V.

Table 25. Current consumption in LPLV-Stop2 mode

Conditions Typ(1) Max(2)
Symbol Parameter Unit
DS13876 Rev 6

MPU SS Tj = Tj = Tj = Tj = Tj = Tj = Tj = Tj =
-
mode 25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C

IDD 7.50 10.5 13.5 21.5 11.5 17.1 28.3 54.9 µA

Supply current
IDDCORE in LPLV-Stop2 All Peripheral disabled CStandby 1.80 13.0 22.0 37.5 6.6 38.3 62.8 98.9
mode mA
IDDCPU 0 0 0 0 0 0 0 0
1. VDDCORE = 0.9 V, VDDCPU = 0 V.
2. VDDCORE = 0.95 V, VDDCPU = 0 V.

STM32MP133A/D
 Table 26. Current consumption in Standby mode(1)

STM32MP133A/D
Conditions Typ Max
Symbol Parameter Unit
MPU SS Tj = Tj = Tj = Tj = Tj = Tj = Tj = Tj=
-
mode 25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C

Backup SRAM OFF,

Supply 3.65 5.95 9 16 3.91 7.63 13.1 26.6
RTC OFF, LSE OFF
current in
IDD Backup SRAM ON, CStandby µA
Standby
mode RTC ON, LSE ON, 8.2 21 33.5 56.5 17 33 57 116
medium_high drive
1. IWDG OFF, LSI OFF, VDDCORE = VDDCPU = 0 V.
DS13876 Rev 6

Electrical characteristics
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 Table 27. Current consumption in VBAT mode
116/218

Electrical characteristics
Conditions Typ Max
Symbol Parameter Unit
Tj = Tj = Tj = Tj = Tj = Tj = Tj = Tj =
- VBAT (V)
25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C

1.6 < 0.1 0.120 0.330 0.905 < 0.1 0.726 2.52 7.24
Backup SRAM OFF,
2.4 < 0.1 0.135 0.365 0.975 < 0.1 0.937 2.84 7.82
RTC OFF, LSE OFF,
LSE CSS OFF, 3 < 0.1 0.195 0.505 1.20 < 0.1 1.13 3.12 8.30
temperature
3.3 < 0.1 0.515 1.30 3.30 < 0.1 1.27 3.34 8.66
monitoring OFF
3.6 < 0.1 0.610 1.45 3.50 0.207 1.55 3.71 9.21
1.6 0.915 1.10 1.35 1.95 0.378 1.35 3.17 7.90
Backup SRAM OFF,
RTC ON, LSE ON, 2.4 1.25 1.45 1.70 2.35 0.985 2.03 3.95 8.96
medium_high drive,
3 1.55 1.80 2.15 2.95 1.79 2.79 4.78 9.95
LSE CSS OFF,
DS13876 Rev 6

temperature 3.3 1.70 2.30 3.15 5.20 2.32 3.28 5.32 10.60
monitoring OFF
Supply current 3.6 1.95 2.60 3.50 5.65 2.92 3.93 6.04 11.6
IDDVBAT µA
in VBAT mode 1.6 3.20 12.5 21.0 35.5 5.22 23.6 42.3 74.9
Backup SRAM ON,
RTC ON,. LSE ON, 2.4 3.65 13.0 22.0 36.5 6.93 27.2 46.8 81.8
medium_high drive,
3 4.05 13.5 22.5 38.5 8.07 29.4 49.2 84.8
LSE CSS OFF,
temperature 3.3 4.40 14.5 24.5 41.5 8.78 30.9 50.9 86.4
monitoring OFF
3.6 4.70 15.5 26.0 43.5 9.59 32.3 52.9 88.5
1.6 3.55 12.5 21.5 35.5 5.19 23.6 42.3 74.9
Backup SRAM ON,
2.4 3.95 13.5 22.0 37.0 5.83 25.6 45.2 79.7
RTC ON,. LSE ON,
high drive, LSE CSS 3 4.40 14.0 23.0 39.0 8.08 29.5 49.2 84.7
OFF, temperature
3.3 4.70 15.0 25.0 41.5 8.79 30.9 51.1 86.5
monitoring OFF

STM32MP133A/D
3.6 5.05 16.0 26.0 43.0 9.60 33.3 52.9 88.6
 Table 27. Current consumption in VBAT mode (continued)

STM32MP133A/D
Conditions Typ Max
Symbol Parameter Unit
Tj = Tj = Tj = Tj = Tj = Tj = Tj = Tj =
- VBAT (V)
25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C

1.6 3.55 12.5 21.0 36.0 7.95 28.0 47.9 82.3

Backup SRAM ON,
2.4 3.95 13.5 22.0 37.0 8.99 29.6 49.4 84.3
RTC ON, LSE ON,
Supply current
IDDVBAT high drive, LSE CSS 3 4.45 14.0 23.0 38.5 10.02 32.1 51.8 87.2 µA
in VBAT mode
ON, temperature
3.3 4.65 15.0 24.5 41.5 10.7 33.2 53.6 89.0
monitoring ON
3.6 5.00 16.0 26.0 43.5 11.2 35.9 55.5 90.8
DS13876 Rev 6

Electrical characteristics
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Electrical characteristics STM32MP133A/D

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 54: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.

I/O dynamic current consumption

The I/Os used by an application contribute to the current consumption. When an I/O pin
switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and
to charge/discharge the capacitive load (internal or external) connected to the pin.
The theoretical formula is provided below:

I SW = V DDx × f SW × C L

where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT

6.3.7 Wakeup time from low-power modes

The wakeup times given in Table 28 are measured starting from the wakeup event trigger up
to the first instruction executed by the MPU:
• For CSleep modes:
– the MPU goes in low-power mode after WFE (Wait For Event) instruction.
• For CStop modes:
– the MPU goes in low-power mode after WFI (Wait For Interrupt) instruction.
• WKUPx pin is used to wakeup from low-power modes.
All timings are derived from tests performed under ambient temperature and VDD = 3.3 V.

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STM32MP133A/D Electrical characteristics

Table 28. Low-power mode wakeup timings

System
Symbol Parameter Conditions (after wakeup) Typ(1) Max(1) Unit
mode

MPU wakeup
mpuss_
tWUCSLEEP MPU wakeup from
Run HSE 24 MHz, SYSRAM 31 32 ck clock
_MPU CSleep
cycles
HSI 64 MHz, SYSRAM 16 17
tWUCSTOP MPU wakeup from
Stop HSE + PLL 1000 MHz, SYSRAM 64 73
_MPU CStop
HSE + PLL 650 MHz, SYSRAM 64 73
MPU wakeup from
tWULPLV_Stop LPLV- µs
CStop with system in HSI 64 MHz, SYSRAM 410 470
_MPU Stop
LPLV-Stop (LVDS=1)
MPU wakeup from
tWULPLV_Stop2 LPLV-
CStandby with system in HSI 64 MHz, SYSRAM 9000(2) -
_MPU Stop2
LPLV-Stop2
1. Evaluated by characterization, not tested in production unless otherwise specified.
2. On exit from LPLV-Stop2 the boot ROM is activated and a branch is done to the address stored in the BSEC_SCRATCH
register. A system initialization is done which duration depends on the user application. Here are application dependent
parameters used for characterization:
- MMU description table size: 32 Bytes (could be up to 20 Kbytes for a Linux application)
- HSI frequency: 64 kHz (waking up with a fast PLL would significantly reduce tWULPLV_Stop2_MPU)
Note: branching directly to a function that toggles a GPIO would result in tWULPLV_Stop2_MPU ≈ 1500 µs.
The wakeup time will depend on the VDDCPU ramp-up time.

Table 29. Wakeup time using USART(1)

Symbol Parameter Conditions Typ Max Unit

Wakeup time needed to calculate the Stop - 6.7 µs

maximum USART baud rate allowing the
tWUUSART
wakeup from stop mode when USART LPLV-Stop - 318(2) µs
clock source is HSI.
1. Specified by design, not tested in production.
2. Including the tSEL_VDDCORETEMPO = 234 μs.

6.3.8 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
Digital and analog bypass modes are available.
The external clock signal has to respect the Table 54: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 14 for digital bypass mode and
in Figure 15 for analog bypass mode. In analog bypass mode the clock can be a sinusoidal
waveform.

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Electrical characteristics STM32MP133A/D

Table 30. High-speed external user clock characteristics

(digital bypass)(1)
Symbol Parameter Min Typ Max Unit

fHSE_ext User external clock source frequency 8 24 48 MHz

VHSEH OSC_IN input pin high level voltage 0.7×VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3×VDD
tW(HSE) OSC_IN high or low time 7 - - ns
1. Specified by design, not tested in production.

Figure 14. High-speed external clock source AC timing diagram (digital bypass)

VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t

THSE

External fHSE_ext
IL
clock source OSC_IN
STM32

ai17528b

Table 31. High-speed external user clock characteristics

(analog bypass)(1)
Symbol Parameter Min Typ Max Unit

User external clock source frequency 8 24 48 MHz

fHSE_ext duty cycle (Square wave) 45 50 55 %
duty cycle deterioration 0 ±10(2) ±20(3) %
VHSE Absolute input range 0 - VDD -
VPP OSC_IN peak-to-peak amplitude 0.2(4) - 0.67×VDD V
tSU(5) Time to start - 1 10(6) µs
Rise and Fall time
tr/tf(HSE) (10% to 90% threshold levels of the 0.05 ×THSE - 0.3 ×THSE ns
input peak-to-peak amplitude)
I(HSE) Power consumption - 150(7) 500(8) µA
1. Specified by design, not tested in production.
2. Specified by design, not tested in production: with a square wave signal (@25 °C, VDD=3.3 V /VPP =
400 mV / VDC=1 V) where VDC is the DC component of the input signal.

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STM32MP133A/D Electrical characteristics

3. Specified by design, not tested in production: with a square wave signal (@25 °C, VDD=1.71 V /VPP =
200 mV / VDC=0.8 V) where VDC is the DC component of the input signal.
4. minimum peak-to-peak amplitude (@25 °C, 0.1<VDC<VDD-0.1 V) where VDC is the DC component of the
input signal.
5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized analog
bypass clock interface is reached. This value is measured with 200 mV peak-to-peak amplitude.
6. Maximum start-up time is obtained with 200 mV peak-to-peak amplitude.
7. with a sine wave signal (VPP = 400 mV / VDC=0.4 V) where VDC is the DC component of the input signal.
8. with a sine wave signal (VDD = 3.6 V / VPP = 800 mV / VDC = 1.8 V) where VDC is the DC component of the
input signal.

Figure 15. High-speed external clock source AC timing diagram (analog bypass)
VHSE

90%

VPP

10%

THSE tr(HSE) t

External
fHSE_ext OSC_IN
clock source IL

STM32
MSv47498V1

Table 32. Low-speed external user clock characteristics

(analog bypass)(1)
Symbol Parameter Min Typ Max Unit

fLSE_ext User external clock source frequency - 32.768 - kHz

VLSE Absolute input range 0 - VSW(2) -
VPP (3)
OSC32_IN peak-to-peak amplitude 0.2 1 - V
I(LSE) Power consumption - 120 - nA
1. Specified by design, not tested in production.
2. VSW is equal to VDD when present or VBAT otherwise
3. Minimum peak-to-peak amplitude (@25 °C, 0.1 < VDC < VSW - 0.1 V) where VDC is the DC component of
the input signal.

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Electrical characteristics STM32MP133A/D

Figure 16. Low-speed external clock source AC timing diagram (analog bypass)
VLSE

VPP

TLSE t

External
fLSE_ext OSC32_IN
clock source IL

STM32
MSv63037V1

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 54: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 17 for digital bypass and Figure 16
for analog bypass.

Table 33. Low-speed external user clock characteristics (digital bypass)(1)

Symbol Parameter Min Typ Max Unit

fLSE_ext User external clock source frequency 5 32.768 40 kHz

VLSE_ext_PP OSC32_IN peak-to-peak amplitude 0.3 - VSW(2)
V
VLSE_ext OSC32_IN input range 0 - VSW(2)
tw(LSEH)
OSC32_IN high or low time for square signal input 10 - - ns
tw(LSEL)
1. Specified by design. Not tested in production.
2. VSW = VDD when VDD is above VBOR0, and VSW=VBAT when VDD is below VBOR0.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 17. AC timing diagram for low-speed external square clock source
VLSE_ext
tw(LSEH)
VLSEH
70%
VLSE_ext_PP
30%
VLSEL
t
tLSE = 1/fLSE_ext tw(LSEL)
MSv67851V3

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STM32MP133A/D Electrical characteristics

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 8 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 34. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 34. 8-48 MHz HSE oscillator characteristics(1)

Symbol Parameter Operating conditions(2) Min Typ Max Unit

F Oscillator frequency - 8 24 48 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 8
VDD = 3.3 V, Rm = 150 Ω
- 0.53 -
CL = 12 pF at 4 MHz
VDD = 3.3 V, Rm = 120 Ω
- 0.61 -
CL = 10 pF at 16 MHz
IDD(HSE) HSE current consumption VDD = 3.3 V, Rm = 100 Ω mA
- 0.63 -
CL = 10 pF at 24 MHz
VDD = 3.3 V, Rm = 80 Ω
- 0.63 -
CL = 8 pF at 32 MHz
VDD = 3.3 V, Rm = 80 Ω
- 0.81 -
CL = 8 pF at 48 MHz
Gmcritmax Maximum critical crystal gm Startup - - 1.15 mA/V
tSU(4) Start-up time VDD is stabilized - 2 - ms
1. Specified by design, not tested in production.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors,
designed for high-frequency applications, and selected to match the requirements of the
crystal or resonator (see Figure 18). CL1 and CL2 are usually the same size. The crystal
manufacturer typically specifies a load capacitance which is the series combination of CL1
and CL2. The PCB and MCU pin capacitance must be included (4 pF can be used as a
rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

DS13876 Rev 6 123/218

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Electrical characteristics STM32MP133A/D

Figure 18. Typical application with a 24 MHz crystal

CL1
OSC_IN fHSE

Bias
24 MHz
RF controlled
crystal
gain

OSC_OUT
STM32
CL2
MSv63062V1

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 35. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 35. Low-speed external user clock characteristics(1)

Symbol Parameter Operating conditions(2) Min Typ Max Unit

F Oscillator frequency - - 32.768 - kHz

LSEDRV[1:0] = 00,
- 303 -
Low drive capability
LSEDRV[1:0] = 01,
- 466 -
LSE current Medium Low drive capability
IDD nA
consumption LSEDRV[1:0] = 10,
- 636 -
Medium high drive capability
LSEDRV[1:0] = 11,
- 1028 -
High drive capability
LSEDRV[1:0] = 00,
- - 0.5
Low drive capability
LSEDRV[1:0] = 01,
- - 0.75
Maximum critical crystal Medium Low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10,
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11,
- - 2.7
High drive capability
tSU(3) Startup time VDD is stabilized - 2 - s
1. Specified by design, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

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STM32MP133A/D Electrical characteristics

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 19. Typical application with a 32.768 kHz crystal

Resonator with
integrated CL1
capacitors OSC32_IN fLSE

Bias
32.768 kHz
RF controlled
resonator
gain

OSC32_OUT STM32
CL2
ai17531d

1. Adding an external resistor between OSC32_IN and OSC32_OUT is forbidden.

6.3.9 External clock source security characteristics

Table 36. High-speed external user clock security system (HSE CSS)(1)
Symbol Parameter Min Typ Max Unit

tDCM(HSE_CSS) Time to detect clock missing - 2 - μs

tDCP(HSE_CSS) Time to detect clock presence - - 250 ns
IVDD(HSE_CSS) Power consumption (fHSE = 48 MHz) - - 50 μA
1. Specified by design, not tested in production.

6.3.10 Internal clock source characteristics

The parameters given in Table 37, Table 38 and Table 39 are derived from tests performed
under ambient temperature and VDD supply voltage conditions summarized in Table 13:
General operating conditions.

64 MHz high-speed internal RC oscillator (HSI)

Table 37. HSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI(2) HSI frequency VDD = 3.3 V, TJ = 30 °C 63.7 64 64.3 MHz

Trimming is not a multiple
- 0.24 0.33
of 32
Trimming is 128, 256 and
- -2.43 -
384

TRIM HSI user trimming step Trimming is 64, 192, 320 %

- -0.70 -
and 448
Other trimming are a
multiple of 32 (not
- -0.30 -
including multiple of 64
and 128)
DuCy(HSI) Duty Cycle - 45 - 55 %

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Electrical characteristics STM32MP133A/D

Table 37. HSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

HSI oscillator frequency drift over VDD

∆VDD (HSI) VDD = 1.71 to 3.6 V -0.12 - 0.03 %
(reference is 3.3 V)

HSI oscillator frequency drift over TJ = -20 to 110 °C -1.25 - 0.75

∆TEMP (HSI)(3) %
temperature after factory calibration TJ = -40 to 125 °C -1.75 - 0.95
HSI oscillator start-up time (Time
tsu(HSI) between Enable rising and First output - - 1.47 2 µs
clock edge.)
tstab(HSI) HSI oscillator stabilization time at 1% of target frequency - 3 - µs
IDD(HSI) HSI oscillator power consumption - - 300 400 µA
1. Specified by design, not tested in production unless otherwise specified.
2. Guaranteed by testing.
3. Evaluated by characterization, not tested in production.

4 MHz low-power internal RC oscillator (CSI)

Table 38. CSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fCSI(2) CSI frequency VDD = 3.3 V, TJ = 30 °C 3.98 4 4.02 MHz

Trimming code is not a
- 0.85 1 %
multiple of 16
TRIM Trimming step
Trimming code is a multiple of
- -1.65 - -
16
DuCy(CSI) Duty Cycle - 45 - 55 %

∆VDD (CSI) + CSI oscillator frequency drift over VDD = 1.71 to 3.6 V
- ±1.43 - %
∆TEMP (CSI)(3) VDD & drift over temperature TJ = 0 to 85 °C
tsu(CSI) CSI oscillator startup time - - 1.5 2.4 µs
CSI oscillator stabilization time
tstab(CSI) TJ = 0 to 85 °C - 5 - cycle
(to reach ±5% of fCSI)
IDD(CSI) CSI oscillator power consumption - - 30 - µA
1. Specified by design, not tested in production.
2. Guaranteed by testing.
3. Evaluated by characterization, not tested in production.

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32 kHz low-speed internal (LSI) RC oscillator

Table 39. LSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

TJ = 30 °C,(2)
31.4 32 32.6
VDD = 3.3 V
fLSI LSI frequency kHz
TJ = -40 to 125 °C,
29 32 33.6
VDD = 1.71 to 3.6 V
LSI oscillator startup time (Time
tsu(LSI) between Enable rising and First - - 64 125
output clock edge.) µs
LSI oscillator stabilization time
tstab(LSI) - - 110 170
(5% of final value)
LSI oscillator power
IDD(LSI) - - 120 230 nA
consumption
1. Specified by design, not tested in production.
2. Guaranteed by testing.

6.3.11 PLL characteristics

The parameters given in Table 41, Table 42, Table 43 are derived from tests performed
under temperature and VDD supply voltage conditions summarized in Table 13: General
operating conditions.

PLL1 characteristics

Table 40. PLL1 characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock Normal mode and Sigma delta mode 8 - 16 MHz
fPLL_IN PLL input clock
- 10 - 90 %
duty cycle
PLL P,Q,R
1000
multiplier output - 3.875 - (2) MHz
clock
Division by 1 47.5 50 52.5
fPLL_P_Q_R_ Even divisions
47.5 50 52.5
OUT (N multiple of 2)
PLL P,Q,R clock
%
duty cycle [100×
[100× [100×
Odd divisions (N+1)/
(N+1)/ (N+1)/
(N not multiple of 2) 2N] +
2N] - 5 2N]
5
PLL VCO output 496 - 1000 MHz
fVCO_OUT PLL VCO Duty Direct VCO clock after internal divider/2
47.5 50 52.5 %
Cycle

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Electrical characteristics STM32MP133A/D

Table 40. PLL1 characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Normal mode - 50 150

tLOCK PLL lock time µs
Sigma-delta mode (CKIN ≥ 8 MHz) - 65 170
Lock Accuracy
(Ratio VCO
ALOCK frequency versus - - - ±2 %
target frequency at
lock)
VCO = 992 MHz - 24(3) -
fPLL_P_Q_R_OUT division = 1
to 16 (3)
VCO = 1066 MHz - 24 -
RMS cycle-to- Without Fractional mode
VCO = 2000 MHz - 23(3) - ±ps
cycle jitter
fPLL_P_Q_R_OUT division = 1 VCO = 992 MHz - 23(3) -
to 16
With Fractional mode VCO = 2000 MHz - 24(3) -

VCO = 992 MHz - 16(3) -

fPLL_P_Q_R_OUT division = 1
to 16 (3)
VCO = 1066 MHz - 16 -
Without Fractional mode (3)
RMS period jitter VCO = 2000 MHz - 14 - ±ps
fPLL_P_Q_R_OUT division = 1 VCO = 992 MHz - 22(3) -
Jitter to 16
With Fractional mode VCO = 2000 MHz - 15(3) -

fPLL_P_Q_R_OUT division = 1 VCO = 992 MHz - 185(4) -

to 16
VCO = 1066 MHz - 180(4) -
fPLL_IN = 8 MHz
Without Fractional mode VCO = 2000 MHz - 103(4) -
Long term jitter ps
fPLL_P_Q_R_OUT division = 1 VCO = 992 MHz - 270(4) -
to 16
VCO = 1066 MHz - 260(4) -
fPLL_IN = 8 MHz
With Fractional mode VCO = 2000 MHz - 104(4) -

Peak to Peak
fVCO_OUT 1000 MHz -30 - 30 ps
Period Jitter
PLL power VCO freq = 2000 MHz - 1000 1050
IVDD_PLL(2) consumption on µA
VDD_PLL (Analog) VCO freq = 992 MHz - 560 600

PLL power VCO freq = 2000 MHz (VDDCORE = 1.26 V) - 4300 10000
IVDDCORE(2) consumption on μA
VDDCORE (Digital) VCO freq = 992 MHz (VDDCORE = 1.26 V) - 2300 7000

1. Specified by design, not tested in production unless otherwise specified.

2. Evaluated by characterization, not tested in production.
3. Measured on DDR high speed IO.
4. Measured on DDR high speed IO for 10000 output clock cycles.

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PLL2 characteristics

Table 41. PLL2 characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock Normal mode and Sigma delta mode 8 - 16 MHz
fPLL_IN PLL input clock
- 10 - 90 %
duty cycle
PLL P,Q,R
multiplier output - 3.125 - 800(2) MHz
clock
Division by 1 45 50 55
fPLL_P_Q_R_ Even divisions
45 50 55
OUT (N multiple of 2)
PLL P,Q,R clock
%
duty cycle [100×
[100× [100×
Odd divisions (N+1)/
(N+1)/ (N+1)/
(N not multiple of 2) 2N] +
2N] - 5 2N]
5
PLL VCO output 400 - 800 MHz
fVCO_OUT PLL VCO Duty Direct VCO clock after internal divider/2
45 50 55 %
Cycle
Normal mode - 50 150
tLOCK PLL lock time µs
Sigma-delta mode (CKIN ≥ 8 MHz) - 65 170
Lock Accuracy
(Ratio VCO
ALOCK frequency versus - - - ±2 %
target frequency at
lock)

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Table 41. PLL2 characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit
(3)
VCO = 800 MHz - 18 -
fPLL_P_Q_R_OUT division = 1
to 16 VCO = 1066 MHz - 14(3) -
RMS cycle-to- Without Fractional mode (3)
VCO = 1600 MHz - 12 - ±ps
cycle jitter (3)
fPLL_P_Q_R_OUT division = 1 VCO = 1066 MHz - 20 -
to 16
With Fractional mode VCO = 1600 MHz - 18(3) -

VCO = 800 MHz - 16(3) -

fPLL_P_Q_R_OUT division = 1
to 16 VCO = 1066 MHz - 12(3) -
Without Fractional mode (3)
RMS period jitter VCO = 1600 MHz - 10 - ±ps
Jitter
fPLL_P_Q_R_OUT division = 1 VCO = 1066 MHz - 16(3) -
to 16
With Fractional mode VCO = 1600 MHz - 15(3) -

fPLL_P_Q_R_OUT division = 1 VCO = 800 MHz - 225(4) -

to 16
VCO = 1066 MHz - 200(4) -
fPLL_IN = 8 MHz
Without Fractional mode VCO = 1600 MHz - 100(4) -
Long term jitter ps
fPLL_P_Q_R_OUT division = 1 VCO = 800 MHz - 350(4) -
to 16
VCO = 1066 MHz - 250(4) -
fPLL_IN = 8 MHz
With Fractional mode VCO = 1600 MHz - 150(4) -

PLL power VCO freq = 1600 MHz - 930 -

IVDD_PLL(2) consumption on µA
VDD_PLL (Analog) VCO freq = 800 MHz - 560 -

PLL power VCO freq = 1600 MHz (VDDCORE = 1.26 V) - 4200 -

IVDDCORE(2) consumption on μA
VDDCORE (Digital) VCO freq = 800 MHz (VDDCORE = 1.26 V) - 2100 -

1. Specified by design, not tested in production unless otherwise specified.

2. Evaluated by characterization, not tested in production.
3. Measured on DDR high speed IO.
4. Measured on DDR high speed IO for 10000 output clock cycles.

PLL3, PLL4 characteristics

Table 42. PLL3, PLL4 characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock Normal mode 4 - 16

MHz
- Sigma delta mode 8 - 16
fPLL_IN
PLL input clock
- 10 - 90 %
duty cycle

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Table 42. PLL3, PLL4 characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

PLL P,Q,R
multiplier output - 3.125 - 800(2) MHz
clock
fPLL_P_Q_R_ Even divisions
45 50 55
OUT (N multiple of 2)
PLL P,Q,R clock
[100× [100× [100× %
duty cycle Odd divisions
(N+1)/ (N+1)/ (N+1)/
(N not multiple of 2) 2N] - 5 2N] 2N] + 5
PLL VCO output 400 - 800 MHz
fVCO_OUT PLL VCO Duty Direct VCO clock (no internal divider/2)
40 - 60 %
Cycle
Normal mode 15 50 150
tLOCK PLL lock time µs
Sigma-delta mode (CKIN ≥ 8 MHz) 25 65 170
Lock accuracy
(Ratio VCO
ALOCK frequency versus - - - ±2 %
target frequency at
lock)
VCO = 400 MHz - 80(3) -
fPLL_P_Q_R_OUT division =
25 to 100 (3)
VCO = 600 MHz - 50 -
RMS cycle-to- Without Fractional mode (3)
VCO = 800 MHz - 45 - ±ps
cycle jitter
fPLL_P_Q_R_OUT division = VCO = 600 MHz - 65(3) -
25 to 100
With Fractional mode VCO = 800 MHz - 60(3) -

VCO = 400 MHz - 75(3) -

fPLL_P_Q_R_OUT division =
25 to 100 (3)
VCO = 600 MHz - 38 -
Without Fractional mode (3)
RMS period jitter VCO = 800 MHz - 30 - ±ps
Jitter
fPLL_P_Q_R_OUT division = VCO = 600 MHz - 55(3) -
25 to 100
With Fractional mode VCO = 800 MHz - 50(3) -

fPLL_P_Q_R_OUT division = VCO = 400 MHz - 225(4) -

25 to 100
VCO = 600 MHz - 150(4) -
fPLL_IN = 8 MHz
Without Fractional mode VCO = 800 MHz - 125(4) -
Long term jitter ps
fPLL_P_Q_R_OUT division = (4)
VCO = 400 MHz - 300 -
25 to 100
VCO = 600 MHz - 200(4) -
fPLL_IN = 8 MHz
With Fractional mode VCO = 800 MHz - 150(4) -

PLL power VCO freq = 800 MHz - 600 610

IVDD_PLL consumption on µA
VDD_PLL (Analog) VCO freq = 400 MHz - 320 350

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Table 42. PLL3, PLL4 characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

PLL power VCO freq = 800 MHz (VDDCORE = 1.26 V) - 2200 5250
IVDDCORE consumption on µA
VDDCORE (Digital) VCO freq = 400 MHz (VDDCORE = 1.26 V) - 1130 4550

1. Specified by design, not tested in production unless otherwise specified.

2. Evaluated by characterization, not tested in production.
3. Measured on GPIO.
4. Measured on GPIO for 10000 output clock cycles.

PLL_USB (2880 MHz) characteristics

Table 43. USB_PLL characteristics(1)

Symbol Parameter Condition Min Typ Max Unit

fPLL_IN PLL input clock 19.2 24 38.4 MHz

fPLL_INFIN PFD input clock 19.2 24 38.4 MHz
fPLL_OUT PLL multiplier output clock - 480 - MHz
fVCO_OUT PLL VCO output - 2880 - MHz
tLOCK PLL lock time - - 100 µs
tPDN PLL power down time 10 - - µs

IDDA1V1_R PLL power consumption on PLL in power down - 5 425 µA

EG(PLL) VDDA1V1_REG (internal connection) fVCO_OUT = 2880 MHz - 4.4 5.6 mA

IDDA1V8_R PLL power consumption on PLL in power down - - 2 µA

EG(PLL) VDDA1V8_REG (internal connection) fVCO_OUT = 2880 MHz - 2 2.5 mA
1. Specified by design, not tested in production unless otherwise specified.

6.3.12 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows the reduction of
electromagnetic interferences (see Table 49: EMI characteristics for fHSE = 24 MHz and
Fmpuss_ck = 650 MHz).

Table 44. SSCG parameters constraint

Symbol Parameter Min Typ Max(1) Unit

fMod Modulation frequency 20 - 60 kHz

md Peak modulation depth 0.25 - 2 %
MODEPER * INCSTEP - - - 215-1 -
1. Specified by design, not tested in production.

Equation 1

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The frequency modulation period (MODEPER) is given by the equation below:

MODEPER = round [ f PLL_IN ⁄ ( 4 × f Mod ) ]

fPLL_IN and fMod must be expressed in Hz.

As an example:
If fPLL_IN = 8 MHz, and fMOD = 40 kHz, the modulation depth (MODEPER) is given by
equation 1:
6 3
MODEPER = round [ 8 × 10 ⁄ 4 × 40 × 10 ] = 50

Equation 2
Equation 2 allows the increment step (INCSTEP) calculation:
15
INCSTEP = round [ ( ( 2 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ]

fVCO_OUT must be expressed in MHz.

With a modulation depth (md) = ±2% (4% peak-to-peak), and PLLN = 240 (in MHz):
15
INCSTEP = round [ ( ( 2 – 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 50 ) ] = 629md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
15
md quantized % = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2 – 1 ) × PLLN )

As a result:
15
md quantized % = ( 50 × 629 × 100 × 5 ) ⁄ ( ( 2 – 1 ) × 240 ) = 2%(peak)

Figure 20 and Figure 21 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.

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Figure 20. PLL output clock waveforms in center spread mode

Frequency (PLL_OUT)

md
F0
md

Time
tmode 2xtmode
ai17291

Figure 21. PLL output clock waveforms in down spread mode

Frequency (PLL_OUT)

F0
2xmd

Time
tmode 2xtmode
ai17292b

6.3.13 Memory characteristics

OTP characteristics
The characteristics are given at TJ = -40 to 125 °C unless otherwise specified.

Table 45. OTP characteristics

Symbol Parameter Conditions Min Max Unit

Programming - 450 µA
IVDDCORE OTP consumption on VDDCORE Reading - 490 µA
PowerDown - 4.2 µA
Programming - 10000 µA
IVDD OTP consumption on VDD Reading - 2200 µA
PowerDown - 1 µA
(1)
FOTP OTP operating Frequency - - 67 MHz
(2)
NB_CYCLE Maximum number of reading cycles - - 500 Million
1. Specified by design, not tested in production.
2. Evaluated by characterization, not tested in production.

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DDR characteristics
DDR3, DDR3L I/O DC specifications
The following table provides input and output DC threshold values and on-die-termination
(ODT) recommended values. The conditions for the output threshold values are un-
terminated outputs loaded with 1 pF capacitor load. The ODT values are measured after
impedance calibration.

Table 46. DC specifications – DDR3 or DDR3L mode(1)

Symbol Parameter Min Typ Max Unit

VIH(DC) DC input voltage high VREF + 0.09 - VDDQ V

VIL(DC) DC input voltage low VSSQ - 0.3 - VREF - 0.09 V
VOH DC output logic high 0.8 × VDDQ - - V
VOL DC output logic low - - 0.2 × VDDQ V
100 120 140
RTT Input termination resistance (ODT) to VDDQ/2 54 60 66 Ω
36 40 44
ILS Input leakage current, SSTL mode, unterminated - 0.01 4.8 μA
1. Specified by design, not tested in production.

LPDDR2, LPDDR3 I/O DC specifications

The following table provides input and output DC threshold values. The conditions for the
output threshold values are un-terminated outputs loaded with 1 pF capacitor load.

Table 47. DC specifications – LPDDR2 or LPDDR3 mode(1)

Symbol Parameter Min Typ Max Unit

VIH(DC) DC input voltage high VREF + 0.13 - VDDQ V

VIL(DC) DC input voltage low VSSQ - VREF - 0.13 V
VOH DC output logic high 0.9 × VDDQ - - V
VOL DC output logic low - - 0.1 × VDDQ V
ILEAK Input leakage current - 0.01 4.51 μA
1. Specified by design, not tested in production.

6.3.14 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

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Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: a burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 48. They are based on the EMS levels and classes
defined in application note AN1709 available from the ST website www.st.com.

Table 48. EMS characteristics

Level/
Symbol Parameter Conditions
Class

Voltage limits to be applied on any I/O pin to induce a

VFESD 2B
functional disturbance VDD = 3.3 V, TA = +25 °C, TFBGA320,
Fast transient voltage burst limits to be applied Fmpuss_ck = 650 or 1000 MHz,
VFTB through 100 pF on V and V pins to induce a conforms to IEC 61000-4-2 5A
DD SS
functional disturbance

As a consequence, it is recommended to add a serial resistor (1 kΩ), located as close as

possible to the STM32MP133 device, to the pins exposed to noise (connected to tracks
longer than 50 mm on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.

Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)

Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened

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to prevent unrecoverable errors occurring (see application note AN1015 available from the
ST website www.st.com.).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.

Table 49. EMI characteristics for fHSE = 24 MHz and Fmpuss_ck = 650 MHz
Monitored
Symbol Parameter Conditions Value Unit
frequency band

0.1 to 30 MHz 4
VDD = 3.6 V, TA = 25 °C, 30 to 130 MHz 8
Peak(1) TFBFGA320 package, dBµV
SEMI conforming to IEC61967-2 130 MHz to 1 GHz 21
1 GHz to 2 GHz 16

Level(2) - 0.1 MHz to 2 GHz 3.5 -

1. Refer to AN1709 "EMI radiated test" section.

2. Refer to AN1709 "EMI level classification" section.

Table 50. EMI characteristics for fHSE = 24 MHz and Fmpuss_ck = 1 GHz
Monitored
Symbol Parameter Conditions Value Unit
frequency band

0.1 to 30 MHz 4
VDD = 3.6 V, TA = 25 °C, 30 to 130 MHz 16
Peak(1) TFBFGA320 package, dBµV
SEMI conforming to IEC61967-2 130 MHz to 1 GHz 19
1 GHz to 2 GHz 20

Level(2) - 0.1 MHz to 2 GHz 4 -

1. Refer to AN1709 "EMI radiated test" section.

2. Refer to AN1709 "EMI level classification" section.

6.3.15 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.

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Table 51. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)

Electrostatic discharge TA = +25 °C conforming

VESD(HBM) voltage (human body to ANSI/ESDA/JEDEC All 2 2000
model) JS-001
V
Electrostatic discharge TA = +25 °C conforming
VESD(CDM) voltage (charge device to ANSI/ESDA/JEDEC All C2a 500
model) JS-002
1. Evaluated by characterization, not tested in production.

Static latchup
Two complementary static tests are required on three parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.

Table 52. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latchup class 130 °C conforming to JESD78 II level A

6.3.16 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
product operation. However, in order to give an indication of the robustness of the device in
cases when an abnormal injection accidentally happens, susceptibility tests are performed
on a sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.

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Table 53. I/O current injection susceptibility(1)

Negative Positive
Symbol Description Unit
injection injection

PB5, PE13 0 NA
IINJ mA
All other FTxx I/Os 5 NA

1. Evaluated by characterization, not tested in production.

6.3.17 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 54: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 13: General
operating conditions. All I/Os are CMOS and TTL compliant.

Table 54. I/O static characteristics

Symbol Parameter Condition Min Typ Max Unit

- - 0.3 × VDD(1)
VIL I/O input low level voltage 1.71 V < VDD < 3.6 V 0.39 x VDD - V
- -
0.07(2)
0.7 × VDD(1) - -
VIH I/O input high level voltage 1.71 V < VDD < 3.6 V 0.45 × VDD + V
- -
0.35(2)
TT_xx, FT_xxx and NRST I/O 0.1 ×
VHYS 1.71 V < VDD < 3.6 V - - mV
input hysteresis VDD
0 < VIN ≤ Max(VDD)(5) - - 250
FT_xx input leakage current Max(VDD) < VIN ≤ 5.5 V
(3)(4)(5) - - 3500

Ileak 0 < VIN ≤ Max(VDD)(5) - - 500 nA

FT_u, IO Max(VDD) < VIN ≤ 5.5 V
(3)(4)(5) - - 5000(6)

TT_xx input leakage current 0 < VIN ≤ Max(VDD) (5) - - 100

RPU Weak pull-up equivalent resistor(7) VIN=VSS 25 40 55
Weak pull-down equivalent kΩ
RPD VIN=VDD(5) 25 40 55
resistor(7)
CIO I/O pin capacitance - - 5 - pF
1. Compliant with CMOS requirements.
2. Specified by Design, not tested in production.
3. All FT_xx IO except FT_uf, FT_u.
4. VIN must be less than Max(VDD) + 3.6 V.
5. Max(VDD) is the maximum value of all the I/O supplies.
6. To sustain a voltage higher than MIN(VDD, VDDA, VDD3V3_USBHS) +0.3 V, the internal pull-up and pull-down resistors must
be disabled.

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7. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 22.

Figure 22. VIL/VIH for FT I/Os

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run mode
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
∑IVDD (see Table 11).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run mode
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
∑IVSS (see Table 11).

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Output voltage levels

Unless otherwise specified, the parameters given in Table 55 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 13: General operating conditions. All I/Os are CMOS and TTL compliant.

Table 55. Output voltage characteristics for all I/Os except PC13, PC14, PC15, PI0 PI1, PI2, PI3(1)
Symbol Parameter Conditions(3) Min Max Unit

CMOS port(2)
VOL Output low level voltage IIO = 8 mA - 0.4
2.0 V ≤ VDD ≤ 3.6 V
CMOS port(2)
VOH Output high level voltage IIO = -8 mA VDD-0.4 -
2.0 V ≤ VDD ≤ 3.6 V
TTL port(2)
VOL(3) Output low level voltage IIO = 8 mA - 0.4
2.0 V ≤ VDD ≤ 3.6 V
TTL port(2)
VOH (3) Output high level voltage IIO = -8 mA 2.4 -
2.0 V ≤ VDD ≤ 3.6 V
IIO = 20 mA
VOL(3) Output low level voltage - 1.3
2.7 V ≤ VDD ≤ 3.6 V
V
IIO = -20 mA
VOH(3) Output high level voltage VDD-1.3 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 1 mA
- 0.2
1.71 V ≤ VDD ≤ 3.6 V
VOL(3) Output low level voltage
IIO = 4 mA
- 0.45
1.71 V ≤ VDD ≤ 3.6 V
IIO = -1 mA
VDD-0.2 -
1.71 V ≤ VDD ≤ 3.6 V
(3)
VOH Output high level voltage
IIO = -4 mA
VDD-0.45 -
1.71 V ≤ VDD ≤ 3.6 V
IIO = 20 mA
- 0.4
Output low level voltage for an FT_f 2.7 V ≤ VDD ≤ 3.6 V
VOLFM+(3)
IO pin in FM+ mode I = 10 mA IO
- 0.4
1.71 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 10:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ∑IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design, not tested in production.

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Table 56. Output voltage characteristics for PC13, PC14, PC15, PI0, PI1, PI2, PI3(1)
Symbol Parameter Conditions(3) Min Max Unit

CMOS port(2)
VOL Output low level voltage IIO = 3 mA - 0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2)
VOH Output high level voltage IIO = -3 mA VDD − 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2)
VOL(3) Output low level voltage IIO = 3 mA - 0.4
V
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2)
VOH (2)
Output high level voltage IIO = -3 mA 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 1.5 mA
VOL(2) Output low level voltage - 0.4
1.71 V ≤ VDD ≤ 3.6 V
IIO = -1.5 mA
VOH(2) Output high level voltage VDD − 0.4 -
1.71 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 10:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design, not tested in production.

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Output buffer timing characteristics (HSLV option disabled)

Table 57. Output timing characteristics (HSLV OFF)(1)(2)

Speed Symbol Parameter conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 19

C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 21
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 23
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 25
Fmax(3) Maximum frequency MHz
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 5
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 5
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 5
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 5
00
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 12
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 10
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 9
Output high to low level C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 8
tr/tf(4) fall time and output low ns
to high level rise time C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 22
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 19
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 17
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 15
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 33
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 44
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 55
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 66
Fmax(3) Maximum frequency MHz
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 15
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 15
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 15
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 15
01
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 6.2
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.2
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 4.5
Output high to low level C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.6
tr/tf(4) fall time and output low ns
to high level rise time C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 11.0
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 9.0
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 8.0
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 7.0

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Table 57. Output timing characteristics (HSLV OFF)(1)(2) (continued)

Speed Symbol Parameter conditions Min Max Unit
(5)
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 83
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 100
(5)
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 133
(5)
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 166
Fmax(3) Maximum frequency MHz
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V (5)
- 32
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 37
(5)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 42
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V (5)
- 50
10
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 3.5
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 2.7
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 2.2
Output high to low level C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 1.6
tr/tf(4) fall time and output low ns
to high level rise time C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 6.6
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 5.0
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 4.2
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 3.3
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 133
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 166
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 200
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 233
Fmax(3) Maximum frequency MHz
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 45
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 50
(5)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 55
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 60
11
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 2.9
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 2.0
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 1.7
Output high to low level C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V(5) - 1.3
tr/tf(4) fall time and output low ns
(5)
to high level rise time C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 5.4
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 4.0
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 3.3
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(5) - 2.5
1. Specified by design, not tested in production.
2. GPIO under VSW domain (PC13, PC14, PC15, PI0, PI1, PI2, PI3) are frequency limited. The maximum frequency is
2 MHz with a maximum load of 30 pF. Only one I/O at a time can be used as GPIO output and these I/Os must not be used
as a current source (e.g to drive a LED). For theses IOs, the speed value must be kept to (default) 00.

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3. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3, skew ≤ 1/20 T and 45% < duty cycle < 55%.
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform,
respectively.
5. Compensation system enabled.

Output buffer timing characteristics (IO structure with _h, HSLV option
enabled)
The HSLVEN bits of SYSCFG_HSLVENxR register (together with OTP bit
PRODUCT_BELOW_2V5) can be used to optimize the I/O speed when the product voltage
is below 2.5 V typ. (2.7 V max.).

Table 58. Output timing characteristics (HSLV ON, _h IO structure)(1)

Speed Symbol Parameter conditions Min Max Unit

C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 21

C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 23
Fmax(2) Maximum frequency MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 25
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 27
00
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 12.5
Output high to low level C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 10.5
tr/tf(3) fall time and output low ns
to high level rise time C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 9
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 7.5
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 33
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 44
Fmax(2) Maximum frequency MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 55
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 66
01
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 7.3
Output high to low level C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 5.7
tr/tf(3) fall time and output low ns
to high level rise time C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 4.8
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 3.8
(4)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 66
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 90
Fmax(2) Maximum frequency MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 110
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 133
10
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 5.0
Output high to low level C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 3.5
tr/tf(3) fall time and output low ns
to high level rise time C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 2.7
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 2.0

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Table 58. Output timing characteristics (HSLV ON, _h IO structure)(1) (continued)

Speed Symbol Parameter conditions Min Max Unit
(4)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 100
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 133
Fmax(2) Maximum frequency MHz
(4)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 166
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 200
11
(4)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 4.6
Output high to low level C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 3.1
tr/tf(3) fall time and output low ns
(4)
to high level rise time C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 2.4
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 1.7
1. Specified by design, not tested in production.
2. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3, skew ≤ 1/20 T and 45% < duty cycle < 55%.
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform,
respectively.
4. Compensation system enabled.

Output buffer timing characteristics (IO structure with _vh, HSLV option
disabled)

Table 59. Output timing characteristics (HSLV OFF, _vh IO structure)(1)

Speed Symbol Parameter conditions Min Max Unit

C = 10, 20, 30, 50 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 17

Fmax(2) Maximum frequency MHz
C = 10, 20, 30, 50 pF, 1.71 V ≤ VDDIOX ≤ 2.7 V - 5
00 Output high to low C = 10, 20, 30, 50 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 12
level fall time and
tr/tf(3) ns
output low to high C = 10, 20, 30, 50 pF, 1.71 V ≤ VDDIOX ≤ 2.7 V - 22
level rise time
C = 50 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 33
C = 30 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 44
Fmax (2) Maximum frequency C = 20 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 55 MHz
C = 10 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 66
C = 10, 20, 30, 50 pF, 1.71 V ≤ VDDIOX ≤ 2.7 V - 15
01
C = 50 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 6.2
Output high to low C = 30 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 5.2
(3) level fall time and
tr/tf C = 20 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 4.5 ns
output low to high
level rise time C = 10 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 3.6
C = 10, 20, 30, 50 pF, 1.71 V ≤ VDDIOX ≤ 2.7 V - 11.0

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Table 59. Output timing characteristics (HSLV OFF, _vh IO structure)(1) (continued)
Speed Symbol Parameter conditions Min Max Unit
(4)
C = 50 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 83
C = 30 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 100
(2) (4)
Fmax Maximum frequency C = 20 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 133 MHz
(4)
C = 10 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 166
C = 10, 20, 30, 50 pF, 1.71 V ≤ VDDIOX ≤ 2.0 V (4)
- 30
10
C = 50 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 3.5
(4)
Output high to low C = 30 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V - 2.7
level fall time and
tr/tf(3) C = 20 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V (4)
- 2.2 ns
output low to high
level rise time C = 10 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 1.6
C = 10, 20, 30, 50 pF, 1.71 V ≤ VDDIOX ≤ 2.0 V(4) - 6.6
C = 50 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 133
C = 30 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 166
Fmax (2) Maximum frequency C = 20 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 200 MHz
C = 10 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 233
C = 10, 20, 30, 50 pF, 1.71 V ≤ VDDIOX ≤ 2.0 V(4) - 45
11
C = 50 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 2.9
Output high to low C = 30 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 2.0
level fall time and
tr/tf(3) C = 20 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 1.7 ns
output low to high
level rise time C = 10 pF, 2.7 V ≤ VDDIOX ≤ 3.6 V(4) - 1.3
C = 10, 20, 30, 50 pF, 1.71 V ≤ VDDIOX ≤ 2.0 V(4) - 5.4
1. Specified by design, not tested in production.
2. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3, skew ≤ 1/20 T and 45% < Duty cycle < 55%.
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform,
respectively.
4. Compensation system enabled.

Output buffer timing characteristics (IO structure with _vh, HSLV option
enabled)
The HSLVEN bits of SYSCFG_HSLVENxR register (together with OTP bit
PRODUCT_BELOW_2V5) can be used to optimize the I/O speed when the product voltage
is below 2.5 V typ. (2.7 V max.).

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Table 60. Output timing characteristics (HSLV ON, _vh IO structure)(1)

Speed Symbol Parameter conditions Min Max Unit

C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 25

C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 30
Fmax(2) Maximum frequency MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 35
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 40
00
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 9.5
Output high to low level C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 7.7
tr/tf(3) fall time and output low ns
to high level rise time C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 6.6
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 5.4
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 44
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 55
Fmax(2) Maximum frequency MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 66
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 77
01
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 6.5
Output high to low level C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V - 4.9
tr/tf(3) fall time and output low ns
to high level rise time C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V - 4.1
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V - 3.1
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 66
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 90
Fmax(2) Maximum frequency MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 110
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 133
10
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 5.1
Output high to low level C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 3.6
tr/tf(3) fall time and output low ns
to high level rise time C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 2.8
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 2.1
(4)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V - 110
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 150
Fmax(2) Maximum frequency MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V (4)
- 190
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 233
11
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 4.5
Output high to low level C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 3.0
tr/tf(3) fall time and output low ns
to high level rise time C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 2.2
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4) - 1.5
1. Specified by design, not tested in production.
2. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3, skew ≤ 1/20 T and 45% < Duty cycle < 55%.
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform,
respectively.

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4. Compensation system enabled.

6.3.18 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 54: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 13: General operating conditions.

Table 61. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

Weak pull-up equivalent

RPU(2) VIN = VSS 30 40 50 kΩ
resistor(1)
VF(NRST)(2) NRST input filtered pulse 1.71 V < VDD < 3.6 V - - 50
ns
(2)
VNF(NRST) NRST input not filtered pulse 1.71 V < VDD < 3.6 V 350 - -
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
2. Specified by design, not tested in production.

Figure 23. Recommended NRST pin protection

VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter

0.1 μF

STM32

ai14132d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 54. Otherwise the reset is not taken into account by the device.

6.3.19 FMC characteristics

Unless otherwise specified, the parameters given in Table 62 to Table 75 for the FMC
interface are derived from tests performed under the ambient temperature, Fmc_hclk (Fhclk6)
frequency and VDD supply voltage conditions summarized in Table 13: General operating
conditions, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5×VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.

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Asynchronous waveforms and timings

Figure 24 through Figure 27 represent asynchronous waveforms and Table 62 through
Table 69 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• DataHoldTime = 0x1 (1×Tfmc_ker_ck for read operations and 2×Tfmc_ker_ck for write
operations)
• ByteLaneSetup = 0x1
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.

Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

tw(NE)

FMC_NE

tv(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

tv(A_NE) t h(A_NOE)

FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)

FMC_NBL[1:0]

t h(Data_NE)

t su(Data_NOE) th(Data_NOE)

t su(Data_NE)

FMC_D[15:0] Data

t v(NADV_NE)

tw(NADV)

FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32753V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

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Table 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3Tfmc_ker_ck-1 3Tfmc_ker_ck+0.5

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 1
tw(NOE) FMC_NOE low time 2Tfmc_ker_ck-1 2Tfmc_ker_ck+0.5
th(NE_NOE) FMC_NOE high to FMC_NE high hold time Tfmc_ker_ck-1 -
tv(A_NE) FMC_NEx low to FMC_A valid - 1
th(A_NOE) Address hold time after FMC_NOE high 2Tfmc_ker_ck-1 -
ns
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck+15.5 -
tsu(Data_NOE) Data to FMC_NOEx high setup time 16 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+1
1. Evaluated by characterization, not tested in production.

Table 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1)(2)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 7Tfmc_ker_ck-0.5 7Tfmc_ker_ck+1

tw(NOE) FMC_NWE low time 6Tfmc_ker_ck-0.5 6Tfmc_ker_ck+1
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck - ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 7Tfmc_ker_ck+2 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 5Tfmc_ker_ck -
1. Evaluated by characterization, not tested in production.
2. NWAIT pulse width is equal to 1 AHB cycle.

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Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)

FMC_NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)

FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)

FMC_D[15:0] Data
t v(NADV_NE)

tw(NADV)
FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32754V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4Tfmc_ker_ck-0.5 4Tfmc_ker_ck+0.5

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck-0.5 Tfmc_ker_ck+1
tw(NWE) FMC_NWE low time Tfmc_ker_ck-0.5 Tfmc_ker_ck+0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time 2Tfmc_ker_ck-0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high 3Tfmc_ker_ck-1 -
ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high 3Tfmc_ker_ck-0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - 3.5
th(Data_NWE) Data hold time after FMC_NWE high 2Tfmc_ker_ck-1 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+1
1. Evaluated by characterization, not tested in production.

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Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8Tfmc_ker_ck-0.5 8Tfmc_ker_ck+0.5

tw(NWE) FMC_NWE low time 5Tfmc_ker_ck-0.5 5Tfmc_ker_ck+1
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 8Tfmc_ker_ck+4 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 6Tfmc_ker_ck -
1. Evaluated by characterization, not tested in production.
2. NWAIT pulse width is equal to 1 AHB cycle.

Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)

FMC_ NE
tv(NOE_NE) t h(NE_NOE)

FMC_NOE

t w(NOE)

FMC_NWE

tv(A_NE) th(A_NOE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)
tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32755V1

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Table 66. Asynchronous multiplexed PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4Tfmc_ker_ck-0.5 4Tfmc_ker_ck+1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck-0.5 2Tfmc_ker_ck+1
ttw(NOE) FMC_NOE low time Tfmc_ker_ck-0.5 Tfmc_ker_ck+0.5
th(NE_NOE) FMC_NOE high to FMC_NE high hold time Tfmc_ker_ck-1 -
tv(A_NE) FMC_NEx low to FMC_A valid - 4
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time Tfmc_ker_ck Tfmc_ker_ck+1
FMC_AD(address) valid hold time after ns
th(AD_NADV) Tfmc_ker_ck-3 -
FMC_NADV high
Address held
th(A_NOE) Address hold time after FMC_NOE high until next read -
operation
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck+15 -
tsu(Data_NOE) Data to FMC_NOE high setup time 16 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
1. Evaluated by characterization, not tested in production.

Table 67. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8Tfmc_ker_ck-0.5 8Tfmc_ker_ck+1

tw(NOE) FMC_NWE low time 5Tfmc_ker_ck-0.5 5Tfmc_ker_ck+1
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 7Tfmc_ker_ck+2 - ns

FMC_NEx hold time after FMC_NWAIT

th(NE_NWAIT) 5Tfmc_ker_ck -
invalid
1. Evaluated by characterization, not tested in production.

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Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)

FMC_ NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NWE)

FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)

tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32756V1

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Table 68. Asynchronous multiplexed PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 5Tfmc_ker_ck-0.5 5Tfmc_ker_ck+1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck-0.5 Tfmc_ker_ck+1
tw(NWE) FMC_NWE low time 2Tfmc_ker_ck-1 2Tfmc_ker_ck+0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time 2Tfmc_ker_ck-0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time Tfmc_ker_ck+0.5 Tfmc_ker_ck+1.5
ns
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck+0.5 -
Address held
th(A_NWE) Address hold time after FMC_NWE high until next write -
operation
th(BL_NWE) FMC_BL hold time after FMC_NWE high 3Tfmc_ker_ck-1 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck+5
th(Data_NWE) Data hold time after FMC_NWE high 2Tfmc_ker_ck+0.5 -
1. Evaluated by characterization, not tested in production.

Table 69. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9Tfmc_ker_ck-0.5 9Tfmc_ker_ck+0.5

tw(NWE) FMC_NWE low time 6Tfmc_ker_ck-0.5 6Tfmc_ker_ck+1 ns

tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 8Tfmc_ker_ck+4 -

th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 6Tfmc_ker_ck -
1. Evaluated by characterization, not tested in production.

Synchronous waveforms and timings

Figure 28 through Figure 31 represent synchronous waveforms and Table 70 through
Table 73 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR flash; DataLatency = 0 for PSRAM
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:

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Conditions: synchronous read or write, NWAIT enabled

• 2.7 V < VDD < 3.6 V, FMC_CLK = 48 MHz at 20 pF
• 1.71 V < VDD < 2.7 V, FMC_CLK = 30 MHz at 20 pF
Conditions: synchronous read, NWAIT disabled
• 2.7 V < VDD < 3.6 V, FMC_CLK = 54 MHz at 20 pF
• 1.71 V < VDD < 2.7 V, FMC_CLK = 34 MHz at 20 pF
Conditions: synchronous write, NWAIT disabled
• 2.7 V < VDD < 3.6 V, FMC_CLK = 130 MHz at 20 pF
• 1.71 V < VDD < 2.7 V, FMC_CLK = 78 MHz at 20 pF

Figure 28. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK
Data latency = 0 (2 cycles)
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE

td(CLKL-ADIV)
td(CLKL-ADV) tsu(ADV-CLKH)
th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2

td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx

td(NExL-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL = 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL = 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V3

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Table 70. Synchronous multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period R×Tfmc_ker_ck-1(2) -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0..2) R×Tfmc_ker_ck/2+0.5(2) -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16..25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16..25) R×Tfmc_ker_ck/2+1.5(2) -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high R×Tfmc_ker_ck /2(2) - ns

td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3

td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 1 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -
((DATLAT+2.5)
td(NExL-NWAITV) FMC_NEx low to FMC_NWAIT active (x=0..2) -
× tw(CLK)) - 4
1. Evaluated by characterization, not tested in production.
2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).

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Figure 29. Synchronous multiplexed PSRAM write timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK
Data latency = 0 (2 cycles)
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE

td(CLKL-Data)
td(CLKL-ADIV)
td(CLKL-ADV)
FMC_AD[15:0] AD[15:0] D1 D2

td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx

td(NExL-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

FMC_NWAIT
(WAITCFG = 0b,
WAITPOL = 0b)
td(CLKH-NBLH)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
FMC_NBL

Expected sampling edge at memory side

MS32758V3

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Table 71. Synchronous multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period, VDD range = 2.7 to 3.6 V R×Tfmc_ker_ck-1(2) -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
(2)
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0..2) R×Tfmc_ker_ck/2+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16..25) - 1
td(CLKH-AIV) (2)
FMC_CLK high to FMC_Ax invalid (x=16..25) R×Tfmc_ker_ck/2+1.5 -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high R×Tfmc_ker_ck /2+0.5(2) -
ns
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 1.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 1 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1 -
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high R×Tfmc_ker_ck /2+0.5(2) -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -
((DATLAT+2.5)
td(NExL-NWAITV) FMC_NEx low to FMC_NWAIT active (x=0..2) -
× tw(CLK)) - 4
1. Evaluated by characterization, not tested in production.
2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).

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Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK
Data latency = 0 (2 cycles)
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE

tsu(ADV-CLKH) th(CLKH-ADV)

FMC_D[15:0] D1 D2

td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx

td(NExL-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL = 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL = 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V3

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Table 72. Synchronous non-multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period R×Tfmc_ker_ck-1(2) -

t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
(2)
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0..2) R×Tfmc_ker_ck/2+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=0..25) - 1
td(CLKH-AIV) (2)
FMC_CLK high to FMC_Ax invalid (x=0..25) R×Tfmc_ker_ck/2+1.5 -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2 ns

td(CLKH-NOEH) FMC_CLK high to FMC_NOE high R×Tfmc_ker_ck/2+1.5(2) -

tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 3 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 1 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -
((DATLAT+2.5)
td(NExL-NWAITV) FMC_NEx low to FMC_NWAIT active (x=0..2) -
× tw(CLK)) - 4
1. Evaluated by characterization, not tested in production.
2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).

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Figure 31. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK
Data latency = 0 (2 cycles)
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE

td(CLKL-ADIV) td(CLKL-Data)

FMC_D[15:0] D1 D2

td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx

td(NExL-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

FMC_NWAIT
(WAITCFG = 0b,
WAITPOL = 0b)
td(CLKH-NBLH)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
FMC_NBL

Expected sampling edge at memory side

MS32760V3

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Table 73. Synchronous non-multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

t(CLK) FMC_CLK period R×Tfmc_ker_ck -1(2) -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
(2)
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0..2) R×Tfmc_ker_ck/2+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=0..25) - 1
td(CLKH-AIV) (2)
FMC_CLK high to FMC_Ax invalid (x=0..25) R×Tfmc_ker_ck/2+1.5 -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1
ns
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high R×Tfmc_ker_ck /2+0.5(2) -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1 -
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high R×Tfmc_ker_ck/2+0.5(2) -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -
((DATLAT+2.5)
td(NExL-NWAITV) FMC_NEx low to FMC_NWAIT active (x=0..2) -
× tw(CLK)) - 4
1. Evaluated by characterization, not tested in production.
2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).

NAND controller waveforms and timings

Figure 32 and Figure 33 represent synchronous waveforms, and Table 74 and Table 75
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
• FMC_SetupTime = 0x01
• FMC_WaitSetupTime = 0x03
• FMC_HoldSetupTime = 0x02
• FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
• CL = 30 pF
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.

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Figure 32. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)

FMC_NOE (NRE)

tsu(D-NOE) th(NOE-D)

FMC_D[y:0]

MSv73150V1

1. y = 7 or 15 depending on the NAND flash memory interface.

Figure 33. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) tw(NWE) th(NWE-ALE)

FMC_NWE

FMC_NOE (NRE)

td(D-NWE)

tv(NWE-D) th(NWE-D)

FMC_D[y:0]

MSv73151V1

1. y = 7 or 15 depending on the NAND flash memory interface.

Table 74. Switching characteristics for NAND flash read cycles(1)

Symbol Parameter Min Max Unit

tw(N0E) FMC_NOE low width 4Tfmc_ker_ck-1 4Tfmc_ker_ck+1

tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 11 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 2Tfmc_ker_ck+1
th(NOE-ALE) FMC_NOE high to FMC_ALE invalid 3Tfmc_ker_ck+0.5 -
1. Evaluated by characterization, not tested in production.

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Table 75. Switching characteristics for NAND flash write cycles(1)

Symbol Parameter Min Max Unit

tw(NWE) FMC_NWE low width 4Tfmc_ker_ck-1 4Tfmc_ker_ck+1

tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3Tfmc_ker_ck -
ns
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 4Tfmc_ker_ck-3.5 -
td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 2Tfmc_ker_ck+1
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 3Tfmc_ker_ck+0.5 -
1. Evaluated by characterization, not tested in production.

6.3.20 QUADSPI interface characteristics

Unless otherwise specified, the parameters given in Table 76 and Table 77 for QUADSPI
are derived from tests performed under the ambient temperature, Faxiss_ck frequency and
VDD supply voltage conditions summarized in Table 13: General operating conditions, with
the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5×VDD
• I/O compensation cell enabled
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics.

Table 76. QUADSPI characteristics in SDR mode

Symbol Parameter Conditions Min Typ Max Unit

2.7 V ≤ VDD < 3.6 V

- - 166
CL = 20 pF
Fck1/t(CLK) QUADSPI clock frequency MHz
1.71 V < VDD <3.6 V
- - 90
CL = 15 pF
tw(CLKH) QUADSPI clock high and low t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
-
tw(CLKL) time t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
ts(IN) Data input setup time - 2.5 - -
ns
th(IN) Data input hold time - 1.5 - -
tv(OUT) Data output valid time - - 1 1.5
th(OUT) Data output hold time - 0 - -

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Table 77. QUADSPI characteristics in DDR mode

Symbol Parameter Conditions Min Typ Max Unit

2.7 V < VDD < 3.6 V

- - 90
QUADSPI clock CL=20 pF
Fck1/t(CLK) MHz
frequency 1.71 V < VDD < 3.6 V
- - 90
CL=15 pF
tw(CLKH) QUADSPI clock high and - t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
tw(CLKL) low time - t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
tsr(IN), tsf(IN) Data input setup time - 2 - -
thr(IN), thf(IN) Data input hold time - 1.5 - -
DHHC = 0 - 1 1.5 ns
tvr(OUT),
Data output valid time DHHC = 1
tvf(OUT) - t(CLK)/4+1 t(CLK)/4+1.5
Pres = 1, 2...
DHHC = 0 0 - -
thr(OUT),
Data output hold time DHHC = 1
thf(OUT) t(CLK)/4 - -
Pres = 1, 2...

Figure 34. QUADSPI timing diagram - SDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V3

Figure 35. QUADSPI timing diagram - DDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output D0 D1 D2 D3 D4 D5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input D0 D1 D2 D3 D4 D5

MSv36879V4

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Electrical characteristics STM32MP133A/D

6.3.21 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 78 for the delay block are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 13: General operating conditions.

Table 78. Dynamics characteristics: Delay block characteristics

Symbol Parameter Conditions Min Typ Max Unit

tinit Initial delay - 350 500 800

ps
t∆ Unit Delay - 37 40 43

6.3.22 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 79, Table 80 and Table 81 are
derived from tests performed under the ambient temperature and VDDA supply voltage
conditions summarized in Table 13: General operating conditions. In Table 79, Table 80 and
Table 81, fADC refers to fadc_ker_ck.
Note: When both ADCs are used, the kernel clock should be the same for both ADCs and the
embedded ADC prescalers cannot be used.

168/218 DS13876 Rev 6

 Table 79. 12-bit ADC characteristics(1)(2)

STM32MP133A/D
Symbol Parameter Conditions Min Typ Max Unit

Analog power supply for ADC

VDDA - 1.62 - 3.6
ON
V
VREF+ Positive reference voltage VDDA ≥ VREF+ 1.62 - VDDA
VREF- Negative reference voltage - VSSA - -
fADC ADC clock frequency 1,62 V ≤ VDDA ≤ 3.6 V 1.5 - 75 MHz
1.8 V ≤ VDDA ≤ 3.6 V
- - 5.00
Continuous fADC = 75 MHz
mode(3) 1.62 V ≤ VDDA ≤ 3.6 V
Resolution = 12 bits - - 4.66
fADC = 70 MHz
–40 °C ≤ TJ ≤ 125 °C
SMP = 2.5 2.4 V ≤ VDDA ≤ 3.6 V
Single or - - 4.00
fADC = 60 MHz(4)
Discontinuous
DS13876 Rev 6

mode 1.62 V ≤ VDDA ≤ 3.6V

- - 3.33
fADC = 50 MHz(4)
Continuous 1.62 V ≤ VDDA ≤ 3.6V
- - 5.77
Sampling rate for fast channels mode(3) fADC = 75 MHz
fS Resolution = 10 bits MSPS
(VIN[0:5])
2.4 V ≤ VDDA ≤ 3.6 V
–40 °C ≤ TJ ≤ 125 °C Single or - - 5.77
fADC = 75 MHz(4)
SMP = 2.5 Discontinuous
mode 1.62 V ≤ VDDA ≤ 3.6V
- - 5.00
fADC = 65 MHz(4)
Resolution = 8 bits
1.62 V ≤ VDDA ≤ 3.6V
–40 °C ≤ TJ ≤ 125 °C All modes(3) - - 6.82

Electrical characteristics
fADC = 75 MHz
SMP = 2.5
Resolution = 6 bits
1.62 V ≤ VDDA ≤ 3.6V
–40 °C ≤ TJ ≤ 125 °C All modes(3) - - 8.33
fADC = 75 MHz
SMP = 2.5
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 Table 79. 12-bit ADC characteristics(1)(2) (continued)
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Electrical characteristics
Symbol Parameter Conditions Min Typ Max Unit

Resolution = 12 bits
–40 °C ≤ TJ ≤ 125 °C - - 2.3
SMP = 2.5
fADC = 35 MHz(4)
Resolution = 10 bits
–40 °C ≤ TJ ≤ 125 °C - - 2.7
SMP = 2.5
fS Sampling rate for slow channels - MSPS
Resolution = 8 bits
–40 °C ≤ TJ ≤ 125 °C - - 4.5
SMP = 2.5
fADC = 50 MHz(4)
Resolution = 6 bits
–40 °C ≤ TJ ≤ 125 °C - - 5.5
SMP = 2.5
DS13876 Rev 6

tTRIG External trigger period Resolution = 12 bits - - 15 1/fADC

VAIN Conversion voltage range - 0 - VREF+
V
VCMIV Common mode input voltage Differential mode VREF/2− 10% VREF/2 VREF/2+ 10%
Resolution = 12 bits, TJ = 125 °C - - 220
Resolution = 10 bits, TJ = 125 °C - - 2100
RAIN(5) External input impedance Ω
Resolution = 8 bits, TJ = 125 °C - - 12000
Resolution = 6 bits, TJ = 125 °C - - 80000
Internal sample and hold
CADC - - 3 - pF
capacitor
tADC
VREG_ ADC LDO startup time - - 5 10 µs

STM32MP133A/D
STUP

con-
tSTAB ADC power-up time LDO already started 1 - - version
cycle
 Table 79. 12-bit ADC characteristics(1)(2) (continued)

STM32MP133A/D
Symbol Parameter Conditions Min Typ Max Unit

tOFF_
Offset calibration time - 135
CAL

CKMODE = 00 1.5 2 2.5

Trigger conversion latency for CKMODE = 01 - - 2.5
tLATR regular and injected channels
without aborting the conversion CKMODE = 10 - - 2.5
CKMODE = 11 - - 2.25
CKMODE = 00 2.5 3 3.5 1/fADC
Trigger conversion latency for
tLATR regular and injected channels CKMODE = 01 - - 3.5
INJ when a regular conversion is CKMODE = 10 - - 3.5
aborted
CKMODE = 11 - - 3.25
time(6)
DS13876 Rev 6

tS Sampling - 2.5 - 640.5

Total conversion time (including
tCONV N-bits resolution tS + 0.5 + N - -
sampling time)
fS= 5 MSPS - 540 -
IDDA_D ADC consumption on VDDA and
fS= 1 MSPS - 190 -
(ADC) VREF, Differential mode
fS=0.1 MSPS - 49 -
µA
fS= 5 MSPS - 416 -
IDDA_SE ADC consumption on VDDA and
fS= 1 MSPS - 153 -
(ADC) VREF, Single-ended mode
fS= 0.1 MSPS - 46 -

Electrical characteristics
fADC = 75 MHz - 180 -
fADC = 50 MHz - 135 -

IDD fADC = 25 MHz - 90 -

ADC consumption on VDD µA
(ADC) fADC = 12.5 MHz - 45 -
fADC = 6.25 MHz - 22 -
171/218

fADC = 3.125 MHz - 11 -

1. Specified by design, not tested in production.
172/218

Electrical characteristics
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. The conversion of the first element in the group is excluded.
4. fADC value corresponds to the maximum frequency that can be reached considering a 2.5 sampling period. For other SMPy sampling periods, the maximum frequency is
fADC value * SMPy / 2.5 with a limitation to 75 MHz.
5. The tolerance is 2 LSBs for 12-bit, 10-bit and 8-bit resolutions. It is otherwise specified.
6. The sampling time can vary depending on the condition with ±0.5 clock cycles. Resulting in minimum of 2.0 cycles and maximum of 641 cycles. Refer to the detailed
description in the reference manual.
DS13876 Rev 6

STM32MP133A/D
STM32MP133A/D Electrical characteristics

Table 80. Minimum sampling time vs RAIN (12-bit ADC)(1)(2)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channels(3) Slow channels(4)

47 3.75E-08 6.12E-08
68 3.94E-08 6.25E-08
100 4.36E-08 6.51E-08
150 5.11E-08 7.00E-08
12 bits
220 6.54E-08 7.86E-08
330 8.80E-08 9.57E-08
470 1.17E-07 1.23E-07
680 1.60E-07 1.65E-07
47 3.19E-08 5.17E-08
68 3.35E-08 5.28E-08
100 3.66E-08 5.45E-08
150 4.35E-08 5.83E-08
220 5.43E-08 6.50E-08
330 7.18E-08 7.89E-08
10 bits
470 9.46E-08 1.00E-07
680 1.28E-07 1.33E-07
1000 1.81E-07 1.83E-07
1500 2.63E-07 2.63E-07
2200 3.79E-07 3.76E-07
3300 5.57E-07 5.52E-07
47 2.64E-08 4.17E-08
68 2.76E-08 4.24E-08
100 3.02E-08 4.39E-08
150 3.51E-08 4.66E-08
220 4.27E-08 5.13E-08
330 5.52E-08 6.19E-08
8 bits 470 7.17E-08 7.72E-08
680 9.68E-08 1.00E-07
1000 1.34E-07 1.37E-07
1500 1.93E-07 1.94E-07
2200 2.76E-07 2.74E-07
3300 4.06E-07 4.01E-07
4700 5.73E-07 5.62E-07

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Table 80. Minimum sampling time vs RAIN (12-bit ADC)(1)(2) (continued)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channels(3) Slow channels(4)

6800 8.21E-07 7.99E-07

8 bits
10000 1.20E-06 1.17E-06
(continued)
15000 1.79E-06 1.74E-06
47 2.14E-08 3.16E-08
68 2.23E-08 3.21E-08
100 2.40E-08 3.31E-08
150 2.68E-08 3.52E-08
220 3.13E-08 3.87E-08
330 3.89E-08 4.51E-08
470 4.88E-08 5.39E-08
680 6.38E-08 6.79E-08
6 bits
1000 8.70E-08 8.97E-08
1500 1.23E-07 1.24E-07
2200 1.73E-07 1.73E-07
3300 2.53E-07 2.49E-07
4700 3.53E-07 3.45E-07
6800 5.04E-07 4.90E-07
10000 7.34E-07 7.11E-07
15000 1.09E-06 1.05E-06
1. Specified by design, not tested in production.
2. Data valid up to 130 °C, with a 22 pF PCB capacitor and VDDA = 1.62 V.
3. Fast channels correspond to ADCx_INx[0:5].
4. Slow channels correspond to all ADC inputs except for the Fast channels.

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Table 81. 12-bit ADC accuracy(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Fast and slow Single ended - ±3.5 ±12

ET Total unadjusted error
channel Differential - ±2.5 ±5
Single ended - ±3 ±5.5
EO Offset error
Differential - ±2 ±3.5
Single ended - ±3.5 ±11
EG Gain error ±LSB
Differential - ±2.5 ±5
Single ended - ±0.75 +1.5/-1
ED Differential linearity error
Differential - ±0.75 +2.5/-1

Fast and slow Single ended - ±2 ±4.5

EL Integral linearity error
channel Differential - ±1 ±2
Single ended - 10.8 -
ENOB Effective number of bits bits
Differential - 11.5 -

Signal-to-noise and Single ended - 68 -

SINAD
distortion ratio Differential - 71 -
Single ended - 70 -
SNR Signal-to-noise ratio dB
Differential - 72 -
Single ended - -70 -
THD Total harmonic distortion
Differential - -80 -
1. Evaluated by characterization, not tested in production.
2. ADC DC accuracy values are measured after internal calibration in Continuous mode.

Figure 36. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+

VSSA

MSv19880V6

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Electrical characteristics STM32MP133A/D

Figure 37. Typical connection diagram using the ADC with FT/TT pins
featuring analog switch function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
(2)
Cparasitic Ilkg(3) CADC
VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to Table 79 and Table 80 for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 54: I/O static characteristics). A high Cparasitic value downgrades
conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 54: I/O static characteristics for value of Ileak.
4. Refer to Figure 10: Power supply scheme.

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6.3.23 Voltage reference buffer characteristics

Table 82. VREFBUF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VSCALE = 000 2.8 3.3 3.6

VSCALE = 001 2.4 - 3.6
Normal mode
VSCALE = 010 2.1 - 3.6
VSCALE = 011 1.95 - 3.6
VDDA Analog supply voltage
VSCALE = 000 1.62 - 2.80
VSCALE = 001 1.62 - 2.40
Degraded mode(2)
VSCALE = 010 1.62 - 2.10
VSCALE = 011 1.62 - 1.95
VSCALE = 000 2.497 2.5 2.503
Normal mode
@30 °C VSCALE = 001 2.045 2.048 2.051
@Iload = 10 uA VSCALE = 010 1.798 1.8 1.802
VDDA = 3.3 V
VSCALE = 011 1.648 1.65 1.652
V
Min
(VDDA-
VSCALE = 000 - 2.502
0.22,
2.498)

VREFBUF Voltage Reference Min

Buffer Output (VDDA-
_OUT VSCALE = 001 - 2.051
0.22,
2.047)
Degraded mode(2)
Min
(VDDA-
VSCALE = 010 - 1.807
0.22,
1.800)
Min
(VDDA-
VSCALE = 011 - 1.657
0.22,
1.65)
TRIM Trim step resolution - - - ±0.05 - %
CL Load capacitor - - 0.5 1 1.50 uF
Equivalent Serial
esr - - - - 2 Ω
Resistor of CL
Iload Static load current - - - - 4 mA
Iload = 500 µA - 200 -
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V ppm/V
Iload = 4 mA - 100 -
500 µA ≤ ILOAD ≤ ppm/
Iload_reg Load regulation Normal Mode - 50 -
4 mA mA

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Electrical characteristics STM32MP133A/D

Table 82. VREFBUF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Tcoeff_
Temperature VREF ppm/
Tcoeff -40 °C < TJ < +125 °C - - -
coefficient INT °C
+75
DC - - 60 -
PSRR Power supply rejection dB
100 kHz - - 40 -
CL = 0.5 µF - - 300 350
tSTART Start-up time(3) CL = 1 µF - - 500 650 µs
CL = 1.5 µF - - 650 800
Control of maximum
DC current drive on
IINRUSH - - 8 13.5 mA
VREFBUF_OUT during
startup phase(4)
ILOAD = 0 µA - - 15 16
VREFBUF
IDDA(VRE
consumption from ILOAD = 500 µA - - 16 21 µA
FBUF) VDDA
ILOAD = 4 mA - - 32 41
RVREF
Pull-down resistor
BUF_PullD - - 100 - Ω
when ENVR = HIZ = 0
own

1. Specified by design, not tested in production.

2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA-drop voltage).
3. if VREF+ pin has residual voltage when VREFBUF is enabled (VREFBUF_CSR.ENVR=1), this might create an overshoot
on VREFBUF output longer than tSTART.
To avoid this, it is necessary that VREF+ pin is correctly discharged before being enabled (below VREFBUF_OUT minus
1 V, for example below 1.5 V for VSCALE = 000)
This could be achieved by ensuring VREFBUF is in OFF mode (VREFBUF_CSR.ENVR=0 and VREFBUF_CSR.HIZ=0) for
sufficient time to discharge CL through VREFBUF pull-down.
4. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be
in the range of 1.95 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.

6.3.24 Temperature sensor characteristics

Table 83. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

VSENSE linearity with temperature (from Vsensor

- - ±3
TL(1) voltage) °C
VSENSE linearity with temperature (from ADC counter) - - ±3
Average slope (from Vsensor voltage) - 2 -
Avg_Slope(2) mV/°C
Average slope (from ADC counter) - 2 -
V30(3) Voltage at 30 °C ± 5 °C - 0.62 - V
(1)
tstart_run Startup time in Run mode (buffer startup) 5.3 - 40.5
µs
tS_temp(1) ADC sampling time when reading the temperature 9.8 - -

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Table 83. Temperature sensor characteristics (continued)

Symbol Parameter Min Typ Max Unit

Isens(1) Sensor consumption 0.11 0.18 0.31

µA
Isensbuf(1) Sensor buffer consumption 2.3 3.8 6.1
1. Specified by design, not tested in production.
2. Evaluated by characterization, not tested in production.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.

Table 84. Temperature sensor calibration values

Symbol Parameter Memory address

TS ADC raw data acquired at temperature of

TS_CAL1 30 °C ±5 °C 0x5C00 525C[15:0](1)(2)
VDDA = VREF+ = 3.3 V ±10 mV
TS ADC raw data acquired at temperature of
TS_CAL2 130 °C ±2 °C 0x5C00 525C[31:16](1)(2)
VDDA = VREF+ = 3.3 V ±10 mV
1. It is mandatory to read a 32-bit word and to do relevant masking and shifting to isolate the required bits.
2. This address is located inside the BSEC and the access is allowed after being enabled in the RCC.

6.3.25 DTS characteristics

Table 85. DTS characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Output Clock frequency (PTAT

fDTS - - 500 - kHz
clock)
TSLOPE Average slope - - 1600 - Hz/°C
Linearity with temperature (from
TL VDDCORE = 1.25 V - - ±3.8 °C
Output clock frequency).
TTOTAL_ Temperature:
Temperature measurement error -5 - +5 °C
ERROR -40 to 125 °C
TVDD Additional error due to VDDCORE
- - 10 - °C/V
CORE variation
tTRIM Calibration time - 2 - - ms
Wake-up time from off state until
tWAKE_UP - - 50 - μs
DTS ready signal = 1
IDDCORE_DTS DTS consumption on VDDCORE - - 20 - µA
1. Specified by design, not tested in production.

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Electrical characteristics STM32MP133A/D

6.3.26 VBAT ADC monitoring characteristics and charging characteristics

Table 86. VBAT ADC monitoring characteristics(1)

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 4×26 - kΩ

Q Ratio on VBAT measurement - 4 - -
(2)
Er Error on Q –10 - +10 %
tS_vbat(2) ADC sampling time when reading VBAT input 9.8 - - µs
1. 1.20 V ≤ VBAT ≤ 3.6 V
2. Specified by design, not tested in production.

Table 87. VBAT charging characteristics

Symbol Parameter Condition Min Typ Max Unit

VBRS in PWR_CR3= 0 - 5 -
RBC Battery charging resistor kΩ
VBRS in PWR_CR3= 1 - 1.5 -

6.3.27 VDDCORE, VDDCPU, VDDQ_DDR monitoring characteristics

Table 88. VDDCORE, VDDCPU, VDDQ_DDR monitoring characteristics

Symbol Parameter Min Typ Max Unit

ADC sampling time when reading VDDCORE

tS_vddcore(1) 1 - - μs
input
tS_vddcpu(1) ADC sampling time when reading VDDCPU input 1 - - μs
ADC sampling time when reading VDDQ_DDR
tS_vddq_ddr(1) 1 - - μs
input
1. Specified by design, not tested in production.

6.3.28 Voltage booster for analog switch

Table 89. Voltage booster for analog switch characteristics

Symbol Parameter Condition Min Typ Max Unit

VDD Supply voltage - 1.71 - 3.6 V

tSU(BOOST) Booster startup time - - - 50 µs
1.71 V ≤ VDD ≤ 2.7 V - - 125
IDD(BOOST) Booster consumption µA
2.7 V < VDD < 3.6 V - - 250

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6.3.29 Compensation cell

Table 90. Compensation cell characteristics

Symbol Parameter Condition Min Typ Max Unit

VDD current consumption 1.71 V ≤ VDD ≤ 2.7 V - - 3.5

ICOMPCELL mA
during code calculation 2.7 V < VDD < 3.6 V - - 10

Time needed for code 1.71 V ≤ VDD ≤ 2.7 V - - 300

TREADY µs
calculation 2.7 V < VDD < 3.6 V - - 250

6.3.30 Digital filter for sigma-delta modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 91 for DFSDM are derived from
tests performed under the ambient temperature, fpclkx frequency and VDD supply voltage
summarized in Table 13: General operating conditions, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5×VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for
DFSDMx).

Table 91. DFSDM measured timing

Symbol Parameter Conditions Min Typ Max Unit

fDFSDMCLK DFSDM clock 1.71 V < VDD < 3.6 V - - fSYSCLK

SPI mode (SITP[1:0]=0,1),
External clock mode
- - 33
(SPICKSEL[1:0]=0),
1.71 V < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
External clock mode
- - 33
(SPICKSEL[1:0]=0),
fCKIN Input clock 2.7 < VDD < 3.6 V
(1/TCKIN) frequency SPI mode (SITP[1:0]=0,1), MHz
Internal clock mode
- - 33
(SPICKSEL[1:0]≠0),
1.71 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
Internal clock mode
- - 33
(SPICKSEL[1:0]≠0),
2.7 < VDD < 3.6 V
Output clock
fCKOUT 1.71 < VDD < 3.6 V - - 33
frequency
Output clock
DuCyCKOUT frequency duty 1.71 < VDD < 3.6 V 45 50 55 %
cycle

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Electrical characteristics STM32MP133A/D

Table 91. DFSDM measured timing (continued)

Symbol Parameter Conditions Min Typ Max Unit

SPI mode (SITP[1:0]=0,1),

twh(CKIN) Input clock high External clock mode
TCKIN/2 - 0.5 TCKIN/2 -
twl(CKIN) and low time (SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
Data input setup External clock mode
tsu 1 - -
time (SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1), ns
Data input hold External clock mode
th 1 - -
time (SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
Manchester mode
Manchester data (SITP[1:0]=2,3),
(CKOUTDIV+1) (2×CKOUTDIV)
TManchester period (recovered Internal clock mode -
×TDFSDMCLK(1) × TDFSDMCLK(1)
clock period) (SPICKSEL[1:0]≠0),
1.71 < VDD < 3.6 V
1. See DFSDM section in Reference manual for definition of CKOUTDIV.

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Figure 38. Channel transceiver timing diagrams

CKINy (SPICKSEL=0)
SPI timing : SPICKSEL = 0

twl twh tr tf
tsu th

SITP = 00
DATINy

tsu th

SITP = 01

SPICKSEL=3
CKOUT

SPICKSEL=2
SPI timing : SPICKSEL = 1, 2, 3

SPICKSEL=1

twl twh tr tf
tsu th

SITP = 0
DATINy

tsu th

SITP = 1

SITP = 2
DATINy
Manchester timing

SITP = 3

recovered clock

recovered data 0 0 1 1 0
MS30766V3

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Electrical characteristics STM32MP133A/D

6.3.31 Timer characteristics

The parameters given in Table 92 are specified by design, not tested in production.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 92. TIMx characteristics(1)(2)

Symbol Parameter Min Max Unit

tres(TIM) Timer resolution time 1 - tTIMxCLK

fTIMxCLK Timer kernel clock 0 209
MHz
fEXT Timer external clock frequency on CH1 to CH4 0 fTIMxCLK/2
ResTIM Timer resolution - 16/32 bit
Maximum possible count with 16-bit counters 65536
tMAX_COUNT Maximum possible count with 32-bit counter - 65536 × tTIMxCLK
(TIM2, TIM5) 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Specified by design, not tested in production.

Table 93. LPTIMx characteristics(1)(2)

Symbol Parameter Min Max Unit

tres(TIM) Timer resolution time 1 - tTIMxCLK

fLPTIMxCLK Timer kernel clock 0 104.5
Timer external clock frequency on Input1 and fLPTIMxCLK/ MHz
fEXT 0
Input2 2
ResTIM Timer resolution - 16 bit
tMAX_COUNT Maximum possible count - 65536 tTIMxCLK
1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers.
2. Specified by design, not tested in production.

6.3.32 Communications interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are specified by design, not tested in production, when the
I2C peripheral is properly configured and when the i2c_ker_ck frequency is greater than the
minimum shown in the table below:

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The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDD is disabled, but is still present.
• The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load Cload supported in Fm+, which is given by these formulas:
tr(SDA/SCL) = 0.8473 × Rp × Cload
Rp(min) = (VDD-VOL(max))/IOL(max)
Where Rp is the I2C lines pull-up. Refer to Section 6.3.17: I/O port characteristics for the I2C
I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 94 for the analog filter
characteristics:

Table 94. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

Maximum pulse width of spikes that

tAF 50(2) 120(3) ns
are suppressed by the analog filter
1. Specified by design, not tested in production.
2. Spikes with widths below tAF(min) are filtered.
At -40 °C it is possible to have 40 ns instead of 50 ns as minimum pulse width.
3. Spikes with widths above tAF(max) are not filtered.

The I2C pins can be set in FM+ mode in SYSCFG_PMCR register.

Unless otherwise specified, the parameters given in Table 95 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 13: General operating conditions.

Table 95. I2C FM+ pin characteristics

Symbol Parameter Conditions Min Max Unit

Fmax(1) Maximum frequency C = 50 pF - 1 MHz

Tf(2) Output high to low level fall time 1.71 ≤ VDD ≤ 3.6 V - 5 ns
1. The maximum frequency is defined with the following conditions:
- (Tr + Tf) ≤ ⅔T
- 45% < duty cycle < 55%.
2. The fall time is defined between 70% and 30% of the output waveform accordingl to I2C specification NXP
UM10204 rev- Oct 2012.

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 96 for the SPI interface are
derived from tests performed under the ambient temperature, fpclkx frequency and VDD

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supply voltage conditions summarized in Table 13: General operating conditions, with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5×VDD
• I/O compensation cell enabled
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 96. SPI dynamic characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode
1.71 V ≤ VDD ≤ 3.6 V 100
SPI1,2,3,4
Master mode
1.71 V ≤ VDD ≤ 3.6 V 52
SPI5
Slave receiver mode
1.71 V ≤ VDD ≤ 3.6 V 100
fSCK SPI clock frequency - - MHz
SPI1,2,3,4
Slave receiver mode
1.71 V ≤ VDD ≤ 3.6 V 52
SPI5
Slave mode transmitter/full duplex
38(2)
2.7 V ≤ VDD ≤ 3.6 V
Slave mode transmitter/full duplex
35(2)
1.71 V ≤ VDD ≤ 3.6 V
tsu(NSS) NSS setup time 2 - -
Slave mode
th(NSS) NSS hold time 2 - -
ns
tw(SCKH),
SCK high and low time Master mode Tpclk - 1 Tpclk Tpclk + 1
tw(SCKL)

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Table 96. SPI dynamic characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

tsu(MI) Master mode 4 - -

Data input setup time
tsu(SI) Slave mode 1 - -
th(MI) Master mode 1.5 - -
Data input hold time
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time Slave mode 8.5 10 16
tdis(SO) Data output disable time Slave mode 4.5 5 7.5
Slave mode ns
- 10 13
2.7 V ≤ VDD ≤ 3.6 V
tv(SO)
Data output valid time Slave mode
- 11 14
1.71 V ≤ VDD ≤ 3.6 V
tv(MO) Master mode - 1.5 2
Slave mode
th(SO) 8 - -
Data output hold time 1.71 V ≤ VDD ≤ 3.6 V
th(MO) Master mode 1 - -
1. Evaluated by characterization, not tested in production.
2. Maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a manager
having tsu(MI) = 0 while Duty(SCK) = 50%.

Figure 39. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH)
CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V2

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Figure 40. SPI timing diagram - slave mode and CPHA = 1(1)

NSS input

tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V2

1. Measurement points are done at 0.5×VDD and with external CL = 30 pF.

Figure 41. SPI timing diagram - master mode(1)

High

NSS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output

CPOL=0

CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output

CPOL=0

CPHA=1
CPOL=1
tsu(MI) th(MI)

MISO input First bit IN Next bits IN Last bit IN

MOSI output First bit OUT Next bits OUT Last bit OUT

tv(MO) th(MO)
MSv72626V1

1. Measurement points are done at 0.5×VDD and with external CL = 30 pF.

I2S interface characteristics

Unless otherwise specified, the parameters given in Table 97 for the I2S interface are
derived from tests performed under the ambient temperature, fpclkx frequency and VDD

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supply voltage conditions summarized in Table 13: General operating conditions, with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5×VDD
• I/O compensation cell enabled
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).

Table 97. I2S dynamic characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK I2S main clock output - 256×8K 256×Fs MHz

Master data - 64×Fs
fCK I2S clock frequency MHz
Slave data - 64×Fs
tv(WS) WS valid time Master mode - 2
th(WS) WS hold time Master mode 1 -
tsu(WS) WS setup time Slave mode 3.5 -
th(WS) WS hold time Slave mode 1 -
tsu(SD_MR) Master receiver 3.5 -
Data input setup time
tsu(SD_SR) Slave receiver 2 -
ns
th(SD_MR) Master receiver 1 -
Data input hold time
th(SD_SR) Slave receiver 1 -
tv(SD_ST) Slave transmitter (after enable edge) - 10
Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 1
th(SD_ST) Slave transmitter (after enable edge) 1 -
Data output hold time
th(SD_MT) Master transmitter (after enable edge) 0.5 -
1. Evaluated by characterization, not tested in production.

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Figure 42. I2S slave timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

Figure 43. I2S master timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

SAI characteristics
Unless otherwise specified, the parameters given in Table 98 for SAI are derived from tests
performed under the ambient temperature, Fpclk2 frequency and VDD supply voltage

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conditions summarized in Table 13: General operating conditions, with the following
configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are performed at CMOS levels: 0.5×VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).

Table 98. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK SAI Main clock output - - 50 MHz

Master transmitter
- 45
2.7 V ≤ VDD ≤ 3.6 V
Master transmitter
- 27
1.71 V ≤ VDD ≤ 3.6 V
Master receiver
- 27
SAI bit clock 1.71 V ≤ VDD ≤ 3.6 V
FCK MHz
frequency(2) Slave transmitter
- 43
2.7 V ≤ VDD ≤ 3.6 V
Slave transmitter
- 30
1.71 V ≤ VDD ≤ 3.6 V
Slave receiver
- 50
1.71 ≤ VDD ≤ 3.6 V
Master mode
- 11
2.7 V ≤ VDD ≤ 3.6 V
tv(FS) FS valid time
Master mode
- 18
1.71 V ≤ VDD ≤ 3.6 V
tsu(FS) FS setup time Slave mode 6.5 -
Master mode 2 - ns
th(FS) FS hold time
Slave mode 2 -
tsu(SD_A_MR) Master receiver 3.5 -
Data input setup time
tsu(SD_B_SR) Slave receiver 2 -
th(SD_A_MR) Master receiver 1 -
Data input hold time
th(SD_B_SR) Slave receiver 0.5 -

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Table 98. SAI characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

Slave transmitter (after enable edge)

- 11.5
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge)
- 16.5
1.71 V ≤ VDD ≤ 3.6 V
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 8 -
ns
Master transmitter (after enable edge)
- 10
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
- 18
1.71 V ≤ VDD ≤ 3.6 V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 6.5 -
1. Evaluated by characterization, not tested in production.
2. APB clock frequency must be at least twice SAI clock frequency.

Figure 44. SAI master timing waveforms

1/fSCK

SAI_SCK_X
(CKSTR = 0)

SAI_SCK_X
(CKSTR = 1)
th(FS)

SAI_FS_X
(output)
tv(FS) tv(SD_MT) th(SD_MT)

SAI_SD_X
(transmit) Slot n Slot n+2

tsu(SD_MR) th(SD_MR)

SAI_SD_X
(receive) Slot n

MS32771V2

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Figure 45. SAI slave timing waveforms

1/fSCK

SAI_SCK_X
(CKSTR = 0)
SAI_SCK_X
(CKSTR = 1)

tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X
(input)
tsu(FS) tv(SD_ST) th(SD_ST)

SAI_SD_X Slot n Slot n+2

(transmit)
tsu(SD_SR) th(SD_SR)

SAI_SD_X
Slot n
(receive)
MS32772V2

SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 99 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, Fhclk6 frequency and VDD
supply voltage conditions summarized in Table 13: General operating conditions, with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5×VDD
• I/O compensation cell enabled
• HSLV activated when VDD ≤ 2.7 V
• Delay block disabled
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.

Table 99. Dynamics characteristics: SD characteristics, VDD = 1.71 V to 3.6 V(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Clock frequency in data transfer 2.7 < VDD < 3.6 V - - 130
fPP MHz
mode 1.71 < VDD < 1.9 V - - 105
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fPP =52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP =52 MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in SD HS/SDR/DDR mode

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Table 99. Dynamics characteristics: SD characteristics, VDD = 1.71 V to 3.6 V(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

tISU Input setup time HS - 2.5 - -

tIHD Input hold time HS - 0.5 - - ns
Tidw(3) Input valid window (variable window) - 2.5 - -
CMD, D outputs (referenced to CK) in SD HS/SDR/DDR mode
tOV Output valid time HS - - 5 6
ns
tOH Output hold time HS - 4.5 - -
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD - 2.5 - -
ns
tIHD Input hold time SD - 0.5 - -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD - - 0.5 1 ns

tOHD Output hold default time SD - 0 - -

1. Data based on characterization results, not tested in production.

2. Above 100 MHz, CL applied is 20 pF.
3. The minimum window of time where the data need to be stable for proper sampling in tuning mode.

Table 100. Dynamics characteristics: e•MMC characteristics VDD = 1.71 V to 3.6 V(1)(2)
Symbol Parameter Conditions Min Typ Max Unit

Clock frequency in data transfer 2.7 < VDD < 3.6 V - - 130
fPP MHz
mode 1.71 < VDD < 1.9 V - - 105
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fPP =52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP =52 MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in e•MMC mode
tISU Input setup time HS - 2.5 - -
tIH Input hold time HS - 0.5 - - ns
Tidw(3) Input valid window (variable window) - 2.5 - -
CMD, D outputs (referenced to CK) in e•MMC mode
tOV Output valid time HS - - 5 6
ns
tOH Output hold time HS - 4 - -
1. ata based on characterization results, not tested in production.
2. CLOAD = 20 pF.
3. The minimum window of time where the data need to be stable for proper sampling in tuning mode.

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Figure 46. SD high-speed mode

tC(CK)
tW(CKH) tW(CKL)

CK
tOH
tOV

D, CMD output
tIH
tISU

D, CMD input
MSv69709V1

Figure 47. SD default mode

CK
tOV tOH

D, CMD output MSv69710V1

Figure 48. SDMMC DDR mode

D input Valid data Valid data

tISU tIH tISU tIH

tW(CKH)

CK

tW(CKL)
tOV tOV
tOH tOH

D output Valid data Valid data

MSv69158V1

FDCAN (controller area network) interface

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (FDCANx_TX and FDCANx_RX).

Ethernet (ETH) characteristics

Unless otherwise specified, the parameters given in Table 101, Table 102, Table 103 and
Table 104 for MDIO/SMA, RMII, RGMII and MII are derived from tests performed under the

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ambient temperature, Faxiss_ck frequency summarized in Table 13: General operating

conditions, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5×VDD.
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Table 101 gives the list of Ethernet MAC timings for the MDIO/SMA and Figure 49 shows
the corresponding timing diagram.

Table 101. Dynamics characteristics: Ethernet MAC timings for MDIO/SMA(1)

Symbol Parameter Min Typ Max Unit

tMDC MDC cycle time(2.5 MHz) 399 400 401

Td(MDIO) Write data valid time 0.5 1 3.5
ns
tsu(MDIO) Read data setup time 17.5 - -
th(MDIO) Read data hold time 0 - -
1. Evaluated by characterization, not tested in production.

Figure 49. Ethernet MDIO/SMA timing diagram

tMDC

ETH_MDC

td(MDIO)

ETH_MDIO(O)

tsu(MDIO) th(MDIO)

ETH_MDIO(I)

MS31384V1

Table 102 gives the list of Ethernet MAC timings for the RMII and Figure 50 shows the
corresponding timing diagram.

Table 102. Dynamics characteristics: Ethernet MAC timings for RMII(1)

Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 2 - -

tih(RXD) Receive data hold time 1.5 - -
tsu(CRS) Carrier sense setup time 1.5 - -
ns
tih(CRS) Carrier sense hold time 1.5 - -
td(TXEN) Transmit enable valid delay time 5.5 8.5 10.5
td(TXD) Transmit data valid delay time 6 8.5 11
1. Evaluated by characterization, not tested in production.

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Figure 50. Ethernet RMII timing diagram

RMII_REF_CLK

td(TXEN)
td(TXD)

RMII_TX_EN
RMII_TXD[1:0]

tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)

RMII_RXD[1:0]
RMII_CRS_DV

ai15667b

Table 103 gives the list of Ethernet MAC timings for MII and Figure 51 shows the
corresponding timing diagram.

Table 103. Dynamics characteristics: Ethernet MAC timings for MII(1)

Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 1.5 - -

tih(RXD) Receive data hold time 1.5 - -
tsu(DV) Data valid setup time 1 - -
tih(DV) Data valid hold time 1.5 - -
ns
tsu(ER) Error setup time 1.5 - -
tih(ER) Error hold time 1 - -
td(TXEN) Transmit enable valid delay time 7 9 12
td(TXD) Transmit data valid delay time 7 9 12
1. Evaluated by characterization, not tested in production.

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Figure 51. Ethernet MII timing diagram

MII_RX_CLK

tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)

MII_RXD[3:0]
MII_RX_DV
MII_RX_ER

MII_TX_CLK

td(TXEN)
td(TXD)

MII_TX_EN
MII_TXD[3:0]

ai15668b

Table 104. Dynamics characteristics: Ethernet MAC signals for RGMII (1)
Symbol Rating Min Typ Max Unit

tsu(RXD) Receive data setup time 1 - -

tih(RXD) Receive data hold time 1.5 - -
tsu(RX_CTL) Receive control valid setup time 1 - -
ns
tih(RX_CTL) Receive control valid hold time 1.5 - -
TskewT(TX_CTL) Transmit control valid delay time -0.25 0.25 0.5
TskewT(TXD) Transmit data valid delay time -0.25 0.25 0.5
1. Evaluated by characterization, not tested in production.

Figure 52. Ethernet RGMII timing diagram

tskewT

RGMII_GTX_CLK

RGMII_TXD[3:0]
RGMII_TX_CTL

tsu tih

RGMII_RX_CLK

RGMII_RXD[3:0]
RGMII_RX_CTL
MSv50971V2

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6.3.33 USART (SPI mode) interface characteristics

Unless otherwise specified, the parameters given in Table 105 for USART are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
conditions summarized in Table 105, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5×VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).

Table 105. USART (SPI mode) characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

SPI master mode - - 13

fCK USART clock frequency MHz
SPI slave mode - - 27
tsu(NSS) NSS setup time SPI slave mode tker+2 - - ns
th(NSS) NSS hold time SPI slave mode 2 - - ns
tw(CKH),
CK high and low time SPI master mode 1/fCK/2 - 1 1/fck/2 1/fCK/2 + 1 ns
tw(CKL)
SPI master mode 16 - -
tsu(RX) Data input setup time ns
SPI slave mode 2.5 - -
SPI master mode 0.5 - -
thRX) Data input hold time ns
SPI slave mode 1 - -
SPI slave mode - 10 18
tv(TX) Data output valid time ns
SPI master mode - 1.5 2.5
SPI slave mode 8 - -
th(TX) Data output hold time ns
SPI master mode 0 - -
1. 1.Evaluated by characterization, not tested in production.

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Figure 53. USART timing diagram in SPI master mode

1/fCK
tw(CKH)
CPHA=0
CK output CPOL=0

CPHA=0
CPOL=1
tw(CKL)
CPHA=1
CK output

CPOL=0

CPHA=1
CPOL=1
tsu(RX) th(RX)

RX input MSB IN BIT6 IN LSB IN

TX output MSB OUT BIT1 OUT LSB OUT

tv(TX) th(TX) MSv65386V6

Figure 54. USART timing diagram in SPI slave mode

NSS input

1/fCK th(NSS)

tsu(NSS) tw(CKH)
CPHA=0
CPOL=0
CK input

CPHA=0
CPOL=1
tw(CKL) tv(TX) th(TX)

TX output First bit OUT Next bits OUT Last bit OUT

tsu(RX) th(RX)

RX input First bit IN Next bits IN Last bit IN

MSv65387V6

6.3.34 USB High-Speed PHY characteristics

Table 106. USB High-Speed PHY characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

RREF Reference resistor on USB_RREF pin - 2.97 3.00 3.03 kΩ

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Table 106. USB High-Speed PHY characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

One USB port - 1.4 -

High-Speed TX(2)
Two USB ports - 2.4 -
IDDA1V1_REG(PHY) One USB port - 5.4 - mA
High-Speed RX(3) / Idle
Two USB ports - 10.4 -
Ful-Speed and Low-Speed mode (Suspend, TX or RX) - 0 -
One USB port - 25.5 -
High-Speed TX(2)
Two USB ports - 50.5 -
IDDA1V8_REG(PHY) One USB port - 2.5 - mA
High-Speed RX(3) / Idle
Two USB ports - 5.5 -
Ful-Speed and Low-Speed mode (Suspend, TX or RX) - 0 -
One USB port - 5 -
High-Speed TX(2)
Two USB ports - 7 -
One USB port - 6 -
High-Speed RX(3) / Idle
Two USB ports - 10 -
One USB port - 0 -
Full-Speed Suspend (host mode)
Two USB ports - 0 -
One USB port - 0.2 -
Full-Speed Suspend (peripheral mode)
Two USB ports - 0.4 -
IDDA3V3_USBHS(PHY) mA
One USB port - 6.5 -
Full-Speed TX(2)
Two USB ports - 10.5 -
One USB port - 6.5 -
Full-Speed RX(3)
Two USB ports - 11.5 -
One USB port - 7 -
Low-Speed TX(2)
Two USB ports - 11.5 -
One USB port - 4.3 -
Low-Speed RX(3)
Two USB ports - 6.1 -
tINIT Initialization time(4) - - - 200 μs
1. Specified by design, not tested in production unless otherwise specified.
2. USB link 100% of the time in transmission
3. USB link 100% of the time in reception
4. This time includes the PLL_USB tLOCK.

6.3.35 JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 107 and Table 108 for
JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck

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frequency and VDD supply voltage summarized in Table 13: General operating conditions,
with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 0x10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5×VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.

Table 107. Dynamics characteristics: JTAG characteristics

Symbol Parameter Conditions Min Typ Max Unit

Fpp TCK clock 2.7 V < VDD < 3.6 V - - 35

MHz
1/tc(TCK) frequency 1.71 V < VDD < 3.6 V - - 27
TMS input
tisu(TMS) - 2.5 - -
setup time
TMS input
tih(TMS) - 1 - -
hold time
TDI input
tisu(TDI) - 2 - -
setup time
TDI input ns
tih(TDI) - 1 - -
hold time

TDO output 2.7 V < VDD < 3.6 V - 9.5 14

tov (TDO)
valid time 1.71 V < VDD< 3.6 V - 9.5 18
TDO output
toh(TDO) - 8 - -
hold time

Table 108. Dynamics characteristics: SWD characteristics

Symbol Parameter Conditions Min Typ Max Unit

Fpp SWCLK 2.7 V < VDD < 3.6 V - - 71

clock MHz
1/tc(SWCLK) frequency 1.71 V < VDD < 3.6 V - - 55

SWDIO input
tisu(SWDIO) - 2.5 - -
setup time
SWDIO input
tih(SWDIO) - 1 - -
hold time
SWDIO 2.7 V < VDD < 3.6 V - 10.5 14 ns
tov (SWDIO) output valid
time 1.71 V < VDD < 3.6 V - 10.5 18

SWDIO
toh(SWDIO) output hold - 9 - -
time

202/218 DS13876 Rev 6

STM32MP133A/D Electrical characteristics

Figure 55. JTAG timing diagram

tc(TCK)

TCK

tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS

tov(TDO) toh(TDO)

TDO

MSv40458V1

Figure 56. SWD timing

tc(SWCLK)

SWCLK

tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)

tov(SWDIO) toh(SWDIO)

SWDIO
(transmit)

MSv40459V1

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Package information STM32MP133A/D

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

7.1 LFBGA289 package information (B0ED)

This LFBGA is a 289 ball, 14x14 mm, 0.8 mm pitch, low profile fine pitch ball grid array
package.

Figure 57. LFBGA289 - Outline

ĭE Q;
ĭHHH0 C A B $EDOOORFDWLRQ
ĭIII0 C
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
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G
H
D1 J D
K
L
M
N
P
R
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H
E1 A E B

%277209,(: 7239,(:
A2 A
M A1
ddd C

S C

6,'(9,(:
B0ED_LFBGA289_ME_V1

1. Drawing is not to scale.

2. The tolerance of position controls the location of the balls within the matrix with respect to each other. For
each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as
defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball
must lie simultaneously in both tolerance zones.

204/218 DS13876 Rev 6

STM32MP133A/D Package information

Table 109. LFBGA289 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 1.700 - - 0.0669

A1 0.210 0.290 - 0.0083 0.0114 -
A2 - 0.816 - - 32.1260 -
(3)
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 13.850 14.000 14.150 0.5453 0.5512 0.5571
D1 - 12.800 - - 0.5039 -
E 13.850 14.000 14.150 0.5453 0.5512 0.5571
E1 - 12.800 - - 0.5039 -
e - 0.800 - - 0.0315 -
M - 0.530 - - 0.0209 -
S - 0.286 - - 0.0113 -
(4)
ddd - 0.120 - - 0.0047 -
(5)
eee - 0.150 - - 0.0059 -
fff - 0.080 - - 0.0031 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. LFBGA stands for low profile fine pitch ball grid array. The total profile height (Dim A) is measured from the
seating plane to the top of the component.
3. Initial ball equal 0.400 mm
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones

Figure 58. LFBGA289 - Recommended footprint

Dpad

Dsm
B02D_FP_V1

DS13876 Rev 6 205/218

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Package information STM32MP133A/D

Table 110. LFBGA289 - Recommended PCB design rules

Dimension Recommended values

Pitch 0.8 mm
Dpad 0.320 mm
Dsm 0.420 mm typ.
Stencil opening 0.320 mm
Stencil thickness 0.125 mm to 0.100 mm

7.2 TFBGA289 package information (B0EB)

This TFBGA is a 289 ball, 9x9 mm, 0.5 mm pitch, thin profile fine pitch ball grid array
package.

Figure 59. TFBGA289 - Outline

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16 14 12 10 8 6 4 2
17 15 13 11 9 7 5 3 1

A
B
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D
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F
G
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M
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E1 A
E B

%277209,(:
M A2 A
A1
ddd C

S
C
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%(%B7)%*$B0(B9

1. Drawing is not to scale.

2. The tolerance of position controls the location of the pattern of balls with respect to datums A and B. For
each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position
with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie
within this tolerance zone.

206/218 DS13876 Rev 6

STM32MP133A/D Package information

Table 111. TFBGA289 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 1.200 - - 0.0472

A1 0.140 0.210 - 0.0055 0.0083 -
A2 - 0.716 - - 28.1890 -
(3)
b 0.250 0.300 0.350 0.0098 0.0118 0.0138
D 8.850 9.000 9.150 0.3484 0.3543 0.3602
D1 - 8.000 - - 0.3150 -
E 8.850 9.000 9.150 0.3484 0.3543 0.3602
E1 - 8.000 - - 0.3150 -
e - 0.500 - - 0.0197 -
M - 0.530 - - 0.0209 -
S - 0.186 - - 0.0073 -
(4)
ddd - 0.080 - - 0.0031 -
(5)
eee - 0.150 - - 0.0059 -
fff - 0.080 - - 0.0031 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. TFBGA stands for thin profile fine pitch ball grid array. The total profile height (dim A) is measured from the
seating plane to the top of the component.
3. Initial ball equal 0.300 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones

DS13876 Rev 6 207/218

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Package information STM32MP133A/D

Figure 60. TFBGA289 - Recommended footprint

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 112. TFBGA289 - Recommended PCB design rules

Dimension Recommended values

Pitch 0.5 mm
Dpad 0.230 mm
Dsm 0.330 mm typ.
Stencil opening 0.230 mm
Stencil thickness 0.125 mm to 0.100 mm

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STM32MP133A/D Package information

7.3 TFBGA320 package information (B0EC)

This TFBGA is a 320 ball, 11x11 mm, 0.5 mm pitch, thin profile fine pitch ball grid array
package.

Figure 61. TFBGA320 - Outline

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21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A
B
C
D
E
F
e G
H
J
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D1 L D
M
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W
Y
AA

e
E1 A E
B

BOTTOM VIEW TOP VIEW

M A2 A
A1
ddd C

S C

SIDE VIEW B0EC_TFBGA320_ME_V1

1. Drawing is not to scale.

2. The tolerance of position controls the location of the pattern of balls with respect to datums A and B. For
each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position
with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie
within this tolerance zone.
Table 113. TFBGA320 - Mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 1.200 - - 0.0472

A1 0.140 0.210 - 0.0055 0.0083 -
A2 - 0.716 - - 0.0282 -
(3)
b 0.250 0.300 0.350 0.0098 0.0118 0.0138
D 10.850 11.000 11.150 0.4272 0.4331 0.4390
D1 - 10.000 - - 0.3937 -
E 10.850 11.000 11.150 0.4272 0.4331 0.4390
E1 - 10.000 - - 0.3937 -

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Package information STM32MP133A/D

Table 113. TFBGA320 - Mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

e - 0.500 - - 0.0197 -
M - 0.530 - - 0.0209 -
S - 0.186 - - 0.0073 -
(4)
ddd - 0.080 - - 0.0031 -
eee(5) - 0.150 - - 0.0059 -
fff - 0.080 - - 0.0031 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. TFBGA stands for thin profile fine pitch ball grid array. The total profile height (dim A) is measured from the
seating plane to the top of the component.
3. Initial ball equal 0.300 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones

Figure 62. TFBGA320 - Recommended footprint

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 114. TFBGA320 - Recommended PCB design rules

Dimension Recommended values

Pitch 0.5 mm
Dpad 0.230 mm
Dsm 0.330 mm typ.
Stencil opening 0.230 mm
Stencil thickness 0.125 mm to 0.100 mm

210/218 DS13876 Rev 6

STM32MP133A/D Package information

7.4 Thermal characteristics

Package thermal characteristics in Table 115 are specified with conditions as per JEDEC
JESD51-6, JESD51-8, JESD51-9, and JESD51-12. These typical values will vary in function
of board thermal characteristics and other components on the board.
ΘJA : Thermal resistance junction-ambient.
ΘJB: Thermal resistance junction-board.
ΘJC: Thermal resistance junction-top-case.
Θjb: Thermal parameter junction-board.
Ψjt: Thermal parameter junction-top-case.
Motherboard type: four layers, JEDEC 2S2P

Table 115. Thermal characteristics

Value
Symbol Parameter Unit
Natural convection 1m/s (200 ft/mn)

LFBGA289 - 289-ball 14x14 mm 0.80 mm pitch 31.7 29.2

ΘJA(1) TFBGA289 - 289-ball 9x9 mm 0.50 mm pitch 29.3 27 °C/W
TFBGA320 - 320-ball 11x11 mm 0.50 mm pitch 29 26.6
LFBGA289 - 289-ball 14x14 mm 0.80 mm pitch 21.2
ΘJB(2) TFBGA289 - 289-ball 9x9 mm 0.50 mm pitch 15.9 °C/W
TFBGA320 - 320-ball 11x11 mm 0.50 mm pitch 16.9
LFBGA289 - 289-ball 14x14 mm 0.80 mm pitch 8.9
ΘJC(3) TFBGA289 - 289-ball 9x9 mm 0.50 mm pitch 8.6 °C/W
TFBGA320 - 320-ball 11x11 mm 0.50 mm pitch 8.5
LFBGA289 - 289-ball 14x14 mm 0.80 mm pitch 21.1 20.9
(4)
Ψjb TFBGA289 - 289-ball 9x9 mm 0.50 mm pitch 15.9 15.8 °C/W
TFBGA320 - 320-ball 11x11 mm 0.50 mm pitch 16.9 16.8
LFBGA289 - 289-ball 14x14 mm 0.80 mm pitch 0.21 0.29
Ψjt (5) TFBGA289 - 289-ball 9x9 mm 0.50 mm pitch 0.18 0.26 °C/W
TFBGA320 - 320-ball 11x11 mm 0.50 mm pitch 0.18 0.26
1. Per JEDEC JESD51-9
2. Per JEDEC JESD51-8
3. Per JEDEC JESD51-12 best practice guidelines
4. Per JEDEC JESD51-12.
5. Per JEDEC JESD51-12.

7.4.1 Reference documents

JESD51-6 Integrated Circuit Thermal Test Method Environmental Conditions - Forced
Convection (Moving Air). Available from www.jedec.org.
JESD51-8 Integrated Circuit Thermal Test Method Environmental Conditions —Junction-to-
Board. Available from www.jedec.org.
JESD51-9 Test Boards for Area Array Surface. Mount Package Thermal. Measurements.

DS13876 Rev 6 211/218

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Package information STM32MP133A/D

Available from www.jedec.org.

JESD51-12 Guidelines for Reporting and Using Electronic Package Thermal Information.
Available from www.jedec.org.

212/218 DS13876 Rev 6

STM32MP133A/D Package information

7.5 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433) available on www.st.com, for the location of ball A1 as well
as the location and orientation of the marking areas versus ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.

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Ordering information STM32MP133A/D

8 Ordering information

Table 116. STM32MP133A/D ordering information scheme

Example: STM32 MP 133 D AE 3 T

Device family
STM32 = Arm-based 32-bit processor

Product type
MP = MPU product

Device subfamily
133 = STM32MP133 line

Security option
A = Basic security, 650 MHz
D = Basic security, 1000 MHz

Package and pin count

AE = LFBGA289 14x14, 289 balls pitch 0.8 mm
AF = TFBGA320 11x11, 320 balls pitch 0.5 mm
AG = TFBGA289 9x9, 289 balls pitch 0.5 mm

Junction temperature range

3 = -40 °C < TJ < +125 °C up to 650 MHz Cortex®-A7(1)
7 = -40 °C < TJ < +105 °C up to 1000 MHz Cortex®-A7(1)

Options
Blank = no options

Packing
T = tape and reel
No character = tray or tube
1. Refer also to the application note AN5438 “STM32MP1 Series lifetime estimates” available from the ST
website www.st.com.

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

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STM32MP133A/D Important security notice

9 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

DS13876 Rev 6 215/218

215
Revision history STM32MP133A/D

10 Revision history

Table 117. Document revision history

Date Revision Changes

16-Feb-2023 1 Initial release.

Updated tWULPLV_Stop2_MPU and associated footnote in
Table 28: Low-power mode wakeup timings.
12-Jun-2023 2
Added tINIT in Table 106: USB High-Speed PHY
characteristics.
Removed row ‘Input voltage on OTG_VBUS pin’ in
Table 10: Voltage characteristics.
Removed row ‘OTG_VBUS I/O’ in Table 13: General
operating conditions.
Updated Figure 32: NAND controller waveforms for read
07-Sep-2023 3 access and Figure 32: NAND controller waveforms for
read access. Suppressed the following 2 figures.
Updated Figure 39: SPI timing diagram - slave mode
and CPHA = 0, Figure 40: SPI timing diagram - slave
mode and CPHA = 1(1) and Figure 41: SPI timing
diagram - master mode(1).
Updated SPI on cover page.
Updated VDDCORE in Section 3.6.1: Power supply
scheme.
Updated Section 3.6.2: Power supply supervisor.
Updated Section 3.20: VBAT operation.
Updated Section 3.27.5: Independent watchdogs
27-Mar-2024 4 (IWDG1, IWDG2).
Updated Figure 19: Typical application with a
32.768 kHz crystal.
Updated Figure 33: NAND controller waveforms for
write access.
Updated Figure 74: Switching characteristics for NAND
flash read cycles.
Updated Up to 29 communication peripherals.
Updated Section 3.32: Universal synchronous
asynchronous receiver transmitter (USART1, USART2,
USART3, USART6 and UART4, UART5, UART7,
UART8).
Updated Table 5: USART/UART features.
Updated Section 3.36: Secure digital input/output
25-Sep-2024 5 MultiMediaCard interfaces (SDMMC1, SDMMC2).
Updated Table 7: STM32MP133A/D ball definitions.
Updated Table 8: Alternate function AF0 to AF7.
Updated Section 6.3.19: FMC characteristics.
Updated Figure 28: Synchronous multiplexed
NOR/PSRAM read timings.
Updated Table 70: Synchronous multiplexed
NOR/PSRAM read timings.

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STM32MP133A/D Revision history

Table 117. Document revision history

Date Revision Changes

Updated Figure 29: Synchronous multiplexed PSRAM

write timings.
Updated Table 71: Synchronous multiplexed PSRAM
write timings.
Updated Figure 30: Synchronous non-multiplexed
NOR/PSRAM read timings.
Updated Table 72: Synchronous non-multiplexed
NOR/PSRAM read timings.
Updated Figure 31: Synchronous non-multiplexed
PSRAM write timings.
Updated Table 73: Synchronous non-multiplexed
PSRAM write timings.
Added Updated Figure 28: Synchronous multiplexed
5 NOR/PSRAM read timings.
25-Sep-2024 Added Figure 36: ADC accuracy characteristics.
(continued)
Added Figure 37: Typical connection diagram using the
ADC with FT/TT pins featuring analog switch function.
Updated Section 6.3.33: USART (SPI mode) interface
characteristics.
Updated Table 105: USART (SPI mode) characteristics.
Added Figure 53: USART timing diagram in SPI master
mode.
Added Figure 54: USART timing diagram in SPI slave
mode.
Added package code in the following section tites:
Section 7.1: LFBGA289 package information (B0ED),
Section 7.2: TFBGA289 package information (B0EB),
Section 7.3: TFBGA320 package information (B0EC).
Updated Section : High-speed external clock generated
from a crystal/ceramic resonator.
Updated Section 6.3.12: PLL spread spectrum clock
generation (SSCG) characteristics.
Updated Figure 2: Power-up/down sequence.
Updated Figure 4: Voltage reference buffer.
Updated Figure 10: Power supply scheme.
Updated Figure 34: QUADSPI timing diagram - SDR
01-Mar-2025 6
mode.
Updated Figure 35: QUADSPI timing diagram - DDR
mode.
Updated Figure 38: Channel transceiver timing
diagrams.
Updated Figure 44: SAI master timing waveforms.
Updated Figure 45: SAI slave timing waveforms.
Removed Section USB OTG_FS characteristics.

DS13876 Rev 6 217/218

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 STM32MP133A/D

IMPORTANT NOTICE – READ CAREFULLY

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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
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acknowledgment.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product
or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2025 STMicroelectronics – All rights reserved

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