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Unit 3 Problems

The document presents a series of problems related to computer architecture, focusing on instruction hazards, pipeline processing, and performance metrics. It includes calculations for speedup ratios, clock cycle times, and utilization of various components in a processor. Each problem is followed by a concise answer detailing the findings and methodologies used.

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akisher987
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7 views18 pages

Unit 3 Problems

The document presents a series of problems related to computer architecture, focusing on instruction hazards, pipeline processing, and performance metrics. It includes calculations for speedup ratios, clock cycle times, and utilization of various components in a processor. Each problem is followed by a concise answer detailing the findings and methodologies used.

Uploaded by

akisher987
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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UNIT-3 PROBLEMS

Problem 1
Consider the following code.
DIV R2 , R5 , R8
SUB R9 , R2 , R7
ADD R5 , R14, R6
MUL R11, R9 , R5
BEQ R10, #10 , R12
OR R8 , R15, R2

a. Identify all of the RAW hazards in the above instruction sequence


b. Identify all of the WAR hazards in the above instruction sequence
c. Identify all of the WAW hazards in the above instruction sequence
d. Identify all of the Control hazards in the above instruction sequence
Problem 1
Ans: a) RAW ➔ DIV & SUB ; ADD & MUL : SUB & MUL ;DIV & OR
b) WAR ➔ DIV & ADD ; DIV & OR
c) WAW ➔ NONE
d)Control➔ BEQ & OR
Problem 2

A unpipeline system tasks 50ns to process a task. The


same task can be processed in 6 segment pipeline
with a clock cycle of 10ns. Determine the speedup
ratio of the pipeline for 100 tasks. What is the
maximum speedup that can be achieved?
Problem 2
• tn = 50ns
• k =6
• tp = 10ns
• n = 100
• S = ntn / (k+n-1)tp = 50*100 / (6+99)*10 =4.76

• S max = tn/tp =50/10 =5


Problem 3

The time delay for the 4 segment in the pipeline are as follows t1= 50
ns, t2 = 30 ns, t3 = 95 ns and t4 = 45 ns. The interface register delay
time tr = 5 ns
(a) How long would it take to add 100 pairs of numbers in the pipeline?
(b)How can we reduce the total time to about one half of the time
calculate in part(a)
Problem 3
Ans:
clock cycle =95 + 5 = 100 ns
for n = 100, k = 4, tp = 100 ns
time to add 100 number = (k+n-1)tp = (4+99) x 100 = 10,300 ns = 10.3 s
(b) Divide the segment 3 into two segment of 50 + 5 = 55 ns
and 45 + 5 = 50 ns
This makes the tp = 55 ns , k = 4
Therefore (k+n-1) tp = (5+99) x 55 = 5720 = 5.72 ns
Problem 4
Assume that individual stages of the data path have the following
latencies:
IF ID EX MEM WB

250ps 400ps 150ps 350ps 200ps

What is the clock cycle time in a pipelined and non-pipelined


processor?
Problem 4
Ans) 400ps and 1350ps
• For a pipeline processor the segment with longest processing time(ID)
=400ps
• For non-pipeline processor the sum of all segments processing time=
1350ps
Problem 5
• Assume that instructions executed by the processor are broken down
as follows:
ALU beq lw Sw
40% 20% 25% 15%

• Assuming there are no stalls or hazards, what is the utilization of the


write-register port of the “Registers” unit?
Problem 5
• Ans: Since store and branch instructions will not write the result to
register unit Only ALU and load writes the result to Register port :
65%
Problem 6
• Assume that individual stages of the data path have the following
latencies:
IF ID EX MEM WB
250ps 400ps 150ps 350ps 200ps

• If we can split one stage of the pipelined datapath into two new
stages, each with half the latency of the original stage, which stage
would you split and identify the new clock cycle time of the
processor?
Problem 6
Ans: The stage with longest processing time can be chosen. ID stage
and next highest processing time 350ps
Problem 9
• What is the longest chain of dependent operations (including the
name dependencies) in the following program?
LD r7,(r8)
SUB r10,r11,r1
MUL r13,r7,r11
ST (r9),r13
ADD r13,r2,r1
LD r5,(r6)
SUB r3,r4,r5.
Problem 9
• Ans:
LD r7,(r8)
MUL r13,r7,r11
ST (r9),r13
ADD r13,r2,r1
Quiz Problem 1

1. what is the cycle time for pipelined and non-pipelined ?


2. Determine the speedup ratio of the pipeline for 100 tasks. What is the maximum speedup that can be
achieved?
3. If you could split one of the pipeline stages into 2 equal halves, which one would you choose? What is
the new cycle time?
4. Determine the speedup ratio of the pipeline for 100 tasks for question 3. What is the maximum
speedup that can be achieved?
Quiz Problem 2
Assume the distribution of instructions that run on the processor is: 50%:
ALU 25%: BEQ 15%: LW 10%: SW Assuming there are no stalls or hazards,
what is the utilization of the data memory? What is the utilization of the
register block’s write port? (Utilization in percentage of clock cycles used)

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