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Mid1

The document outlines the structure and content of the MID Term Examinations-I for the M. Tech/I course in Low Power VLSI Design at GITAM School of Technology, Hyderabad Campus. It includes two parts: Part 1 consists of five short answer questions worth 10 marks, and Part 2 includes three longer questions where students must answer any two, totaling 20 marks. The exam covers topics such as CMOS transistor limits, body bias effects, power estimation, and circuit design styles.

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Chetan Cherry
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30 views

Mid1

The document outlines the structure and content of the MID Term Examinations-I for the M. Tech/I course in Low Power VLSI Design at GITAM School of Technology, Hyderabad Campus. It includes two parts: Part 1 consists of five short answer questions worth 10 marks, and Part 2 includes three longer questions where students must answer any two, totaling 20 marks. The exam covers topics such as CMOS transistor limits, body bias effects, power estimation, and circuit design styles.

Uploaded by

Chetan Cherry
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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GITAM School of Technology – Hyderabad Campus

MID Term Examinations-I

Branch/Semester: M. Tech/I Date: 30-09-2024


Course Code:19EEC770 Course Name: Low Power VLSI Design
Max. Marks: 15 Exam Duration: 60 min
=======================================================================

Part 1

Answer all the questions (5 x 2 Marks = 10


Marks)

1 Question CO PO BL
a List out the hierarchy of limits of CMOS transistors. 1 1 1
b Write the impact of body bias effect. 1 2 1
c What is signal probability and signal activity in the context of power 2 3 1
estimation?
d What DIBL short channel effect? 2 3 1
e List out the various leakage currents in deep submicrometer 2 3 1
transistors.

Part 2

Answer any 2 from the following. (2 x 10 Marks = 20 Marks)

Question CO PO BL
2 Derive the short circuit power and switching power dissipation of a 1 1 5
CMOS inverter circuit.
3 Derive the depth of the depletion region and threshold voltage 1 1 5
expressions with the help of the energy band diagrams.
4 Explain the non-clocked and clocked circuit design styles in terms 2 3 4
of power dissipation and performance with the help of examples.

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