1.

INTRODUCTION
This project focuses on advanced power electronics for efficient Electric Vehicle (EV)
charging systems and fault management. With the increasing demand for electric
vehicles, optimizing the performance and reliability of EV chargers is crucial. Power
Factor Correction (PFC), interleaved boost converters, LLC resonant converters,
synchronous rectification, and fault management are key technologies that ensure
these systems operate efficiently and reliably. By integrating these technologies, the
project aims to improve power conversion efficiency, reduce energy loss, and enhance
the durability of EV chargers, making them more effective and environmentally
friendly.

1.1 Introduction to PFC

Power Factor Correction (PFC) is essential for enhancing system efficiency in high-
power applications. It ensures the power delivered to the load is used effectively,
reducing energy losses. Traditional passive PFC solutions, relying on capacitors and
inductors, can be inefficient and bulky. Active PFC solutions, particularly those using
boost converter topologies, offer a more efficient and compact alternative. Interleaved
boost converters, in particular, improve power density, reduce the size of magnetics,
and decrease strain on bulk capacitors, enhancing performance and reliability.

A boost converter increases input voltage to a higher output voltage through an

inductor, a switch, and a diode. The process occurs in two phases: storing energy in
the inductor during the switch-on phase, and transferring the energy to the load during
the switch-off phase. A well-designed control loop, which typically includes voltage
control, current control, and current balancing, is crucial for achieving effective PFC.
By employing interleaving techniques and advanced control strategies, boost
converters minimize harmonics, enhance efficiency, and maintain stable operation.

1.2 Introduction to Interleaved Boost Converter

The Interleaved Boost Converter (IBC) improves upon traditional boost converters by
using multiple phases, typically two or more, which operate in parallel with a 180°
phase shift. This interleaving technique enhances efficiency, reduces size, improves
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thermal management, and lowers Total Harmonic Distortion (THD). By
synchronizing the phases, IBCs share the load across multiple inductors and switches,
reducing ripple currents and improving system reliability.

In Continuous Conduction Mode (CCM), the IBC alternates phases between on and
off states, allowing for efficient energy transfer. The interleaving operation reduces
ripple in input and output currents, minimizing electromagnetic interference (EMI)
and improving efficiency. Additionally, the IBC design helps distribute thermal stress
across multiple components, leading to better thermal management and higher
reliability in power supplies for high-demand systems.

1.3 Introduction to LLC

The LLC resonant converter is a highly efficient DC-to-DC converter used in power
electronics applications, especially in high-power systems. It features a resonant tank
circuit composed of inductors and capacitors, allowing for soft switching techniques
like zero-voltage switching (ZVS) and zero-current switching (ZCS). These
techniques reduce switching losses and improve efficiency, making the converter ideal
for high-demand applications, such as EV chargers.

The LLC converter operates by converting input DC voltage into a high-frequency

square wave, which is then processed through a resonant tank to generate a sine wave.
The sine wave is passed through a high-frequency transformer to scale the voltage,
and a diode rectifier is used to stabilize the DC output. This design maintains high
efficiency across various power levels, making it suitable for applications where
minimizing power loss is essential.

1.4 Introduction to Synchronous Rectification

As EV adoption grows, optimizing the efficiency of EV chargers becomes more

critical. Synchronous rectification replaces traditional diodes with actively controlled
MOSFETs, reducing power losses and improving efficiency. This technique enhances
thermal management and reduces heat generation, making it ideal for EV chargers.

Synchronous rectification is particularly beneficial in LLC resonant converters, where

it replaces diodes with MOSFETs to reduce conduction losses and reverse recovery
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losses. Optimizing the switching of the MOSFETs minimizes switching and
conduction losses, leading to better power conversion efficiency. By employing
techniques such as Zero Voltage Switching (ZVS), switching losses are reduced,
further improving the converter’s performance.

1.5 Introduction to Fault Management

Fault management is a vital part of designing reliable and efficient chargers. Faults
can occur during operation, impacting performance and safety. Therefore, quick fault
detection and resolution are essential. Pre-sale testing, including continuous running,
on-off testing, and extended operation, ensures the charger functions as expected.
Logging internal parameters during operation helps identify issues, track faults, and
pinpoint failed components, improving the charger’s reliability.

The dsPIC33CK64MP506 Digital Signal Processor from Microchip is a prime

example of a component used in chargers for precise digital control and fault
management. It offers features such as a 100 MHz core, integrated DSP, and various
communication protocols like SPI, I2C, and CAN, enhancing fault detection and
troubleshooting. Its watchdog timer, fail-safe clock monitor, and flash error correction
code provide safeguards to ensure reliable operation, preventing failures and ensuring
safety in critical environments.

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 2.PFC USING BOOST CONVERTER

In higher power applications, efficiency is to be maintained very higher. To achieve

the maximum efficiency or to utilize the full power, power factor correction (PFC) is
a necessity. Passive solutions were developed first, which need bulky capacitors and
inductors. To avoid this, some of the active solutions came into light to achieve PFC.
Using boost topology, we can reduce the volume of bulky capacitors. The active
power solutions had higher power densities than passive solution. In this boost
topology, interleaving the pfc has some extra advantages like increasing power
densities, reducing the volume of the magnetics and reduce the burden on bulk
capacitors in terms of rms current of boost capacitor.

2.1 Operation of PFC

Boost converters are a type of DC-DC switching converter that efficiently increase
(step-up) the input voltage to a higher output voltage. By storing energy in an inductor
during the switch-on phase and releasing it to the load during the switch-off phase,
this voltage conversion is made possible. Power electronics applications requiring a
greater output voltage than the input source, in particular, depend on boost converters.

Fig. 2.1 Boost converter circuit diagram

The basic principle of operation for a boost converter can be understood through the
following two stages:Switch-on period (S1 closed, S2 open): During this stage, the
input voltage (Vin) is applied across the inductor (L), causing the current through the
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inductor to increase linearly. The energy stored in the inductor builds up, and the
diode (D) is reverse-biased, preventing current flow to the load. The inductor current
can be expressed as:

ΔIL=VinL⋅tonΔIL=VinL⋅ton

where ΔIL is the change in inductor current, L is the inductance, and t on is the duration
of the switch-on period.

Switch-off period (S1 open, S2 closed): When the switch S1 opens, the inductor
current must continue to flow. This forces the diode D to become forward-biased, and
the inductor releases its stored energy to the load (R) and the output capacitor (C).
During this period, the voltage across the inductor (VL) is equal to the difference
between the output voltage (Vout) and the input voltage (Vin). The inductor current
decreases linearly as the energy is transferred to the load, and the equation for the
inductor current becomes:

ΔIL=(Vout−Vin)L⋅toffΔIL=(Vout−Vin)L⋅toff

where toff is the duration of the switch-off period.

Fig. 2.2 Boost converter operation

By equating the inductor current equations for both stages and rearranging the terms,
we can derive the voltage conversion relationship for the boost converter:

Vout=Vin(1−D)Vout=Vin(1−D)

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where D is the duty cycle, defined as the ratio of the switch-on time (t on) to the total
switching period (T), or

D=ton(ton+Toff)D=ton(ton+Toff)

This equation shows that the output voltage can be controlled by adjusting the duty
cycle of the switching waveform, allowing for a higher output voltage than the input
voltage.

Waveforms:

Fig. 2.3 Waveforms

The input capacitor is calculated based on the input current and the input voltage
ripples. The input current ripple and the input voltage ripple considered for the
calculation are 20% and 2% respectively.

For obtaining the Cin value, we obtain the ripple current (ΔI) and the ripple voltage.

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 𝐼𝑟𝑖𝑝𝑝𝑙𝑒 = ∆𝐼𝑟𝑖𝑝𝑝𝑙𝑒×𝐼𝑖𝑛_𝑚𝑎𝑥

𝐼𝑟𝑖𝑝𝑝𝑙𝑒 =0.2 *( √2∗𝑃𝑜𝑢𝑡/ ∗𝑉𝑖𝑛

𝜂 _𝑚𝑖𝑛∗ 𝑃𝐹)

Let us consider we design a750w converter with wide variation of input voltage from
180 to 270v.

Assuming input current ripple as 20% of the rated current, then

𝐼𝑟𝑖𝑝𝑝𝑙𝑒 =0.2 *(√2∗750/0.95*180*0.98)

=6.32A

𝑉 𝑖𝑛_𝑟𝑖𝑝𝑝𝑙𝑒= ∆𝑉𝑟𝑖𝑝𝑝𝑙𝑒∗𝑉𝑖𝑛min(max)

=0.02*(180*√2)

=5.09v

Input capacitance value can be calculated as:

C𝑖𝑛= 𝐼𝑟𝑖𝑝𝑝𝑙𝑒/( 8∗𝑓𝑠𝑤∗𝑉𝑖𝑛_𝑟𝑖𝑝𝑝𝑙𝑒)

=6.32/(8*100*1000*5.09)

=1.55uF

2.2 Bridge Rectifier

Bridge rectifier has been selected based on the average input current and input voltage
and considering all the losses at worst-case condition. The calculations are included as
below:

Maximum input RMS current through the diode is:

I_RMS=P_OUT/(V in_min* 𝜂)

=750/(180*0.95)

=4.38A

Average current through diode is:

Id_avg= (√2∗ I_RMS/ pie)

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 =(√2∗4.38/3.14)

=1.97A

To lower the power dissipation ,we need to select the diodes (bridge )with lesser
forward voltage drop.

P_bridge =2 * I_d * V_f (2 diodes)

2.3 Boost Inductor

To select the inductor for SMPS applications, some of the features need to be
considered . They are: Temperature, Saturation and Core

In core aspect, we should consider the current flow because as powdered core
inductance decreases linearly with increase in current, but ferrite core inductance
decrease non-linearly with increase in current.

The boost inductor stores energy during turn-on period and delivers the load during
turn-off period. Here a powdered core is selected for lower core losses, high saturation
flux density and good temperature performance.

2.4 Boost Diode:

The selection of diode in a PFC circuit has major impact on the efficiency of the
converter. Conventionally fast recovery diodes are selected as a boost diode as their
reverse recovery characteristics make them affect the converter ‘s overall
performance.

The reverse blocking voltage is usually selected based on maximum output voltage.

I_d_avg = P_out/V_out

=750/390

=1.92 A

The conduction losses in the diode are:

P_d = V_f * I_d_avg

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To reduce conduction losses, we usually prefer Schottky diodes for lower forward
voltage drop.

Output capacitor also known as bulk capacitor is usually designed on the minimum
hold-up time (tmin) in case of a power outage. Here, tmin is considered as 10ms, the
duration of one-half cycle of the ac-line. (50Hz).

2.5 How To achieve PFC using boost topology

Power Factor is a measurement of effectiveness of applied power , which is used by

an electric circuit . Power factor correction improves the power factor and increases
efficiency of applied power supply.

In high power applications involving power electronics devices offers more

harmonics in the supply . To reduce the harmonic component and power loss ,we need
to incorporate PFC circuit.We can achieve PFC in SMPS by some topologies like
boost topology (interleaving) and totem pole topology.Boost topology offers small
size and space., even though it has more switches and conduction losses than totem -
pole.

2.5.1 Control Loop

The current loop uses average current mode control for achieving power factor
correction. In this control the scheme matches the average input current to the
reference. The control operates in the Continuous Conduction Mode (CCM) across all
levels depending on the inductor values and provides several benefits such as.

• Higher degree of accuracy

• Suitable for higher power levels

• No need of slope compensation

• Improved Total Harmonic Distortion (THD) Reduction

• Good noise immunity

• Better Dynamic Response

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 Fig. 2.4 Pfc control loop

The control structure can be divided into 3 main loops:

• Voltage Control Loop

• Current Control Loop

• Current Balancing Loop

2.5.2 Voltage Control Loop

The voltage loop constitutes the outermost loop of the control structure. This loop
takes care of regulating the output voltage across all loads and supply conditions. The
actual DC bus voltage (Vbus _sense) and the reference bus voltage (Vref) are
compared. The difference between the reference value gives the error value. The error
signal is fed to a PI controller. The output of the PI controller is the input to the
current control loop, which acts as the reference (I ac_ref). Usually, the voltage loop
is operated at a very low rate (~ 1/10 times) when compared to the current loop and

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has a smaller bandwidth. The bandwidth is selected considering the effect of input
frequency ripple on the bus voltage.

2.5.3 Current Control Loop

The current control loop is the inner loop of the control structure that decides the duty
of the switches. The reference signal from the voltage loop is compared with the input
current sense (Iac_sense). The error signal is fed to a PI controller. This corrects the
error by forcing the Input current to follow the reference current, which takes care of
the essential operation of the PFC. The current control loop needs to operate at a
relative higher frequency and higher bandwidth when compared to the voltage control
loop, The current loop requires to sample the rectified AC signal at twice the input
frequency and is operated at a frequency that is a multiple of the switching frequency.

2.5.4 Current Balance Loop:

As explained in the previous section, interleaved topology adds several advantages.

However, as the control structure of the loop gets affected to accommodate additional
current balance and ensure that the switches share the load equally. Due to the
variation of multiple parameters across both the switches, there is also a drift in the
values measured across each leg. If same duty is applied to both the switches, it may
lead to over-stressing a particular leg causing thermal stress. This may lead to
triggering of protection functions. Hence, a current balancing loop becomes
necessary. Here, a cycle-by-cycle duty ratio adjustment method is adopted for current
balancing. The current across each leg is sensed and then compared with each other.
The error determines the imbalance in the legs. If the first leg current is higher, the
error is positive and negative for vice-versa. The multiplier increases / decreases the
duty cycle based on the polarity of the error.

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 3 Interleaved Boost Converter

3.1 Block Diagram of Interleaved Boost Converter (IBC)

The Interleaved Boost Converter (IBC) consists of two boost converters c

onnected in parallel with a 180° phase delay, and operating at the same frequency.
The IBC has better characteristics when compared to a boost converter with
improved efficiency, reduced size, greater reliability and lower Total Harmonic
Distortions (THD). The gating pulses of the two switches in the converter are
shifted by a phase difference of 360/n where n is the number of parallel boost
converters. The converter considered is operating in Continuous Conduction Mode
(CCM) which results in lower input peak current (amplitude) and less conduction
losses. It operates at larger duty cycle say 0.5 due to high output voltage and low
input voltage.

3.2 Operation Interleaved Boost Converter (IBC)

Fig. 3.1 general block diagram of IBC

An interleaved boost converter is a type of DC-DC power converter designed to

improve efficiency, reduce output ripple, and enhance thermal management. It
achieves these benefits by using multiple boost converter phases operating in
parallel. Each phase consists of essential components such as a power switch

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(MOSFET or IGBT), an inductor, and a diode. These phases share a common
output capacitor, which helps smooth voltage fluctuations. The key aspect of this
topology is that the phases are synchronized but operate with a phase shift,
allowing better current sharing and ripple reduction.

During operation, the power switches in each phase turn ON and OFF in an
interleaved manner. This means that when one phase is conducting (ON state), the
others are non-conducting (OFF state), and vice versa. This alternating operation
significantly reduces input and output current ripple since the ripple currents from
different phases partially cancel each other out. As a result, the system achieves
lower electromagnetic interference (EMI) and better power quality. Additionally,
spreading the load across multiple inductors and switches minimizes conduction
losses, leading to improved overall efficiency.

In the ON state, when a particular phase’s power switch is activated, current flows
from the input source through the inductor to the ground. This process causes the
inductor to store energy by generating a magnetic field. During this phase, the
voltage across the inductor equals the input voltage, leading to a linear increase in
inductor current. The rate of current increase depends on parameters such as input
voltage, inductance value, and switching frequency. Meanwhile, the output diode
remains reverse-biased, preventing current flow to the capacitor and load.

When the switch turns OFF, the stored energy in the inductor is released. The
inductor voltage reverses polarity, allowing current to flow through the output
diode to the capacitor and load. The output capacitor helps stabilize the voltage
and ensures a smooth DC output. The phase shift between multiple interleaved
boost converters ensures continuous power delivery to the load while keeping
ripple and switching noise at a minimum.

The interleaved boost converter is widely used in high-power applications such as

electric vehicle (EV) charging stations, renewable energy systems, and power
supplies for industrial automation. By improving efficiency, reducing THD (Total
Harmonic Distortion), and enhancing thermal performance, this topology provides
a reliable and scalable solution for modern power electronics applications.

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 Fig. 3.2 Simulation diagram of IBC in MATLAB

In the OFF state of the interleaved boost converter, the power switch is turned
OFF, causing the inductor to release the energy stored during the ON phase. When
the switch is deactivated, the magnetic field surrounding the inductor collapses,
inducing a voltage that forces current through the forward-biased output diode.
This allows energy to flow seamlessly from the inductor to both the output
capacitor and the load, ensuring continuous power delivery. The inductor current
gradually decreases in this phase, and the rate of this decrease depends on
multiple factors, including the input voltage, output voltage, inductance value,
and switching frequency. The output diode plays a crucial role by providing a
pathway for current when the switch is off, preventing sudden disruptions in
power transfer and maintaining circuit stability.

The output capacitor is vital in ensuring a steady and smooth DC output. It serves
as a buffer that filters out unwanted voltage ripples and fluctuations, maintaining a
stable voltage level at the output. As the converter operates in interleaved phases,
with multiple inductors sharing the load, the continuous energy transfer mechanism
significantly reduces output ripple. This not only enhances the efficiency of power
delivery but also improves the overall performance of the system by minimizing
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electromagnetic interference (EMI) and reducing thermal stress on individual
components. The combination of properly timed switching, controlled inductor
behavior, and effective capacitor filtering ensures that the interleaved boost
converter delivers high efficiency, improved power factor, and reliable
performance for various high-power applications.

Fig. 3.3 Interleaved Boost Converter Simulation in LTspice

An interleaved boost converter reduces ripple currents by sharing the load across
multiple inductors and using out-of-phase operation, improving system
performance and reducing EMI. It enhances efficiency by lowering current stress
on components, reducing conduction and switching losses. Thermal stress is also
minimized by distributing power across phases, improving thermal management
and reliability. Additionally, the parallel operation of inductors provides a faster
transient response to load changes.

3.3 Parameters Considered

The values of the parameters used in the simulation are as follows:

 Input Voltage (Vin): 12 V, 100 V

 Output Voltage (Vout): 24 V, 200 V
 Inductors (L1, L2): 96 µH, 96 µH
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  Output Capacitor (Co): 48 µF, 48 µF
 Resistance (Ro): 5.76 Ω, 5.76 Ω
 Switching Frequency (fs): 25 kHz, 25 kHz
 Duty Cycle (D): 0.5, 0.5

3.4 Waveforms Analysis

Fig. 3.4 Waveforms of Interleaved Boost Converter Simulation in LTspice

Overall, the waveforms demonstrate the effective operation of the interleaved

boost converter. The reduction in ripple current, improved load sharing, and
proper phase-shifted switching contribute to better efficiency, lower EMI, and
enhanced thermal management.

The waveform analysis for the load current I(R1)I(R1) indicates an average
current of 4.0495A and an RMS value of 4.0581A over a 10 ms interval. The small
difference between the average and RMS values suggests minimal ripple in the
load current, indicating efficient current sharing and smooth operation. This
confirms the interleaved boost converter's effectiveness in maintaining a stable
output current.

The output voltage V(n003) of the interleaved boost converter has an average
value of 23.325V and an RMS value of 23.375V over a 10 ms interval. The
minimal difference between the average and RMS values indicates low voltage

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ripple, reflecting stable and efficient voltage regulation. This suggests that the
interleaved design effectively reduces output fluctuations and enhances
performance

Fig. 3.5 output current and output voltage

3.5 Design Equations

1. Boost Ratio

The boosting ratio of the IBC is a function of the duty ratio. It is same as in
conventional boost converter .It is defined as;

V(o) / V(in)=1 / (1-D)

Where, Vo is the output voltage, Vin is the input Voltage and D is the duty ratio.

2. Selection of Inductor

In the power electronic systems the magnetic components play a major role for
energy storage and filtering. As discussed in the operation of IBC the inductor is
used to transform the energy from the input voltage to the inductor current and to
convert it back from the inductor current to the output voltage. As per the principle
the two inductors are identical in order to balance the current in the two boost
converters.

3. Duty Cycle Formula

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The first step to calculate the switch current is to determine the duty cycle, D, for
the minimum input voltage. The minimum input voltage is used because this leads
to the maximum switch current.

D=1-(Vin*efficiency) / Vout

The efficiency is added to the duty cycle calculation, because the converter has to
deliver also the energy dissipated. This calculation gives a more realistic duty
cycle than just the equation without the efficiency factor.

4. Output Current

The output current is measured by using the below formula Iout = Pout / Vout
Where;

Pout = Output Power & Vout = Output Voltage

Boost Converter Design

STEP – 1

To begin with, we need a thorough understanding of what our load requires. It is

highly recommended (from experience) that if you attempt to build a boost
converter at the beginning it is very important to know the output voltage and
current independently, the product of which is our output power.

STEP – 2

Once we have the output power, we can divide that by the input voltage (which
should also be decided) to get the average input current needed

We increase the input current by 40% to account for ripple. This new value is the
peak input current.

Also the minimum input current is 0.8 times the average input current, so multiply
the average input current by 0.8.

Now that we have peak and minimum current, we can calculate the total change in
current by subtracting the peak and minimum current.

STEP – 3
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Now we calculate the duty cycle of the converter, i.e. the ratio of the on and off
times of the oscillator.

Duty cycle is given by this textbook formula:

D.C. = (Vout – Vin)/(Vout)

This should give us a reasonable decimal value, above 0 but below 0.999.

STEP – 4

Now it is time to decide upon the frequency of the oscillator. This has been
included as a separate step because the signal source can be anything from a 555
timer (where the frequency and duty cycle are completely under your control) or a
fixed frequency PWM controller.

Once the frequency is determined, we can find out the total time period by taking
an inverse. Now the time period is multiplied by the duty cycle value to get the on
time.

STEP – 5

Since we have determined the on time, input voltage and change in current, we
can plug those values into the inductor formula which has been rearranged a little:

L = (V*dt)/dI

Where V is the input voltage, dt is the on time and dI is the change in current.

3.6 Selection of Inductor and Capacitor

The operation of IBC, the inductor is used to transform the

energy from the input voltage to the inductor current and to convert it back from
the inductor current to the output voltage. As per the principle the two inductors
are identical in order to balance the current in the two boost converters. The value
of the inductor can be found out by the following formula.

L = (Vin*D)/(ΔIl*fs)

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where Vs represents the source voltage and ΔIl represents the inductor current
ripple, D represents the duty ratio. The value of the
capacitor is given by the formula

C = (Vin*D)/(R*Δvo)

where Vo represents the output voltage (V), D represents the duty ratio, R
represents the resistance and ΔVo represents the change in the output voltage.

3.7 Simulation and Results

The interleaved boost converter simulation in MATLAB and LTspice demonstrates

improved efficiency, reduced ripple, and faster transient response due to phase-
shifted operation. MATLAB provided quicker simulation times, while LTspice
offered a more detailed circuit-level analysis. The phase-shifted control reduced
input and output ripple by evenly sharing the current between two inductors. This
design also improved thermal management by distributing the load across multiple
switches and inductors. Both simulation platforms produced consistent results,
validating the converter's performance and efficiency.

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 4. LLC OPERATION

LLC resonant converter is a type of DC-to-DC power converter that is widely used in
electronic applications for efficient power conversion. It uses a resonant tank circuit
composed of two inductors (L) and a capacitor (C) to convert an input voltage to a
different output voltage.

The resonant operation allows for zero-voltage switching (ZVS) or zero-current

switching (ZCS), reducing switching losses and improving efficiency, especially
under varying load conditions.

LLC resonant converters have gained significant attention in power electronics due to
their ability to meet the demanding performance requirements of modern power
supply designs. Among the diverse family of resonant converter topologies, LLC
stands out as one of the most prominent.

Resonant tanks, the foundation of LLC converters, are circuits composed of inductors
and capacitors that oscillate at a specific frequency known as the resonant frequency.
This unique characteristic of resonant tanks enables LLC converters to achieve higher
switching frequencies (fSW) and minimize switching losses.

In high-power, high-efficiency applications, switch-mode DC/DC power converters

with LLC resonant converters are particularly advantageous. They are ideal for power
supply systems with delicate components (e.g., high-end consumer electronics) or
power-demanding operations (e.g., charging electric vehicles).

An LLC converter comprises four essential blocks: power switches, resonant tank,
transformer, and diode rectifier (as depicted in Figure 1). The process begins with the
MOSFET power switches converting the input DC voltage into a high-frequency
square wave. This square wave then enters the resonant tank, where it undergoes a
process of harmonic elimination, resulting in the generation of a sine wave with the
fundamental frequency.

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Fig. 4.1 Half bridge LLC Circuit in LTSpice

The sine wave is subsequently transmitted to the secondary side of the converter
through a high-frequency transformer. This transformer plays a crucial role in scaling
the voltage, ensuring that it meets the specific requirements of the application. Finally,
the diode rectifier converts the sine wave into a stable DC output.

The remarkable ability of LLC converters to maintain high efficiency even at

extremely high power levels stems from their resonant nature. This resonant
characteristic enables soft switching in both the primary and secondary sides of the
converter, leading to increased efficiency by reducing switching losses.

4.1 LLC Resonance Converter Topology Variants

Single Phase LLC

For low power application, single phase is more preferable because the current on the
power devices is only small. Single phase means that there is only one path for the
current. Below diagrams are examples of single phase LLC.

Single phase LLC can be configured as half bridge or full bridge. In above diagrams,
Lr denotes the resonant inductor, Cr refers to resonant capacitor while Lm symbolizes
the transformer magnetizing inductance. In actual application, there is no inductance
across the transformer because it is just art of the transformer primary. The diagrams
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above are only showing the representation of the magnetizing inductance to
emphasize the LLC (Lr, Lm and Cr).

4.1.1 Half Bridge LLC

Fig. 4.2 Half bridge topology

A half bridge LLC means that there is only one pair of switching devices in the
primary side like the diagrams above. They are both half bridge configurations since
there are only S1 and S2 which form a single pair. In the first diagram, the equivalent
resonant capacitance (the Cr in the second diagram) is the sum of the Csplit_A and
Csplit_B.

Half bridge variant is mostly use in low power since the effective voltage across the
LLC resonant network is only half the level of Vin. This results to a higher current in
the resonant network, so the power devices may have high power loss.

4.1.2 Full Bridge LLC

Below is a full bridge LLC converter. There are two pairs of switching devices in the
primary section (S1/S2 and S3/S4). Each pair will not conduct at the same time but it
is S1 and S4 that turn on together as well as S2 and S3.

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 Fig. 4.3 Full bridge topology

Full bridge is more popular at higher power application because the effective voltage
across the LLC network is the whole Vin. This results to a smaller current in the
resonant network.

4.1.3 Secondary Circuit Configuration

The secondary circuit configuration are either using diodes or switches. Switch is
could be BJT, IGBT or MOSFET. First diagram above uses a MOSFETs switch while
the second diagram uses a diodes.

Using a diode is simpler than using a switch because it requires no control

mechanism. On the other hand, switch needs a control mechanism that synchronizes
to the switches in the primary making it complex to implement.

The advantage of using a switch however is low voltage drop and low power loss.
This means, high system efficiency.

4.2 LLC Converter Modes of Operation

4.2.1 At Resonance (Fswitch = Fresonant)

LLC can operate in three modes. First is at resonance. This means that the switching
frequency of the LLC equates to the first resonant frequency discussed above. This is
the ideal scenario an LLC converter must behave in order to maximize the soft
switching action. Below are the attributes of operation at resonance frequency.

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 The tank or the resonant network input current (Ires) is near perfect sinusoid
(critically discontinuous) because the reactive inductance and reactive capacitance
cancels each other. See below plots.
 Input voltage to the tank or the resonance network leads current because of Lmag
 Before the current (I_Q1 and I_Q2) on the MOSFET starts to increase, the drain
voltage is already zero therefore no switching losses (soft switching, ZVS)
 Secondary current (Isec) is softly commutated
 Magnetizing current (Imag) is triangular

Fig. 4.4 wave forms at resonance frequency (82KHz)

4.2.2 Above Resonance (Fswitch>Fresonant)

The characteristics of LLC at above resonance are below.

 Tank input current (Ires) is continuous and not a perfect sinusoid

 Resonant choke peak current is low
 Lower magnetizing current
 Input voltage to the tank leads current
 Before the current on the MOSFET starts to increase, the drain voltage is already
zero therefore no switching losses (soft switching, ZVS)
 Lower peak current on MOSFET but not softly commutated that maybe a liability
in terms of efficiency
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 Secondary current is not softly commutated (but has lower peak and RMS value)

Fig 4.5 wave forms at above resonance frequency(100KHz)

4.2.3 Below Resonance (Fswitching<Fresonant)

The attributes of LLC operating below resonance are below.

 Tank input current (Ires) is discontinuous

 High peak current seen by the resonant choke (prone to saturation)
 Magnetizing current (Imag) is high and core losses are also high (watch out core
saturation). This is not good on efficiency.
 Input voltage to the tank leads current as courtesy of Lmag
 Before the current on the MOSFET starts to increase, the drain voltage is already
zero therefore no switching losses (soft switching, ZVS).
 Higher peak and RMS current on MOSFET. This is not good on efficiency.
 Secondary current is softly commutated but has high peak and RMS value. This is
not good on efficiency. This is also result to a higher ripple current on the output
capacitors.

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 Fig. 4.6 waveforms at below resonance frequency(75KHz)

4.3 ZVS operation

4.3.1 MODE 1

Fig. 4.7 power delivery cycle

First mosfet M1 is conducting and current flows form supply into the transformer
primary. The resoant inductor Lr and resonant capacitor Cr starts to resonate and
current starts to raise and due to electromagnetic induction voltage is induced in

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transformer secondary and diode D2 is forward biased and starts conducting and
power is transferred to the load.

In this time the top split capacitor discharges and transfers energy and bottom split
capacitor charges and stores energy. And the current through the magnetising inductor
raises and Lm stores energy.

Now after some time the Lr and Cr no longer resonates and load current falls to zero.
Now the primary is disconnected with the secondary and only the magnetising current
flows through the primary and freewheels.

4.3.2 MODE 2

Fig. 4.8 Dead time operation

Now the mosfet M1 is turned off but ILm continuous to freewheel so its takes
alternate path that is it starts to charge the Coss of mosfet M1 to Vdc and discharge
Coss of mosfet M2 to zero . the charging and discharging of parasitic capacitances of
both the mosfets takes place in this dead time between the agte pulses to the
mosfets.The Ilm starts to flow through the body diode of mosfet M2 and the bottom
split cap is completely charged to +Vdc/2 .

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4.3.3 MODE 3

As the voltage across mosfet M2 is now zero it is turned on, this called zero voltage
switching . i.e, the switch is turned on with the voltage across it zero or nearly zero.
This reduces the overlap of drain current and drain to source voltage and thus
reducing the turn on losses. Now the current direction in the primary winding is
reversed and Lr and Cr starts to resonate in the reverse direction and due to electro
magnetic induction emf is induced in secondary winding and diode D1 is forward
biased and transfers energy to the load. The bottom split cap discharges and the top
split cap charges and stores energy. Now the resonance stops and secondary and
primary are disconnected. And ILm does not change its direction and freewheels.

4.3.4 MODE 4

Now the mosfet M2 is turned off but the ILm does not change its direction so the
Coss of mosfet M1 is discharged and the Coss of mosfet M2 is charged to Vdc. After
the Coss of mosfets are charges and discharged ILm starts to flow through the body
diode of mosfet M1.

4.3.5 MODE 5

As voltage across the mosfet M1 is zero it is turned on so ZVS is achieved for M1.
The same cycle continuous.

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 5.SYNCHRONOUS RECTIFICATION OF LLC
CONVERTER

As the adoption of electric vehicles (EVs) continues to grow, the demand for efficient,
reliable, and fast-charging solutions becomes increasingly critical. One of the key
challenges in electric vehicle charging infrastructure is optimizing the efficiency of
chargers to reduce energy loss, enhance performance, and minimize charging time. In
this context, the focus of this project is to improve the efficiency of EV chargers
through the use of synchronous rectification.

Synchronous rectification is an advanced power conversion technique that replaces

traditional diodes with actively controlled switches, typically MOSFETs, to rectify
alternating current (AC) to direct current (DC). This method significantly reduces
power losses that are typically caused by the forward voltage drop of conventional
diodes, leading to higher efficiency and better thermal management. By integrating
synchronous rectification into the EV charger design, the system can deliver a more
efficient power conversion, reducing heat generation and energy waste, ultimately
enhancing the overall charging process.

5.1 Synchronization

Synchronous rectification is a technique used in LLC resonant converters where

traditional diodes are replaced with actively controlled MOSFETs for rectification.
This method reduces conduction losses by leveraging the low on-state resistance of
MOSFETs, eliminating the forward voltage drop of diodes. It also mitigates reverse
recovery losses, resulting in improved efficiency, reduced heat generation, and better
overall performance, particularly at higher current loads.

5.2 Need for synchronization

In the previous chapter, we discussed the operation of the primary side of the LLC
resonant converter. Now, we will delve deeper into the operation of the secondary side
and consider the losses associated with the diodes used in this stage.
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To recap, the LLC resonant converter is used to convert a fixed DC supply into a
variable DC supply. As we saw earlier, the DC supply is first converted into a square
wave using a half-bridge inverter. Then, the LLC resonant circuit is employed to
shape the waveform into a sinusoidal form. After this, the rectification process begins.

Now, let's focus on the secondary operation in more detail. In an LLC resonant
converter, the transformer used is typically a centre-tapped transformer. This means
the secondary winding is split into two parts, with each half connected to a diode.
Depending on the polarity of the AC waveform at any given time, one diode will
conduct while the other remains off. This ensures that the current flows in the correct
direction, providing the necessary rectification for the converter.

However, a critical factor in this process is the inherent losses associated with diodes,
which impact the overall efficiency of the converter. Each diode has a forward voltage
drop, which is a major source of power loss during conduction. The forward voltage
drop can be represented as the voltage difference between the anode and cathode
when the diode is conducting current. As the current increases, these conduction
losses also increase.

For example, consider a typical silicon diode. At a current of 1A, the forward voltage
drop might be around 0.6V, resulting in a power loss of approximately 0.6W.
However, when the current increases to 30A, the power loss increases significantly,
reaching up to 18w. This increase in power loss is a direct result of the higher voltage
drop across the diode at higher currents.

In addition to conduction losses, another significant issue is the reverse recovery of

the diode. When the diode switches from conducting to non-conducting, there is a
brief period during which the diode continues to conduct in the reverse direction
before it fully recovers. This reverse recovery phenomenon leads to additional losses,
especially at higher switching frequencies. The energy dissipated during reverse
recovery contributes to further inefficiency, making it another challenge to manage in
the design of high-performance LLC converters.

In conclusion, while diodes are essential for the rectification process in LLC resonant
converters, they introduce significant losses, both due to their forward voltage drop
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and reverse recovery characteristics. These losses impact the overall efficiency of the
converter, especially as the load current increases. In the following sections, we will
explore how synchronous rectification can address these losses and improve the
overall performance of the LLC resonant converter.

5.3 Synchronous LLC converter operation

The below picture shows the general circuit diagram for synchronous rectification of
llc converter.

Fig. 5.1 General circuit diagram of Synchronised LLC

From the above circuit we can observe that QHS and QLS acts as half bridge inverter
circuit and QSR1 and QSR2 acts as rectificater circuit. The pulses to these mosfets are
given in such a way to achieve less switching as possible.one of the possible way to
give pulse is as fallows

5.3.1 Pulses to mosfet

In a typical LLC converter, the switching of MOSFETs plays a crucial role in its
efficiency. When observing the circuit for synchronous rectification, particularly in a
half-bridge inverter configuration, we note that when the top MOSFET conducts, Q1
in the LLC converter will also conduct. In such scenarios, if pulses are applied to the
MOSFET, the body diode of the MOSFET will conduct first, behaving similarly to a

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diode rectifier. This can lead to inefficiencies if not managed properly, as the body
diode is typically slower and less efficient than an actively switched MOSFET.

To ensure more efficient operation, it is essential to control the timing of the pulses
applied to the MOSFETs. The reason for this is that if both voltage and current are
non-zero when the MOSFET switches, it results in higher switching losses. This is
due to the simultaneous voltage and current overlap, which causes increased
dissipation during the switching transitions.

One method to mitigate these losses is to utilize the body diode of the MOSFET. By
timing the gate pulses such that the MOSFET switches only after the body diode has
conducted and the current has been properly managed, switching losses can be
reduced. The time delay between the pulse for the half-bridge MOSFET and the
conduction of the body diode can be calculated by analyzing the voltage and current
waveforms. This calculation will allow for precise timing of the gate drive pulses to
minimize switching losses.

In general applications, a microcontroller can be used to generate the gate drive pulses
with a user-defined format. By adjusting the timing and ensuring that the MOSFETs
switch at the optimal moment, the overall efficiency of the LLC converter can be
significantly improved. While giving pulses from the micro controller the specific pin
of microcontroller from specific port shoulde be made high.The circuit diagram used
for simulation in LtSpice is as fallows.

Fig. 5.2 Circuit diagram for simulation

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In the above figure the mosfet M3 and M4 represents the mosfets in secondary side
and the resistance 2.5 ohms is considered as the load

Fig. 5.3 Pulses given to primary and secondary mosfet

From the above figure we can observe that there is some delay between the turn on of
mosfet in half bridge circuit (VN006,N007) to the turn of mosfet in rectifier
circuit(VN015). During this period the diode of the mosfet will conduct and power
consumption during this period is less

In the context of synchronous rectification, every MOSFET is associated with two

primary types of losses: conduction losses and switching losses. Understanding these
losses and how to minimize them is essential for improving the overall efficiency of
the LLC converter. Let’s dive deeper into these losses and explore how we can
mitigate them.

5.4 Various losses in converter

5.4.1 Conduction Losses

Conduction losses occur due to the resistance in the MOSFET channel when current
flows through it. Every MOSFET has a characteristic RDS(on), which is the on-
resistance between the drain and source terminals when the MOSFET is conducting.
This resistance is a result of the minority carriers present in the MOSFET junctions. A

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key point to note is that RDS(on) increases with the temperature, which means that as
the MOSFET heats up, the conduction losses will also increase.

To minimize conduction losses, we need to select MOSFETs with low RDS(on). By

choosing MOSFETs with low on-resistance, we can reduce the power dissipated
during conduction. For example, in this project, the specifications of the mosfet
selected is as fallows

Fig. 5.4 Specifications of Mosfet

As an example, let's assume that an RMS current of 30A is flowing through the
MOSFET. If the R_DS(on) is low, the conduction losses can be kept around 9W—
which is roughly half of the losses that would occur in a typical diode rectifier. This
significantly improves efficiency compared to using standard diode rectifiers, where
conduction losses can be higher.

5.4.2 Switching losses

Switching losses occur during the transition of a MOSFET from its "off" state (cut-off
region) to its "on" state (saturation region). This transition period is referred to as the
transition period, during which both the voltage across the MOSFET and the current
through it are non-zero. When both voltage and current are non-zero, power is
dissipated, leading to switching losses.

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In a typical scenario, the losses during this transition can be significant. However, by
increasing the switching frequency, the losses can be reduced. The reason behind
switching losses is the simultaneous presence of both voltage and current during the
switching event. To reduce these losses, it is ideal to minimize the overlap of voltage
and current.

Two primary techniques used to reduce switching losses are Zero Voltage Switching
(ZVS) and Zero Current Switching (ZCS). In this project, we utilize the ZVS (Zero
Voltage Switching) method to reduce switching losses, and we will now analyze how
it works and how it is implemented in our operation.

Zero Voltage Switching (ZVS)

As the name suggests, Zero Voltage Switching (ZVS) is a technique designed to

minimize switching losses by ensuring that the voltage across the MOSFET is nearly
zero during the switching transition. In traditional switching methods, both voltage
and current can be non-zero simultaneously, leading to power dissipation in the form
of heat. However, by implementing ZVS, the overlap between voltage and current is
significantly reduced, which effectively decreases switching losses and enhances
overall efficiency.

In our design, we utilize the body diode of the MOSFET as an integral part of the
ZVS technique. During specific periods, the body diode is allowed to conduct before
the MOSFET is turned on. This conduction phase ensures that the voltage across the
MOSFET is nearly zero before the switching action occurs. Since the MOSFET is
switched on only when the voltage across it is minimal, the amount of energy
dissipated as heat is greatly reduced, improving the thermal performance of the
system.

The key advantage of ZVS lies in its ability to lower power losses without
compromising the switching speed. By reducing the stress on the MOSFET and other
switching components, ZVS extends the lifespan of power devices and enhances the
reliability of the LLC converter. Additionally, the technique helps in reducing
electromagnetic interference (EMI), making it highly beneficial for high-frequency
power conversion applications.
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By implementing the ZVS method, we ensure that the MOSFET switches with
minimal voltage overlap, leading to efficient power conversion and lower heat
dissipation. This results in an optimized LLC resonant converter that not only
operates at higher efficiency but also maintains better thermal stability. The
integration of ZVS into the power stage significantly contributes to improving the
overall performance of the system, making it ideal for applications requiring high-
efficiency power electronics.

Fig. 5.5 Mosfet current wave form

From the above figure we can observe that how voltage and current waveforms are
therein these specific condtion

In the above diagram we can observe that first mosfet body diode starts conducting
then the voltage across it drops nearly equal to zero

The conduction losses in above mosfet is alos nearly less

5.5 Comparison

Now let us compare the efficiency of llc converter with the diode and synchronized llc
converter

5.5.1 Efficiency of converter with diode :

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 Fig. 5.6 Efficiency of llc with diode

From below figures we can observe the input power and output power of the diode
converter and its efficiency as 1.2968KW, 1.1212KW and 86.4% respectively

5.5.2 Efficiency of converter with mosfet

Fig. 5.7 Efficiency of llc with mosfet

From the below figures we can observe the input power and output power of
synchronized llc converter are 1.1817KW, 1.1719KW and efficiency as 99%.

From the two efficiency comparision we can clearly see that efficiency got increased.

Thus synchronous rectification is one of the method to increase the efficiency of LLc
converetr and as losses decreses the which reduces the burden on the heat sink

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 6.FAULT MANAGEMENT

Fault management is a critical aspect in designing reliable and efficient chargers.

Ideally, a charger should operate without any faults, but in reality, faults can occur
during operation. When a fault happens, it's important to understand the cause and
how to resolve it quickly to prevent further issues. For this reason, implementing a
robust fault management system is essential for both the host and client sides of the
charger system.

Before a charger is sold to customers, it undergoes rigorous testing to ensure its

proper functionality. These tests often involve continuous running, on-off testing, and
operating the charger for extended periods (such as 30 minutes, 1 hour, or 4 hours).
However, simply running the charger through these tests is not enough. It’s crucial to
have insights into the internal workings of the charger to identify any faults that may
occur during operation.

For instance, if the charger unexpectedly turns off, it's important to understand why
this happens. Without an effective fault management system, troubleshooting such an
issue would be extremely difficult. In the absence of data, one would have to
physically open up the charger, check the system, and start testing the components
from scratch. This is inefficient and time-consuming.

By logging these parameters at regular intervals, we are able to track the charger’s
performance over time. If a fault occurs, we can quickly refer to the logged data to
determine what went wrong, when the fault occurred, and which component may have
failed. This enables faster debugging, improves the reliability of the charger, and
ensures that the product is thoroughly tested and ready for the customer.

6.1 MICROCHIP dsPIC33CK64MP506 Digital Signal Processor

Microchip’s dsPIC33CK family of digital signal controllers (DSCs) feature a 100

MHz dsPIC DSC core with integrated DSP and enhanced on-chip peripherals. It is
mainly designed for demanding real-time embedded control applications. These DSCs

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enable the design of digital power, motor control, advanced sensing and control, high-
performance general-purpose and robust applications.

The DSCs simplify the design of high-performance, precision motor control systems
that are more energy efficient, quieter in operation and provide extended motor life.
They can be used to control Brushless DC (BLDC), Permanent Magnet Synchronous
Motors (PMSM), AC Induction Motors (ACIM), Switched Reluctance (SR) motors,
and stepper motors.

In the digital power segment, this family of devices is ideal for designing switched
mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-
precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC
and other power circuits to reach the highest possible energy efficiency.

The dsPIC33CK32MP506, a notable member of this family, incorporates critical

safety features essential for reliable operation in safety-sensitive applications. These
include a windowed watchdog timer that monitors system activity, a fail-safe clock
monitor ensuring accurate timing, and flash error correction code (ECC) that enhances
data integrity and reliability. These safeguards are indispensable in maintaining
operational safety and preventing system failures in critical environments.

Equipped with 32 KB of RAM and 512 KB of Flash memory, the

dsPIC33CK32MP506 provides ample storage for both program instructions and data.
Supporting a variety of communication protocols, the dsPIC33CK32MP506 includes
UART, SPI, I2C, and CAN interfaces. This versatility enables seamless connectivity
with external devices, sensors, and networks, enhancing its utility in interconnected
and communication-intensive applications.

The dsPIC33CK32MP506 Digital Signal Controller (DSC) includes pins for power
supply and ground, with VDD providing the positive supply voltage (typically +3.3V)
and VSS serving as the ground reference. For clock and oscillator connectivity, the
device features XTAL1 and XTAL2 pins, which accommodate external crystal
oscillators or resonators, ensuring stable clock signals essential for precise timing in
operations.

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Communication interfaces are robustly covered with UART pins for serial
communication (TX and RX), SPI pins for serial peripheral communication (SCK,
SDI, SDO, and SS/CS), I2C pins (SCL and SDA) for inter-integrated circuit
communication, and CAN pins (CAN_TX and CAN_RX) dedicated to controller area
network communication.

Analog inputs and outputs are facilitated through dedicated ADC and DAC pins,
enabling accurate conversion between analog signals and digital values, crucial for
applications requiring precise measurement and control of analog voltages.

The controller also provides PWM outputs via specific pins, essential for generating
variable-width pulses to control devices such as motors and actuators, offering
flexibility in voltage regulation and power management. Reset and programming
functions are handled by MCLR for master clear and reset operations, along with
PGC and PGD pins utilized for in-circuit programming and debugging (ICSP),
streamlining development and testing processes.

General-purpose I/O (GPIO) pins are available for configuring as inputs or outputs,
facilitating interfacing with external sensors, peripherals, and other components,
offering flexibility in system integration and functionality expansion. Special
functionality includes interrupt pins for managing external events and processing
interrupts, as well as clock output pins for synchronizing operations in applications
requiring precise timing and coordination.

6.2 Timer Interrupts

Timer interrupts are utilized in embedded systems to manage and synchronize time-
based operations. They are typically implemented using hardware timers integrated
into the microcontroller, such as the dsPIC33CK64MP506, which features multiple
Timer modules. These timers can be configured to generate interrupts at specific
intervals or when certain conditions are met, providing precise timing control for
critical tasks within the system.

When a timer interrupt occurs, the microcontroller interrupts its current execution to
handle the interrupt service routine (ISR) associated with the timer. This ISR is a

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specialized function programmed by the developer to execute specific actions or tasks
in response to the timer event. For example, ISR routines may involve updating
system states, processing data, or triggering other events based on the timing
requirements of the application.

Timer interrupts are essential for time-sensitive applications where tasks need to be
executed at precise intervals or in synchronization with external events. They enable
efficient multitasking by allowing the microcontroller to perform background
operations while simultaneously responding to time-critical events. This capability
enhances the responsiveness and real-time performance of embedded systems across
various domains, including industrial automation, automotive electronics, and
consumer electronics.

In our applications, we configure timer modules to match the timing requirements of

their specific tasks. This involves setting parameters such as timer period, prescaler
values, and interrupt enablement to achieve desired interrupt frequencies and timing
accuracy. By fine-tuning these settings, developers ensure that the system operates
reliably and efficiently, meeting performance objectives while conserving power and
resources.

6.3 Communication Protocols

6.3.1 SPI
The Serial Peripheral Interface (SPI) is a synchronous serial communication protocol
developed by Motorola in the mid-1980s. It has become a staple in embedded systems
due to its straightforward design and high-speed data transfer capabilities. SPI is
particularly favoured for its ability to facilitate efficient and reliable communication
over short distances, making it ideal for interconnecting microcontrollers, sensors, and
other peripheral devices.

One of the defining features of SPI is its synchronous communication mechanism,

which uses a shared clock signal to synchronize the data transfer between the master
and slave devices. This synchronous nature enables SPI to achieve full-duplex data
transfer, allowing simultaneous data transmission and reception. This is accomplished
through separate data lines: MOSI (Master Out Slave In) for sending data from the
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master to the slave, and MISO (Master In Slave Out) for receiving data from the slave
to the master.

SPI operates on a master-slave architecture, where a single master device controls the
communication, while one or more slave devices respond to the master’s commands.
The master generates the clock signal and selects which slave device to communicate
with by pulling the corresponding chip select (CS) line low. This architecture allows
for a flexible and straightforward communication setup, though it requires a dedicated
CS line for each slave, which can increase the pin count on the master device.

The SPI interface typically consists of four main lines: MOSI, MISO, SCLK (Serial
Clock), and CS/SS (Chip Select/Slave Select). During communication, the master
device selects the appropriate slave by activating the corresponding CS line. The
master then generates the clock signal on the SCLK line, synchronizing the data
exchange. Data is transferred bit by bit on the MOSI and MISO lines, with each bit
being clocked out by the master and clocked in by the slave, and vice versa, in a
synchronized manner.

SPI offers several advantages, including high-speed data transfer capabilities and a
simple hardware interface. The absence of addressing overhead, as seen in other
protocols like I²C, allows for more efficient communication, as the master directly
selects the slave devices using the CS line. However, SPI also has its drawbacks. The
lack of a standardized protocol can lead to variations in implementation across
different devices. Additionally, SPI is designed for short-distance communication,
typically within the same circuit board, and the requirement for additional CS lines for
each slave can increase the overall pin count. Its versatility and efficiency make SPI a
reliable choice for a broad range of embedded applications.

6.3.2 I2C

The Inter-Integrated Circuit (I2C) is a synchronous serial communication protocol

developed by Philips Semiconductors (now NXP Semiconductors) in the early 1980s.
It was designed to allow communication between low-speed peripheral devices over a
two-wire bus. I2C has become widely adopted in embedded systems, particularly in

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applications where multiple devices need to communicate with minimal wiring and
reduced pin count. It is commonly used in systems with microcontrollers, sensors, and
peripheral devices that need to be interconnected.

One of the defining features of I2C is its ability to support multi-master and multi-
slave communication. This means that multiple master devices can control the
communication bus, although only one master can control the bus at a time. In
contrast to protocols like SPI, which require multiple lines for each slave device, I2C
uses only two signal lines: SDA (Serial Data Line) and SCL (Serial Clock Line). This
simple two-wire setup significantly reduces the number of pins required, making it
ideal for systems where space and pin count are limited.

I2C operates on a master-slave architecture. The master device generates the clock
signal and controls the communication process, while the slave devices respond to the
master’s commands. Each device on the I2C bus has a unique address, and
communication is initiated by the master device selecting a slave using its address.
The data is transferred serially, with each bit being transmitted on the SDA line while
the clock signal is generated on the SCL line to synchronize the data transfer.

The typical communication process in I2C begins with a start condition, where the
master generates a signal by pulling the SDA line low while the SCL line remains
high. Following this, the master sends the address of the target slave device along
with a read/write bit to specify the direction of data transfer. The slave device
acknowledges the address by pulling the SDA line low. After the address phase, the
master and slave exchange data, with each byte followed by an acknowledgment bit.
The communication ends with a stop condition, where the master releases the SDA
line while keeping the SCL line high.

I2C has several advantages, including its simple wiring. With only two signal lines,
I2C can connect a large number of devices with minimal complexity, making it
particularly useful for connecting sensors, EEPROMs, and other peripheral devices.
Additionally, I2C supports multi-master configurations, allowing multiple devices to
initiate communication. The protocol also supports addressing, meaning each device

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on the bus has a unique identifier, making it possible to share the bus among multiple
devices.However, I2C also has limitations. Its data transfer rate is relatively lower
compared to protocols like SPI, with standard speeds of up to 100 kbps and higher-
speed modes reaching up to 1 Mbps. This makes it less suitable for high-speed
applications. Furthermore, I2C is generally designed for short-distance
communication, making it ideal for use within a single circuit board or within close
proximity. As the bus is shared, the protocol can also experience bus contention,
where multiple devices attempt to communicate at the same time, potentially leading
to conflicts.

6.3.3 CAN

Controller Area Network (CAN) is a robust, high-speed serial communication

protocol designed for real-time control applications, originally developed by Bosch in
the mid-1980s. It was specifically created for the automotive industry, where reliable
and efficient communication between various electronic control units (ECUs) is
crucial. Over time, CAN has become widely used in many other fields, including
industrial automation, medical equipment, and embedded systems, due to its ability to
facilitate reliable communication even in electrically noisy environments.

One of the defining features of CAN is its multi-master architecture, which allows
multiple devices (called nodes) to be connected on the same bus. Each node can
transmit and receive data, but the protocol ensures that only one node sends data at
any given time, thus preventing data collisions. CAN uses a priority-based arbitration
system to manage access to the bus, which ensures that the highest-priority message
always gets through first. This feature is essential for applications like automotive
systems, where certain messages, such as safety-critical signals, must be transmitted
immediately.

CAN communication is based on a two-wire twisted pair bus, typically consisting of

CAN_H (CAN High) and CAN_L (CAN Low) lines. These lines are used for
differential signaling, which allows for greater noise immunity and reliable data
transmission over long distances (up to several kilometers). The use of differential

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signaling also helps CAN systems operate effectively in harsh environments with
electromagnetic interference (EMI), making it a reliable protocol in challenging
conditions.

The CAN protocol uses a message-based communication structure, where each node
sends and receives messages instead of data packets. Each message consists of a
header (containing identifiers, control bits, and other information) and a data section
(which holds the actual payload). The identifier field is particularly important, as it
determines the priority of the message in the arbitration process. CAN supports both
standard (11-bit) and extended (29-bit) identifiers, allowing for a large number of
unique message IDs, making it scalable for complex systems with many nodes.

In terms of data transmission, CAN supports both data frames (for standard data
transmission) and remote frames (used to request data from another node). It also
includes error handling mechanisms, such as cyclic redundancy check (CRC) and
acknowledgement bits, to ensure reliable communication and minimize the impact of
transmission errors. If a message is corrupted or not acknowledged, the CAN protocol
will automatically retransmit the message, ensuring data integrity.

One of the major advantages of CAN is its high-speed data transfer capabilities. With
data rates up to 1 Mbps (in the case of high-speed CAN), it is suitable for applications
requiring fast and real-time communication. Additionally, the protocol supports long-
distance communication (up to several kilometers) without significant data
degradation, which is an essential feature for automotive and industrial applications.

6.4 Client Side - Data Logging Through EEPROM

The I2C communication in code is responsible for writing data to an EEPROM. The
I2C2_Write function is used for this, and it requires three parameters: the slave
address (either 0x50 or 0x51), a data buffer containing the data to be written, and the
data length (typically 16 bytes). The EEPROM uses a 7-bit addressing scheme, where
the first four bits indicate the device ID, the next two bits select the slave, and the last
bit denotes the page size. The page size can either be for addresses 0-255 or 256-511,
depending on the configuration. When writing data to the EEPROM, the address to
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which the data is written is specified by the first byte of the data_buffer, and the
subsequent bytes hold the actual data. The EEPROM can only write 16 bytes at a
time, so the data is sent in chunks of 16 bytes, ensuring efficient memory utilization.

Fig. 6.1. EEPROM Pin Diagram and Connection

To ensure data integrity, a delay is introduced between consecutive write operations,

typically between 1ms and 10ms. This allows the EEPROM to properly commit the
data. The data written to the EEPROM includes fault status, status flags, and various
other parameters, such as temperature readings and dummy values for future use. The
memory addressing is handled by the cntwrite_buffer, which is updated during each
cycle. The address is incremented after each write cycle, and if it exceeds a certain
limit (e.g., 240), it wraps around to start again.

The interrupt service routine, _PWM6Interrupt, triggers various operations, including

temperature calibration, CAN communication, and EEPROM write. The timer
variable increments with each cycle, and based on the timer value, specific data write
operations to the EEPROM are performed. For example, when timer reaches 20 or 40,
the data is written to the EEPROM. The interrupt also handles data transmission to the
CAN bus and other system tasks.

Additionally, error handling mechanisms are implemented to detect and recover from
communication failures during I2C transactions. If an acknowledgment (ACK) is not
received from the EEPROM, the write operation is retried after a short delay. This
ensures reliable data storage and prevents data corruption due to transient errors.

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Proper clock stretching is also considered to allow the EEPROM sufficient time to
process the received data.

Fig. 6.2. I2C Initializations

Fig. 6.3. Test Code

In summary, the I2C write operation in your code efficiently handles data logging to
the EEPROM, ensuring that the data is written in the correct format and at the proper
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address. The use of delays between write cycles, along with the careful management
of memory addresses and data buffers, guarantees the integrity of the data being
stored.

6.5 HOST SIDE - Logging using SD Card and RTC Module

The host-side system is designed to log data from various parameters like mains
voltage, mains current, battery voltage, battery current, and fault statuses using an SD
card. The data is collected and logged via SPI communication, and each data entry is
timestamped using an RTC (Real-Time Clock) module for accurate event logging.
The real-time timestamp is crucial because, without it, we cannot determine the
duration of faults or events like the charging process or when a fault occurs. Having a
timestamp ensures that we can track how long a fault has persisted or when a specific
event, such as the turning on/off of a charger, happens.

6.5.1 Data Writing to the SD Card

The data is written to the SD card via the SPI protocol. Initially, charger data is
continuously transmitted through the CAN (Controller Area Network) bus. Using
CAN transmission and reception, the microcontroller receives continuous data about
all the parameters inside the charger. The data is received in hexadecimal format from
CAN messages and is then converted into readable decimal values to log on the SD
card.

To facilitate this process, we use the FatFS library for handling the file system on the
SD card and the SD_SPI library for SPI communication. The MPLAB X IDE is used
for development, and the SPI protocol is configured using driver files. The
microcontroller chosen for this project is the DSPIC33CK64MP506, which has three
SPI modules. Based on the available pins, the appropriate SPI interface is selected.
The configuration includes settings like number, frequency, mode, and data sampling,
with predefined pins for MISO, MOSI, SCK, and a customizable CS pin.

The received data is processed and structured before being written to the SD card to
ensure proper logging and easy retrieval. Error handling mechanisms are implemented
to detect and manage communication failures, ensuring data integrity during
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transmission and storage. Additionally, timestamps are included in the logged data to
track events accurately and analyze trends over time.

Fig. 6.4. SD Card Module

6.5.2 Real Time Stamp With RTC Module

The RTC module is used to get real-time timestamps. In MPLAB X IDE, the I2C
module is configured to communicate with the RTC module. The I2C interface is used
because the RTC module communicates over I2C. There are three available I2C
modules in the DSPIC33CK64MP506, and we select the host configuration with a
frequency setting for reading data every 500ms. The RTC module provides three
primary time parameters: seconds, minutes, and hours, which are then used to
generate a timestamp for each data log entry.

Fig. 6.5. RTC Module

6.5.3 Code Flow

1. SPI Protocol: SPI is used for communication with the SD card to store the data.
Once the CAN messages are received by the microcontroller, the hex data is
converted into readable decimal values, and the formatted data is logged onto the
SD card. The FatFsDemo_Tasks function handles the SD card operations, writing
the data into a CSV file.

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 Fig. 6.6. Data Logger Circuit

2. RTC Timestamping: The RTC module is configured to fetch the current time
(hours, minutes, and seconds) and append it to each data entry. This timestamp
helps to keep track of the time when each reading is taken.
3. CAN Communication: The data from the charger system is transmitted using
CAN communication. The can_packet_transmit and can_packet_receive functions
manage the transmission and reception of data packets. These packets contain
various parameters such as serial number, status, faults, and readings for battery,
mains voltage, and current. The received data is processed and stored for logging.
4. SD Card File Management: The f_mount and f_open functions mount and open
the SD card for file operations. If the SD card is available, the data is appended to
a CSV file (FINALOG.CSV). The first time the file is accessed, headers are
written, and subsequent data entries are logged with the timestamp and various
parameters.
5. If we remove power and again connect it then you get the header in excel sheet.
For evrey power on reset you get the header in created file. We have dedicated
excel sheet which contains fault calculation. That will help to find the which fault
occur inside the charger. Some of the faults we observed is Mains overcurrent, DC
Link undervoltage, Temperature Fault.

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 Fig. 6.7. Main Code

Fig. 6.8. Output File

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