DATA SHEET

PRELIMINARY PRODUCT INFORMATION

MOS INTEGRATED CIRCUIT

µPD780948(A), µPD780949(A)
8-BIT SINGLE-CHIP MICROCONTROLLER

Description
The µPD780948/780949 is a member of the 78K/0 series microcontrollers. Besides a high speed, high
performance CPU, these microcontrollers have on-chip ROM, RAM, I/O ports, 8-bit resolution A/D converter,
timer, CAN-interface, serial interface, interrupt control, LCD-controller/driver and various other peripheral
hardware.

The µPD78F0948/780949 device includes a FLASH EEPROM version which can operate in the same
power supply voltage range as the mask ROM version, and various development tools are available.

The details of the functions are described in the following user manuals. Be sure to read it before
starting design.
µPD780949, Subseries User's Manual : U12670EE1V0UM00
78K/0 Series User's Manual - Instructions : U12336EJ3V0UM00

Features
• Internal high capacity ROM and RAM

Data Memory
Item Program
Package
Internal
Part Memory LCD Display Internal
High-Speed EEPROM
Number (ROM) RAM Expansion RAM
RAM
µPD780948(A) 60K bytes 1024 bytes 40 bytes 992 bytes - 100-pin plastic QFP (fine pitch)

µPD780949(A) 60K bytes 1024 bytes 40 bytes 992 bytes 256 bytes 100-pin plastic QFP (fine pitch)

• External memory expansions space : 1K bytes • CAN-Interface

• Instruction execution time can be changed from • Serial interface : 3 channels
high speed (0.25 µs) to ultra low speed • 2-wire mode : 1 channel
• I/O ports: 79 (N-ch open drain : 5) • 3-wire mode : 1 channel
• 8-bit resolution A/D converter : 8 channels • UART mode : 1 channel
• Sound generator • Timer : 6 channels
• LCD-controller / driver • Supply voltage : VDD = 4.0 to 5.5 V

Application
Dashboard, climate controller, security unit etc.

The information in this document is subject to change without notice.

Document No. U12237EE1V2PM00 (2 nd edition)  NEC Corporation 1998

© 19
Date : April 1998
 µPD780948(A), µPD780949(A)

Ordering Information

Part Number Package

µPD780948GF(A)-3BA 100-pin plastic QFP (14 x 20 mm, resin thickness 2.7 mm)
µPD780949GF(A)-3BA 100-pin plastic QFP (14 x 20 mm, resin thickness 2.7 mm)

78K/0 Series Development

These products are a further development in the 78K/0 Series. The designations appearing inside the
boxes are subseries names.
Products in mass production

Products under development

Y subseries products are compatible with I2C bus.
For control
100-pin µ PD78078 µ PD78078Y Timer added to the µPD78054, external interface functions enhanced
100-pin µ PD78070A µ PD78070AY ROM-less product for the µPD78078
80-pin µ PD78054 µ PD78054Y UART and D/A added to the µPD78014, I/O enhanced
64-pin µ PD78018F µ PD78018FY Low-voltage (1.8 V) operation version of the µPD78014, ROM and RAM variations enhanced
64-pin µ PD78014 µ PD78014Y A/D and 16-bit timer added to the µPD78002
64-pin µ PD780001 A/D added to the µPD78002
64-pin µ PD78002 µ PD78002Y Basic subseries for control
42/44-pin µ PD78083 Internal UART, low-voltage (1.8 V) operation possible

For FIP driving

100-pin µ PD780208 I/O, FIP C/D of the µPD78044A enhanecd, display output total: 53
78K/0
80-pin µ PD78044A 6-bit U/D counter added to the µ PD78024, display output total: 34
Series
64-pin µ PD78024 Basic subseries for FIP driving, display output total: 26

For LCD driving

100-pin µ PD78064 µ PD78064Y Subseries for LCD driving, internal UART

For IEBusTM
80-pin µ PD78098 IEBus controller added to the µPD78054

For CANBus
100-pin µ PD780949 CANBus controller

Major functional differences among the subseries

Function Timer VDD

ROM 8-bit 8-bit Serial External
I/O MIN.
Capacity A/D D/A Interface Expansion
Subseries Name 8-bit 16-bit Watch WDT Value

For Control µPD78078 32 K-60 K 4ch 1ch 1ch 1ch 8ch 2ch 3ch (UART: 1ch) 88 1.8 V O
µPD78070A — 61 2.7 V
µPD78054 16 K-60 K 2ch 69 2.0 V
µPD78018F 8 K-60 K — 2ch 53 1.8 V
µPD78014 8 K-32 K 2.7 V
µPD780001 8K — — 1ch 39 —
µPD78002 8 K-16 K 1ch — 53 O
µPD78083 — 8ch 1ch (UART: 1ch) 33 1.8 V —
For FIP µPD780208 32 K-60 K 2ch 1ch 1ch 1ch 8ch — 2ch 74 2.7 V —
driving µPD78044A 16 K-40 K 68
µPD78024 24 K-32 K 54
For LCD µPD78064 16 K-32 K 2ch 1ch 1ch 1ch 8ch — 2ch (UART: 1ch) 57 2.0 V —
driving
For IEBus µPD78098 32 K-60 K 2ch 1ch 1ch 1ch 8ch 2ch 3ch (UART: 1ch) 69 2.7 V O
For CANBus µPD780949 60 K 2ch 2ch 1ch 1ch 8ch — 3ch (UART: 1ch) 79 4.0 V O
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 µPD780948(A), µPD780949(A)

Overview of Functions
Part Number
µPD780948 µPD780949
Item
ROM 60 Kbytes
Internal high-speed RAM 1024 bytes
Internal
LCD Display RAM 40 bytes
memory
Internal Expansion RAM 992 bytes
EEPROM - 256 bytes
Memory space 64 Kbytes
General registers 8 bits x 32 registers ( 8 bits x 8 registers x 4 banks)
Instruction cycle On-chip instruction execution time selective function
When main system clock
0,25 µs/0,5 µs/1 µs/2 µs/4 µs (at 8 MHz)
selected
When subsystem clock
122 µs (at 32.768 kHz)
selected
• 16-bit operation
• Multiplication/division ( 8 bits x 8 bits, 16 bits – 8 bits )
Instruction set
• Bit manipulation ( set, reset, test, boolean operation )
• BCD adjustment, etc.
Total : 79
I/O ports • CMOS input : 8
• CMOS I/O : 71
A/D converter • 8 bit resolution x 8 channels
• 3-wire mode : 1 channel
Serial Interface • 2-wire mode : 1 channel
• UART mode : 1 channel
• 16 bit timer / event counter : 2 channels
• 8 bit timer / event counter : 2 channels
Timer
• Watch timer : 1 channel
• Watchdog timer : 1 channel
Timer output 3 ( 16-bit RWM output x 1, 8-bit RWM output x 2 )
62,5 kHz, 125 kHz, 250 kHz, 500 kHz, 1 MHz, 2 MHz,
Clock output
4 MHz, 8 MHz (at main system clock of 8.0 MHz)
CAN 1 channel
Internal : 22
Maskable interrupts
Vectored External : 5
interrupts Non-maskable interrupts Internal : 1
Software interrupts Internal : 1
Supply voltage VDD = 4,0 V to 5,5 V
Package 100-pin plastic QFP ( 14 mm x 20 mm )

Major Changes

Page Description

18 The internal high-speed RAM is 1024 x 8 bits

Note: The mark ★ shows major revised points.

3
 µPD780948(A), µPD780949(A)

Contents

1. Pin Configuration (Top View) ........................................................................................................ 5

2. Block Diagram ................................................................................................................................ 7

3. Pin Functions ................................................................................................................................. 8

3.1 Normal Operating Mode Pins ........................................................................................................ 8
3.2 Non-port Pins ............................................................................................................................... 10
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ............................................ 12

4. Memory Space .............................................................................................................................. 18

5. Peripheral Hardware Functions .................................................................................................. 19

5.1 Ports .............................................................................................................................................. 19
5.2 Clock Generator ........................................................................................................................... 20
5.3 Main System Clock Oscillator ..................................................................................................... 20
5.4 Subsystem Clock Oscillator ........................................................................................................ 21
5.5 Timer/Event Counter .................................................................................................................... 21
5.6 Clock Output Control Circuit ....................................................................................................... 27
5.7 Sound Generator .......................................................................................................................... 29
5.8 A/D Converter ............................................................................................................................... 30
5.9 Power Fail Detector ...................................................................................................................... 31
5.10 Serial Interfaces ............................................................................................................................ 32
5.11 CAN-Bus Interface ........................................................................................................................ 34
5.12 LCD Controller/Driver................................................................................................................... 34

6. Interrupt Functions and Test Functions ..................................................................................... 36

6.1 Interrupt Functions ...................................................................................................................... 36
6.2 Interrupts ...................................................................................................................................... 37

7. External Device Expansion Functions ........................................................................................ 39

8. EEPROM Function ........................................................................................................................ 39

9. Standby Function ......................................................................................................................... 39

10. Reset Function ............................................................................................................................. 39

11. Instruction Set .............................................................................................................................. 40

12. Electrical Specifications .............................................................................................................. 43

13. Package Drawings ........................................................................................................................ 60

14. Recommended Soldering Conditions ......................................................................................... 61

Appendix A. Development Tools .................................................................................................... 62

Appendix B. Related Documents .................................................................................................... 64

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 µPD780948(A), µPD780949(A)

1. Pin Configuration (Top View)

Ý100-pin plastic QFP (14 x 20 mm)
µPD780948GF(A)-XXX-3BA
µPD780949GF(A)-XXX-3BA
Figure 1-1: Pin Configuration

P52/A10/S37
P53/A11/S36
P54/A12/S35
P55/A13/S34
P56/A14/S33
P57/A15/S32
P50/A8/S39
P51/A9/S38
P67/ASTB
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P65/WR
P64/RD
CRxD

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
CTxD 1 80 P70/S31
P00/INTP0 2 79 P71/S30
P01/INTP1 3 78 P72/S29
P02/INTP2 4 77 P73/S28
P03/INTP3/T2PO 5 76 P74/S27
P04/INTP4/TI01 6 75 P75/S26
P05/TI00/TO0 7 74 P76/S25
P06/TI50/TO50 8 73 P77/S24
P07/TI51/TO51 9 72 P120/S23
P20/SI0 10 71 P121/S22
P21/SO0 11 70 P122/S21
P22/SCK0 12 69 P123/S20
P23/SI1/SO1 13 68 P124/S19
P24/SCK1 14 67 P125/S18
P25/RxD 15 66 P126/S17
P26/TxD 16 65 P127/S16
RESET 17 64 P130/S15
X1 18 63 P131/S14
X2 19 62 P132/S13
VPP(/IC) 20 61 P133/S12
CL1/CCLK 21 60 P134/S11
CL2 22 59 P135/S10
VSS2 23 58 P136/S9
VDD2 24 57 P137/S8
AVDD 25 56 P140/S7
P10/ANI0 26 55 P141/S6
P11/ANI1 27 54 P142/S5
P12/ANI2 28 53 P143/S4
P13/ANI3 29 52 P144/S3
P14/ANI4 30 51 P145/S2
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P15/ANI5
P16/ANI6
P17/ANI7
AVSS
P30/TI20
P31/TI21
P32/TI22
P33/PCL/SGOA
P34/SGO/SGOF
VSS1
VDD1
VLC0
VLC1
VLC2
COM0
COM1
COM2
COM3
P147/S0
P146/S1

Cautions: 1. Connect IC (internally connected) pin directly to V SS.

2. AVSS pin should be connected to VSS.
3. AVDD pin should be connected to VDD.

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 µPD780948(A), µPD780949(A)

Pin Identifications

P00 to P07 : Port0 RxD : Receive Data

P10 to P17 : Port1 TxD : Transmit Data
P20 to P26 : Port2 SGO : Sound Generator Output
P30 to P34 : Port3 SGOA : Sound Generator Amplitude
P40 to P47 : Port4 SGOF : Sound Generator Frequency
P50 to P57 : Port5 PCL : Programmable Clock Output
P64, P65, P67 : Port6 AD0 to AD7 : Address / Data Bus
P70 to P77 : Port7 A8 to A15 : Address Bus
P120 to P127 : Port12 RD : Read Strobe
P130 to P137 : Port13 WR : Write Strobe
P140 to P147 : Port14 ASTB : Address Strobe
INTP0 to INTP4 : Interrupt from Peripherals S0 to S39 : Segment Output
TI00, TI01, TI50, TI51 : Timer Input COM0 to COM3 : Common Output
TI20 to TI22 : Timer Input X1, X2 : Crystal (Main System Clock)
TO0 , TO51, TO52 : Timer Output CL1, CL2 : RC (Subsystem Clock)
T2PO : Timer Output RESET : Reset
CRxD : CAN Receive Data ANI0 to ANI7 : Analog Input
CTxD : CAN Transmit Data AVSS : Analog Ground
CCLK : CAN Clock AVDD : Analog Reference Voltage
SI0 : Serial Input VDD : Power Supply
SO0 : Serial Output VPP : Programming Power supply
SIO1 : Serial Input / Output VSS : Ground
SCK0, SCK1 : Serial Clock IC : Internally Connected

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 µPD780948(A), µPD780949(A)

2. Block Diagram

Figure 2-1: Block Diagram

IC/VPP
VDD
VDD
TI00/TO0

VSS
VSS
16 bit Timer 0 Port 0 8
TI01

TI20
Port 1 8
TI21
16 bit Timer 2
TI22
T2PO Port 2 6

TI50/TO50 8 bit Timer 50

Port 3 5

TI51/TO51 8 bit Timer 51

Port 4 8

Watch Timer
Port 5 8

Watchdog Timer
Port 6 3
SI0 78K/0 RAM
Serial Interface CPU 1K EEPROM
SO0
Channel 0 Core Byte 256 Byte Port 7 8
SCK0
SIO1 Serial Interface
Port 12 8
SCK1 Channel 1

RxD
UART Port 13 8
TxD

ANI0-
Port 14 8
ANI7
A/D Converter
AVSS Interface
AVDD S0-S7
AD0- 60 K ROM
S8-S15
AD7
A8-
External S16-S23
A15 Access LCD
/RD CCLK DCAN RAM
Controller S24-S31
/WR Interface 992 Byte
CRxD driver
ASTB S32-S39
CTxD
INTP0- Interrupt
INTP4 Control COM0-COM3
System RESET
Control X1 VLC0-VLC2
8MHz / SV X2
SGO/SGOF
CL1 Sound Generator
RC Oscillator SGOA
CL2
Clock Output
PCL
Control

Standby
Control

Remark: The EEPROM capacity depends on the product.

µPD780948 - no EEPROM
µPD780949 - with EEPROM

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 µPD780948(A), µPD780949(A)

3. Pin Functions
3.1 Normal Operating Mode Pins / Pin Input/Output Types

Table 3-1: Pin Input/Output Types (1/2)

Input / Pin Alternate After

Function
Output Name Function Reset
P00 INTP0 Input
P01 INTP1 Input
P02 Port 0 INTP2 Input
P03 8 bit input / output port INTP3/T2P0 Input
Input /
Input / output mode can be specified bit-wise
Output P04 INTP4/TI01 Input
If used as an input port, a pull-up resistor can be
P05 connected by software bit-wise TI00/TO0 Input
P06 TI50/TO50 Input
P07 TI51/TO51 Input
Port 1
Input P10-P17 8 bit input port ANI0-ANI7 Input
Input mode can be specified bit-wise
P20 SI0 Input
P21 SO0 Input
P22 /SCK0 Input
Port 2
Input /
P23 7 bit input/output port SI/SO1 Input
Output
Input / output mode can be specified bit-wise
P24 /SCK1 Input
P25 RxD Input
P26 TxD Input
Port 4
8 bit input / output port
Input/
P40-P47 Input / output mode can be specified bit-wise AD0-AD7 Input
Output
If used as an input port, a pull-up resistor can be
connected by software
Port 5
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used in External Memory
Input/
P50-P57 Expansion Mode with the 4, 6 or 8 bit address by A8/S39-A15/S32 Input
Output
setting the
Memory Expansion Mode Register
Not for external memory expansion used ports can
be used either for LCD or port function
P64 /RD Input
Port 6
Input /
P65 3 bit input / output port /WR Input
Output
input / output mode can be specified bit-wise
P67 ASTB Input

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 µPD780948(A), µPD780949(A)

Table 3-1: Pin Input/Output Types (2/2)

Input / Alternate After

Pin Name Function
Output Function Reset
Port 7
8 bit input / output port
Input / output mode can be specified bit-wise
Input/
P70-P77 If used as an input port, a pull-up resistor can be S31-S24 Input
Output
connected by software
This port can be used as a segment signal output port
or an I/O port in 1 bit units by setting port function
Port 12
8 bit input / output port
Input/ Input / output mode can be specified bit-wise
P120-P127 S23-S16 Input
Output This port can be used as a segment signal output port
or an I/O port in 8 bit units by setting LCD control
register
Port 13
8 bit input / output port
Input / output mode can be specified bit-wise
Input/ If used as an input port, a pull-up resistor can be
P130-P137 S15-S8 Input
Output connected by software
This port can be used as a segment signal output port
or an I/O port in 8 bit units by setting LCD control
register
Port 14
8 bit input / output port
Input/ Input / output mode can be specified bit-wise
P140-P147 S7-S0 Input
Output This port can be used as a segment signal output port
or an I/O port in 8 bit units by setting LCD control
register

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 µPD780948(A), µPD780949(A)

3.2 Non-Port Pins

Table 3-2: Non-Port Pins (1/2)

After Alternate
Pin Name I/O Function
Reset Function Pin
INTP0 P00
INTP1 P01
External interrupts with specifiable valid edges (rising
INTP2 Input Input P02
edge, falling edge, both rising and falling edges)
INTP3 P03/T2P0
INTP4 P04/TI01
SI0 P20
Input Serial interface serial data input Input
SI1 P23/SO1
SO0 P21
Output Serial interface serial data output Input
SO1 P23/SI1
SCK0 Input/ P22
Serial interface serial clock input / output Input
SCK1 Output P24
RxD Input Asynchronous serial interface data input Input P25
TxD Output Asynchronous serial interface data output Input P26
CRxD Input CAN serial data input Input -
CTxD Output CAN serial data output Output -
CCLK Input CAN serial clock input - CL1
TI00 P05/TO0
External count clock input to 16-bit timer (TM0)
Ti01 P04/INTP4
TI20 Capture trigger input P30
TI21 Input Capture trigger input Input P31
TI22 Capture trigger input P32
TI50 External count clock input to 8-bit timer (TM50) P06/TO50
TI51 External count clock input to 8-bit timer (TM51) P07/TO51
TO0 16-bit timer output P05/TI00
T2P0 16-bit timer output P03/INTP3
Output Input
TO50 8-bit timer output (also used for PWM output) P06/TI50
TO51 8-bit timer output (also used for PWM output) P07/TI51
PCL Output Clock output (for main system clock trimming) Input P33/SGOA
Input/ Low-order address/data bus at external memory
AD0 to AD7 Input P40 to P47
Output expansion
High-order address/data bus at external memory P50 to P57
A8 to A15 Output Input
expansion S39 to S32
Strobe signal output for read operation from external
RD P64
memory
Output Input
Strobe signal output for read operation from external
WR P65
memory
Strobe output externally latching address information
ASTB - Input P67
output to ports 4, 5 to access external memory
S0 to S7 P147 to P140
S8 to S15 P137 to P130
S16 to S23 Output Segment signal output of LCD controller / driver Input P127 to P120
S24 to S31 P77 to P70
P57 to P50
S32 to S39
A15 to A8

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 µPD780948(A), µPD780949(A)

Table 3-2: Non-Port Pins (2/2)

After Alternate
Pin Name I/O Function
Reset Function Pin
COM0-COM3 Output Common signal output of LCD controller/driver Output -
VLC0 to V LC2 - LCD drive voltage - -
SGO Output Sound generator output Input P34/SGOF
SGOA Output Sound generator amplitude output Input P33/PCL
SGOF Output Sound generator frequency output Input P34/SGO
ANI0 to ANI7 Input A/D Converter analog input Input P10 – P17
A/D Converter reference voltage input and power
AVDD - - -
supply
AVSS - A/D Converter ground potential. Connect to VSS. - -
RESET Input System reset input - -
X1 - Crystal connection for main system clock - -
X2 - - -
CL1 Input RC connection for subsystem clock - CCLK
CL2 - - -
VDD1, VDD2 - Positive power supply - -
VSS1, VSS2 - Ground potential - -
High voltage supply for flash programming (only
VPP - - IC
flash version)
Internal connection. Connect directly to VSS (only
IC - - VPP
MaskROM version)

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 µPD780948(A), µPD780949(A)

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in the
following table.
For the input/output circuit configuration of each type, see table.

Table 3-3: Types of Pin Input/Output Circuits (1/3)

Input/Output
Pin Name I/O Recommended Connection for Unused Pins
Circuit Type
P00/INTP0
P01/INTP1
P02/INTP2
P03/INPT3/T2P0
8-A I/O Connect to Vdd or Vss via a resistor individually
P04/INTP4/TI01
P05/TI00/TO0
P06/TI50/TO50
P07/TI51/TO51
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
11-B I Connect to Vdd or Vss via a resistor individually
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
P20/SI0
P21/SO0
P22/SCK0 10
P23/SI1/SOA I/O Connect to Vdd or Vss via a resistor individually
P24/SCK1
P25/RxD 8
P26/TxD 5
P30/TI20
P31/TI21 8
P32/TI22 I/O Connect to Vdd or Vss via a resistor individually
P33/PCL/SGOA
5
P34/SGO/SGOF
P40/AD0
P41/AD1
P42/AD2
P43/AD3
5-A I/O Connect to Vdd or Vss via a resistor individually
P44/AD4
P45/AD5
P46/AD6
P47/AD7

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 µPD780948(A), µPD780949(A)

Table 3-3: Types of Pin Input/Output Circuits (2/3)

Input/Output
Pin Name I/O Recommended Connection for Unused Pins
Circuit Type
P50/A8/S39
P51/A9/S38
P52/A10/S37
P53/A11/S36
17 I/O Connect to Vdd or Vss via a resistor individually
P54/A12/S35
P55/A13/S34
P56/A14/S33
P57/A15/S32
P64/RD
P65/WR 5-A I/O Connect to Vdd or Vss via a resistor individually
P67/ASTB
P70/S31
P71/S30
P72/S29
P73/S28
17-B I/O Connect to Vdd or Vss via a resistor individually
P74/S27
P75/S26
P76/S25
P77/S24
P120/S23
P121/S22
P122/S21
P123/S20
17-C I/O Connect to Vdd or Vss via a resistor individually
P124/S19
P125/S18
P126/S17
P127/S16
P130/S15
P131/S14
P132/S13
P133/S12
17-A I/O Connect to Vdd or Vss via a resistor individually
P134/S11
P135/S10
P136/S9
P137/S8
P140/S7
P141/S6
P142/S5
P143/S4
17-A I/O Connect to Vdd or Vss via a resistor individually
P144/S3
P145/S2
P146/S1
P147/S0

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 µPD780948(A), µPD780949(A)

Table 3-3: Types of Pin Input/Output Circuits (3/3)

Input/Output
Pin Name I/O Recommended Connection for Unused Pins
Circuit Type
COM0 – COM3 18 O
Leave open
VLC0 – VLC2 - -
CRxD 1 I Connect to Vdd or Vss via a resistor individually
CTxD 2 O Leave open
CL1/CCLK - - Connect to Vdd or Vss via a resistor individually
C2 - - Leave open
RESET 1 I -
AVREF - - Connect to VDD
AVSS - - Connect to VSS
IC
- - Connect directly to VSS
VPP

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 µPD780948(A), µPD780949(A)

Figure 3-1: Pin Input/Output Circuits (1/3)

Type 1 Type 2

VDD

P-ch
IN
Data OUT

N-ch

Type 5 Type 5-A V DD

V DD Pullup
P-ch
enable
Data P-ch V DD

IN/OUT Data
P-ch
Output N-ch
disable IN/OUT
Output N-ch
disable
Input
disable
Input
enable

Type 8 Type 8-A

V DD

V DD Pullup
P-ch
enable
Data
P-ch
V DD
IN/OUT
Output Data
N-ch P-ch
disable
IN/OUT
Output N-ch
disable

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 µPD780948(A), µPD780949(A)

Figure 3-1: Pin Input/Output Circuits (2/3)

Type 10 Type 11-B

VDD
P-ch
Data P-ch Comparator
IN/OUT + IN
-
Open drain
output disable N-ch N-ch
V REF (Threshold Voltage)

Input
enable

Type 17 Type 17-A VDD

Pullup
VDD P-ch
enable

Data VDD
P-ch
IN/OUT Data
P-ch
Output N-ch
disable IN/OUT
Output N-ch
disable
Input
enable
Input
VLC0 enable

P-ch
VLC0
VLC1
P-ch
N-ch
P-ch VLC1
N-ch
SEG P-ch
Data
SEG
N-ch Data
P-ch
VLC2
P-ch N-ch
N-ch
VLC2
N-ch

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 µPD780948(A), µPD780949(A)

Figure 3-1: Pin Input/Output Circuits (3/3)

Type 17-B V DD Type 17-C

Pullup
P-ch V DD
enable

V DD Data P-ch

Data IN/OUT
P-ch
Output N-ch
IN/OUT disable
Output N-ch
disable

V LC0
P-ch
V LC0
V LC1
P-ch
N-ch
V LC1 P-ch
N-ch
P-ch SEG
Data
SEG
Data N-ch
P-ch
V LC2
P-ch N-ch
N-ch
V LC2
N-ch

Type 18

P-ch

VLC0

VLC1

OUT

COM

VLC2

N-ch

17
 µPD780948(A), µPD780949(A)

4. Memory Space
The memory map of the µPD780949 is shown in Figure 4-1.

Figure 4-1: Memory Map

FFFFH Special Function Registers

FF20H (SFRs) 256 x 8 bits
FF1FH
FF00H
FEFFH
General Registers
FEE0H 32 x 8 bits
FEDFH Internal High-speed RAM
FE20H 1024 x 8 bits
FB00H
FAFFH
Not usable
FA80H
FA7FH
LCD Display RAM
FA58H 40 x 4 bits
FA57H
Not usable
FA00H
F9FFH nnnnH
EEPROM
256 x 8 bits Program Area
F900H
F8FFH 1000H
Not usable 0FFFH
F800H
F7DFH CALLF Entry Area
Internal Expansion RAM
992 x 8 bits 0800H
F400H 07FFH
Not usable Program Area

F3FFH 0080H
External Memory 007FH
F000H
CALLT Table Area
EFFFH
0040H
Internal ROM 003FH
61440 x 8 bits
Vector Table Area

0000H 0000H

Remark: The EEPROM is only available in the µPD780949 und not in the µPD780948.

18
 µPD780948(A), µPD780949(A)

5. Peripheral Hardware Function

5.1 Ports
Input/output ports are classified into three types.
• CMOS input/output (Port 0, Port 2 to 5, P64, P65, P67, Port 7,
Port 8, Port 12, Port 13, Port 14) : 71
• Input (P10 to P17) : 8
Total : 79

Table 5-1: Functions of Ports

Port Name Pin Name Function

Port 0 P00 to P07 Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used bit-wise by software.

Port 1 P10 to P17 Input port.

Port 2 P20 to P26 Input/output port. Input/output can be specified bit-wise.

When used as an output port, on-chip output buffer can be used by software.

Port 3 P30 to P34 Input/output port. Input/output can be specified bit-wise.

Port 4 P40 to P47 Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used bit-wise by software.
Port 5 P50 to P57 Input/output port. Input/output can be specified bit-wise.
When used as an output port, port function can be specified by software.

Port 6 P64, P65, P67 Input/output port. Input/output can be specified bit-wise.

Port 7 P70 to P77 Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used bit-wise by software.
When used as an output port, port function can be specified by software.
Port 12 P120 to P127 Input/output port. Input/output can be specified bit-wise.
When used as an output port, port function can be specified by software.

Port 13 P130 to P137 Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used bit-wise by software.
When used as an output port, port function can be specified by software.

Port 14 P140 to P147 Input/output port. Input/output can be specified bit-wise.

19
 µPD780948(A), µPD780949(A)

5.2 Clock Generator

There are two kinds of clock generators: main system and subsystem clock generators.
It is possible to change the instruction execution time.
• 0.25 µs/0.5 µs/1 µs/2 µs/4 µs (at main system clock frequency of 8.0 MHz)
• 122 µs (at subsystem clock frequency of 32.768 kHz)

Figure 5-1: Clock Generator Block Diagram

CL1
Subsystem f XT
Watch Timer
Clock
CL2 Oscillator
Prescaler

X1
Main System f X
Clock to peripheral
Clock Prescaler 1 hardware
Oscillator 2
X2
fX fX fX fX fX f XT
2 22 23 24 2

STOP

Selector
Standby
Control CPU Clock (fCPU)
Circuit

5.3 Main system clock oscillator

The main system clock oscillator oscillates with a crystal or a ceramic resonator connected to the X1 and
X2 pins.

Figure 5-2: Oscillator Circuit

(a) Crystal and ceramic oscillation (b) External clock

IC
X2 X2

External
X1 X1
Clock
Crystal
resonator
or ceramic
resonator

20
 µPD780948(A), µPD780949(A)

5.4 Subsystem Clock Oscillator

Subsystem clock oscillator is for RC oscillation with very low frequency.

Figure 5-3: Oscillator Circuit

CL2
R

CL1
C

5.5 Timer/Event Counter

There are the following seven timer/event counter channels:
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 4 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel

Table 5-2: T ypes and Functions of Timer/Event Counters

16-bit Timer/Event 8-bit Timer/Event Watch Watchdog 16-bit

Counter Counter Timer Timer Timer
Type Interval timer 2 channels 2 channels 1 channel 1 channel 1 channel

External event counter 1 channel 2 channels

Timer output 1 output 2 outputs

PWM output 1 output 2 outputs

Pulse with measurement 2 inputs 3 inputs

Function Square wave output 1 output 2 outputs

One-shot pulse output 1 output

Interrupt request 2 2 2 1 4
Test input 1 3

21
 µPD780948(A), µPD780949(A)

Figure 5-4: 16 bit Timer TM0

Internal Bus

INTP4

Noise
TI01/P04/ Rejection

Selector
Selector
INTP4 16-bit Capture/
Circuit Compare Control INTTM00
Register (CR00)

fx / 2
Match

fx / 16
Selector

fx / 128 16-bit Timer Clear Output TO0/P05/

Register (TM0) Circuit Control TI00

Match

fx / 2 Noise
Rejection
Circuit

Selector
Noise 16-bit Capture/
TI00/P05/
Rejection Compare Control INTTM01
TO0
Circuit Register (CR01)

Internal Bus

22
 Figure 5-5: 16 Bit Timer TM2

fx / 4

fx / 8

Selector
fx / 32 16-Bit Timer Register (TM2) Overflow INT

fx / 128

TI22 Schmitt Trigger Digital Prescaler Edge Detection

Input Buffer Filter 1, 1/2, 1/4, 1/8 Circuit 1) 16-Bit Capture Register (CR22)

INTTM22

Schmitt Trigger Digital Edge Detection

TI21 Input Buffer Filter Circuit 1) 16-Bit Capture Register (CR21)

µPD780948(A), µPD780949(A)
INTTM21

Schmitt Trigger Digital Edge Detection

TI20 Input Buffer Filter Circuit 1) 16-Bit Capture Register (CR20)

INTTM20

DCAN
T2PO Terminal to
related output port
TPOE Internal Bus

1) Valid edge (rising edge, falling edge or both edges) is selectable via software
23
24

µPD780948(A), µPD780949(A)
Figure 5-6: Digital Capture Input Filter

3 bit
TI22 D Q D Q D Q S Q Counter

C C C R 1/1 1/2 1/4 1/8

Selector

CLK
To
Edge Internal
Detection

To
Edge Internal
TI20, D Q D Q D Q S Q
TI21 Detection

C C C R

CLK
 µPD780948(A), µPD780949(A)

Figure 5-7: 8-Bit Timer/Event Counter 51 Block Diagram

Internal Bus

8-bit Compare Register

(CR51)

fx
Match
fx / 21 INTTM 51
fx / 23
Selector

fx / 25 Output Control
8-bit Timer Register n OVF TO51 / P07 / TI51
Circuit
fx / 27 (TM51)
fx / 212
Clear
TI51 / P07 / TO51

Internal Bus

Figure 5-8: 8-Bit Timer/Event Counter 50 Block Diagram

Internal Bus

8-bit Compare Register

(CR50)

fx
Match
fx / 21 INTTM 50
fx / 23
Selector

fx / 25 Output Control
8-bit Timer Register n OVF TO50 / P06 / TI50
Circuit
fx / 27 (TM50)
fx / 29
Clear
TI50 / P06 / TO50

Internal Bus

25
 µPD780948(A), µPD780949(A)

Figure 5-9: Watch Timer Block Diagram

25
fw

Selector
fx/2 8 2 14 5-bit Counter INTWT
Selector fw
Prescaler
fw

fxT
fw fw fw fw fw fw
24 25 26 27 28 29

Selector
INTWTI

Figure 5-10: Watchdog Timer Block Diagram

fx/2 12 Prescaler

fx/213 fx/214 fx/215 fx/216 fx/217 fx/218 fx/220

INTWDT
Maskable
interrupt request
Selector

Control
Circuit

RESET

INTWDT
Non-maskable
interrupt request

26
 µPD780948(A), µPD780949(A)

5.6 Clock Output Control Circuit

This circuit can output clocks of the following frequencies:
• 62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz/2 MHz/4 MHz/8 MHz (at main system clock frequency of
8.0 MHz)

Figure 5-11: Clock Output Control Circuit Block Diagram

fX
fX/2
fX/22
Selector

fX/23 Synchronization Output Control

PCL / P33 / SGOA
fX/24 Circuit Circuit
fX/25
fX/26
fX/27

27
28

µPD780948(A), µPD780949(A)
5.7 Sound Generator
The sound generator will produce sounds composed of a rectangular frequency signal and a PWM signal
for volume control.

Figure 5-12: Block Diagram of the Sound Generator

Selector 2
CLK (FSYS) 1/2 Selector 1
fSG1
fSG2

Clear

Selector 3
Comparator 1/2
SGO/SGOF/P34

SGBR=1
To counter
PWM @ Amplitude
S
Comparator SGOA/PCL/P33
R

SGCR TCE SGOB SGCL2 SGCL1 SGCL0 SGBR SGBR3 SGBR2 SGBR1 SGBR0 SGAM SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0

Internal Bus Internal Bus Internal Bus

 µPD780948(A), µPD780949(A)

The sound generator output is selectable as separate frequency-/volume-output SGOF/SGOA or as

composed signal SGO.
The output signal at the composed output has the following principle shape:

Figure 5-13: Composed Sound Generator Output SGO

SGOF Output

SGOA Output
(Amplitude)

SGO Output

29
 µPD780948(A), µPD780949(A)

5.8 A/D Converter

The A/D converter consists of eight 8-bit resolution channels.
A/D conversion can be started by software.

Figure 5-14: A/D Converter Block Diagram

Series Resistor String

ANI0/P10
AV DD
ANI1/P11 Sample & Hold Circuit

Tap Selector
ANI2/P12
Voltage Comparator
Selector

ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
AV SS
ANI7/P17 Successive Approximation
Register (SAR)

Control
INTAD
Circuit

A/D Conversion Result

Register (ADCR1)

Internal Bus

30
 µPD780948(A), µPD780949(A)

5.9 Power Fail Detector

The block diagram of the power fail detector is shown in figure 5-15.

Figure 5-15: Block Diagram Power Fail Detector

ANI7/P17

Result Register (ADCR1)

ANI6/P16

A/D Conversion
ANI5/P15
Selector

ANI4/P14 Compare
A/D Comparator
ANI3/P13 Register (PFT)

ANI2/P12
ANI1/P11
ANI0/P10

Selector Internal Bus

INTAD
(A/D Conversion termination interrupt)
(Power fail / Power on detection interrupt)

31
 µPD780948(A), µPD780949(A)

5.10 Serial Interfaces

There are the following three on-chip serial interface channels synchronous with the clock:
• Serial interface channel 0
• Serial interface channel 1
• Serial interface channel 2

Table 5-3: Types and Functions of Serial Interfaces

Serial Interface Serial Interface Serial Interface

Function
Channel 0 Channel 1 Channel 2
3-wire serial I/O mode (MSB first)
2-wire serial I/O mode (MSB first)
(On-chip
Asynchronous serial
dedicated baud
interface (UART) mode
rate generator)

Figure 5-16: Serial Interface Channel 0 Block Diagram

Internal Bus

Serial I/O Shift

SI0/P20
Register 1 (SIO13O)

SO0/P21

SCK0/P22 Serial Clock Counter INTCSI0

fX/23
Selector

Serial Clock fX/27

Control Circuit TO50

32
 µPD780948(A), µPD780949(A)

Figure 5-17: Serial Interface Channel 1 Block Diagram

Internal Bus

Serial I/O Shift

SI1/SO1/P23
Register 1 (SIO3O)

SCK1/P24 Serial Clock Counter INTCSI1

fX/26

Selector
Serial Clock fX/27
Control Circuit TO50

Figure 5-18: Serial Interface UART Block Diagram

Internal Bus

Receive Buffer Direction Control

Register (RXB0) Circuit

Direction Control Transmit Shift

Circuit Register (TXS0)

RXD/P25 Receive Shift Transmit Control

Register (RXS0) Circuit INTST

TXD/P26

Receive Control INTSER

Circuit INTSR
Selector

Baud Rate fSCK

fX/21 - fX/28
Generator

33
 µPD780948(A), µPD780949(A)

5.11 CAN-Bus Interface

The CAN-Bus Interface has the following functions:
• CAN 2.0 B protocol with active extended frame.
• The maximum Baud rate is 500 kB (@ 8 MHz clock).
• Receice messages will be stored in RAM area depending on message identifier, at which unused
bytes can be used by CPU.
• Unique identifier for all 16 messages usable.
• Up to 2 transmit channels with masks.

Figure 5-19: CAN-Bus Interface

DMA Control
Extended
CPU RAM

CTxD
DCAN-Interface
CRxD

High Speed
RAM

5.12 LCD Controller/Driver

Table 5-4: Display Mode Types and Maximum Number of Display Pixels

Bias Method Time Multiplexing Common Signal used Maximum Number of Display Pixels
1/3 4 COM0 to COM3 160 (40 segments x 4 commons)

34
 µPD780948(A), µPD780949(A)

Figure 5-20: LCD Controller/Driver Block Diagram

Internal Bus

fx
Prescaler
214
fx fx fx
217 216 215
Display
Data Memory
fLCD
Timing Controller Selector

Segment
Data Selector

LCD Drive Voltage

Generator

Segment Driver Common Driver

S0/P147..........S39/P50 COM0 COM1 COM2 COM3 VLC2 VLC1 VLC0

35
 µPD780948(A), µPD780949(A)

6. Interrupt Functions and Test Functions

6.1 Interrupt Functions
A total of 29 interrupt functions are provided, divided into the following three types.
• Non-maskable interrupt : 1
• Maskable interrupt : 27
• Software interrupt : 1
Table 6-1: Interrupt Vector Table
Interrupt Source Note 2
Note 1
Maska- Internal/ External Basic
bility Interrupt Vector Address
Name Trigger Structure
Priority
Type

Non- Overflow of watchdog timer (When the

_ INTWDT (A)
maskable watchdog timer NMI is selected)
0004H
Overflow of watchdog timer (When the
0 INTWDT
interval timer mode is selected)
1 INTAD End of A/D converter conversion 0006H
2 INTOVF Overflow of 16-bit timer 2 Internal 0008H
Generation of 16-bit timer 2 capture register (B)
3 INTTM20 000AH
(CR20) match signal
Generation of 16-bit timer 2 capture register
4 INTTM21 000CH
(CR21) match signal
Generation of 16-bit timer 2 capture register
5 INTTM22 000EH
(CR22) match signal
6 INTP0 0010H
7 INTP1 0012H
8 INTP2 Pin input edge detection External 0014H (C)
9 INTP3 0016H
10 INTP4 0018H
11 INTCE CAN Error 001AH
12 INTCR CAN Receive 001CH
13 INTCT0 CAN Transmitbuffer 0 001EH
Maskable 14 INTCT1 CAN Transmitbuffer 1 0020H
15 INTCSI0 End of serial interface channel 0 transfer 0022H
16 INTCSI1 End of serial interface channel 1 transfer 0024H
Serial interface channel 1 UART reception
17 INTSER 0026H
error generation
End of serial interface channel 1 UART
18 INTSR 0028H
reception
End of serial interface channel 1 UART
19 INTST Internal 002AH (B)
transfer
Generation of 16-bit timer 0 capture/compare
20 INTTM00 002CH
register (CR00) match signal
Generation of 16-bit timer 0 capture/compare
21 INTTM01 002EH
register (CR01) match signal
Generation of 8-bit timer/event counter 50
22 INTTM50 0030H
match signal
Generation of 8-bit timer/event counter 51
23 INTTM51 0032H
match signal
24 INTWE EEPROM write completion interrupt 0034H
Reference time interval signal from watch
25 INTWTI
timer
0036H
Reference time interval signal from watch
26 INTWT
timer
_
Software BRK BRK instruction execution Internal 003EH (D)
36
 µPD780948(A), µPD780949(A)

Notes: 1. Default priority is the priority order when several maskable interruptions are generated at
the same time. 0 is the highest order and 20 is the lowest order.
2. Basic structure types (A) to (D) correspond to (A) to (D) in Figure 6-1.

6.2 Interrupts

Figure 6-1: Interrupt Function Basic Configuration (1/2)

(A) Internal non-maskable interrupt

Internal Bus

Priority Vector Table

Interrupt Control Address
request Circuit Generator

Standby release
signal

(B) Internal maskable interrupt

Internal Bus

MK IE PR ISP

Priority Vector Table

Interrupt Control Address
request IF Circuit Generator

Standby release
signal

(C) External maskable interrupt

Internal bus

External Interrupt
Mode Register MK IE PR ISP
(EGP, EGN)

Priority Vector Table

Interrupt Edge Control Address
request Detector IF Circuit Generator

Standby
release
signal

37
 µPD780948(A), µPD780949(A)

Figure 6-1: Interrupt Function Basic Configuration (1/2)

(D) Software interrupt

Internal Bus

Interrupt Vector Table

Priority Control Address
request Circuit Generator

38
 µPD780948(A), µPD780949(A)

7. External Device Expansion Functions

The external device expansion functions connect external devices to areas other than the internal ROM,
RAM and SFR. External devices connection uses ports 4 to 6.
The external device expansion function has the following mode:
• Multiplexed bus mode: External devices are connected by using a time-division multiplexed
address /data bus. This mode is useful for reducing the number of ports
used when external devices are connected.

8. EEPROM Function
The µPD780948 incorporates not only a 2016 byte x 8-bit RAM but also 256 byte x 8-bit EEPROM
(Electrically Erasable PROM) as data memory.
EEPROM, unlike static RAM, can retain its contents when the power is turned off. Unlike EPROM, it‘s
contents can electrically be erased without using ultraviolet rays. EEPROM is manipulated by 8-bit memory
manipulation instructions.

Note: The EEPROM is only avaiable in the µPD780949.

9. Standby Function
The standby function intends to reduce current consumption. It has the following two modes:
• HALT mode: In this mode, the CPU operation clock is stopped. The average current consump-
tion can be reduced by intermittent operation by combining this mode with the
normal operation mode.
• STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations
performed on the main system clock are suspended, and only the subsystem
clock is used for extremely small power consumption.

Figure 9-1: Standby Function

CSS = 1
Main System Clock Operation Subsystem Clock OperationNote
CSS = 0
STOP HALT instruction HALT instruction
instruction
Interrupt
request Interrupt Interrupt
request request
Note
HALT Mode HALT Mode
STOP Mode
(Supply of clock to CPU is (Supply of clock to CPU is
(Oscillation of the main system
stopped although clock stopped although clock
clock is stopped.)
is generated.) is generated.)

Note: Current consumption is reduced by shutting off the main system clock.
If the CPU is operating on subsystemclock, shut off the main system clock by setting MCC.

Caution: When switching on the main system clock again after the subsystem clock has been used
with the main system clock stopped, be sure to provide enough time for the generation
to be stable with the program first.

10. Reset Function

There are the following two reset methods.
• External reset input by RESET pin
• Internal reset by watchdog timer runaway time detection

39
 µPD780948(A), µPD780949(A)

11. Instruction Set

(1) 8-Bit Instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL,
RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ.

Table 11-1: 8-Bit Instructions

2nd Operand
[HL+byte]
#byte A r Note sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 1 None
[HL + C]
1st Operand

ADD MOV MOV MOV MOV MOV MOV MOV MOV MOVU ROR
ADDC XCH XCH XCH XCH XCH XCH XCH ROL
SUB ADD ADD ADD ADD ADD RORC
SUBC ADDC ADDC ADDC ADDC ADDC ROLC
AND SUB SUB SUB SUB SUB
A OR SUBC SUBC SUBC SUBC SUBC
XOR AND AND AND AND AND
CMP OR OR OR OR OR
XOR XOR XOR XOR XOR
CMP CMP CMP CMP CMP

MOV MOV INC

ADD DEC
ADDC
SUB
r SUBC
AND
OR
XOR
CMP

r1 DBNZ

sfr MOV MOV

MOV DBNZ INC

ADD DEC
ADDC
SUB
saddrMOV SUBC
AND
OR
XOR
CMP

!addr16 MOV

MOV MOV PUSH

PSW POP

[DE] MOV

MOV ROR4
[HL] ROL4

[HL+byte] MOV
[HL + B]
[HL + C]

X MULU

C DIVUW

Note: Except r = A

40
 µPD780948(A), µPD780949(A)

(2) 16-Bit Instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW.

Table 11-2: 16-Bit Instructions

2nd Operand
#word AX rp sfrp saddrp !addr16 SP None
1st Operand

ADDW MOVW MOVW MOVW MOVW MOVW

AX SUBW XCHW
CMPW

MOVW MOVW INCW, DECW

rp
PUSH, POP

sfrp MOVW MOVW

saddrp MOVW MOVW

Note
!addr16 MOVW

SP MOVW MOVW

Note: Only when rp = BC, DE, HL

(3) Bit Manipulation Instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR.

Table 11-3: Bit Manipulation Instructions

2nd Operand
A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
1st Operand

MOV1 BT SET1
A.bit BF CLR1
BTCLR

MOV1 BT SET1
sfr.bit BF CLR1
BTCLR

MOV1 BT SET1
saddr.bit BF CLR1
BTCLR

MOV1 BT SET1
PSW.bit BF CLR1
BTCLR

MOV1 BT SET1
[HL].bit BF CLR1
BTCLR

MOV1 MOV1 MOV1 MOV1 MOV1 SET1

AND1 AND1 AND1 AND1 AND1 CLR1
CY OR1 OR1 OR1 OR1 OR1 NOT1
XOR1 XOR1 XOR1 XOR1 XOR1

41
 µPD780948(A), µPD780949(A)

(4) Call instructions/Branch instructions

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ.

Table 11-4: Call Instructions/Branch Instructions

2nd Operand
AX !addr16 !addr11 [addr5] $addr16
1st Operand

Basic instruction BR CALL CALLF CALLT BR, BC

BR BNC
BZ, BNZ

Compound instruction BT, BF

BTCLR
DBNZ

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP.

42
 µPD780948(A), µPD780949(A)

12. Electrical Specifications

Absolute Maximum Ratings (TA = 25° C)

Table 12-1: Absolute Maximum Ratings

Parameter Symbol Conditions Rating Unit

VDD -0.3 to +5.5
VPP -0.3 to +11.0
Supply voltage
AVDD -0.3 to VDD +0.3
AVSS -0.3 to +0.3
P00 to P07, P10 to P17, P20 to P26, P30 to V
P34, P40 to P47, P50 to P57, P64, P65, P67,
Input voltage V1 -0.3 to VDD +0.3
P70 to P77, P120 to P127, P130 to P137,
P140 to P147, X1, X2, CL1, RESET
Output voltage V0 -0.3 to VDD +0.3
Analog input
VAN P10 to P17 Analog input pin AVSS -0.3 to AVDD +0.3
voltage
1 pin (except P34) -10
P34 -30
High level output
IOH P00 to P07, P20 to P26, P30 to P33, P40 to
current -30
P47, P50 to P57, P64, P65, P67, P70 to P77,
P120 to P127, P130 to P137, P140 to P147,
CTxD total
Peak value 20
1 pin (except P34) Effective
10
value
Peak value 30 mA
P34 Effective
20
value
High level output Note
P00 to P07, P20 to P26, P30 to P33,
IOL Peak value 50
Current P40 to P47, P64, P65, P67, CTxD total
Effective
P40 to P47, P64, P65, P67, CTxD total 20
value
P50 to P57, P70 to P77, P120 to P127,
Peak value 50
P130 to P137, P140 to P147 total
Effective
P130 to P137, P140 to P147 total 20
value
Operating
ambient TA -40 to +85
o
temperature C
Storage
TSTG -65 to +150
temperature

Note: Effective value should be calculated as follows: [Effective value] = [Peak value] x Öduty

Caution: Product quality may suffer if the absolute maximum ratings are exceeded for even a single
parameter or even momentarily. That is, the absolute maximum ratings are rated values
at which the product is on the verge of suffering physical damage, and therefore the
product must be used under conditions which ensure that the absolute maximum ratings
are not exceeded.

Remark: The characteristics of the dual-function pins are the same as those of the port pins unless
otherwise specified.

43
 µPD780948(A), µPD780949(A)

Capacitance (TA = 25° C, VDD = VSS = 0 V)

Table 12-2: Capacitance

Parameter Symbol Function Min. Typ Max. Unit

Input F = 1 MHz
CIN 15 pF
capacitance Other than measured pins: 0 V
P00 to P07, P10 to P17, P20 to
P26, P30 to P33, P40 to P47, P50
F = 1 MHz to P57, P64, P65, P67, P70 to P77, 15 PF
Input/output
CIO Other than P100 to P103, P120 to P127,
capacitance
measured pins: 0 V P130 to P137, P140 to P147
P34 20 pF

Remark: The characteristics of the dual-function pins are the same as those of the port pins unless
otherwise specified.

44
 µPD780948(A), µPD780949(A)

Main System Clock Oscillation Circuit Characteristics (T A = -40 to +85° C, VDD = 1.8 to 5.5 V)

Table 12-3: Main System Clock Oscillation Circuit Characteristics

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Oscillator
IC X2 X1 VDD = 4.0 to 5.5 V 4.0 8.0 8.5 MHz
frequency (fx) Note 1
Ceramic
resonator
C2 C1 After VDD reaches
Oscillation
oscillator voltage 10 ms
stabilization time Note2
range MIN. 4.0 V

Oscillator
IC X2 X1 VDD = 4.0 to 5.5 V 4.0 8.0 8.5 MHz
frequency (fx) Note 1
Crystal
resonator C2 C1 After VDD reaches
Oscillation
oscillator voltage 10 ms
stabilization time Note2
range MIN. 4.0 V

X1 input
X2 X1 VDD = 4.0 to 5.5 V 4.0 8.0 8.5 MHz
frequency (fx) Note 1
External
clock
X1 input
µ PD74HCU04
high/low-level width VDD = 4.0 to 5.5 V 55 125 ns
(tXH, tXL)

Notes: 1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction
execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions: 1. When using the main system clock oscillation circuit, wiring in the area enclosed with
the broken line should be carried out as follows to avoid an adverse effect from wiring
capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillation circuit capacitor ground should always be the same
as that of VSS.
• Do not ground wiring to a ground pattern in which a high current flows.
• Do not fetch a signal from the oscillation circuit.

2. When the main system clock is stopped and the system is operated by the subsystem
clock, the subsystem clock should be switched again to the main system clock after
the oscillation stabilization time is secured by the program.

45
 µPD780948(A), µPD780949(A)

Subystem Clock Oscillation Circuit Characteristics (TA = -40 to +85° C, VDD = 1.8 to 5.5 V)

Table 12-4: Subsystem Clock Oscillation Circuit Characteristics

Recommended
Parameter Test Conditions MIN. TYP. MAX. Unit
Resonator circuit
CL1 CL2
4.0 V ≤ VDD ≤ 5.5 V
Oscillator
RC osc. R R = 518 kΩ 32 40 tbd kHz
frequency (fxt)
C C = 33 pF

CL1 Input Note

4.0 V ≤ VDD ≤ 5.5 V tbd 8.0 8.5 MHz
CL1 CL2 frequency (fxt)
External CL1 Input
clock high/low level
4.0 V ≤ VDD ≤ 5.5 V 55 tbd ns
width
tXTH, tXTL)

Note: Only oscillator circuit characteristics are shown. Regarding instruction execute time, please
refer to AC characteristics.

Cautions: 1. When using the subsystem clock oscillation circuit, wiring in the area enclosed with
the broken line should be carried out as follows to avoid an adverse effect from wiring
capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillation circuit capacitor ground should always be the same
as that of VSS.
• Do not ground wiring to a ground pattern in which a high current flows.
• Do not fetch a signal from the oscillation circuit.

2. The subsystem clock oscillation circuit is designed to be a circuit with a low amplifi-
cation level, for low power consumption more prone to misoperation due to noise than
that of the main system clock. Therefore, when using the subsystem clock, take special
cautions for wiring methods.

46
 µPD780948(A), µPD780949(A)

DC Characteristics (TA = -40 to +85° C, VDD = 4.0 to 5.5 V)

Table 12-5: DC Characteristics

Parameter Symbol Conditions MIN. TYP MAX Unit
P00 to P07, P10 to P17, P20 to
P26, P30 to P34, P40 to P47,
High-level
VIH1 P50 to P57, P64, P65, P67, P70 0.7 VDD
input VDD
to P77, P120 to P127, P130 to
voltage
P137, P140 to P147
VIH4 X1, X2, CL1, CL2 VDD - 0.5
P00 to P07, P10 to P17, P20 to
P26, P30 to P34, P40 to P47,
Low-level 0.3
VIL1 P50 to P57, P64, P65, P67, P70 0
input VDD
to P77, P120 to P127, P130 to
voltage
P137, P140 to P147
VIL4 X1, X2, CL1, CL2 0 0.4
P00 to P07, P10 to P17, P20 to
P26, P30 to P34, P40 to P47,
VDD = 4.0 to 5.5 V
VOH1 P50 to P57, P64, P65, P67, P70 VDD - 1.0
IOH = -1 mA V
High-level to P77, P120 to P127, P130 to
output P137, P140 to P147
voltage VDD = 4.0 to 5.5 V
IOH = -20 mA
VOH3 SGO tbd
VDD = 4.0 to 5.5 V
ION = -20 mA
P00 to P07, P10 to P17, P20 to
Low-level P26, P30 to P34, P40 to P47,
VDD = 4.0 to 5.5 V
output VOL1 P50 to P57, P64, P65, P67, P70 0.07 0.5
IOL = 1.6 mA
voltage to P77, P120 to P127, P130 to
P137, P140 to P147
VDD = 4.0 to 5.5 V
0.5
IOL = 20 mA
VOL3 SGO
VDD = 4.0 to 5.5 V
tbd
ION = 20 mA
P00 to P07, P10 to P17, P20 to
High-level P26, P30 to P34, P40 to P47,
input ILIH1 P50 to P57, P64, P65, P67, P70 VIN = VDD 3
leakage to P77, P120 to P127, P130 to
current P137, P140 to P147
ILIH2 X1, X2, CL1, CL2 20
P00 to P07, P10 to P17, P20 to
Low-level P26, P30 to P34, P40 to P47,
input ILIL1 P50 to P57, P64, P65, P67, P70 VIN = 0 V -3
leakage to P77, P120 to P127, P130 to µA
current P137, P140 to P147
ILIL2 X1, X2, CL1, CL2 -20
High-level
output
ILOH VOUT = VDD 3
leakage
current
Low-level
output
ILOL VOUT = 0 V -3
leakage
current
Software
pull-up R2 VIN = 0 V 4.5 V ≤ VDD ≤ 5.5 V 10 30 100 k
resistor

Remark: The characteristics of the dual-function pins are the same as those of the port pins unless
otherwise specified.

47
 µPD780948(A), µPD780949(A)

DC Characteristics (TA = -40 to +85° C, VDD = 4.0 to 5.5 V)

Mask ROM Version

Table 12-6: DC Characteristics Mask ROM Version

Parameter Symbol Conditions MIN TYP MAX Unit

8.0 MHz crystal oscillation
IDD1 9.5 tbd mA
operating mode (PCC = 00H)
8.0 MHz crystal oscillation
IDD2 1.2 tbd mA
HALT mode
Note
Power supply RC oscillation operating mode
IDD3 180 tbd µA
current (fxT = 40 kHz)
RC oscillation HALT mode
IDD4 60 tbd µA
(fxT = 40 kHz)
CL1 = VDD
IDD5 1 30 µA
STOP mode

Note: The AVREF current, port current (including a current flowing in the on-chip pull-up resistor), the
LCD split resistors and the EEPROM access are not included.
Remarks: 1. fX: Main system clock oscillator frequency.
2. fXT: Subsystem clock oscillator frequency.

DC Characteristics (TA = -10 to +85° C, VDD = 4.0. to 5.5 V)

LCD C/D 1/3 Bias Method

Table 12-7: DC Characteristics 1/3 Bias Method

Parameter Symbol Test Conditions MIN TYP MAX. Unit

LCD drive voltage VLCD 3.0 VDD V
LCD split resistor RLCD tbd 15 tbd k
LCD output voltage
Note VODC IO = ± 5 µA 3.0 V ≤ VLCD ≤ VDD 0 0.2
deviation (common) VLCD0 = VLCD V
LCD output voltage VLCD1 = VLCD x 2/3
Note VODS IO = ± 1 µA 0 0.2
deviation (segment) VLCD2 = VLCD x 1/3

Note: The voltage deviation is the difference from the output voltage corresponding to the ideal value
of the segment and common outputs (VLCDN; n = 0, 1, 2).

48
 µPD780948(A), µPD780949(A)

AC Characteristics

(1) Basic Operation (TA = -40 to +85° C, VDD = 4.0. to 5.5 V)

Table 12-8: AC Characteristics Basic Operation

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Cycle time (min. instruction TCY 4.5 V ≤ VDD ≤ 5.5 V 0.25 100 µs
execution time) 4.0 V ≤ VDD ≤ 5.5 V 0.5 100
TI50, TI51 input frequency fTI5 0 4 MHz
TI50, TI51 input high/low level tTIH5, 100 ns
width tTIL5
TI20, TI21, TI22 input high/low tTIH2, 3/ fSMP2 µs
level width tTIL2 Note1

TI00, TI01 input high/low level TCAPH, 3/ fSMP0 µs

width TCAPL Note2

Interrupt input high/low level TINTH, INTP0-4 1 µs

width TINTL
RESET low level width tRSL 10 µs

Notes: 1. fSMP2 (sampling clock) = fx/4, fx/8, fx/32, fx/128

2. fSMP0 (sampling clock) = fx/2, fx/16, fx/128

Figure 12-1: TCY vs VDD (At fx = fx/2 main system clock operation)

60

10
Cycle time TCY [µ s]

Operation guaranteed
range

2.0

1.0

0.5
0.4

0
1 2 3 4 5 6
Supply voltage VDD [V]

49
 µPD780948(A), µPD780949(A)

(2) Read/Write Operation (TA = -40 to +85° C, VDD = 4.0. to 5.5 V)

Table 12-9: Read/Write Operation

Parameter Symbol Conditions MIN. MAX. Unit

ASTB high-level width tASTH 0.5 tCY
Address setup time tADS 0.5 tCY - 54
Address hold time tADH 10
tADD1 (2.2 + 2n) tCY - 108
Data input time from address
tADD2 (3 + 2n) tCY - 120
Data input time from RD ↓ tRDD1 (2 + 2n) tCY - 148
tRDD2 (3 + 2n) tCY - 162
Address output time from RD ↓ tRDAD 0 200
Read data hold time tRDH 0
tRDL1 (1.5 + 2n) tCY - 40
RD low-level width
tRDL2 (2.5 + 2n) tCY - 40
Write data setup time tWDS 60 ns
Write data hold time tWDH 10
WR low-level width tWRL (1.5 + 2n) tCY - 30
RD ↓ delay time from ASTB ↓ tASTRD 10
WR ↓ delay time from ASTB ↓ tASTWR 2 tCY - 30
ASTB ↑ delay time from RD ↑
tRDAST 0.8 tCY - 30 1.2 tCY
at external fetch
Address hold time from RD ↑
tRDADH 0.8 tCY - 30 1.2 tCY + 60
at external fetch
Write data output time from
tRDWD 40
RD ↑
Write data output time from
tWRDWD 20 120
WR ↑
Address hold time from WR ↑ tWRADH 0.8 tCY - 30 1.2 tCY + 60

Remarks: 1. tCY = TCY/4

2. n indicates the number of waits
3. CL = 100 pF (CL are capacitances of AD0 to AD7, A8 to A15, RD, WR, ASTB pin)

50
 µPD780948(A), µPD780949(A)

(3) Serial Interface (TA = -40 to +85° C, VDD = 4.0. to 5.5 V)

(a) Serial Interface Channel 30

Table 12-10: 3-wire serial I/O mode (SCK0... Internal clock output)

Parameter Symbol Conditions MIN. MAX. Unit

SCK0 cycle time TKCY1 1000
SCK0 high/low-level width tKH1, tKL1 tKCY1/2 - 50
SI0 setup time ( to SCK0) ↑ tSIK1 100 ns
SI0 hold time (from SCK0) ↑ tKSI1 400
SO0 output delay time (from SCK0) ↓ tKSO1 C = 100 pF
Note
300

Note: C is the load capacitance of SO0, SCK0 output line

Table 12-11: 3-wire serial I/O mode (SCK0... External clock output)

Parameter Symbol Conditions MIN. MAX. Unit

SCK0 cycle time tKSO1 800
SCK0 high/low-level width tKH1, tKL1 400
SI0 setup time ( to SCK0) ↑ tSIK1 100 ns
SI0 hold time (from SCK0) ↑ tKSI1 400
SO0 output delay time (from SCK0) ↓ tKSO1 C = 100 pF
Note
300

Note: C is the load capacitance of SO0, SCK0 output line.

51
 µPD780948(A), µPD780949(A)

Table 12-12: 2-wire serial I/O mode (SCK0... Internal clock output)

Parameter Symbol Conditions MIN. TYP MAX Unit

SCK1 cycle time tKCY5 2000
SCK1 high -level width tKH5 tKCY5/2 - 160
SCK1 low-level width tKL5 R = 1k Ω tKCY5/2 - 160
Note ns
SI1 setup time ( to SCK1) ↑ tSIK5 C = 100 pF 300
SI1 hold time (from SCK1) ↑ tKSI5 600
SO1 output delay time (from SCK1) ↓ tKSO5 300

Note: R and C are the load resistance and load capacitance of the SI1/SO1 and SCK1 output line.

Table 12-13: 2-wire serial I/O mode (SCK0... External clock output)

Parameter Symbol Conditions MIN. TYP MAX Unit

SCK1 cycle time tKCY5 2000
SCK1 high -level width tKH5 840
SCK1 low-level width tKL5 R = 1k Ω 840
Note ns
SI1, SO1 setup time ( to SCK1) ↑ tSIK5 C = 100 pF 300
SI1, SO1 hold time (from SCK1) ↑ tKSI5 600
SI1, SO1 output delay time (from SCK1) ↓ tKSO5 300

Note: R and C are the load resistance and load capacitance of the SI1/SO1 and SCK1 output line.

Table 12-14: UART Mode (Dedicated baud rate generator output)

Parameter Symbol Conditions MIN. TYP MAX. Unit

Transfer rate 125 bps

52
 µPD780948(A), µPD780949(A)

Figure 12-2: AC Timing Test Points (excluding X1, CL1 inputs)

0.8 VDD 0.8 VDD

Test points
0.2 VDD 0.2 VDD

Figure 12-3: Clock Timing

1/fX

tXL tXH

VDD – 0.5 V
X1 Input
0.4 V

1/fXT

tXTL tXTH

VDD – 0.5 V
CL1 Input
0.4 V

Figure 12-4: TI Timing

t CAPL t CAPH

TI00, TI01

tTIL2 tTIH2

TI20, TI21, TI22

53
 µPD780948(A), µPD780949(A)

Read/Write Operation

Figure 12-5: External fetch (no wait)

A8 - A15 Upper (lower) 8-bit address

Lower 8-bit
address tADD1
Hi-Z Operation
AD0 - AD7
code
tADS tRDADH
tADH tRDD1
tASTH
tRDAST
ASTB

RD

tASTRD tRDL1
tRDH

Figure 12-6: External fetch (wait insertion)

A8 - A15 Upper (lower) 8-bit address

Lower 8-bit
address tADD1
Hi-Z Operation
AD0 - AD7
code
tADS tRDD1 tRDADH
tADH
tASTH
tRDAST
ASTB

RD

tASTRD tRDL1 tRDH

54
 µPD780948(A), µPD780949(A)

Figure 12-7: External data access (no wait)

A8 - A15 Upper (lower) 8-bit address

Lower
8-bit tADD2
address
Hi-Z Hi-Z Hi-Z
AD0 - AD7 Read data Write data

tADS tRDD2
tADH
tRDH
tASTH
ASTB

RD
tASTRD
tRDL2 tRDWD tWDS tWDH
tWRWDÊ tWRADH

WR

tASTWR tWRL

Figure 12-8: External data access (wait insertion)

A8 - A15 Upper (lower) 8-bit address

Lower
8-bit tADD2
address
Hi-Z Hi-Z Hi-Z
AD0 - AD7 Read data Write data

tADS tRDD2
tADH tRDH
tASTH
ASTB

tASTRD

RD
tWDH
tRDL2 tRDWD tWDS

tWRWD
WR

tASTWR tWRL tWRADH

55
 µPD780948(A), µPD780949(A)

Serial Transfer Timing

Figure 12-9: 3-wire serial I/O mode

tKCYm

tKLm tKHm

SCK0

tSIKm tKSIm

SI0 Input data

tKSO m

SO0 Output data

Remark: m=1

Figure 12-10: 2-wire serial I/O mode

tKCY5

tKL5 tKH5

SCK1

tSIK5 tKSI5
tKSO5

SI1, SO1

56
 µPD780948(A), µPD780949(A)

A/D Converter Characteristics (TA = -40 to +85° C, VDD = 4.0 to 5.5 V, AVSS = VSS =0 V, fx = 8 MHz)

Table 12-16: A/D Converter Characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution 8 8 8 bit
Overall error ± 0.6 %
Conversion time tCONV 18 µs
Analog input voltage VIAN AVSS AVDD
V
Reference voltage AVREF 4.0 VDD
Resistor string RAIREF CS-bit = 1 21 kΩ

Note: Overall error excluding quantization error (± 1/2 LSB). It is indicated as a ratio to the full-scale value.

Remark: fx: Main system clock oscillation frequency

EEPROM Characteristics (TA = -40 to +85° C, fx = 8.0 MHz)

Table 12-17: EEPROM Characteristics

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Voltage range for R/W VEERW 4.0 5.5 V
Write time tEEW 3 6 ms
Erase/Write cycles NEEWT 100000 cycle
Additional current when EEPROM is
IEE-W VDD = 5.0 V 1 tbd mA
erased/written

Note: The EEPROM is only available in the µPD780949 and not in the µPD780948.

57
 µPD780948(A), µPD780949(A)

Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85° C)

Table 12-18: Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Data retention power supply voltage VDDDR 4.0 5.5 V
Data retention power supply current IDDDR VDDDR = 4.0 V 1 30 µA
Release signal set time tSREL 0 µS
17
Release by RESET 2 /fx
Oscillation stabilization wait time tWAIT ms
Release by interrupt Note

Note: In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register,
selection of 212/fx and 214/fx to 217/fx is possible

Remark: fx: Main system clock oscillation frequency

Figure 12-11: Data Retention Timing (STOP mode release by RESET)

Internal reset operation

HALT mode

STOP mode Operating mode

Data retension mode

VDD VDDDR
tSREL
STOP instruction execution

RESET

tWAIT

Figure 12-12: Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)

HALT mode

STOP mode Operating mode

Data retension mode

VDD VDDDR
tSREL
STOP instruction execution

Standby release signal

(interrupt request)

tWAIT

58
 µPD780948(A), µPD780949(A)

Figure 12-13: Interrupt Input Timing

tINTL tINTH

INTP0 - INTP4

Figure 12-14: RESET Input Timing

tRSL

RESET

59
 µPD780948(A), µPD780949(A)

13. Package Drawing

Figure 13-1: Package Drawing

A
B

80 51
81 50
Detail of lead end

C
D

5¡±5¡
Q
100 31
1 30
F

G H I M J
K
P

N L
P100GF-65-3BA1-2
Note: Item Millimeters Inches
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at A 23.6 ± 0.4 0.929 ± 0.016
maximum material condition. B 20.0 ± 0.2 0.795 +0.009
–0.008

C 14.0 ± 0.2 0.551+0.009

–0.008

D 17.6 ± 0.4 0.693 ± 0.016

F 0.8 0.031
G 0.6 0.024
H 0.30 ± 0.10 0.012+0.004
–0.005

I 0.15 0.006
J 0.65 (T.P.) 0.026 (T.P.)
K 1.8 ± 0.2 0.071+0.008
–0.009

L 0.8 ± 0.2 0.031+0.009

–0.008

M 0.15+0.10
–0.05 0.006+0.004
–0.003

N 0.10 0.004
P 2.7 0.106
Q 0.1 ± 0.1 0.004 ± 0.004
S 3.0 MAX. 0.119 MAX.

Remark: The shape and material of the ES product is the same as the mass produced product.

60
 µPD780948(A), µPD780949(A)

14. Recommended Soldering Conditions

The µPD780948 should be soldered and mounted under the conditions in the table below. For detail
of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (IEI-1207).
For soldering methods and conditions other than those recommended below, consult our sales personnel.

µPD780948GF-XXX-3BA : 100-pin plastic QFP (14 x 20 mm)

µPD780949GF-XXX-3BA : 100-pin plastic QFP (14 x 20 mm)

Table 14-1: Surface Mounting Type Soldering Conditions

Recommended
Soldering Method Soldering Conditions
Condition Symbol
Package peak temperature: 235° C, Duration: 30 sec. max.
(at 210° C or above).
Number of times: twice max.
Infrared reflow <Precautions> IR35-00-2
(1) The second reflow schold be started after the first reflow
device temperature has retumed to the ordinary state.
(2) Flux washing must not be performed by the use of water
after the first reflow.
Package peak temperature: 215° C, Duration: 40 sec. max.
(at 210° C or above).
Number of times: twice max.
VPS <Precautions> VP15-00-2
(3) The second reflow schold be started after the first reflow
device temperature has retumed to the ordinary state.
(4) Flux washing must not be performed by the use of water
after the first reflow.
Soldering bath temperature: 260° C max.
Duration: 10 sec. max.
Wave soldering Number of times: once, Preheating temperature: 120° C WS60-00-1
max. (package surface temperature)

Pin part heating Pin temperature: 300° C max. -

Duration: 3 sec. max. (per device side).

Caution: Use of more than one soldering method should be avoided (exept in the case of pin part
heating).

61
 µPD780948(A), µPD780949(A)

Appendix A. Development Tools

The following tools are available for system development using the µPD780948.

Language Processing Software

Notes 1, 2, 3
RA78K/0 Assembler package used in common for the 78K/0 series
Notes 1, 2, 3
CC78K/0 C compiler package used in common for the 78K/0 series
DF780948, DF780949 Device file used for the µPD780949 subseries
Notes 1, 2, 3
CC78K/0-L C compiler library source file used in common for the 78K/0 series

PROM Writing Tools

Flashpro Dedicated flash writer for micro controllers with on-chip flash memory
FA-100GF Programmer adapter connected to the Flash-Pro

Debugging Tools

IE-78001-R-A In-circuit emulator used in common for the 78K/0 series

IE-78001-R-BK Break board used in common for the 78K/0 series
IE-70000-PC-IF-B This adapter is required when using an IBM PC/AT or compatible as host
IE-780948-SL-EM1 Emulation board and probe board for the µPD780949 subseries
IE-780948-SL-EM4
EP-100GF-SL Emulation probe used in common for the µPD780949 subseries
SM78K0 System simulator used in common for the 78K/0 series
ID78K/0 Integrated debugger for the IE-78001-R-A
DF780948, DF780949 Device file used for the µPD780949 subseries

Real-Time OS
Notes 1, 2, 3
RX78K/0 Real-time OS used for the 78K/0 series
Notes 1, 2, 3
MX78K0 OS used for the 78K/0 series

Fuzzy Interference Development Support System

Note 1 Note 5
FE9000 /FE9200 Fuzzy knowledge data creating tool
Note 1 Note 2
FT9080 /FT9085 Translator
Note 1, 2
FI78K0 Fuzzy interference module
Note 1, 2
FD78K0 Fuzzy interference debugger

Notes: 1. Based on PC-9800 series (MS-DOSTM)

2. Based on IBM PC/ATTM (PC DOSTM)
3. Based on HP9000 series 300TM, HP9000 series 700TM (HP-UXTM), SPARCstationTM (SunOSTM),
and EWS-4800 series (EWS-UX/V)
4. Based on PC-9800 series (MS-DOS + WindowsTM)
5. Based on IBM PC/AT (PC DOS + Windows)
Remarks: 1. For development tools supplied by third-party manufacturers, refer to 78K/0 series Selection
Guide (IF-1185).
2. Use the RA78K/0, CC78K/0, SM78K0 and D78K/0 in combination with the DF780945/F0948.
62
 µPD780948(A), µPD780949(A)

Appendix B. Related Documents

Documents Related to Devices

Document No.
Document
Japanese English
78K0 Series User’s Manual-Instruction IEU-849 IEU-1372
78K0 Series Instruction Table IEM-5522 —
78K0 Series Instruction Set IEM-5521 —
78K0 Series Application Note-Fundamental (III) IEA-767 To be prepared

Documents on Development Tools (User's Manuals)

Document No.
Document
Japanese English
Operation EEU-809 EEU-1399
RA78K Series Assembler Package
Language EEU-815 EEU-1404
RA78K Series Structured Assembler Reprocessor EEU-817 EEU-1402
Operation EEU-656 EEU-1280
CC78K Series C Compiler
Language EEU-655 EEU-1284
CC78K0 C Compiler Application Note Programming Know-how EEU-618 To be prepared
CC78K Series Library Source File EEU-777 —
IE78001-R-A EEU-810 U10057
IE-78001-R-BK EEU-867 To be prepared
IE-780948-SL-EM1 EEU-978 U12412
IE-780948-SL-EM4 — U12412
EP-100GF-SL EEU-934 EEU-1522
SM78K0 System Simulator Reference — U10181
IBM PC/AT (PC DOS) Base External Port Specification — U10092
ID78K0 Integrated Debugger Reference — U11539
IBM PC/AT (PC DOS) Base Guide — U11649

Caution: The above documents are subject to change without notice. Be sure to use the latest
documents for design or for any other similar purpose.

63
 µPD780948(A), µPD780949(A)

Documents on Embeded Software (User's Manuals)

Document No.
Document
Japanese English
78K0 Series Real-time OS Basic EEU-912 —
Installation EEU-911 —
Technical EEU-913 —
78K0 Series OS MX78K0 Fundamental EEU-5010 —
Fuzzy Knowledge Data Creation Tool EEU-829 EEU-1438
78K0, 78K/II, 87AD Series
EEA-862 EEU-1444
Fuzzy Inference Development Support System Translator
78K0 Fuzzy Inference Development Support System Fuzzy Inference Module EEU-858 EEU-1441
78K0 Fuzzy Inference Development Support System Fuzzy Inference
EEU-921 EEU-1458
Debugger

Other Documents

Document No.
Document
Japanese English
Package Manual IEI-635 IEI-1213
Semiconductor Device Mounting Technology Manual IEI-616 IEI-1207
Quality Grade on NEC Semiconductor Devices IEI-620 IEI-1209
NEC Semiconductor Device Reliability/Quality Control System IEM-5068 —
Electrostatic Discharge (ESD) Test MEM-539 —
Semiconductor Device Quality Assurance Guide MEI-603 MEI-1202
Microcontroller-Related Product Guide - Third Party Products - MEI-604 —

Caution: The above documents are subject to change without notice. Be sure to use the latest
documents for design or for any other similar purpose.

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Notes for CMOS Devices

1 Precaution against ESD for Semiconductors

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate
oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it once, when
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.

2 Handling of unused input pins for CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection
is provided to the input pins, it is possible that an internal input level may be generated
due to noise, etc., hence causing malfunction. CMOS device behave differently than
Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by
using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD
or GND with a resistor, if it is considered to have a possibility of being an output pin.
All handling related to the unused pins must be judged device by device and related
specifications governing the devices.

3 Status before initialization of MOS devices

Note: Power-on does not necessarily define initial status of MOS device. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the devices with reset function have not yet been initialized.
Hence, power-on does not guarantee out-pin levels, I/O settings or contents of
registers. Device is not initialized until the reset signal is received. Reset operation
must be executed immediately after power-on for devices having reset function.

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Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and components,
host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Santa Clara, California Benelux Office Hong Kong
Tel: 800-366-9782 Eindhoven, The Netherlands Tel: 2886-9318
Fax: 800-729-9288 Tel: 040-2445845 Fax: 2886-9022/9044
Fax: 040-2444580
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Duesseldorf, Germany NEC Electronics (France) S.A. Seoul Branch
Tel: 0211-65 03 02 Velizy-Villacoublay, France Seoul, Korea
Fax: 0211-65 03 490 Tel: 01-30-67 58 00 Tel: 02-528-0303
Fax: 01-30-67 58 99 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd.
Tel: 01908-691-133 Spain Office United Square, Singapore 1130
Fax: 01908-670-290 Madrid, Spain Tel: 253-8311
Tel: 01-504-2787 Fax: 250-3583
NEC Electronics Italiana s.r.l. Fax: 01-504-2860
Milano, Italy NEC Electronics Taiwan Ltd.
Tel: 02-66 75 41 NEC Electronics (Germany) GmbH Taipei, Taiwan
Fax: 02-66 75 42 99 Scandinavia Office Tel: 02-719-2377
Taeby, Sweden Fax: 02-719-5951
Tel: 08-63 80 820
Fax: 08-63 80 388 NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689

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FIP is a registered trademark of NEC Corporation.

IEBus is a trademark of NEC Corporation.
MS-DOS and MS-Windows are either registered trademarks or trademarks of Microsoft
Corporation in the United States and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corp.
HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett Packard Co.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of SUN Microsystems, Inc.

The related documents in this publication may include preliminary versions. However, prelimi-
nary versions are not marked as such.

The export of this product from Japan is regulated by the Japanese government. To export this
product may be prohibited without governmental license, the need for which must be judged by the
customer. The export or re-export of this product from a country other than Japan may also be
prohibited without a license from that country. Please call an NEC sales representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear
in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor
devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to
persons or property arising from a defect in an NEC semiconductor device, customer must incorporate
sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based
on a customer designated “quality assurance program“ for a specific application. The recommended
applications of a device depend on its quality grade, as indicated below. Customers must check the quality
grade of each device before using it in a particular application.
Standard:Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is “Standard“ unless otherwise specified in NEC's Data Sheets or Data
Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality
grade, they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.

M4 94.11

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