Data Sheet

ADXL354/ADXL355
Low Noise, Low Drift, Low Power, 3-Axis MEMS Accelerometers

FEATURES FUNCTIONAL BLOCK DIAGRAMS

► Hermetic package offers optimal long-term stability
► 0 g offset vs. temperature (all axes): 0.15 mg/°C maximum
► Ultralow noise spectral density, all axes: 22.5 µg/√Hz
► Low power, VSUPPLY (LDO regulator enabled)
► ADXL354 in measurement mode: 150 µA
► ADXL355 in measurement mode: 200 µA
► ADXL354/ADXL355 in standby mode: 21 µA
► ADXL354 has user adjustable analog output bandwidth
► ADXL355 digital output features
► Digital SPI and I2C interfaces supported Figure 1. ADXL354
► 20-bit ADC
► Data interpolation routine for synchronous sampling
► Programmable high- and low-pass digital filters
► Electromechanical self test
► Integrated temperature sensor
► Voltage range options
► VSUPPLY with internal regulators: 2.25 V to 3.6 V
► V1P8ANA, V1P8DIG with internal LDO regulator bypassed: 1.8 V
typical ± 10%
Figure 2. ADXL355
► Operating temperature range: −40°C to +125°C
► 14-terminal, 6 mm × 5.6 mm × 2.2 mm, LCC package GENERAL DESCRIPTION
APPLICATIONS The analog output ADXL354 and the digital output ADXL3551 are
low noise density, low 0 g offset drift, low power, 3-axis accelerome-
► Inertial measurement units (IMUs)/attitude and heading refer- ters with selectable measurement ranges. The ADXL354B supports
ence systems (AHRSs) the ±2 g and ±4 g ranges, the ADXL354C supports the ±2 g
► Platform stabilization systems and ±8 g ranges, and the ADXL355 supports the ±2 g, ±4 g,
► Structural health monitoring and ±8 g ranges. The ADXL354/ADXL355 offer industry leading
► Seismic imaging noise, minimal offset drift over temperature, and long-term stability
► Tilt sensing enabling precision applications with minimal calibration.
► Robotics Highly integrated in a compact form factor, the low power ADXL355
► Condition monitoring is ideal in an Internet of Things (IoT) sensor node and other
wireless product designs.
The ADXL355 multifunction pin names may be referenced by their
relevant function only for either the serial peripheral interface (SPI)
or I2C interface.

1 Protected by U.S. Patents 8,472,270; 9,041,462; 8,665,627; 8,917,099; 6,892,576; 9,297,825; and 7,956,621.

Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
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Data Sheet ADXL354/ADXL355
TABLE OF CONTENTS

Features................................................................ 1 FIFO_FULL...................................................... 32
Applications........................................................... 1 FIFO_OVR....................................................... 32
Functional Block Diagrams....................................1 Activity.............................................................. 32
General Description...............................................1 NVM_BUSY......................................................32
Specifications........................................................ 4 External Synchronization and Interpolation......32
Analog Output for the ADXL354.........................4 ADXL355 Register Map.......................................35
Digital Output for the ADXL355.......................... 5 Register Definitions............................................. 36
SPI Digital Interface Characteristics for the Analog Devices ID Register............................. 36
ADXL355.......................................................... 7 Analog Devices MEMS ID Register..................36
I2C Digital Interface Characteristics for the Device ID Register........................................... 36
ADXL355.......................................................... 8 Product Revision ID Register........................... 36
Absolute Maximum Ratings.................................10 Status Register.................................................36
Thermal Resistance......................................... 10 FIFO Entries Register.......................................37
Recommended Soldering Profile......................10 Temperature Data Registers............................ 37
ESD Caution.....................................................10 X-Axis Data Registers...................................... 37
Pin Configurations and Function Descriptions.....11 Y-Axis Data Registers...................................... 38
Typical Performance Characteristics................... 13 Z-Axis Data Registers...................................... 38
Root Allan Variance (RAV) ADXL355 FIFO Access Register...................................... 39
Characteristics................................................21 X-Axis Offset Trim Registers............................ 39
Theory of Operation.............................................22 Y-Axis Offset Trim Registers............................ 39
Applications Information...................................... 23 Z-Axis Offset Trim Registers............................ 40
Analog Output.................................................. 23 Activity Enable Register................................... 40
Digital Output....................................................23 Activity Threshold Registers.............................40
Axes of Acceleration Sensitivity....................... 24 Activity Count Register..................................... 41
Power Sequencing........................................... 24 Filter Settings Register..................................... 41
Power Supply Description................................ 24 FIFO Samples Register....................................41
Overrange Protection....................................... 24 Interrupt Pin (INTx) Function Map Register......42
Mechanical Headroom vs. Frequency..............25 Data Synchronization....................................... 42
Self Test............................................................25 I2C Speed, Interrupt Polarity, and Range
Filter................................................................. 25 Register.......................................................... 42
Serial Communications........................................28 Power Control Register.................................... 43
SPI Protocol..................................................... 28 Self Test Register............................................. 43
SPI Bus Sharing............................................... 28 Reset Register..................................................43
I2C Protocol...................................................... 29 PCB Footprint Pattern......................................... 44
Reading Acceleration or Temperature Data Outline Dimensions............................................. 45
From the Interface.......................................... 29 Ordering Guide.................................................45
FIFO.................................................................... 31 Output Mode, Measurement Range, and
Interrupts............................................................. 32 Specified Voltage Options.............................. 45
DATA_RDY.......................................................32 Evaluation Boards............................................ 45
DRDY Pin......................................................... 32

REVISION HISTORY

9/2024—Rev. B to Rev. C
Changed Master to Main and Slave to Subordinate (Throughout).................................................................. 1
Changes to Quality Factor Parameter, Table 1................................................................................................ 4
Changes to Table 5........................................................................................................................................ 10
Changes to Figure 58 and Figure 59............................................................................................................. 23
Changes to Power Sequencing Section........................................................................................................ 24

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Data Sheet ADXL354/ADXL355
TABLE OF CONTENTS

Changes to Overrange Protection Section.................................................................................................... 24

Added Figure 61; Renumbered Sequentially................................................................................................. 25
Added Mechanical Headroom Vs. Frequency Section, Figure 62, and Figure 63......................................... 25
Change to EXT_SYNC = 00, EXT_CLK = 0—No External Synchronization or Interpolation Section........... 33
Added Output Mode, Measurement Range, and Specified Voltage Options................................................. 45
Changes to Evaluation Boards...................................................................................................................... 45

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Data Sheet ADXL354/ADXL355
SPECIFICATIONS

ANALOG OUTPUT FOR THE ADXL354

TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, and z-axis acceleration = 1 g, unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
SENSOR INPUT Each axis
Output Full-Scale Range (FSR) ADXL354B supports two ranges ±2, ±4 g
ADXL354C supports two ranges ±2, ±8 g
Resonant Frequency1 2.4 kHz
Quality Factor X-axis and y-axis 7.4
Z-axis 1.5
Nonlinearity ±2 g 0.1 %
±8 g 1.15 %
Cross Axis Sensitivity 1 %
SENSITIVITY Ratiometric to V1P8ANA
Sensitivity at XOUT, YOUT, ZOUT ±2 g 368 400 432 mV/g
±4 g 184 200 216 mV/g
±8 g 92 100 108 mV/g
Sensitivity Change Due to Temperature −40°C to +125°C ±0.01 %/°C
Repeatability2 X-axis and y-axis 0.16 %
Z-axis 0.3 %
0 g OFFSET Each axis, ±2 g
0 g Output for XOUT, YOUT, ZOUT Referred to V1P8ANA/2 −75 ±25 +75 mg
0 g Offset vs. Temperature (X-Axis, Y-Axis, and −40°C to +125°C −0.15 ±0.1 +0.15 mg/°C
Z-Axis)3
Repeatability2 X-axis and y-axis ±2 mg
Z-axis ±3 mg
Vibration Rectification Error (VRE)4 ±2 g range, in a 1 g orientation, offset due to 2.5 g rms <0.4 g
vibration
NOISE
Spectral Density5
X-Axis, Y-Axis, and Z-Axis6 ±2 g 22.5 µg/√Hz
Velocity Random Walk ±2 g
X-Axis and Y-Axis 5.3 mm/sec/ÖHr
Z-Axis 7.7 mm/sec/ÖHr
BANDWIDTH 3 dB, overall transfer function7 1.9 kHz
SELF TEST
Output Change8
X-Axis 0.1 0.3 0.6 g
Y-Axis 0.1 0.3 0.6 g
Z-Axis 0.5 1.5 3.0 g
POWER SUPPLY
Voltage Range
VSUPPLY9 2.25 2.5 3.6 V
VDDIO V1P8DIG 2.5 3.6 V
V1P8ANA, V1P8DIG Internal low dropout (LDO) regulator bypassed, 1.62 1.8 1.98 V
VSUPPLY = 0 V
Current
Measurement Mode
VSUPPLY LDO regulator enabled 150 µA

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Data Sheet ADXL354/ADXL355
SPECIFICATIONS

Table 1. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
V1P8ANA LDO regulator disabled 138 µA
V1P8DIG LDO regulator disabled 12 µA
Standby Mode
VSUPPLY LDO regulator enabled 21 µA
V1P8ANA LDO regulator disabled 7 µA
V1P8DIG LDO regulator disabled 10 µA
Turn On Time10 2 g range <10 ms
Power-off to standby <10 ms
OUTPUT AMPLIFIER XOUT, YOUT, ZOUT, and TEMP pins
Swing No load 0.03 V1P8ANA − 0.03 V
Output Series Resistance 32 kΩ
TEMPERATURE SENSOR
Output at 25°C 967 mV
Scale Factor 3.0 mV/°C
TEMPERATURE
Operating Temperature Range −40 +125 °C

1 The resonant frequency is a sensor characteristic.

2 Repeatability is predicted for a 10 year life and includes shifts due to the high temperature operating life test (HTOL) (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours),
temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the
square root law. For example, to obtain offset repeatability of the x-axis for 2.5 years, use the following equation: ±2 mg × √(2.5 years/10 years) = ±1 mg.
3 The temperature change is −40°C to +25°C, or +25°C to +125°C.
4 The VRE measurement is the shift in dc offset while the device is subject to 2.5 g rms of random vibration from 50 Hz to 2 kHz. The device under test (DUT) is configured
for the ±2 g range and an output data rate of 4 kHz. The VRE scales with the range setting.
5 Based on characterization.
6 The noise spectral density for ±8 g range is estimated by design to be 50% more than that of the ±2 g range.
7 Overall transfer function includes the sensor mechanical response and all other filters on the signal chain.
8 The self test result converted to the acceleration value is independent of the selected range.
9 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS.
10 Standby to measurement mode. This specification is valid when the output is within 1 mg of the final value.

DIGITAL OUTPUT FOR THE ADXL355

TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, and z-axis acceleration = 1 g, and output data rate (ODR) = 500
Hz, unless otherwise noted. Note that multifunction pin names may be referenced by their relevant function only.

Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
SENSOR INPUT Each axis
Output Full-Scale Range (FSR) User selectable, supports three ranges ±2, ±4, ±8 g
Nonlinearity ±2 g 0.1 % FS
±8 g 1.6 %
Cross Axis Sensitivity 1 %
SENSITIVITY1 Each axis
X-Axis, Y-Axis, and Z-Axis Sensitivity ±2 g 235,520 256,000 276,480 LSB/g
±4 g 117,760 128,000 138,240 LSB/g
±8 g 58,880 64,000 69,120 LSB/g
X-Axis, Y-Axis, and Z-Axis Scale Factor ±2 g 3.9 µg/LSB
±4 g 7.8 µg/LSB

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Data Sheet ADXL354/ADXL355
SPECIFICATIONS

Table 2. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
±8 g 15.6 µg/LSB
Sensitivity Change due to Temperature −40°C to +125°C ±0.01 %/°C
Repeatability2 X-axis and y-axis 0.16 %
Z-axis 0.3 %
0 g OFFSET Each axis, ±2 g
X-Axis, Y-Axis, and Z-Axis 0 g Output −75 ±25 +75 mg
0 g Offset vs. Temperature (X-Axis, Y-Axis, and Z‑Axis)3 −40°C to +125°C −0.15 ±0.02 +0.15 mg/°C
Repeatability2 X-axis and y-axis ±2 mg
Z-axis ±3 mg
VRE4 ±2 g range, in a 1 g orientation, offset due to <0.4 g
2.5 g rms vibration
NOISE
Spectral Density5
X-Axis, Y-Axis, and Z-Axis ±2 g 22.5 µg/√Hz
±8 g 25 µg/√Hz
Velocity Random Walk ±2 g
X-Axis and Y-Axis 5.3 mm/sec/ÖHr
Z-Axis 7.7 mm/sec/ÖHr
BANDWIDTH AND OUTPUT DATA RATE
Analog-to-Digital Converter (ADC) Resolution 20 Bits
Low-Pass Filter Passband Frequency User programmable, Register 0x28 0.977 1000 Hz
High-Pass Filter Passband Frequency When Enabled User programmable, Register 0x28 for 4 kHz 0.0095 10 Hz
(Disabled by Default) ODR
SELF TEST
Output Change6
X-Axis 0.1 0.3 0.6 g
Y-Axis 0.1 0.3 0.6 g
Z-Axis 0.5 1.5 3.0 g
POWER SUPPLY
Voltage Range
VSUPPLY Operating7 2.25 2.5 3.6 V
VDDIO V1P8DIG 2.5 3.6 V
V1P8ANA and V1P8DIG Internal LDO regulator bypassed, VSUPPLY = 1.62 1.8 1.98 V
0V
Current
Measurement Mode
VSUPPLY LDO regulator enabled 200 µA
V1P8ANA LDO regulator disabled 160 µA
V1P8DIG LDO regulator disabled 35.5 µA
Standby Mode
VSUPPLY LDO regulator enabled 21 µA
V1P8ANA LDO regulator disabled 7 µA
V1P8DIG LDO regulator disabled 10 µA
Turn On Time8 2 g range <10 ms
Power-off to standby <10 ms
TEMPERATURE SENSOR
Output at 25°C 1885 LSB
Scale Factor −9.05 LSB/°C

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Data Sheet ADXL354/ADXL355
SPECIFICATIONS

Table 2. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
TEMPERATURE
Operating Temperature Range −40 +125 °C

1 Characterized but not 100% tested.

2 Repeatability is predicted for a 10 year life and includes shifts due to the HTOL (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and
1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the square root law. For example, to obtain offset
repeatability of the x-axis for 2.5 years, use the following equation: ±2 mg × √(2.5 years/10 years) = ±1 mg.
3 The temperature change is −40°C to +25°C or +25°C to +125°C.
4 The VRE measurement is the shift in dc offset while the device is subject to 2.5 g rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the ±2 g range and
an output data rate of 4 kHz. The VRE scales with the range setting.
5 Based on characterization.
6 The self test result converted to the acceleration value is independent of the selected range.
7 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS.
8 Standby to measurement mode. This specification is valid when the output is within 1 mg of final value.

SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355

Note that multifunction pin names may be referenced only by their relevant function.

Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DC INPUT LEVELS
Input Voltage
Low Level VIL 0.3 × VDDIO V
High Level VIH 0.7 × VDDIO V
Input Current
Low Level IIL Input voltage (VIN) = 0 V −0.2 µA
High Level IIH VIN = VDDIO 0.2 µA
DC OUTPUT LEVELS
Output Voltage
Low Level VOL IOL = IOL, MIN 0.2 × VDDIO V
High Level VOH IOH = IOH, MAX 0.8 × VDDIO V
Output Current
Low Level IOL VOL = VOL, MAX −10 mA
High Level IOH VOH = VOH, MIN 4 mA
AC INPUT LEVELS
SCLK Frequency 0.1 10 MHz
SCLK High Time tHIGH 40 ns
SCLK Low Time tLOW 40 ns
Setup Time tCSS 20 ns
CS Hold Time tCSH 20 ns
CS Disable Time tCSD 40 ns
Rising SCLK Setup Time tSCLKS 20 ns
MOSI Setup Time tSU 20 ns
MOSI Hold Time tHD 20 ns
AC OUTPUT LEVELS
Propagation Delay tP Load capacitance (CLOAD) = 30 pF 30 ns
Enable MISO Time tEN 30 ns
Disable MISO Time tDIS 20 ns

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Data Sheet ADXL354/ADXL355
SPECIFICATIONS

Figure 3. SPI Interface Timing Diagram

I2C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355

Note that multifunction pin names may be referenced by their relevant function only.

Table 4.
Test Conditions/ I2C_HS = 0 (Fast Mode) I2C_HS = 1 (High Speed Mode)
Parameter Symbol Comments Min Typ Max Min Typ Max Unit
DC INPUT LEVELS
Input Voltage
Low Level VIL 0.3 × VDDIO 0.3 × VDDIO V
High Level VIH 0.7 × VDDIO 0.7 × VDDIO V
Hysteresis of Schmitt VHYS 0.05 × VDDIO 0.1 × VDDIO V
Triggered Inputs
Input Current IIL 0.1 × VDDIO < VIN < 0.9 × −10 +10 µA
VDDIO
DC OUTPUT LEVELS
Output Voltage IOL = 3 mA
Low Level VOL1 VDDIO > 2 V 0.4 0.4 V
VOL2 VDDIO ≤ 2 V 0.2 × VDDIO 0.2 × VDDIO V
Output Current
Low Level IOL VOL = 0.4 V 20 20 mA
VOL = 0.6 V 6 6 mA
AC INPUT LEVELS
SCL Frequency 0 1 0 3.4 MHz
SCL High Time tHIGH 260 60 ns
SCL Low Time tLOW 500 160 ns
Start Setup Time tSUSTA 260 160 ns
Start Hold Time tHDSTA 260 160 ns
SDA Setup Time tSUDAT 50 10 ns
SDA Hold Time tHDDAT 0 0 ns
Stop Setup Time tSUSTO 260 160 ns
Bus Free Time tBUF 500 ns
SCL Input Rise Time tRCL 120 80 ns
SCL Input Fall Time tFCL 120 80 ns
SDA Input Rise Time tRDA 120 160 ns
SDA Input Fall Time tFDA 120 160 ns
Width of Spikes to Suppress tSP Not shown in Figure 4 50 10 ns
AC OUTPUT LEVELS
Propagation Delay CLOAD = 500 pF
Data tVDDAT 97 450 27 135 ns
Acknowledge tVDACK 450 ns

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Data Sheet ADXL354/ADXL355
SPECIFICATIONS

Table 4. (Continued)
Test Conditions/ I2C_HS = 0 (Fast Mode) I2C_HS = 1 (High Speed Mode)
Parameter Symbol Comments Min Typ Max Min Typ Max Unit
Output Fall Time tF Not shown in Figure 4 20 × (VDD/5.5) 120 ns

Figure 4. I2C Interface Timing Diagram

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Data Sheet ADXL354/ADXL355
ABSOLUTE MAXIMUM RATINGS

Table 5.
RECOMMENDED SOLDERING PROFILE
Parameter Rating
Acceleration (Any Axis) Figure 5 and Table 7 provide details about the recommended
Unpowered 5000 g peak, 0.5 ms pulse soldering profile.
duration
Powered 10000 g peak, 0.1 ms pulse
duration
Vibration (Any Axis, Powered, or Unpowered) Per MIL-STD-883 Method
2007, Test Condition A1
VSUPPLY, VDDIO 5.4 V
V1P8ANA, V1P8DIG Configured as Inputs 1.98 V
ADXL354
Digital Inputs (RANGE, ST1, ST2, STBY) −0.3 V to VDDIO + 0.3 V
Analog Outputs (XOUT, YOUT, ZOUT, TEMP) −0.3 V to V1P8ANA + 0.3 V
ADXL355
Figure 5. Recommended Soldering Profile
Digital Pins (CS/SCL, SCLK/VSSIO, MOSI/SDA, −0.3 V to VDDIO + 0.3 V
MISO/ASEL, INT1, INT2, DRDY) Table 7. Recommended Soldering Profile
Operating Temperature Range −40°C to +125°C Condition
Storage Temperature Range −55°C to +150°C
Profile Feature Sn63/Pb37 Pb-Free
1 Sine-wave excitation swept logarithmically from 20 Hz to 2 kHz, 20 g peak Average Ramp Rate from Liquid Temperature 3°C/sec 3°C/sec
amplitude. Sweep duration of 4 minutes. Repeat sweep four times per axis. (TL) to Peak Temperature (TP) maximum maximum
Stresses at or above those listed under Absolute Maximum Ratings Preheat
may cause permanent damage to the product. This is a stress Minimum Temperature (TSMIN) 100°C 150°C
rating only; functional operation of the product at these or any other Maximum Temperature (TSMAX) 150°C 200°C
conditions above those indicated in the operational section of this Time from TSMIN to TSMAX (tS) 60 sec to 120 60 sec to 180
specification is not implied. Operation beyond the maximum operat- sec sec
ing conditions for extended periods may affect product reliability. TSMAX to TL Ramp-Up Rate 3°C/sec 3°C/sec
maximum maximum
THERMAL RESISTANCE Liquid Temperature (TL) 183°C 217°C
Thermal performance is directly linked to printed circuit board Time Maintained Above TL (tL) 60 sec to 150 60 sec to 150
sec sec
(PCB) design and operating environment. Careful attention to PCB
Peak Temperature (TP) 240°C + 0°C/ 260°C + 0°C/
thermal design is required.
−5°C −5°C
θJA is the natural convection junction to ambient thermal resistance Time of Actual TP − 5°C (tP) 10 sec to 30 sec 20 sec to 40
measured in a one cubic foot sealed enclosure. ψJB is the junction sec
to board thermal resistance. Ramp-Down Rate 6°C/sec 6°C/sec
maximum maximum
Table 6. Thermal Resistance
Time from 25°C to Peak Temperature (t25°C TO 6 minutes 8 minutes
Package Type θJA ψJB Unit
PEAK) maximum maximum
E-14-11 42 17.6 °C/W
ESD CAUTION
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
ESD (electrostatic discharge) sensitive device. Charged devi-
test board with four thermal vias. See JEDEC JESD51.
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.

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Data Sheet ADXL354/ADXL355
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 6. ADXL354 Pin Configuration

Table 8. ADXL354 Pin Function Descriptions

Pin No. Mnemonic Description
1 RANGE Range Selection Pin. Set this pin to ground to select the ±2 g range, or set this pin to VDDIO to select the ±4 g or ±8 g range. This pin is
model dependent (see the Ordering Guide section).
2 ST1 Self Test Pin 1. This pin enables self test mode. This pin must be forced low when not in self test mode.
3 ST2 Self Test Pin 2. This pin activates electromechanical self test actuation. This pin must be forced low when not in self test mode.
4 TEMP Temperature Sensor Output.
5 VDDIO Digital Interface Supply Voltage.
6 VSSIO Digital Ground.
7 STBY Standby or Measurement Mode Selection Pin. Set this pin to ground to enter standby mode, or set this pin to VDDIO to enter
measurement mode.
8 V1P8DIG Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this pin externally.
9 VSS Analog Ground.
10 V1P8ANA Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this pin externally.
11 VSUPPLY Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDO regulators to generate V1P8DIG and V1P8ANA.
For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied.
12 XOUT X-Axis Output.
13 YOUT Y-Axis Output.
14 ZOUT Z-Axis Output.

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Data Sheet ADXL354/ADXL355
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 7. ADXL355 Pin Configuration

Table 9. ADXL355 Pin Function Descriptions

Pin No. Mnemonic Description
1 CS/SCL Chip Select for SPI (CS).
Serial Communications Clock for I2C (SCL).
2 SCLK/VSSIO Serial Communications Clock for SPI (SCLK).
I2C Mode Enable (VSSIO). Connect this pin to Pin 6 (VSSIO) to enable I2C mode.
3 MOSI/SDA Main Output, Subordinate Input for SPI (MOSI).
Serial Data for I2C (SDA).
4 MISO/ASEL Main Input, Subordinate Output for SPI (MISO).
Alternate I2C Address Select for I2C (ASEL).
5 VDDIO Digital Interface Supply Voltage.
6 VSSIO Digital Ground.
7 RESERVED Reserved. This pin can be connected to ground or left open.
8 V1P8DIG Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this pin externally.
9 VSS Analog Ground.
10 V1P8ANA Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this pin externally.
Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDO regulators to generate V1P8DIG and V1P8ANA.
11 VSUPPLY For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied.
12 INT1 Interrupt Pin 1.
13 INT2 Interrupt Pin 2.
14 DRDY Data Ready Pin.

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Data Sheet ADXL354/ADXL355
TYPICAL PERFORMANCE CHARACTERISTICS

All figures include data for multiple devices and multiple lots, and they were taken in the ±2 g range and TA = 25°C, unless otherwise noted. For
Figure 52, the ODR is derived from a main clock, with a frequency of 1.024 MHz and ±1.4% device to device variation (similar to ODR device to
device variation). For a given device, however, clock frequency variation over the temperature range (−40°C to +125°C) is no more than ±1.2%,
guaranteed by design.

Figure 8. ADXL354 Frequency Response for X-Axis Figure 11. ADXL355 Frequency Response for X-Axis at 4 kHz ODR

Figure 9. ADXL354 Frequency Response for Y-Axis Figure 12. ADXL355 Frequency Response for Y-Axis at 4 kHz ODR

Figure 10. ADXL354 Frequency Response for Z-Axis Figure 13. ADXL355 Frequency Response for Z-Axis at 4 kHz ODR

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Data Sheet ADXL354/ADXL355
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 14. ADXL354 Zero g Offset Normalized Relative to 25°C vs. Figure 17. ADXL354 Sensitivity Normalized Relative to 25°C vs. Temperature
Temperature, X-Axis X-Axis

Figure 15. ADXL354 Zero g Offset Normalized Relative to 25°C vs. Figure 18. ADXL354 Sensitivity Normalized Relative to 25°C vs. Temperature
Temperature, Y-Axis Y-Axis

Figure 16. ADXL354 Zero g Offset Normalized Relative to 25°C vs. Figure 19. ADXL354 Sensitivity Normalized Relative to 25°C vs. Temperature
Temperature, Z-Axis Z-Axis

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Data Sheet ADXL354/ADXL355
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 20. ADXL354 Zero g Offset Histogram at 25°C, X-Axis Figure 23. ADXL354 Sensitivity Histogram at 25°C, X-Axis

Figure 21. ADXL354 Zero g Offset Histogram at 25°C, Y-Axis Figure 24. ADXL354 Sensitivity Histogram at 25°C, Y-Axis

Figure 22. ADXL354 Zero g Offset Histogram at 25°C, Z-Axis Figure 25. ADXL354 Sensitivity Histogram at 25°C, Z-Axis

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Data Sheet ADXL354/ADXL355
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 26. ADXL354 VRE, X-Axis Offset from −1 g, ±2 g Range, X-Axis Figure 29. ADXL354 VRE, X-Axis Offset from −1 g, ±8 g Range, X-Axis
Orientation = −1 g Orientation = −1 g

Figure 27. ADXL354 VRE, Y-Axis Offset from +1 g, ±2 g Range, Y-Axis Figure 30. ADXL354 VRE, Y-Axis Offset from +1 g, ±8 g Range, Y-Axis
Orientation = +1 g Orientation = +1 g

Figure 28. ADXL354 VRE, Z-Axis Offset from +1 g, ±2 g Range, Z-Axis Figure 31. ADXL354 VRE, Z-Axis Offset from +1 g, ±8 g Range, Z-Axis
Orientation = +1 g Orientation = +1 g

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 32. ADXL355 Zero g Offset Normalized Relative to 25°C vs. Figure 35. ADXL355 Sensitivity Normalized Relative to 25°C vs. Temperature
Temperature, X-Axis X-Axis

Figure 33. ADXL355 Zero g Offset Normalized Relative to 25°C vs. Figure 36. ADXL355 Sensitivity Normalized Relative to 25°C vs. Temperature
Temperature, Y-Axis Y-Axis

Figure 34. ADXL355 Zero g Offset Normalized Relative to 25°C vs. Figure 37. ADXL355 Sensitivity Normalized Relative to 25°C vs. Temperature
Temperature, Z-Axis Z-Axis

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Data Sheet ADXL354/ADXL355
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 38. ADXL355 Zero g Offset Histogram at 25°C, X-Axis Figure 41. ADXL355 Sensitivity Histogram at 25°C, X-Axis

Figure 39. ADXL355 Zero g Offset Histogram at 25°C, Y-Axis Figure 42. ADXL355 Sensitivity Histogram at 25°C, Y-Axis

Figure 40. ADXL355 Zero g Offset Histogram at 25°C, Z-Axis Figure 43. ADXL355 Sensitivity Histogram at 25°C, Z-Axis

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Data Sheet ADXL354/ADXL355
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 44. ADXL355 VRE, X-Axis Offset from −1 g, ±2 g Range, X-Axis Figure 47. ADXL355 VRE, X-Axis Offset from −1 g, ±8 g Range, X-Axis
Orientation = −1 g Orientation = −1 g

Figure 45. ADXL355 VRE, Y-Axis Offset from +1 g, ±2 g Range, Y-Axis Figure 48. ADXL355 VRE, Y-Axis Offset from +1 g, ±8 g Range, Y-Axis
Orientation = +1 g Orientation = +1 g

Figure 46. ADXL355 VRE, Z-Axis Offset from +1 g, ±2 g Range, Z-Axis Figure 49. ADXL355 VRE, Z-Axis Offset from +1 g, ±8 g Range, Z-Axis
Orientation = +1 g Orientation = +1 g

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Data Sheet ADXL354/ADXL355
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 50. ADXL354 Temperature Sensor Output and Linear Offset vs.
Figure 53. ADXL355 Temperature Sensor Output and Linear Offset vs.
Temperature
Temperature

Figure 51. ADXL354 Total Supply Current, 3.3 V

Figure 54. ADXL355 Total Supply Current, 3.3 V

Figure 52. ADXL355 Output Data Rate (Internal Clock) Histogram

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Data Sheet ADXL354/ADXL355
TYPICAL PERFORMANCE CHARACTERISTICS

ROOT ALLAN VARIANCE (RAV) ADXL355 CHARACTERISTICS

All figures include data for multiple devices and multiple lots, and they were taken in the ±2 g range, unless otherwise noted.

Figure 55. ADXL355 RAV, X-Axis Figure 57. ADXL355 RAV, Z-Axis

Figure 56. ADXL355 RAV, Y-Axis

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Data Sheet ADXL354/ADXL355
THEORY OF OPERATION

The ADXL354 is a complete 3-axis, ultralow noise and ultrasta- drift and noise. The signal path is fully differential, except for a
ble offset microelectromechanical systems (MEMS) accelerometer differential to single-ended conversion at the analog outputs of the
with outputs ratiometric to the analog 1.8 V supply, V1P8ANA. The ADXL354.
ADXL355 adds three high resolution analog-to-digital converters
(ADCs) that use the analog 1.8 V supply as a reference to provide The analog accelerometer outputs of the ADXL354 are ratiometric
digital outputs insensitive to the supply voltage. The ADXL354B to V1P8ANA. Therefore, digitize them carefully. The temperature
is pin selectable for ±2 g or ±4 g full scale, the ADXL354C is sensor output is not ratiometric. The XOUT, YOUT, and ZOUT analog
pin selectable for ±2 g or ±8 g full scale, and the ADXL355 is outputs are filtered internally with an antialiasing filter. These analog
programmable for ±2 g, ±4 g, or ±8 g full scale. The ADXL355 offers outputs also have an internal 32 kΩ series resistor that can be used
both SPI and I2C communications ports. with an external capacitor to set the bandwidth of the output.

The micromachined, sensing elements are fully differential, com- The ADXL355 includes antialias filters before and after the high
prising the lateral x-axis and y-axis sensors and the vertical, teeter resolution Σ-Δ ADC. User-selectable output data rates and filter
totter z-axis sensors. The x-axis and y-axis sensors and the z-axis corners are provided. The temperature sensor is digitized with a
sensors go through separate signal paths that minimize offset 12-bit successive approximation register (SAR) ADC.

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Data Sheet ADXL354/ADXL355
APPLICATIONS INFORMATION

ANALOG OUTPUT and noise reduction prior to the external ADC. The antialias filter
cutoff frequency must be significantly higher than the desired signal
Figure 58 shows the ADXL354 application circuit. The analog bandwidth. If the antialias filter corner is too low, ratiometricity can
outputs (XOUT, YOUT, and ZOUT) are ratiometric to the 1.8 V analog degrade where the signal attenuation is different from the reference
voltage from the V1P8ANA pin. V1P8ANA can be powered with an attenuation.
on-chip LDO regulator that is powered from VSUPPLY. V1P8ANA
can also be supplied externally by forcing VSUPPLY to VSS, which DIGITAL OUTPUT
disables the LDO regulator. Due to the ratiometric response, the
analog output requires referencing to the V1P8ANA supply when Figure 59 shows the ADXL355 application circuit with the recom-
digitizing to achieve the inherent noise and offset performance of mended bypass capacitors. The communications interface is either
the ADXL354. The 0 g bias output is nominally equal to V1P8ANA/2. SPI or I2C (see the Serial Communications section for additional
The recommended option is to use the ADXL354 with a ratiometric information).
ADC (for example, the Analog Devices, Inc., AD7682) and V1P8ANA The ADXL355 includes an internal configurable digital band-pass
providing the voltage reference. This configuration results in self filter. Both the high-pass and low-pass poles of the filter are adjust-
cancellation of errors due to minor supply variations. able, as detailed in the Filter Settings Register section and Table
The ADXL354 outputs two forms of filtering: internal anti-aliasing 44. At power-up, the default conditions for the filters are as follows:
filtering with a cutoff frequency of approximately 1.5 kHz, and ► High-pass filter (HPF) = dc (off)
external filtering. The external filter uses a fixed, on-chip, 32 ► Low-pass filter (LPF) = 1000 Hz
kΩ resistance in series with each output in conjunction with the ► Output data rate = 4000 Hz
external capacitors to implement the low-pass filter antialiasing

Figure 58. ADXL354 Application Circuit

Figure 59. ADXL355 Application Circuit

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Data Sheet ADXL354/ADXL355
APPLICATIONS INFORMATION

AXES OF ACCELERATION SENSITIVITY reference. Not adhering to these power cycling recommendations
can result on lost communications and/or erroneous output data.
Figure 60 shows the axes of acceleration sensitivity. Note that the
output voltage increases when accelerated along the sensitive axis. POWER SUPPLY DESCRIPTION
The ADXL354/ADXL355 have four different power supply domains:
VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal analog and
digital circuitry operates at 1.8 V nominal.

VSUPPLY
VSUPPLY is 2.25 V to 3.6 V, which is the input range to the two LDO
regulators that generate the nominal 1.8 V outputs for V1P8ANA and
V1P8DIG. Connect VSUPPLY to VSS to disable the LDO regulators,
which allows driving V1P8ANA and V1P8DIG from an external source.

Figure 60. Axes of Acceleration Sensitivity

V1P8ANA
All sensor and analog signal processing circuitry operates in this
POWER SEQUENCING domain. Offset and sensitivity of the analog output ADXL354 are
There are two methods for applying power to the device. Typically, ratiometric to this supply voltage. When using external ADCs, use
internal LDO regulators generate the 1.8 V power for the analog V1P8ANA as the reference voltage The ADXL354 includes ADCs
and digital supplies, V1P8ANA and V1P8DIG, respectively. Optionally, that are ratiometric to V1P8ANA, thereby rendering the offset and
the internal LDO regulators can be disabled and V1P8ANA and sensitivity of the digital output ADXL354 insensitive to the value of
V1P8DIG are driven by external 1.8 V supplies. V1P8ANA. V1P8ANA can be an input or an output as defined by the
state of the VSUPPLY voltage.
When using the internal LDO regulators, connect VSUPPLY to a
voltage source between 2.25 V and 3.6 V. In this case, the recom- V1P8DIG
mended power sequence is to apply power to VDDIO, followed by
applying power to VSUPPLY approximately 10 µs later. If necessary, V1P8DIG is the supply voltage for the internal logic circuitry. A
VSUPPLY and VDDIO can be powered from the same voltage source, separate LDO regulator decouples the digital supply noise from the
so that both are powered at the same time. However, VSUPPLY analog signal path. V1P8ANA can be an input or an output as defined
cannot be powered before VDDIO. by the state of the VSUPPLY voltage. If driven externally, V1P8DIG
must be the same voltage as the V1P8ANA voltage.
To disable the internal LDO regulators, tie VSUPPLY to ground and
use external 1.8 V supplies to power V1P8ANA and V1P8DIG. V1P8ANA VDDIO
and V1P8DIG must have the same voltage level. The maximum
acceptable tolerance between the external V1P8ANA and V1P8DIG The VDDIO value determines the logic high levels. On the analog
voltage levels is 50 mV. In the case of bypassing the LDO regula- output ADXL354, VDDIO sets the logic high level for the self test
tors, the recommended power sequence is to apply power to VDDIO, pins, ST1 and ST2, as well as the \s\up5(\f(,STBY)) pin. On the
followed by applying power to V1P8DIG approximately 10 µs later, digital output ADXL355, VDDIO sets the logic high level for commu-
and then applying power to V1P8ANA approximately 10 µs later. nications interface ports, as well as the interrupt and DRDY outputs.
If necessary, V1P8DIG and VDDIO can be powered from the same
The LDO regulators are operational when VSUPPLY is between 2.25
external 1.8 V supply, which can also be tied to V1P8ANA with proper
V and 3.6 V. V1P8ANA and V1P8DIG are the regulator outputs in
isolation, so that all are powered at the same time. In this case,
this mode. Alternatively, when tying VSUPPLY to VSS, V1P8ANA and
proper decoupling and low frequency isolation are important to
V1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range.
maintain the noise performance of the sensor.
OVERRANGE PROTECTION
When power cycling the ADXL354/ADXL355, it is highly recom-
mended to fully discharge the device to ground level (VSUPPLY and The maximum nominal measurement range for the ADXL354/
VDDIO = 0 V), for at least 200 ms, on each power cycle. It is also ADXL355 is ±8 g. Do not subject the device to (or use the device
highly recommended to help the internal LDOs discharge properly in) applications or assembly processes that reasonably expect to
by adding external resistors of approximately 100 kΩ between the exceed this level of acceleration, particularly for long durations or
LDO outputs (V1P8ANA and V1P8DIG) and ground (0 V), especially on an ongoing basis. In such applications, the ADXL354/ADXL355
when power cycling at temperatures below −20°C. See the recom- offer higher g ranges that may be better suited for such applica-
mended application circuits shown in Figure 58 and Figure 59 for tions.

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Data Sheet ADXL354/ADXL355
APPLICATIONS INFORMATION

To avoid electrostatic capture of the proof mass when the acceler-

ometer is subject to input acceleration beyond its full-scale range,
all sensor drive clocks turn off for 0.5 ms. In the ±2 g range
setting, the overrange protection activates for input signals beyond
approximately ±8 g (±25%), and for the ±4 g and ±8 g range
settings, the threshold corresponds to about ±16 g (±25%).
When overrange protection occurs, the XOUT, YOUT, and ZOUT pins
on the ADXL354 begin to drive to midscale, whereas the ADXL355
floats toward zero, as shown in Figure 61.

Figure 63. Z-Axis Mechanical Headroom vs. Frequency Comparison for

ADXL354/ADXL355

SELF TEST
The ADXL354 and ADXL355 incorporate a self test feature that
effectively tests their mechanical and electronic systems simultane-
ously. Enabling self test stimulates the sensor electrostatically to
produce an output corresponding to the test signal applied as well
as the mechanical force exerted.
Figure 61. ADXL355 Overrange Behavior, ODR = 4 kHz In the ADXL354, drive the ST1 pin to VDDIO to invoke self test
mode. Then, by driving the ST2 pin to VDDIO, the ADXL354 applies
MECHANICAL HEADROOM VS. FREQUENCY an electrostatic force to the mechanical sensor and induces a
change in output in response to the force. The self test delta (or
The mechanical headroom defines the level of acceleration at response) is the difference in output voltages between when ST2
which the proof mass makes contact with the mechanical stops. is high vs. ST2 is low, while ST1 is asserted. After the self test
Repetitive contact can introduce both operational and reliability measurement is complete, bring both pins low to resume normal
problems. Figure 62 and Figure 63 provide the mechanical head- operation.
room over frequency for the ADXL354/ADXL355.
The self test operation is similar in the ADXL355, except ST1 and
The ADXL354 and ADXL355 are not suitable for applications where ST2 can be accessed through the SELF_TEST register (Register
the accelerometer is exposed to vibration operation conditions that 0x2E).
exceed the limits described in the Absolute Maximum Ratings
section. The self test feature rejects externally applied acceleration and
only responds to the self test force, which allows an accurate
measurement of the self test, even in the presence of external
mechanical noise. When the self test feature is not used, both ST1
and ST2 must be kept low.
FILTER
The ADXL354/ADXL355 use an analog, low-pass, antialiasing filter
to reduce out of band noise and to limit bandwidth. The ADXL355
provides further digital filtering options to maintain optimal noise
performance at various ODRs.
The analog, low-pass antialiasing filter in the ADXL354/ADXL355
provides a fixed 3 dB bandwidth of approximately 1.5 kHz, the
frequency at which the voltage output response is attenuated by
approximately 30%. The shape of the filter response in the frequen-
Figure 62. X-Axis and Y-Axis Mechanical Headroom vs. Frequency for
cy domain is that of a sinc filter. While the analog antialiasing
ADXL354/ADXL355 filter attenuates the output response around and above its cutoff

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Data Sheet ADXL354/ADXL355
APPLICATIONS INFORMATION

frequency, the MEMS sensor has a resonance at 2.4 kHz and setting in the filter register (Register 0x28, Bits[6:4]). Table 11
mechanically amplifies the output response at around 1 kHz and shows the HPF_CORNER response. Figure 65 and Figure 66 show
above. These competing trends are apparent in the overall transfer the simulated high-pass filter pass-band and delay responses for a
function of the ADXL354, as shown in Figure 8 to Figure 10. 9.88 Hz cutoff.
Therefore, the overall 3 dB bandwidth of the ADXL354 is 1.9 kHz.
The ADXL354 x-axis, y-axis, and z-axis analog outputs include an
amplifier followed by a series 32 kΩ resistor and output to the XOUT,
the YOUT, and the ZOUT pins, respectively.
The ADXL355 provides an internal 20-bit, Σ-Δ ADC to digitize
the filtered analog signal. Additional digital filtering (beyond the
analog, low-pass, antialiasing filter) consists of a low-pass digital
decimation filter and a bypassable high-pass filter that supports
output data rates between 4 kHz and 3.9 Hz. The decimation filter
consists of two stages. The first stage is fixed decimation with a
4 kHz ODR and a low-pass filter cutoff (3 dB) at about 1 kHz. A
variable second stage decimation filter is used for the 2 kHz output
data rate and below (it is bypassed for 4 kHz ODR). Figure 64
shows the low-pass filter response with a 1 kHz corner (4 kHz
ODR) for the ADXL355. Note that Figure 64 does not include the Figure 65. High-Pass Filter Pass-Band Response for a 4 kHz ODR and an
fixed frequency analog, low-pass, antialiasing filter with a fixed 3 dB HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])
bandwidth of approximately 1.5 kHz.
The ADXL355 pass band of the signal path relates to the combined
filter responses, including the analog filter previously described, and
the digital decimation filter/ODR setting. Table 10 shows the delay
associated with the decimation filter for each setting and provides
the attenuation at the ODR/4 corner.

Figure 66. High-Pass Filter Delay Response for a 4 kHz ODR and an
HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])

The ADXL355 also includes an interpolation filter after the deci-

mation filters that produces oversampled/upconverted data and
provides an external synchronization option. See the Data Synchro-
nization section for more details. Table 12 shows the delay and
Figure 64. ADXL355 Digital LPF Response for 4 kHz ODR attenuation relative to the programmed ODR.

The ADXL355 also includes an optional digital high-pass filter with Group delay is the digital filter delay from the input to the ADC until
a programmable corner frequency. By default, the high-pass filter data is available at the interface (see the Filter section). This delay
is disabled. The high-pass corner frequency, where the output is is the largest component of the total delay from sensor to serial
attenuated by 50%, is related to the ODR, and the HPF_CORNER interface.
Table 10. Digital Filter Group Delay and Profile
Delay Attenuation
Programmed ODR (Hz) ODR (Cycles) Time (ms) Decimator at ODR/4 (dB) Full Path at ODR/4 (dB)
4000 2.52 0.63 −3.44 −3.63
4000/2 = 2000 2.00 1.00 −2.21 −2.26

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APPLICATIONS INFORMATION

Table 10. Digital Filter Group Delay and Profile (Continued)

Delay Attenuation
Programmed ODR (Hz) ODR (Cycles) Time (ms) Decimator at ODR/4 (dB) Full Path at ODR/4 (dB)
4000/4 = 1000 1.78 1.78 −1.92 −1.93
4000/8 = 500 1.63 3.26 −1.83 −1.83
4000/16 = 250 1.57 6.27 −1.83 −1.83
4000/32 = 125 1.54 12.34 −1.83 −1.83
4000/64 = 62.5 1.51 24.18 −1.83 −1.83
4000/128 ≈ 31 1.49 47.59 −1.83 −1.83
4000/256 ≈ 16 1.50 96.25 −1.83 −1.83
4000/512 ≈ 8 1.50 189.58 −1.83 −1.83
4000/1024 ≈ 4 1.50 384.31 −1.83 −1.83

Table 11. Digital High-Pass Filter Response

HPF_CORNER Register Setting (Register
0x28, Bits[6:4]) HPF_CORNER Frequency, −3 dB Point Relative to ODR Setting −3 dB at 4 kHz ODR (Hz)
000 Not applicable, no high-pass filter enabled Off
001 24.7 × 10−4 × ODR 9.88
010 6.2084 × 10−4 × ODR 2.48
011 1.5545 × 10−4 × ODR 0.62
100 0.3862 × 10−4 × ODR 0.1545
101 0.0954 × 10−4 × ODR 0.03816
110 0.0238 × 10−4 × ODR 0.00952

Table 12. Combined Digital Interpolation Filter and Decimation Filter Response
Interpolator Data Rate Resolution Relative Combined Interpolator/ Decimator Combined Interpolator/ Combined Interpolator/Decimator Output
to 64 × ODR (Hz) Delay (ODR Cycles) Decimator Delay (ms) Attenuation at ODR/4 (dB)
64 × 4000 = 256,000 3.51661 0.88 −6.18
64 × 2000 = 128,000 3.0126 1.51 −4.93
64 × 1000 = 64,000 2.752 2.75 −4.66
64 × 500 = 32,000 2.6346 5.27 −4.58
64 × 250 = 16,000 2.5773 10.31 −4.55
64 × 125 = 8000 2.5473 20.38 −4.55
64 × 62.5 = 4000 2.53257 40.52 −4.55
64 × 31.25 = 2000 2.52452 80.78 −4.55
64 × 15.625 = 1000 2.52045 161.31 −4.55
64 × 7.8125 = 500 2.5194 322.48 −4.55
64 × 3.90625 = 250 2.51714 644.39 −4.55

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Data Sheet ADXL354/ADXL355
SERIAL COMMUNICATIONS

The 4-wire serial interface communicates in either the SPI or I2C SPI BUS SHARING
protocol. The interface affectively autodetects the format being
used, requiring no configuration control to select the format. Use a gated buffer on the SCLK line for the ADXL355 device to
achieve the ultralow noise performance and possibly offset shift
The ADXL355 multifunction pins are referred to by a single function when the ADXL355 must share a SPI bus with another subordinate
of the pin, for example, CS, when only that function is relevant. device. This gated SCLK allows the clock signal through only when
the chip select (CS) line is low. See Figure 68 for the example
SPI PROTOCOL
circuit that provides this type of protection.
Wire the ADXL355 for SPI communication as shown in the connec-
tion diagram in Figure 67. The SPI protocol timing is shown in
Figure 69 to Figure 72. The timing scheme follows the clock polarity
(CPOL) = 0 and clock phase (CPHA) = 0. The SPI clock speed
ranges from 100 kHz to 10 MHz.

Figure 68. SCLK Protection Example

Figure 67. 4-Wire SPI Connection

Figure 69. SPI Timing Diagram—Single-Byte Read

Figure 70. SPI Timing Diagram—Single-Byte Write

Figure 71. SPI Timing Diagram—Multibyte Read

Figure 72. SPI Timing Diagram—Multibyte Write

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Data Sheet ADXL354/ADXL355
SERIAL COMMUNICATIONS

I2C PROTOCOL Figure 73 to Figure 75 detail the I2C protocol timing. The I2C
interface can be used on most buses operating in I2C standard
The ADXL355 supports point to point I2C communication. However, mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz),
when sharing an SDA bus, the ADXL355 may prevent communica- and high speed mode (3.4 MHz). The ADXL355 I2C device ID is as
tion with other devices on that bus. If at any point, even when follows:
the ADXL355 is not being addressed, the 0x3A and 0x3B bytes
(when the ADXL355 device address is set to 0x1D), or the 0xA6 ► MISO/ASEL pin = 0, device address = 0x1D
and 0xA7 bytes (when the ADXL355 device address is set to ► MISO/ASEL pin = 1, device address = 0x53
0x53) are transmitted on the SDA bus, the ADXL355 responds with
an acknowledge bit and pulls the SDA line down. For example, READING ACCELERATION OR TEMPERATURE
this response can occur when reading or writing the data bytes DATA FROM THE INTERFACE
(0x3A/0x3B or 0xA6/0xA7) to another sensor on the bus. When Acceleration data is left justified and has a register address order
the ADXL355 pulls the SDA line down, communication with other of most significant data to least significant data, which allows the
devices on the bus may be interrupted. To resolve this interruption, user to use multibyte transfers and to take only as much data as
the ADXL355 must be connected to a separate SDA bus, or the required—8 bits, 16 bits, or 20 bits, plus the marker. Temperature
CS/SCL pin must be switched high when communication with the data is 12 bits unsigned, right justified. The ADXL355 temperature
ADXL355 is not desired (it is normally grounded). value is split over two bytes, but is not double buffered, meaning the
The ADXL355 supports standard (100 kHz), fast (up to 1 MHz) value can update between readings of the two registers. The data
and high speed (up to 3.4 MHz) data transfer modes when the in XDATA, YDATA, and ZDATA is always the most recent available.
bus parameters in Table 4 are met. There is no minimum SCL It is not guaranteed that XDATA, YDATA, and ZDATA form a set
frequency, with the exception that, when reading data, the clock corresponding to one sample point in time. The routine used to
must be fast enough to read an entire sample set before new retrieve the data from the device controls this data set continuity. If
data overwrites it. Single-byte or multiple byte reads/writes are data transfers are initiated when the DATA_RDY bit goes high and
supported. With the MISO/ASEL pin low, the I2C address for the completes in a time approximately equal to 1/ODR, XDATA, YDATA,
device is 0x1D and an alternate I2C address of 0x53 can be chosen and ZDATA apply to the same data set.
by pulling the MISO/ASEL pin high. For multibyte read or write transactions through either serial inter-
There are no internal pull-up or pull-down resistors for any unused face, the internal register address auto-increments. When the top of
pins. Therefore, there is no known state or default state for the pins the register address range, 0x3FF, is reached, the auto-increment
if left floating or unconnected. It is required that SCLK/VSSIO be stops and does not wrap back to Address 0x00.
connected to ground when communicating to the ADXL355 using The address auto-increment function disables when the FIFO ad-
I2C. dress is used, so that data can be read continuously from the FIFO
Due to communication speed limitations, the maximum output data as a multibyte transaction. In cases where the starting address of
rate when using the 400 kHz I2C mode is 800 Hz, and it scales line- a multibyte transaction is less than the FIFO address, the address
arly with a change in the I2C communication speed. For example, auto-increments until reaching the FIFO address, and then stops at
using I2C at 100 kHz limits the maximum ODR to 200 Hz. Operation the FIFO address.
at an output data rate above the recommended maximum may
result in an undesirable effect on the acceleration data, including
missing samples or additional noise.

Figure 73. I2C Timing Diagram—Single-Byte Read

Figure 74. I2C Timing Diagram—Single-Byte Write

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Data Sheet ADXL354/ADXL355
SERIAL COMMUNICATIONS

Figure 75. I2C Timing Diagram—Multibyte Write

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Data Sheet ADXL354/ADXL355
FIFO

The FIFO operates in a stream mode. That is, when the FIFO logic inserts the two virtual bits (0b00) between the data bits and
overruns, new data overwrites the oldest data in the FIFO. A read the empty indicator bit. Bit 1 indicates that an attempt was made
from the FIFO address guarantees that the three bytes associated to read an empty FIFO, and that the data is not valid acceleration
with the acceleration measurement on an axis all pertain to the data. Bit 0 is a marker bit to identify the x-axis, which allows a
same measurement. The FIFO never overflows, and the data is user to verify that the FIFO data was correctly read. An acceleration
always taken out in sets (multiples of three data points). data point for a given axis occupies one FIFO location. The read
pointer, RD_PTR, points to the oldest stored data that was not read
There are 96 21-bit locations in the FIFO. Each location contains already from the interface (see Figure 76). There are no physical
20 bits of data and a marker bit for the x-axis data. A single-byte x-acceleration, y-acceleration, or z-acceleration data registers. The
read from the FIFO address pops one location from the FIFO. A data read from data registers (Register 0x08 to Register 0x10) also
multibyte read to the FIFO location pops the FIFO on the read of comes directly from the most recent data set in the FIFO, which is
the first byte and every third byte read thereafter. pointed to by the z pointer, Z_PTR, (see Figure 76).
Figure 76 shows the organization of the data in the FIFO. The ac-
celeration data is twos complement, 20-bit data. The FIFO control

Figure 76. FIFO Data Organization

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Data Sheet ADXL354/ADXL355
INTERRUPTS

The status register (Register 0x04) contains five individual bits, FIFO_OVR
four of which can be mapped to the INT1 pin, the INT2 pin, or
both. The polarity of the interrupt, active high or active low, is The FIFO_OVR bit is set when the FIFO is so far overrange that
also selectable via the INT_POL bit in the range (Register 0x2C) data is lost. The specified size of the FIFO is 96 locations. The
register. In general, the status register clears when read, but this FIFO_OVR bit is set only when there is an attempt to write past this
is not the case if the condition that caused the interrupt persists 96-location limit.
after the read of the register. The definition of persist varies slightly A read of the status register clears FIFO_OVR. FIFO_OVR is not
in each case, but it is described in the DATA_RDY, DRDY Pin, set again until data is lost subsequent to this status register read.
FIFO_FULL, FIFO_OVR, and Activity sections. The DRDY pin is
similar to an interrupt pins (INTx) but clears differently. This case is ACTIVITY
also described. The activity bit (Register 0x04, Bit 3) is set when the measured ac-
DATA_RDY celeration on any axis is above the value set in the ACT_ THRESH
bits for ACT_COUNT consecutive measurements. An overthreshold
The DATA_RDY bit is set when new acceleration data is available condition can shift from one axis to another on successive meas-
to the interface and clears on a read of the status register. This bit urements and is still counted toward the consecutive ACT_COUNT
is not set again until acceleration data that is newer than the status count.
register read is available.
A read of the status register clears the activity bit (Register 0x04,
Special logic on the clearing of the DATA_RDY bit covers the corner Bit 3), but the bit sets again at the end of the next measurement if
case where new data arrives during the read of the status register. the activity bit (Register 0x04, Bit 3) conditions are still satisfied.
In this case, the data ready condition may be missed completely.
This logic results in a delay of the clearing of DATA_RDY of up to NVM_BUSY
four 512 kHz cycles. The NVM_BUSY bit indicates that the nonvolatile memory (NVM)
DRDY PIN controller is busy and, therefore, the NVM cannot be accessed to
read or write. The interrupt functionality requires the NVM_BUSY bit
The DRDY pin is not a status register bit. DRDY instead behaves to be cleared to function.
similar to an unmaskable interrupt. DRDY is set when new acceler-
ation data is available to the interface. DRDY clears on a read A status register read that occurs after the NVM controller is no
of the FIFO, on a read of XDATA, YDATA, or ZDATA, or by longer busy clears NVM_BUSY.
an autoclear function that occurs approximately halfway between EXTERNAL SYNCHRONIZATION AND
output acceleration data sets. INTERPOLATION
DRDY is always active high. The INT_POL bit does not affect
There are four possible synchronization options for the ADXL355,
DRDY. In external synchronization modes (EXT_SYNC = 01,
three of which are shown in Figure 77 to Figure 79. For clarity,
EXT_SYNC = 10), the first few DRDY pulses after initial synchro-
the clock frequencies and delays are drawn to scale. The labels in
nization can be lost or corrupted. The length of this potential
Figure 77 to Figure 79 are defined as follows:
corruption is equal to or less than the group delay. Therefore,
the samples within one group delay is lost or corrupted after the ► Internal ODR is the alignment of the decimated output data
first synchronization signal. Depending on the decimation setting based on the internal clock.
and interpolation setting (see Table 12), between one and three ► ADC modulator clock shows the internal main clock rate.
samples after the first synchronization pulse is lost, provided that all ► DRDY is an output indicator signaling a sample is ready.
the restrictions set in the External Synchronization and Interpolation
section is met. The four possible synchronization options are as follows:
FIFO_FULL ► No external synchronization (internal clocks used)
► Synchronization with an external synchronization signal and in-
The FIFO_FULL bit is set when the entries in the FIFO are equal
ternal clock, interpolation filter enabled
to the setting of the FIFO_SAMPLES bits. FIFO_FULL clears as
► Synchronization with external synchronization and clock signals,
follows:
no interpolation filter
► If the number of entries in the FIFO is less than the number of ► Synchronization with external synchronization and clock signals,
samples indicated by the FIFO_SAMPLES bits, which is only the interpolation filter enabled
case if sufficient data is read from the FIFO.
► On a read of the status register, but only when the entries in the
FIFO are less than the FIFO_SAMPLES bits.

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Data Sheet ADXL354/ADXL355
INTERRUPTS

EXT_SYNC = 00, EXT_CLK = 0—No External Table 13. EXT_SYNC = 10, DRDY Delay (Continued)
Synchronization or Interpolation ODR_LPF SYNC to DRDY Delay (Oscillator Cycles)
0x7 262
This is the default mode of operation for the device. The sensor
0x8 1031
runs on an internal ODR and an internal clock that is generated
by an internal oscillator. The internal ODR serves as the synchroni- 0x9 2054
zation controller, which generates the data. Register 0x28 is used 0xA 4102
to program the ODR. No external signals are required, and this
mode is used typically when the external processor retrieves data EXT_SYNC = 01, EXT_CLK = 1—External
from the device asynchronously and absolute synchronization to an Synchronization and External Clock, No
external source is not required. Interpolation Filter
The device outputs DRDY (active high) to signal that a new sample When configured for EXT_SYNC = 01 and EXT_CLK = 1 (sync
is available, and data is retrieved from the real-time registers or register, see Table 47), the user must supply an external clock
the FIFO. The group delay is based on the decimation setting, as (enabled via the EXT_CLK bit) at 1.024 MHz on the INT2 pin (Pin
shown in Table 10. This mode is shown in Figure 77. 13) and an external synchronization signal, SYNC, on the DRDY
pin (Pin 14), as shown in Table 14. If configured in this mode and
EXT_SYNC = 10, EXT_CLK = 0—External an external clock is not supplied, the device does not process any
Synchronization With Interpolation data and reading from the output results in null values. This mode is
schematically shown in Figure 79.
Synchronization using interpolation filters and an external ODR
clock is commonly used when the external processor can provide Special restrictions when using this mode include the following:
a synchronization signal that is asynchronous to the internal clock,
► The external clock frequency on INT2 (Pin 13, see Table 14)
SYNC, at the desired ODR. In this case, an interpolation filter
must be 1.024 MHz.
provides additional time resolution of 64 times the programmed
► The pulse width of the SYNC signal must be at least 3.91 µs,
ODR (see Table 12). Synchronization with the interpolation filter
enabled (EXT_SYNC = 10) allows the sensor to operate on an which represents four cycles of the external clock (4 ÷ 1.024
internal clock and output data most closely associated with the MHz = ~3.91 µs).
SYNC rising edge. ► The phase of SYNC must meet an approximate 25 ns setup time
to the external clock rising edge.
The advantage of this mode is that data is available at an arbitrary
user defined SYNC sample rate and is asynchronous to the internal When using the EXT_SYNC mode and without providing the SYNC
clock oscillator. The maximum sample rate cannot exceed 4000 signal, the device runs on its own internal ODR. Similarly, after
SPS. The disadvantage of this mode is that the group delay is in- external synchronization, the device continues to run synchronized
creased, with increased attenuation at the band edge. Additionally, to the last SYNC pulse it received, which means that EXT_SYNC =
because there is a limit to the time resolution, there is some distor- 01 mode can be used with only a single synchronization pulse.
tion related to the mismatch of the external synchronization relative For more information about the lost sample in Figure 79, see the
to the internal clock oscillator. This mismatch degrades spectral DRDY Pin section.
performance. The group delay is based on the decimation setting
and interpolation setting (see Table 12). Figure 78 schematically EXT_SYNC = 10, EXT_CLK = 1—External
shows the timings in this mode, and Table 13 shows the delay Synchronization and External Clock, With
between the SYNC signal (input) and DRDY (output).
Interpolation Filter
Table 13. EXT_SYNC = 10, DRDY Delay
This mode can be used to run the device on an external clock
ODR_LPF SYNC to DRDY Delay (Oscillator Cycles)
and synchronization with an arbitrary sample rate set by the SYNC
0x0 8 signal rate. Conditions for external SYNC and external clock signals
0x1 10 is the same as EXT_SYNC = 01, EXT_CLK = 1 mode. The inter-
0x2 14 polation filter provides a frequency resolution related to the ODR
0x3 22 (see Table 12). In this case, the data provided corresponds to the
0x4 38 external SYNC signal, which can be greater than the set ODR and
0x5 70 less than 4000 SPS, but the output pass band remains the same it
0x6 134 was prior to the interpolation filter.

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Data Sheet ADXL354/ADXL355
INTERRUPTS

Table 14. Multiplexing of INT2 and DRDY

Register or Bit Fields Pins
EXT_SYNC, INT_MAP, DRDY (Pin
EXT_CLK Bits[1:0] Bits[7:4] INT2 (Pin 13) 14) Comments
0 00 0000 Low DRDY Synchronization is to the internal clocks, and there is no external clock
0 00 Not 0000 INT2 DRDY synchronization.
1 00 0000 EXT_CLK DRDY
1 00 Not 00001 EXT_CLK DRDY
0 01 0000 DRDY2 SYNC These options reset the digital filters on every synchronization pulse and are not
0 013 Not 0000 INT2 SYNC recommended.
1 013 0000 EXT_CLK SYNC External synchronization, no interpolation filter, and DRDY (active high) signals that
1 013 Not 00001 EXT_CLK SYNC data is ready. Data represents a sample point group delay earlier in time.
0 10 0000 DRDY2 SYNC External synchronization, interpolation filter, and DRDY (active high) signals that data
0 103 Not 0000 INT2 SYNC is ready. Data sample group delay earlier in time.
1 103 0000 EXT_CLK SYNC
1 103 Not 0000 EXT_CLK SYNC

1 No INT2, even though it is enabled.

2 DRDY routing through the INT_MAP register takes precedence over the default, per Table 14.
3 No DRDY.

Figure 77. EXT_SYNC = 00, EXT_CLK = 0, Internal Synchronization, Internal Clock

Figure 78. EXT_SYNC = 10, EXT_CLK = 0, External Synchronization, Internal Clock, Interpolation Filter

Figure 79. EXT_SYNC = 01, EXT_CLK = 1, External Synchronization, External Clock, No Interpolation Filter

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Data Sheet ADXL354/ADXL355
ADXL355 REGISTER MAP

Note that while configuring the ADXL355 in an application, all configuration registers must be programmed before enabling measurement mode
in the POWER_CTL register. When the ADXL355 is in measurement mode, only the following configurations can change: the HPF_CORNER
bits in the filter register, the INT_MAP register, the ST1 and ST2 bits in the SELF_TEST register, and the reset register.

Table 15. ADXL355 Register Map

Hex.
Addr. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x00 DEVID_AD DEVID_AD 0xAD R
0x01 DEVID_MST DEVID_MST 0x1D R
0x02 PARTID PARTID 0xED R
0x03 REVID REVID 0x01 R
0x04 Status Reserved NVM_BUSY Activity FIFO_OVR FIFO_FULL DATA_RDY 0x00 R
0x05 FIFO_ENTRIES Reserved FIFO_ENTRIES 0x00 R
0x06 TEMP2 Reserved Temperature, Bits[11:8] 0x00 R
0x07 TEMP1 Temperature, Bits[7:0] 0x00 R
0x08 XDATA3 XDATA, Bits[19:12] 0x00 R
0x09 XDATA2 XDATA, Bits[11:4] 0x00 R
0x0A XDATA1 XDATA, Bits[3:0] Reserved 0x00 R
0x0B YDATA3 YDATA, Bits[19:12] 0x00 R
0x0C YDATA2 YDATA, Bits[11:4] 0x00 R
0x0D YDATA1 YDATA, Bits[3:0] Reserved 0x00 R
0x0E ZDATA3 ZDATA, Bits[19:12] 0x00 R
0x0F ZDATA2 ZDATA, Bits[11:4] 0x00 R
0x10 ZDATA1 ZDATA, Bits[3:0] Reserved 0x00 R
0x11 FIFO_DATA FIFO_DATA 0x00 R
0x1E OFFSET_X_H OFFSET_X, Bits[15:8] 0x00 R/W
0x1F OFFSET_X_L OFFSET_X, Bits[7:0] 0x00 R/W
0x20 OFFSET_Y_H OFFSET_Y, Bits[15:8] 0x00 R/W
0x21 OFFSET_Y_L OFFSET_Y, Bits[7:0] 0x00 R/W
0x22 OFFSET_Z_H OFFSET_Z, Bits[15:8] 0x00 R/W
0x23 OFFSET_Z_L OFFSET_Z, Bits[7:0] 0x00 R/W
0x24 ACT_EN Reserved ACT_Z ACT_Y ACT_X 0x00 R/W
0x25 ACT_THRESH_H ACT_THRESH, Bits[15:8] 0x00 R/W
0x26 ACT_THRESH_L ACT_THRESH, Bits[7:0] 0x00 R/W
0x27 ACT_COUNT ACT_COUNT 0x01 R/W
0x28 Filter Reserved HPF_CORNER ODR_LPF 0x00 R/W
0x29 FIFO_SAMPLES Reserved FIFO_SAMPLES 0x60 R/W
0x2A INT_MAP ACT_EN2 OVR_EN2 FULL_EN2 RDY_EN2 ACT_EN1 OVR_EN1 FULL_EN1 RDY_EN1 0x00 R/W
0x2B Sync Reserved EXT_CLK EXT_SYNC 0x00 R/W
0x2C Range I2C_HS INT_POL Reserved Range 0x81 R/W
0x2D POWER_CTL Reserved DRDY_OFF TEMP_OFF Standby 0x01 R/W
0x2E SELF_TEST Reserved ST2 ST1 0x00 R/W
0x2F Reset Reset 0x00 W

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Data Sheet ADXL354/ADXL355
REGISTER DEFINITIONS

This section describes the functions of the ADXL355 registers. The ADXL355 powers up with the default register values, as shown in the reset
column of Table 15.

ANALOG DEVICES ID REGISTER

This register contains the Analog Devices ID, 0xAD.

Address: 0x00, Reset: 0xAD, Name: DEVID_AD

Table 16. Bit Descriptions for DEVID_AD
Bits Bit Name Settings Description Reset Access
[7:0] DEVID_AD Analog Devices ID 0xAD R

ANALOG DEVICES MEMS ID REGISTER

This register contains the Analog Devices MEMS ID, 0x1D.

Address: 0x01, Reset: 0x1D, Name: DEVID_MST

Table 17. Bit Descriptions for DEVID_MST
Bits Bit Name Settings Description Reset Access
[7:0] DEVID_MST Analog Devices MEMS ID 0x1D R

DEVICE ID REGISTER
This register contains the device ID, 0xED (355 octal).

Address: 0x02, Reset: 0xED, Name: PARTID

Table 18. Bit Descriptions for PARTID
Bits Bit Name Settings Description Reset Access
[7:0] PARTID Device ID (355 octal) 0xED R

PRODUCT REVISION ID REGISTER

This register contains the product revision ID, beginning with 0x00 and incrementing for each subsequent revision.

Address: 0x03, Reset: 0x01, Name: REVID

Table 19. Bit Descriptions for REVID
Bits Bit Name Settings Description Reset Access
[7:0] REVID Mask revision 0x01 R

STATUS REGISTER
This register includes bits that describe the various conditions of the ADXL355.

Address: 0x04, Reset: 0x00, Name: Status

Table 20. Bit Descriptions for Status
Bits Bit Name Settings Description Reset Access
[7:5] Reserved Reserved. 0x0 R
4 NVM_BUSY NVM controller is busy with a refresh, programming, or a built in self test (BIST). 0x0 R

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Data Sheet ADXL354/ADXL355
REGISTER DEFINITIONS

Table 20. Bit Descriptions for Status (Continued)

Bits Bit Name Settings Description Reset Access
3 Activity Activity, as defined in the ACT_THRESH_x and ACT_COUNT registers, is detected. 0x0 R
2 FIFO_OVR FIFO has overrun, and the oldest data is lost. 0x0 R
1 FIFO_FULL FIFO watermark is reached. 0x0 R
0 DATA_RDY A complete x-axis, y-axis, and z-axis measurement was made and results can be read. 0x0 R

FIFO ENTRIES REGISTER

This register indicates the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 96.

Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES

Table 21. Bit Descriptions for FIFO_ENTRIES
Bits Bit Name Settings Description Reset Access
7 Reserved Reserved 0x0 R
[6:0] FIFO_ENTRIES Number of data samples stored in the FIFO 0x0 R

TEMPERATURE DATA REGISTERS

These two registers contain the uncalibrated temperature data. The nominal intercept is 1885 LSB at 25°C and the nominal slope is −9.05
LSB/°C. TEMP2 contains the four most significant bits, and TEMP1 contains the eight least significant bits of the 12-bit value. The ADXL355
temperature value is not double buffered, meaning the value can update between reading of the two registers.

Address: 0x06, Reset: 0x00, Name: TEMP2

Table 22. Bit Descriptions for TEMP2
Bits Bit Name Settings Description Reset Access
[7:4] Reserved Reserved.
[3:0] Temperature, Bits[11:8] Uncalibrated temperature data 0x0 R

Address: 0x07, Reset: 0x00, Name: TEMP1

Table 23. Bit Descriptions for TEMP1
Bits Bit Name Settings Description Reset Access
[7:0] Temperature, Bits[7:0] Uncalibrated temperature data 0x00 R

X-AXIS DATA REGISTERS

These three registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x08, Reset: 0x00, Name: XDATA3

Table 24. Bit Descriptions for XDATA3
Bits Bit Name Settings Description Reset Access
[7:0] XDATA, Bits[19:12] X-axis data 0x00 R

Address: 0x09, Reset: 0x00, Name: XDATA2

Table 25. Bit Descriptions for XDATA2
Bits Bit Name Settings Description Reset Access
[7:0] XDATA, Bits[11:4] X-axis data 0x00 R

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Data Sheet ADXL354/ADXL355
REGISTER DEFINITIONS

Address: 0x0A, Reset: 0x00, Name: XDATA1

Table 26. Bit Descriptions for XDATA1
Bits Bit Name Settings Description Reset Access
[7:4] XDATA, Bits[3:0] X-axis data 0x0 R
[3:0] Reserved Reserved 0x0 R

Y-AXIS DATA REGISTERS

These three registers contain the y-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x0B, Reset: 0x00, Name: YDATA3

Table 27. Bit Descriptions for YDATA3
Bits Bit Name Settings Description Reset Access
[7:0] YDATA, Bits[19:12] Y-axis data 0x00 R

Address: 0x0C, Reset: 0x00, Name: YDATA2

Table 28. Bit Descriptions for YDATA2
Bits Bit Name Settings Description Reset Access
[7:0] YDATA, Bits[11:4] Y-axis data 0x00 R

Address: 0x0D, Reset: 0x00, Name: YDATA1

Table 29. Bit Descriptions for YDATA1
Bits Bit Name Settings Description Reset Access
[7:4] YDATA, Bits[3:0] Y-axis data 0x0 R
[3:0] Reserved Reserved 0x0 R

Z-AXIS DATA REGISTERS

These three registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x0E, Reset: 0x00, Name: ZDATA3

Table 30. Bit Descriptions for ZDATA3
Bits Bit Name Settings Description Reset Access
[7:0] ZDATA, Bits[19:12] Z-axis data 0x00 R

Address: 0x0F, Reset: 0x00, Name: ZDATA2

Table 31. Bit Descriptions for ZDATA2
Bits Bit Name Settings Description Reset Access
[7:0] ZDATA, Bits[11:4] Z-axis data 0x00 R

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Data Sheet ADXL354/ADXL355
REGISTER DEFINITIONS

Address: 0x10, Reset: 0x00, Name: ZDATA1

Table 32. Bit Descriptions for ZDATA1
Bits Bit Name Settings Description Reset Access
[7:4] ZDATA, Bits[3:0] Z-axis data 0x0 R
[3:0] Reserved Reserved 0x0 R

FIFO ACCESS REGISTER

Address: 0x11, Reset: 0x00, Name: FIFO_DATA

Read this register to access data stored in the FIFO.

Table 33. Bit Descriptions for FIFO_DATA

Bits Bit Name Settings Description Reset Access
[7:0] FIFO_DATA FIFO data is formatted to 24 bits, three bytes, most significant byte first. A read to this address pops an 0x0 R
effective three equal byte words of axis data from the FIFO. Two subsequent reads or a multibyte read
completes the transaction of this data onto the interface. Continued reading or a sustained multibyte read
of this field continues to pop the FIFO every third byte. Multibyte reads to this address do not increment
the address pointer. If this address is read due to an auto-increment from the previous address, it does
not pop the FIFO. Instead, it returns zeros and increments on to the next address.

X-AXIS OFFSET TRIM REGISTERS

Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H

Table 34. Bit Descriptions for OFFSET_X_H
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_X, Offset added to x-axis data after all other signal processing. Data is in twos complement format. The 0x0 R/W
Bits[15:8] significance of OFFSET_X, Bits[15:0] matches the significance of XDATA, Bits[19:4].

Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L

Table 35. Bit Descriptions for OFFSET_X_L
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_X, Offset added to x-axis data after all other signal processing. Data is in twos complement format. The 0x0 R/W
Bits[7:0] significance of OFFSET_X, Bits[15:0] matches the significance of XDATA, Bits[19:4].

Y-AXIS OFFSET TRIM REGISTERS

Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H

Table 36. Bit Descriptions for OFFSET_Y_H
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Y, Offset added to y-axis data after all other signal processing. Data is in twos complement format. The 0x0 R/W
Bits[15:8] significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA, Bits[19:4].

Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L

Table 37. Bit Descriptions for OFFSET_Y_L
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Y, Offset added to y-axis data after all other signal processing. Data is in twos complement format. The 0x0 R/W
Bits[7:0] significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA, Bits[19:4].

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Data Sheet ADXL354/ADXL355
REGISTER DEFINITIONS

Z-AXIS OFFSET TRIM REGISTERS

Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H

Table 38. Bit Descriptions for OFFSET_Z_H
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Z, Offset added to z-axis data after all other signal processing. Data is in twos complement format. The 0x0 R/W
Bits[15:8] significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA, Bits[19:4].

Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L

Table 39. Bit Descriptions for OFFSET_Z_L
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Z, Offset added to z-axis data after all other signal processing. Data is in twos complement format. The 0x0 R/W
Bits[7:0] significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA, Bits[19:4].

ACTIVITY ENABLE REGISTER

Address: 0x24, Reset: 0x00, Name: ACT_EN

Table 40. Bit Descriptions for ACT_EN
Bits Bit Name Settings Description Reset Access
[7:3] Reserved Reserved. 0x0 R
2 ACT_Z Z-axis data is a component of the activity detection algorithm. 0x0 R/W
1 ACT_Y Y-axis data is a component of the activity detection algorithm. 0x0 R/W
0 ACT_X X-axis data is a component of the activity detection algorithm. 0x0 R/W

ACTIVITY THRESHOLD REGISTERS

Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H

Table 41. Bit Descriptions for ACT_THRESH_H
Bits Bit Name Settings Description Reset Access
[7:0] ACT_THRESH, Threshold for activity detection. Acceleration magnitude must be above ACT_THRESH to 0x0 R/W
Bits[15:8] trigger the activity counter. ACT_THRESH is an unsigned magnitude. The significance of
ACT_THRESH, Bits[15:0] matches the significance of Bits[18:3] of XDATA, YDATA, and
ZDATA.

Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L

Table 42. Bit Descriptions for ACT_THRESH_L
Bits Bit Name Settings Description Reset Access
[7:0] ACT_THRESH, Threshold for activity detection. The acceleration magnitude must be greater than the value 0x0 R/W
Bits[7:0] in ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned magnitude.
The significance of ACT_THRESH, Bits[15:0] matches the significance of Bits[18:3] of XDATA,
YDATA, and ZDATA.

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Data Sheet ADXL354/ADXL355
REGISTER DEFINITIONS

ACTIVITY COUNT REGISTER

Address: 0x27, Reset: 0x01, Name: ACT_COUNT

Table 43. Bit Descriptions for ACT_COUNT
Bits Bit Name Settings Description Reset Access
[7:0] ACT_COUNT Number of consecutive events above threshold (from ACT_THRESH) required to detect activity 0x1 R/W

FILTER SETTINGS REGISTER

Address: 0x28, Reset: 0x00, Name: Filter

Use this register to specify parameters for the internal high-pass and low-pass filters.

Table 44. Bit Descriptions for Filter

Bits Bit Name Settings Description Reset Access
7 Reserved Reserved 0x0 R
[6:4] HPF_CORNER −3 dB filter corner for the first-order, high-pass filter relative to the ODR 0x0 R/W
000 Not applicable, no high-pass filter enabled
001 24.7 × 10−4 × ODR
010 6.2084 × 10−4 × ODR
011 1.5545 × 10−4 × ODR
100 0.3862 × 10−4 × ODR
101 0.0954 × 10−4 × ODR
110 0.0238 × 10−4 × ODR
[3:0] ODR_LPF ODR and low-pass filter corner 0x0 R/W
0000 4000 Hz and 1000 Hz
0001 2000 Hz and 500 Hz
0010 1000 Hz and 250 Hz
0011 500 Hz and 125 Hz
0100 250 Hz and 62.5 Hz
0101 125 Hz and 31.25 Hz
0110 62.5 Hz and 15.625 Hz
0111 31.25 Hz and 7.813 Hz
1000 15.625 Hz and 3.906 Hz
1001 7.813 Hz and 1.953 Hz
1010 3.906 Hz and 0.977 Hz

FIFO SAMPLES REGISTER

Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES

Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The default value of this register is 0x60 to avoid
triggering the FIFO watermark interrupt.

Table 45. Bit Descriptions for FIFO_SAMPLES

Bits Bit Name Settings Description Reset Access
7 Reserved Reserved. 0x0 R
[6:0] FIFO_SAMPLES Watermark number of samples stored in the FIFO that triggers a FIFO_FULL condition. Values range 0x60 R/W
from 1 to 96.

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Data Sheet ADXL354/ADXL355
REGISTER DEFINITIONS

INTERRUPT PIN (INTX) FUNCTION MAP REGISTER

Address: 0x2A, Reset: 0x00, Name: INT_MAP

The INT_MAP register configures the interrupt pins. Bits[7:0] select which functions generate an interrupt on the INT1 and INT2 pins. Multiple
events can be configured. If the corresponding bit is set to 1, the function generates an interrupt on the interrupt pins.

Table 46. Bit Descriptions for INT_MAP

Bits Bit Name Settings Description Reset Access
7 ACT_EN2 Activity interrupt enable on INT2 0x0 R/W
6 OVR_EN2 FIFO_OVR interrupt enable on INT2 0x0 R/W
5 FULL_EN2 FIFO_FULL interrupt enable on INT2 0x0 R/W
4 RDY_EN2 DATA_RDY interrupt enable on INT2 0x0 R/W
3 ACT_EN1 Activity interrupt enable on INT1 0x0 R/W
2 OVR_EN1 FIFO_OVR interrupt enable on INT1 0x0 R/W
1 FULL_EN1 FIFO_FULL interrupt enable on INT1 0x0 R/W
0 RDY_EN1 DATA_RDY interrupt enable on INT1 0x0 R/W

DATA SYNCHRONIZATION

Address: 0x2B, Reset: 0x00, Name: Sync

Use this register to control the external timing triggers.

Table 47. Bit Descriptions for Sync

Bits Bit Name Settings Description Reset Access
[7:3] Reserved Reserved. 0x0 R
2 EXT_CLK Enable external clock. See Table 14 for configuration details. 0x0 R/W
[1:0] EXT_SYNC Enable external synchronization control. 0x0 R/W
00 Internal synchronization.
01 External synchronization, no interpolation filter. After synchronization, and for EXT_SYNC within
specification, DATA_RDY occurs on EXT_SYNC.
10 External synchronization, interpolation filter, next available data indicated by DATA_RDY 14 to 8204
oscillator cycles later (longer delay for higher ODR_LPF setting), data represents a sample point group
delay earlier in time.
11 Reserved.

I2C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER

Address: 0x2C, Reset: 0x81, Name: Range

Table 48. Bit Descriptions for Range
Bits Bit Name Settings Description Reset Access
7 I2C_HS I2C speed. 0x1 R/W
1 High speed mode.
0 Fast mode.
6 INT_POL Interrupt polarity. 0x0 R/W
0 INT1 and INT2 are active low.
1 INT1 and INT2 are active high.
[5:2] Reserved Reserved. 0x0 R
[1:0] Range Range. 0x1 R/W
01 ±2 g.

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Data Sheet ADXL354/ADXL355
REGISTER DEFINITIONS

Table 48. Bit Descriptions for Range (Continued)

Bits Bit Name Settings Description Reset Access
10 ±4 g.
11 ±8 g.

POWER CONTROL REGISTER

Address: 0x2D, Reset: 0x01, Name: POWER_CTL

Table 49. Bit Descriptions for POWER_CTL
Bits Bit Name Settings Description Reset Access
[7:3] Reserved Reserved. 0x0 R
2 DRDY_OFF Set to 1 to force the DRDY output to 0 in modes where it is normally signal data ready. 0x0 R/W
1 TEMP_OFF Set to 1 to disable temperature processing. Temperature processing is also disabled when standby = 1. 0x0 R/W
0 Standby Standby or measurement mode. 0x1 R/W
1 Standby mode. In standby mode, the device is in a low power state, and the temperature and acceleration
datapaths are not operating. In addition, digital functions, including FIFO pointers, reset. Changes to the
configuration setting of the device must be made when standby = 1. An exception is a high-pass filter that
can be changed when the device is operating.
0 Measurement mode.

SELF TEST REGISTER

Address: 0x2E, Reset: 0x00, Name: SELF_TEST

Refer to the Self Test section for more information on the operation of the self test feature.

Table 50. Bit Descriptions for SELF_TEST

Bits Bit Name Settings Description Reset Access
[7:2] Reserved Reserved. 0x0 R
1 ST2 Set to 1 to enable self test force 0x0 R/W
0 ST1 Set to 1 to enable self test mode 0x0 R/W

RESET REGISTER

Address: 0x2F, Reset: 0x00, Name: Reset

Table 51. Bit Descriptions for Reset
Bits Bit Name Settings Description Reset Access
[7:0] Reset Write Code 0x52 to reset the device, similar to a power-on reset (POR) 0x0 W

In case of a software reset, an unlikely race condition may occur in products with REVID = 0x01 or earlier. If the race condition occurs, some
factory settings in the NVM load incorrectly to shadow registers (the registers from which the internal logic configures the sensor and calculates
the output after a power-on or a software reset). The incorrect loading of the NVM affects overall performance of the sensor, such as an
incorrect 0 g bias and other performance issues. The incorrect loading of NVM does not occur from a power-on or after a power cycle. To
guarantee reliable operation of the sensor after a software reset, the user can access the shadow registers after a power-on, read and store
the values on the host microprocessor, and compare the values read from the same shadow registers after a software reset. This method
guarantees proper operation in all devices and under all conditions. The recommended steps are as follows:
1. Read the shadow registers, Register 0x50 to Register 0x54 (five 8-bit registers) after power-up, but before any software reset.
2. Store these values in a host device (for example, a host microprocessor).
3. After each software reset, read the same five registers. If the values differ, perform a software reset again until they match.

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Data Sheet ADXL354/ADXL355
PCB FOOTPRINT PATTERN

Figure 80 shows the PCB footprint pattern and dimensions in millimeters.

Figure 80. PCB Footprint Pattern and Dimensions in Millimeters

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Data Sheet ADXL354/ADXL355
OUTLINE DIMENSIONS

Package Drawing (Option) Package Type Package Description

E-14-1 LCC 14-Terminal Ceramic Leadless Chip Carrier

For the latest package outline information and land patterns (footprints), go to Package Index.

ORDERING GUIDE

Model1 Temperature Range Package Description Packing Quantity Package Option

ADXL354BEZ −40°C to +125°C 14-Terminal LCC Tray, 280 E-14-1
ADXL354BEZ-RL −40°C to +125°C 14-Terminal LCC Reel, 2000 E-14-1
ADXL354BEZ-RL7 −40°C to +125°C 14-Terminal LCC Reel, 500 E-14-1
ADXL354CEZ −40°C to +125°C 14-Terminal LCC Tray, 280 E-14-1
ADXL354CEZ-RL −40°C to +125°C 14-Terminal LCC Reel, 2000 E-14-1
ADXL354CEZ-RL7 −40°C to +125°C 14-Terminal LCC Reel, 500 E-14-1
ADXL355BEZ −40°C to +125°C 14-Terminal LCC Tray, 280 E-14-1
ADXL355BEZ-RL −40°C to +125°C 14-Terminal LCC Reel, 2000 E-14-1
ADXL355BEZ-RL7 −40°C to +125°C 14-Terminal LCC Reel, 500 E-14-1

1 Z = RoHS Compliant Part.

OUTPUT MODE, MEASUREMENT RANGE, AND SPECIFIED VOLTAGE OPTIONS

Model1 Output Mode Measurement Range (g) Specified Voltage (V)

ADXL354BEZ Analog ±2, ±4 3.3
ADXL354BEZ-RL Analog ±2, ±4 3.3
ADXL354BEZ-RL7 Analog ±2, ±4 3.3
ADXL354CEZ Analog ±2, ±8 3.3
ADXL354CEZ-RL Analog ±2, ±8 3.3
ADXL354CEZ-RL7 Analog ±2, ±8 3.3
ADXL355BEZ Digital ±2, ±4, ±8 3.3
ADXL355BEZ-RL Digital ±2, ±4, ±8 3.3
ADXL355BEZ-RL7 Digital ±2, ±4, ±8 3.3

1 Z = RoHS Compliant Part.

EVALUATION BOARDS
Model1 Description
EVAL-ADXL354BZ Evaluation Board for ADXL354BEZ
EVAL-ADXL354CZ Evaluation Board for ADXL354CEZ
EVAL-ADXL355Z Evaluation Board for ADXL355BEZ
EVAL- ADXL355-SDP ADXL355 Customer Evaluation System
1 Z = RoHS Compliant Part.

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