Module 4
The Metal– Insulator– Semiconductor FET
The Ideal MOS Capacitor
➢ Modified work function is
measured from the metal Fermi
level to the conduction band of the
oxide.
➢ Similarly, is the modified
work function at the
semiconductor– oxide interface.
➢ In this idealized case we assume
that
➢ measures the position of the
Band diagram for the ideal MOS
structure at equilibrium Fermi level below the intrinsic level
➢ The MOS structure is essentially a capacitor in Ei
which one plate is a semiconductor
Accumulation (VG<0)
➢ Negative voltage in metal causes hole accumulation in the p-type semiconductor.
➢ There is no carrier transport through the oxide and no current passes through the MOS structure,
there can be no variation in the Fermi level within the semiconductor.
➢ The Fermi level for the metal EFm lies above its equilibrium position by qV, where V is the applied
voltage.
➢ Moving EFm up in energy relative to EFs causes a tilt in the oxide conduction band.
➢ The energy bands of the semiconductor bend near the interface to accommodate the accumulation
of holes.
➢ Ei – EF is to increase, it must occur by Ei moving up in energy near the surface
Depletion (0<VG<VT)
➢ When apply a positive voltage from the metal to the semiconductor. This raises the potential of
the metal, lowering the metal Fermi level by qV relative to its equilibrium position.
➢ The positive voltage deposits positive charge on the metal and calls for a corresponding net
negative charge at the surface of the semiconductor.
➢ Such a negative charge in p- type material arises from depletion of holes from the region near
the surface, leaving behind uncompensated ionized acceptors.
➢ In the depleted region the hole concentration decreases, moving Ei closer to EF, and bending the
bands down near the semiconductor surface.
➢ The space charge per unit area, Qsc, in the semiconductor is equal to – qNAW , where W is the
width of the surface depletion region
Inversion (VG>VT)
➢ If we continue to increase the positive voltage, the bands at the semiconductor surface bend down
more strongly a sufficiently large voltage can bend Ei below EF .
➢ If Ei lies far below EF implies a large electron concentration in the conduction band.
➢ The region near the semiconductor surface in this case has conduction properties typical of n-
type material, with an electron concentration
➢ This n- type surface layer is formed not by doping, but instead by inversion of the originally p-
type semiconductor due to the applied voltage.
➢ This inverted layer, separated from the underlying p- type material by a depletion region, is the
key to MOS transistor operation
➢ Let represents the band bending at the surface.
➢ = 0 is the flat band condition for this ideal MOS case .
➢ When, < 0 the bands bend up at the surface, and we have hole accumulation
➢ Similarly, when >0 we have depletion
➢ Finally, when is positive and larger than q the bands at the surface are bent down
such that Ei(x = 0) lies below EF, and inversion is obtained.
➢ The best criterion for strong inversion is that the surface should be as strongly n- type as the
substrate is p type
That is, Ei should lie as far
below EF at the surface as it is
above EF far from the surface.
➢ A surface potential of q is
required to bend the bands down
to the intrinsic condition at the
surface (Ei = EF), and Ei must
then be depressed another q at
the surface to obtain the condition
we call strong inversion
➢ The electron and hole concentrations are
➢ The positive charge Qm on the metal is balanced by the negative charge Qs in the
semiconductor, which is the depletion layer charge plus the charge due to the inversion region
Qn.(charge per unit area (Q))
Derivation for threshold voltage
➢ Applied voltage V appears
partially across the insulator (Vi)
and partially across the depletion
region of the semiconductor
➢ The voltage across the insulator is obviously related to the charge on either side, divided by
the capacitance
Where is permittivity of the insulator and Ci is the insulator capacitance per unit area. The
charge Qs will be negative for the n channel, giving a positive Vi
➢ Using the depletion approximation, we can solve for W as a function of
➢ Depletion region grows with increased voltage across the capacitor until strong inversion is
reached.
➢ After that, further increases in voltage result in stronger inversion rather than in more depletion.
➢ Under Strong Inversion
ϕs = 2 ϕF
➢ Thus the maximum value of the depletion width is
➢ The charge per unit area in the depletion region Qd at strong inversion
➢ The applied voltage must be large enough to create this depletion charge plus the surface
potential.
➢ The threshold voltage required for strong inversion
➢ This assumes the negative charge at the semiconductor surface Qs at inversion is mostly
due to the depletion charge Qd.
REAL MOS Device
➢ For real MOS system work function of metal and semiconductor may be different.
➢ Let ϕms be the difference in work function of metal and semiconductor.
ϕms = ϕm - ϕsc
➢ Due to this difference in work function there is a band bending at semiconductor side of
MOS system under equilibrium condition (Without any external bias)
➢ To obtain flat band condition in MOS system a negative voltage (If semiconductor is P type)
must be applied to the gate called Flat band voltage
V FB = ϕms
Effects of Real Surfaces
Effect of a negative work function difference
Band bending and formation of negative Achievement of the flat band condition by
charge at the Semiconductor surface; application of a negative voltage
➢ Consider an oxide interface charges (Positive charge) in the inter face of MOS system is
𝑄𝑖 . This charge induce an equivalent negative charge in the semiconductor.
➢ Then Flat band voltage becomes.
𝑸
𝑽𝑭𝑩 = ϕ𝒎𝒔 − 𝒊
𝑪𝒊
Interface capacitance 𝐶𝑖 = 𝐶𝑜𝑥
➢ The voltage required to achieve flat band should be added to the threshold voltage .
Effective Threshold voltage of Real MOS become
𝑸𝒊 𝑸𝒅
𝑽𝑻 = 𝑽𝒕𝒉 = ϕ𝒎𝒔 − − + 𝟐ϕ𝑭
𝑪𝒊 𝑪𝒊
Interface capacitance 𝐶𝑖 = 𝐶𝑜𝑥
➢ The voltage required to create strong inversion must be large enough to first achieve the flat
𝑄
band condition (ϕ𝑚𝑠 − 𝑖 )
𝐶𝑖
𝑄𝑑
➢ Then accommodate the charge in the depletion region( )
𝐶𝑖
➢ Finally to induce the inverted region (2ϕ𝐹 )
C – V Characteristics of Ideal MOS system
➢ MOS capacitor is the series combination of a fixed, voltage- independent gate oxide
(insulator) capacitance, and a voltage-dependent semiconductor capacitance.
➢ Capacitance in accumulation is very high. Since, for negative voltage, holes are
accumulated at the the MOS structure appears almost like a parallel-plate capacitor,
dominated by the insulator capacitor
➢ Capacitance in depletion gets reduced since the depletion capacitance comes in series
with insulator capacitance.
➢ The effective capacitance becomes
➢ After inversion is reached, Capacitance depends on frequency of the applied signal.
➢ If the gate voltage is varied rapidly much greater than the thermal generation of minorit
carriers, the charge in the inversion layer cannot change in response.
➢ Hence, the semiconductor capacitance is at a minimum, corresponding to a maximum
depletion width.
➢ On the other hand, if the gate bias is changed slowly, there is time for minority carriers
to be generated in the bulk, drift across the depletion region to the inversion layer, or go
back to the substrate and recombination.
➢ Now, the semiconductor capacitance, is very large because. Hence, the low frequency
MOS series capacitance in strong inversion is basically Ci once again.
MOSFET
➢ Based on the working of MOSFET it classified into Enhancement type and Depletion type
➢ Enhancement MOSFET.: In this type MOSFET initially no channel is exist between
Source and Drain.
➢ Depletion MOSFET: In this type MOSFET, an inversion layer exist in substrate and
which act as channel.
➢ When 0 < VGS < Vt, the gated region between the source and the drain is depleted; no carrier
flow can be observed in the channel.
➢ As the gate voltage is increased beyond the threshold voltage (VGS > Vt), however, the mid-
gap energy level at the surface is pulled below the Fermi level, causing the surface potential
to turn positive and to invert
➢ Once the inversion layer is established on the surface, an n-type conducting channel forms
between the source and the drain, which is capable of carrying the drain current.
linear region
➢ At VDS = 0, thermal equilibrium exists in the inverted channel region, and the drain current
ID is equal to zero.
➢ If a small drain voltage VDS > 0 is applied, a drain current proportional to VDS will flow
from the source to the drain through the conducting channel.
➢ This operation mode is called the linear mode, or the linear region. Thus, in linear region
operation, the channel region acts as a voltage-controlled resistor.
Saturation region
➢ As the drain voltage is increased, the
inversion layer charge and the channel depth
at the drain end start to decrease.
➢ Eventually, for VDS = VDSAT, = VGS –Vt the
inversion charge at the drain is reduced to
zero, which is called the pinch-off point.
➢ This operation mode of the MOSFET is
called the saturation mode or the saturation
region.
➢ Beyond the pinch-off point, i.e., for VDS > VDSAT, a depleted surface region forms
adjacent to the drain, and this depletion region grows toward the source with
increasing drain voltages
Output Characteristics of MOSET
Saturation Region
Linear Region
Cut off Region
I-V CHARACTERISTICS OF MOSFET
DERIVATION OF DRAIN CURRENT IN MOSFET
Assumptions taken for derivation
1. Current flow through the channel is one dimension. No current flow between source and
gate.
2. Source and Substrate are grounded
3. Depletion layer charge density remain constant from source to drain.
4. The potential gradient form Drain to Source is much smaller than that from gate to channel.
Therefore, the electron density in the channel is decided by the gate to channel potential. This
approximation is know as Gradual Channel approximation.
5. It is assumed that the entire channel region between the source and the drain is inverted,
Schematic view of the n-
channel region of a MOS
transistor under
bias below pinch-off,
And the variation of
voltage Vx along the
conducting channel
I-V CHARACTERISTICS OF MOSFET
DERIVATION OF DRAIN CURRENT IN MOSFET
VS = 0 Grounded
VDS = VD
VGS = VG
Substrate also grounded
➢ For active operation of MOSFET , the applied gat voltage VG must greater than
threshold voltage
➢ Applied Gate voltage VG consist of Flat band voltage and remaining voltage drop
across oxide and semiconductor
VFB = Flat Band voltage
(1) Q S = Charge in Semiconductor
QS =Qd + Qn (2) (Depletion & Inversion Charge)
➢ Then Inversion layer charge can be represented as
Substitute 2 in 1 and rearrange
(3)
➢ Due to applied Drain voltage VD , Voltage at any point on depletion region can represented as
Vx , x be the distance form source.
➢ Thus the potential required for strong inversion at any point x now become ϕs (x) (function of x
as the voltage across the channel varies from source side to drain side)
ϕs (x) = 2ϕF + Vx (4)
➢ Then Inversion layer charge can be represented as ( Substitute 4 in 3)
(5)
➢ By neglect the variation of Qd(x) with bias voltage Vx. Then Inversion layer charge per unit
area become
(6)
Substituting the equation for VT in 5
➢ This equation describes the amount of mobile charge at any point x of MOSFET channel
➢ Then conductance of the differential element dx can represented as
σ = (7)
➢ where Z is the width of the channel and is surface electron mobility (indicating the
mobility in a thin region near the surface is not the same as in the bulk material).
➢ Then current density at any point x of the channel become
JD = σ E (8) E = dV/dx
Substituting 7 in 8
(9) σ =
➢ If the current density s integrate over channel length L
(8)
(9)
➢ This equation not account the increases in depletion layer charge form source to drain
➢ Due reduction of channel towards drain reduce the drain current and Actual drain current
is less than that given equation
➢ When VD = VDsat Channel depleted at Drain end(pinch off) and current though MOSFET
saturated
VDsat = VG - VT
➢ Equation of Saturation Drain current become
➢ Drain current of MOSFET under different bias condition can write as
VG < VT ID = 0 Cutoff Region
VG > VT && VD < VG - VT
Linear Region of Operation
VG > VT && VD > VG - VT
Saturation Region
Conductance of MOSFET
➢ Drain current of MOSFET in saturation region is
➢ Then conductance of MOSFET is
TRANSFER CHARACTERISTICS
It is the plot of Output current ID vs input voltage VGS; keeping
drain to source voltage constant VDS
Effect of change in VGS
Chara looks like forward biased diode
When VGS < VT ID =0
No channel exist between source and Drain,
No current flow between source and drain for any value of VDS
When VGS = VT
VGS create an inversion layer between Source and Drain which act as a
channel and current flow.
Current flow between Source and Drain and value depends on given VDS
