Altera®

Product Catalog

• Cover TBD

Version 25.1
Contents

Overview Acceleration Platform and Card Solutions

Altera® FPGA and Custom Logic Solutions Portfolio 1
Acceleration Card Solutions 62
Open FPGA Stack 65
Devices
FPGA IPU F2000X-PL 66
Agilex™ FPGA Portfolio
FPGA IPU C5000X-PL 67
- Agilex FPGAs and SoCs 2
- Agilex 7 FPGA and SoC Overview 3 FPGA SmartNIC N6000-PL Platform 68
- Agilex 7 FPGA and SoC F-Series Features 5 Accelerated Workload Solutions 70
- Agilex 7 FPGA and SoC I-Series Features 7
- Agilex 7 FPGA and SoC M-Series Features Acceleration Card Comparison 71
9
- Agilex 5 FPGA and SoC Overview 11 Accelerator Cards That Fit Your Performance Needs 72
- Agilex 5 FPGA and SoC E-Series Features 13
- Agilex 5 FPGA and SoC D-Series Features 17
- Agilex 3 FPGA and SoC C-Series Features 19 Design Tools, OS Support, and Processors
Quartus® Prime Design Software 73
Generation 10 Device Portfolio FPGA AI Suite 76
- Generation 10 FPGAs and SoCs 21
- Stratix® 10 FPGA and SoC Overview 22 DSP Builder 78
- Stratix 10 GX FPGA Features 24 Embedded Software and Tools for Altera SoC FPGA 79
- Stratix 10 TX FPGA Features 26 SoC FPGA Operating System Support 80
- Stratix 10 DX FPGA Features 28
- Stratix 10 SX SoC Features 30 Nios® V Processor 81
- Arria® 10 FPGA and SoC Overview 32 RiscFree* IDE for Altera FPGAs 82
- Arria 10 FPGA Features 33
- Arria 10 SoC Features 35
- Cyclone® 10 FPGA Overview 37 Intellectual Property
- Cyclone 10 GX FPGA Features 38 Altera and Intel Partner Alliance IP Functions 83
- Cyclone 10 LP FPGA Features 39
Design Store 85
- MAX® 10 FPGA Overview 41
- MAX 10 FPGA Features 42
Development Kits
28 nm Device Portfolio Altera and Partner Development Kits 86
- Arria V FPGA and SoC Features 44 FPGA-Based SoM Partner Ecosystem 90
- Cyclone V FPGA Features 46
- Cyclone V SoC Features 48 Partner Program
60 nm Device Portfolio Partner Alliance Program 91
- Cyclone IV FPGA Features 50
Training
MAX CPLD Series Training Overview 92
- MAX V CPLD Features 52
Instructor-Led and Virtual Classes 92
Ordering Codes 54
 Overview

Altera® FPGA and Custom Logic

Solutions Portfolio
Altera delivers a broad portfolio of custom logic solutions — FPGAs, SoCs, structured ASICs, and CPLDs—together with software
tools, intellectual property (IP), embedded processors, customer support, and technical training. Altera's product leadership,
excellent value, and superior quality of service give you a measurable advantage. Bring your great ideas to life faster, better, and
more cost effectively.

FPGAs, Structured ASICs, and CPLDs

Altera FPGAs and CPLDs give you the flexibility to innovate, differentiate, and stay ahead in the market. We have five classes of
FPGAs to meet your market needs, from the industry’s highest density and performance to the most cost effective.

Agilex FPGAs Cyclone Series

The Agilex portfolio presents a broad range The Cyclone FPGA series is built to meet
of product offerings that address the full your low-power, cost-sensitive design
breadth of programmable logic needs needs, enabling you to get to market
across every technology sector from edge faster.
and embedded, to communications and
data centers.

Stratix Series MAX Series

The Stratix FPGA and SoC family enables The MAX 10 FPGAs revolutionize
you to deliver high-performance, non-volatile integration by delivering
state-of-the-art products to market faster advanced processing capabilities in a
with lower risk and higher productivity. low-cost, single-chip small form.

Arria Series eASIC Devices

The Arria device family delivers eASIC structured ASIC devices
performance and power efficiency in the complete the gap between FPGA and
midrange. ASIC by delivering lower power and
lower unit price versus FPGAs and lower
non-recurring engineering (NRE) and
faster time to market versus standard cell
ASICs.

Acceleration Platform or Card Solutions

Intel FPGA-based acceleration platforms or cards enable a scalable volume deployment of various workloads in edge, network,
cloud, enterprise, and other types of data center environment through Intel FPGA Programmable Acceleration Cards (Intel FPGA
PACs) and development software, such as the Altera Acceleration Stack for Intel Xeon® CPU with FPGAs and the OpenVINOTM
toolkit.

Productivity-Enhancing Design Software, Embedded

Processing, IP, Development Kits, and Training
With Intel, you get a complete design environment and a
wide choice of design tools—all built to work together so your
designs are up and running fast. You can try one of our training
classes to get a jump-start on your designs. Choose Intel and
see how we enhance your productivity and make a difference
to your bottom line.

Altera Product Catalog 1

 Devices: Agilex FPGA Portfolio

Agilex™ FPGAs and SoCs:

A Comprehensive Programmable Logic Portfolio for the
Connected World intel.com/agilex

The Agilex FPGA portfolio presents a broad range of product offerings that address the full
breadth of programmable logic needs across every technology sector from edge and embedded,
to communications and data centers. In all these sectors, a data explosion is driving demand for
new products to move, process, and store data, as well as derive actionable insights from it. The
developers of these products need hardware flexibility to address the challenges of changing market
requirements, integrating multiple functions, adopting evolving standards, and supporting diverse
workloads. Agilex FPGAs provide the flexibility needed to tackle these challenges, as well as advanced
application-optimized features and capabilities that help developers deliver innovation with agility.

The Agilex FPGA Portfolio

Pushing beyond the limits of mainstream programmable logic—these FPGAs

Higher Performance provide unprecedented capabilities and optimization for their target applications
Increasing Logic Capacity
More Features / Capabilities
Greater I/O Bandwidth Highest performance FPGAs delivering industry-leading fabric and I/O speeds,
ideal for the most bandwidth- and compute-intensive applications

Midrange FPGAs optimized for applications requiring high performance, lower

power, and smaller form factors
More Cost Optimizations
Smaller Form Factors
Less Logic Capacity
Power- and cost-optimized FPGAs in compact form factors—essential
Lower Power
building blocks targeted for a wide range of applications across many markets

Altera Product Catalog 2

 Devices: Agilex FPGA Portfolio

Agilex™ 7 FPGA and SoC Overview

Agilex 7 Devices
The Agilex 7 devices include the industry’s highest performance FPGAs providing a range of premium
features for the most demanding applications, including the F-Series, I-Series, and M-Series. This tier
offers the industry’s highest data rate transceivers—up to 116 Gbps—the first PCI Express* (PCIe*) 5.0
and Compute Express Link (CXL) support, and options to integrate in-package HBM2E memory delivering
the industry’s highest memory bandwidth (over 1 TBps). These capabilities enable customized connectivity
and acceleration for the most compute, bandwidth, and memory-intensive use cases in communications,
data center, defense, high-performance computing, video, high-end test/measurement/medical, and
more.

F-Series FPGAs and SoCs I-Series FPGAs and SoCs M-Series FPGAs and SoCs
F-Series devices are general purpose I-Series devices offer the highest- M-Series devices are optimized for
FPGAs built on the Intel 10 nm SuperFin performance I/O interfaces to address compute- and memory-intensive
process technology. With features including bandwidth-intensive applications. applications. Leveraging the Intel 7 process
transceiver rates up to 58 Gbps, advanced Manufactured on the Intel 10 nm SuperFin technology, this series builds upon I-Series
digital signal processing (DSP) blocks process technology, this series builds device features offering an extensive
supporting multiple precisions of fixed-point upon the F-Series device features offering memory hierarchy including integrated
and floating-point operations, and high- transceiver rates up to 116 Gbps, PCIe 5.0 high-bandwidth memory (HBM) and high-
performance crypto blocks, they are ideal support, and cache- and memory-coherent efficiency interfaces to DDR5 memory with
for a wide range of applications across many attach to processors with CXL. a hard memory Network-on-Chip (NoC) to
markets. maximize memory bandwidth.

Efficient Network Transformation

Datapath Acceleration
VNF Performance Optimization
• Load balancing
• Data integrity
2x200 GbE • Network translation
Significant Improvements
• Throughput
• Jitter
• Latency
Infrastructure Offload
PCIe 4.0/5.0 Optimized Architecture
• Infrastructure Processing Unit (IPU)
• vRouter
• Security
Small Form Factor and Low Power
• Wide range of servers

Altera Product Catalog 3

 Devices: Agilex FPGA Portfolio

Converged Workload Acceleration for the Data Center

Infrastructure Acceleration
• Network
• Security
• Remote memory access
Memory Application Acceleration
Coherent
• Artificial intelligence (AI)
(CXL)
• Search
• Video transcode
• Database
• 38 TFLOPs of DSP performance1
Coherent
DDR5 Memory Pool Memory Storage Acceleration
• Compression
• Decompression
• Encryption
• Memory hierarchy management

Agility and Flexibility for All Stages of 5G Implementation

Custom Logic Continuum
Antenna Radio FPGA Flexibility
Data Converter • High flexibility
DFE
Beamforming • Short time to market
Fronthaul
Rapid eASIC Device Optimization
• Power and cost optimization
Full Custom ASIC Optimization
Core • Best power1
Baseband
Network • Best performance1
FEC (Turbo/LDPC) • Best cost1
uRLLC
Fronthaul Application-Specific Tile Options
• Data converter
• Vector engine
• Custom compute

Smart, Safe, and Secure Factory Acceleration

Acceleration and Analytics
• In-line protocol acceleration
• Look-aside application acceleration
PCIe 4.0/5.0
CXL Safety and Security
• Secure boot
• Encryption
• Authentication
Customized Connectivity
• Time-sensitive networks
• Flexible I/O

10011100101
001010100010
0110100010110

Cameras, Sensors, Industrial PC / Cloud

Actuators Gateway Node

Product and Performance Information:

1
This comparison is based on the Agilex FPGA and SoC family vs. Stratix 10 FPGA using simulation results and is subject to change. This document contains information on products, services
and/or processes in development. All information provided here is subject to change without notice. Contact your Altera representative to obtain the latest forecast, schedule, specifications, and
roadmaps.

Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at www.intel.com, or from the OEM or
retailer. No computer system can be absolutely secure. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors.
Altera Product Catalog 4
Devices: Agilex FPGA Portfolio Devices: Agilex FPGA Portfolio

Agilex™ 7 FPGA and SoC F-Series Features View device ordering codes on page 53.

Product Line AGF 006 AGF 008 AGF 012 AGF 014 AGF 019 AGF 023 AGF 022 AGF 027
Specification Options² A, B A, B A, B A, B A, B, C, D A, B, C, D A, B A, B
Logic elements (LEs) 573,480 764,640 1,178,525 1,437,240 1,918,975 2,308,080 2,208,075 2,692,760
Adaptive logic modules (ALMs) 194,400 259,200 399,500 487,200 650,500 782,400 748,500 912,800
ALM registers 777,600 1,036,800 1,598,000 1,948,800 2,602,000 3,129,600 2,994,000 3,651,200
High-performance crypto blocks 0 0 0 0 2 2 0 0
eSRAM memory blocks 0 0 2 2 1 1 0 0
eSRAM memory size (Mb) 0 0 36 36 18 18 0 0
M20K memory blocks 2,844 3,792 5,900 7,110 8,500 10,464 10,900 13,272
Resources

M20K memory size (Mb) 56 74 115 139 166 204 212 259
MLAB memory count 9,720 12,960 19,975 24,360 32,525 39,120 37,425 45,640
MLAB memory size (Mb) 6 8 12 15 20 24 23 28
Fabric PLL 6 6 8 8 5 5 12 12
I/O PLL 12 12 16 16 10 10 16 16
Variable-precision digital signal processing (DSP) blocks 1,640 2,296 3,743 4,510 1,354 1,640 6,250 8,528
18 x 19 multipliers 3,280 4,592 7,486 9,020 2,708 3,280 12,500 17,056
Single-precison or half-precision tera floating point
2.5 / 5.0 3.5 / 6.9 6.0 / 12.0 6.8 / 13.6 2.0 / 4.0 2.5 / 5.0 9.4 / 18.8 12.8 / 25.6
operations per second (TFLOPS)
Maximum EMIF x72 3
4 4 4 4 3 3 4 4
Maximum differential (RX or TX) pairs 192 288 384 384 240 240 384 384
Available Device

Maximum AIB interfaces 2 2 2 2 4 4 4 4

Resources
Maximum

Memory devices supported DDR4 and QDR IV

Secure device manager (SDM) AES-256/SHA-256 bitstream encryption/authentication, physically unclonebale function (PUF), ECDSA 256/384 boot code autentication, side channel attack protection
Quad-core 64 bit Arm Cortex*-A53 up to 1.41 GHz with 32 KB I/D cache, Neon* coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard memory controllers, USB 2.0x2, 1G EMAC x3, UART x2, serial
Hard processor system (HPS)
peripheral interface (SPI) x4, I2C x5, general purpose timers x7, watchdog timer x4
PCI Express* (PCIe*) hard IP block (Gen4 x16 ) or Bifurcateable 2x PCIe Gen4 x8 (EP) or 4x Gen4 x4 (RP)
Transceiver channel count : 16 channels at 32 Gbps (NRZ) /12 channels at 58 Gbps (PAM4) - RS & KP FEC
Advanced networking support:
- Bifurcatable 400 GbE hard IP block (10/25/50/100/200/400 GbE FEC/PCS/MAC)
F-Tile
- Bifurcatable 200 GbE hard IP block (10/25/50/100/200 Gbps FEC/PCS)
300G Interlaken
Tile Resources

IEEE 1588 v2 support

PMA direct
Transceiver channel count : Up to 24 channels at 28.9 Gbps (NRZ) / 12 channels at 57.8 Gbps (PAM4) - RS & KP FEC1
Networking support :
E-Tile - 400GbE (4 x 100GbE hard IP blocks (10/25 GbE FEC/PCS/MAC))
IEEE 1588 v2 support
PMA direct
PCIe hard IP block (4.0 x16) or Bifurcateable 2x PCIe 4.0 x8 (EP) or 4x 4.0 x4 (RP)
SR-IOV 8PF / 2kVF
P-Tile
VirtIO support
Scalable IOV
F- Tile - Package Options and I/O Pins Tile Configuration GPIO (LVDS) / HPS IO / F-Tile 32G NRZ (58G PAM4)
1546A 384(192)/48/32(24) 384(192)/48/32(24)
F-Tile x2
(37.5 mm x 34 mm, 0.92 mm Hex)
2340A 576(288)/48/32(24) 576(288)/48/32(24) 744(372)/48/32(24) 744(372)/48/32(24) 480(240)/48/32(24) 480(240)/48/32(24) 744(372)/48/32(24) 744(372)/48/32(24)
F-Tile x2
(45 mm x 42 mm, 0.92 mm Hex)
2340A 576(288)/48/16(12) 576(288)/48/16(12) 744(372)/48/16(12) 744(372)/48/16(12)
F-Tile x1
(45 mm x 42 mm, 0.92 mm Hex)
3184C 480(240)/48/64(48) 480(240)/48/64(48) 720(360)/48/64(48) 720(360)/48/64(48)
F-Tile x4
(56 mm x 45 mm, 0.92 mm Hex)

E-Tile and P-Tile - Package Options and I/O Pins GPIO (LVDS) / HPS IO / E-Tile 28.9G NRZ (57.8G PAM4) / P-Tile 16G PCIe

2486A 768(384)/48/16(8)/16 768(384)/48/16(8)/16

E-Tile x1 & P-Tile x1
(55 mm x 42.5 mm, 1.0 mm Hex)

2581A 480(240)/48/24(12)/32 480(240)/48/24(12)/32 624(312)/48/24(12)/32 624(312)/48/24(12)/32

E-Tile x1 & P-Tile x2
(52.5 mm x 40.5 mm, 0.92/0.94 mm Hex)4

Notes:
1. Only 4 instances of KP-FEC are supported when using 100GE MAC.
2. Specification code definition: 3. Max EMIF count achieved using AVST x8 mode Compact - Address/Cmd lane [3 lanes] configuration.
4. Conditional migration path from AGF 019/023 to AGF 022/027 devices.
Code HPS Crypto 5. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.
A No No
B Yes No
C No Yes
D Yes Yes

5 Altera Product Catalog Altera Product Catalog 6

Devices: Agilex FPGA Portfolio Devices: Agilex FPGA Portfolio

Agilex™ 7 FPGA and SoC I-Series Features View device ordering codes on page 53.

Product Line AGI 019 AGI 023 AGI 022 AGI 027 AGI 035 AGI 040 AGI 041
Specification Options¹ A, B, C, D A, B, C, D A, B A, B A, C A, C A, B, C, D
Logic elements (LEs) 1,918,975 2,308,080 2,208,075 2,692,760 3,540,000 4,047,400 4,000,672
Adaptive logic modules (ALMs) 650,500 782,400 748,500 912,800 1,200,000 1,372,000 1,356,160
ALM registers 2,602,000 3,129,600 2,994,000 3,651,200 4,800,000 5,488,000 5,424,640
High-performance crypto blocks 2 2 0 0 4 4 4
eSRAM memory blocks 1 1 0 0 3 3 2
eSRAM memory size (Mb) 18 18 0 0 54 54 36
Resources

M20K memory blocks 8,500 10,464 10,900 13,272 14,931 19,908 17,136
M20K memory size (Mb) 166 204 212 259 292 389 335
MLAB memory count 32,525 39,120 37,425 45,640 60,000 68,600 67,808
MLAB memory size (Mb) 20 24 23 28 37 42 42
Fabric PLL 5 5 12 12 6 6 8
I/O PLL 10 10 16 16 12 12 16
Variable-precision digital signal processing (DSP) blocks 1,354 1,640 6,250 8,528 9,594 12,792 0
18 x 19 multipliers 2,708 3,280 12,500 17,056 19,188 25,584 0
Single-precison or half-precision tera floating point operations
2.4 / 4.9 2.4 / 4.9 9.4 / 18.8 12.8 / 25.6 14.3 / 28.7 19.1 / 38.3 0
per second (TFLOPS)
Maximum EMIF x722 3 3 4 4 4 4 4
Maximum Available
Device Resources

Maximum differential (RX or TX) pairs 240 240 360 360 288 288 372
Maximum AIB Interfaces 4 4 4 4 6 6 4
Memory devices supported DDR4 and QDR IV
Secure device manager (SDM) AES-256/SHA-256 bitstream encryption/authentication, physically unclonebale function (PUF), ECDSA 256/384 boot code autentication, side channel attack protection
Quad-core 64 bit Arm Cortex*-A53 up to 1.41 GHz with 32 KB I/D cache , Neon* coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory
Hard processor system (HPS) management unit, cache coherency unit, hard memory controllers, USB 2.0x2, 1G EMAC x3, UART x2, serial peripheral interface (SPI) x4, I2C x5, general n/a HPS support3
purpose timers x7, watchdog timer x4
PCI Express* (PCIe*) hard IP block (4.0 x16 ) or Bifurcateable 2x PCIe 4.0 x8 (EP) or 4x 4.0 x4 (RP)
Transceiver channel count :
- 4 channels at 116 Gbps (PAM4) / 58 Gbps (NRZ)
- 16 channels at 32 Gbps (NRZ) /12 channels at 58 Gbps (PAM4) - RS & KP FEC
Advanced networking support:
F-Tile
- Bifurcatable 400 GbE hard IP block (10/25/50/100/200/400 GbE FEC/PCS/MAC)
Tile Resources

- Bifurcatable 200 Gb hard IP block (10/25/50/100/200 Gbs FEC/PCS)

300G Interlaken
IEEE 1588 support
PMA direct
Compute Express Interface (CXL) - Link width x16 lanes, x8 lanes
PCIe hard IP block (5.0 x16) or Bifurcateable 2x PCIe 5.0 x8 (EP) or 4x 5.0 x4 (RP)
Virtualization (SR-IOV) supporting 8 PFs/2k VFs
R-Tile Scalable IOV
VirtIO support
Precise time management
PIPE direct
F-Tile - Package Options and I/O Pins Tile Configuration GPIO (LVDS) / HPS IO / F-Tile 32G NRZ(58G PAM4) / High-Speed Transceiver 58G NRZ (116G PAM4) Channels

3184B 480(240)/48/64(48)/8(8) 480(240)/48/64(48)/8(8) 720(360)/48/64(48)/8(8) 720(360)/48/64(48)/8(8) 732(366)/48/64(48)/8(8)

F-Tile x4
(56 mm x 45 mm, 0.92 mm Hex)

3948A 576(288)/0/96(72)/24(24) 576(288/0/96(72)/24(24)

F-Tile x6
(56mm x 56mm, 0.92 mm Hex)

F-Tile and R-Tile - Package Options and I/O

Tile Configuration GPIO (LVDS) / HPS IO / F-Tile 32G NRZ(58G PAM4) / High-Speed Transceiver 58G NRZ( 116G PAM4) Channels / R- Tile 32G PCIe (CXL) Lanes
Pins

1805A 480(240)/48/16(12)/0(0)/16(16) 480(240)/48/16(12)/0(0)/16(16)

F-Tile x1 & R-Tile x 1
(42.5mm x 42.5mm, 1.025 mm Hex)

2957A4 720(360)/48/16(12)/4(4)/48(32) 720(360)/48/16(12)/4(4)/48(32) 720(360)/48/16(12)/4(4)/48(32)

F-Tile x1 & R-Tile x 3
(56 mm x 45 mm, 1.0 / 0.92 mm Hex)

3184A 720(360)/48/48(36)/8(8)/16(16) 720(360)/48/48(36)/8(8)/16(16)

F Tile x3 & R-Tile x1
(56 mm x 45 mm, 0.92 mm Hex)

3184E 744(372)/48/32(24)/8(8)/32(32)
F Tile x2 & R-Tile x2
(56 mm x 45 mm, 0.92 mm Hex)

Notes:
1. Specification code definition:
2. Max EMIF count achieved using AVST x8 mode Compact - Address/Cmd lane [3 lanes] configuration
Code HPS Crypto 3. Same HPS as AGI 027/022/023/019
A No No 4. Conditional pin migration from AGI 022/027 to AGI 041 device.
5. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.
B Yes No
C No Yes
D Yes Yes

7 Altera Product Catalog Altera Product Catalog 8

Devices: Agilex FPGA Portfolio Devices: Agilex FPGA Portfolio

Agilex™ 7 FPGA and SoC M-Series Features View device ordering codes on page 53.

Product Line AGM 032 AGM 039

Specification Options¹ A, B, E, F, G, H A, B, E, F, G, H
Logic elements (LEs) 3,245,000 3,851,520
Adaptive logic modules (ALMs) 1,100,000 1,305,600
ALM registers 4,400,000 5,222,400
M20K memory blocks 15,932 18,960
M20K memory size (Mb) 311 370
Resources

MLAB memory count 55,000 65,280

MLAB memory size (Mb) 33 40
HBM2E High Bandwidth DRAM Memory (Gbytes) Size 16 / 32 16 / 32
Fabric PLL 8 8
I/O PLL 16 16
Variable-precision digital signal processing (DSP) blocks 9,375 12,300
18 x 19 multipliers 18,750 24,600
Single-precison or half-precision tera floating point operations per second (TFLOPS) 14 / 28 18.4 / 37
Maximum EMIF x72 4
Available Device

Memory devices supported DDR5, LPDDR5, and DDR4

Resources
Maximum

Maximum AIB Interfaces 4

Secure device manager (SDM) AES-256/SHA-256 bitstream encryption/authentication, physically unclonebale function (PUF), ECDSA 256/384 boot code autentication, side channel attack protection
Quad-core 64 bit Arm Cortex*-A53 up to 1.41GHz with 32KB I/D cache, Neon* coprocessor, 1 MB L2 Cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard memory controllers,
Hard processor system (HPS)
USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general prupose timers x7, watchdog timer x4
PCI Express* (PCIe*) hard IP block (4.0 x16 ) or bifurcateable 2x PCIe 4.0 x8 (EP) or 4x 4.0 x4 (RP)
Transciever channel count :
- 4 channels at 116 Gbps (PAM4) / 58 Gbps (NRZ)
- 16 channels at 32 Gbps (NRZ) /12 channels at 58 Gbps (PAM4) - RS & KP FEC
Advanced networking support:
F-Tile
- Bifurcatable 400 GbE hard IP block (10/25/50/100/200/400 GbE FEC/PCS/MAC)
Tile Resources

- Bifurcatable 200 Gb hard IP block (10/25/50/100/200 Gbs FEC/PCS)

300G Interlaken
IEEE 1588 support
PMA direct
Compute Express Interface (CXL) - Link width x16 lanes, x8 lanes
PCIe hard IP block (5.0 x16 ) or Bifurcateable 2x PCIe 5.0 x8 (EP) or 4x 5.0 x4 (RP)
Virtualization (SR-IOV) supporting 8 PFs/2k VFs
R-Tile Scalable IOV
VirtIO Support
Precise Time Management
PIPE Direct

Package Options (Non-HBM Packages) Tile Configuration GPIO(LVDS) / F-Tile 32G NRZ (58G PAM4) / High-Speed Transceiver 58G NRZ (116G PAM4) / R- Tile 32G PCIe (CXL) Lanes

4700A (56mm x 66mm, 0.92mm Hex) F-Tile x3, R-Tile x1 768(384) / 48(36) / 8(8) / 16(16) 768(384) / 48(36) / 8(8) / 16(16)

3184B (56 mm x 45 mm, 0.92 mm Hex) F-Tile x4 720(360) / 64(48) / 8(8) 720(360) / 64(48) / 8(8)

Package Options (HBM Packages) Tile Configuration GPIO(LVDS) / F-Tile 32G NRZ (58G PAM4) / High-Speed Transceiver 58G NRZ (116G PAM4) / R- Tile 32G PCIe (CXL) Lanes

4700A (56mm x 66mm, 0.92mm Hex) F-Tile x3, R-Tile x1, HBM 768(384) / 48(36) / 8(8) / 16(16) 768(384) / 48(36) / 8(8) / 16(16)

4700B (56mm x 66mm, 0.92mm Hex) F-Tile x4, HBM 768(384) / 64(48) / 8(8) 768(384) / 64(48) / 8(8)

Notes:
1. Specification code definition:
Code HPS Crypto HBM2e Density
A No No None
B Yes No None
C No Yes None
D Yes Yes None
E Yes No 16 GB
F Yes No 32 GB
G No No 16 GB
H No No 32 GB

2. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

9 Altera Product Catalog Altera Product Catalog 10

 Devices: Agilex FPGA Portfolio

Agilex™ 5 FPGA and SoC Overview

Agilex 5 Devices
Agilex 5 devices serve a broad range of applications that require high performance, lower power, and
smaller form factors. This tier consists of the performance-optimized D-Series FPGAs and the power-
optimized E-Series FPGAs. Agilex 5 devices also feature the industry’s first Enhanced DSP with AI Tensor
Block, which deliver high-efficiency AI and digital signal processing (DSP) functionality, and the FPGA
industry’s first asymmetric applications processor system consisting of dual Arm Cortex-A76 cores and
dual Cortex-A55 cores, which enable you to optimize the performance and power efficiency of their
workloads. These characteristics make them ideal for midrange FPGA applications across the edge and
core including wireless and wireline communications, video and broadcast equipment, industrial
applications, test and measurement products, medical electronics, and defense applications.

E-Series FPGAs and SoCs D-Series FPGAs and SoCs

E-Series FPGAs and SoCs are optimized for power and size— with D-Series FPGAs and SoCs are optimized for performance and
50% lower power while delivering up to 2.5X better performance power efficiency— with 42% lower power while delivering up to 1.5X
as compared to Cyclone® V devices, also with features including better performance as compared to Stratix 10 FPGAs, also with
transceiver rates up to 24x28 Gbps, PCIe 4.0x4, 6x25GbE, 3,600 features including transceiver rates up to 32x28 Gbps, PCIe 4.0x8,
Mbps DDR5, dual-core Arm Cortex-A76 and dual-core Cortex-A5 16x25GbE, 4,000 Mbps DDR5, dual-core Cortex-A76 and dual-core
processors make it ideal for intelligent applications at the edge, Cortex-A55 processors make it deal for various applications across
embedded, and more. multiple markets.

Image Sensor Processing

Inline image processing

• Pixel defect correction
• Vignette correction
Cameras • Adaptive noise reduction
Display
Customized Connectivity
• High-definition multimedia interface (HDMI)
• MIPI D-PHY
Image Sensors
Hard Processor System
Cloud • Flexible embedded software stack
• Graphical user interface

Altera Product Catalog 11

 Devices: Agilex FPGA Portfolio

Autonomous Mobile Robots

Flexible I/O
• MIPI
• HDMI
MIPI
• Time-Sensitive Networking (TSN)
• LVDS
HDMI FPGA Acceleration
Display • Sensor fusion
Custom • Point of cloud processing
Sensor I/O
Hard Processor System
TSN
• RTOS
Endpoint • Hypervisor functions
• Network features
• User application

Clinical System

Power Optimized
• Low-density option
• Battery-powered clinical equipment
Display
Analog FPGA Acceleration
Front-end
• Custom image progressing
• AR/VR innovations
• Deterministic low latency
Hard Processor System
Digital Ethernet / • Real-time waveform analysis
Front-end Backplane • Graphic controls for Human-Machine Interaction (HMI)

Altera Product Catalog 12

Devices: Agilex FPGA Portfolio Devices: Agilex FPGA Portfolio

Agilex™ 5 FPGA and SoC E-Series Features View device ordering codes on page 53.

Device Group A FPGAs

Product Line
A5E 013A A5E 028A A5E 043A A5E 052A A5E 065A
Specification Options¹ C, D C, D C, D C, D C, D
Logic elements (LEs) 138,060 282,256 434,240 523,920 656,080
Adaptive logic modules (ALMs) 46,800 95,680 147,200 177,600 222,400
ALM registers 187,200 382,720 588,800 710,400 889,600
M20K memory blocks 358 716 1,050 1,288 1,611
M20K memory size (Mb) 6.99 13.98 20.51 25.16 31.46
Resources

MLAB memory count 2,340 4,784 6,720 8,440 11,120

MLAB memory size (Mb) 1.43 2.92 4.10 5.15 6.79
I/O PLL 4 4 8 8 8
Fabric-feeding I/O PLL 2
8 10 13 13 13
Variable-precision digital signal processing (DSP) blocks 188 376 564 676 846
18 x 19 multipliers 376 752 1,128 1,352 1,692
Peak INT8 (TOPS) 5.78 11.55 17.33 20.78 25.99
LVDS pairs at 1.6 Gbps 96 96 192 192 192
DDR4/5 and LPDDR4/5 interfaces (x32) 2 2 4 4 4
Maximum Available Device Resources

MIPI D-PHY interface 14 14 28 28 28

Differential (RX or TX) pairs at 28 Gbps 4 12 16 24 24
PCIe 4.0 x4 instance 1 3 4 6 6
High-speed I/O (HSIO) 192 192 384 384 384
High-voltage I/O (HVIO) 200 200 120 120 120
Provides SHA-384 bitstream integrity, ECDSA 256/384 bitstream authentication, AES-256 bitstream encryption, physically unclonable function (PUF) protected key storage, side-channel attack resistance, SPDM attestation,
Secure device manager (SDM)
cryptographic services, physical anti-tamper support

Multi-core with 32-bit/64-bit dual-core Arm Cortex*-A55 up to 1.5 GHz with 32 KB I/D cache and 128 KB L2 cache, and dual-core Arm Cortex-A76 up to 1.8 GHz with 64 KB I/D cache and 256 KB L2 cache, and up to 2 MB L3 shared
Hard processor system (HPS)
cache, multi-channels direct memory access (DMA), 512 KB on-chip RAM, USB 3.1 x1, USB 2.0 OTG x2, TSN MAC x3, UART x2, SPI M x2, SPI S x2, I3C x2, I2C x5, NAND x1, SDMMC x1, Osc timer x2, SP timer x2, watchdog x5, GPIO x2.

PCI Express* (PCIe*) hard IP up to PCIe 4.0 x4 EP and RP

Transceiver Transceiver channel count: up to 24 channels at 28 Gbps (NRZ)
Ethernet IP: up to 6 x10/25 GbE hard IP (MAC, PCS, and FEC)

Package Options3 and I/O Pins

Package code ( Package size, ball pitch)​ HVIO/ HSIO6/HPSIO/Transceivers

120/96/48/4​ 120/96/48/12​ 120/96/48/12 120/96/48/12 120/96/48/12

B23A (23 mm x 23 mm, Variable4, 5)

200/192/48/4​ 200/192/48/12​ 120/384/48/16​ 120/384/48/24​ 120/384/48/24​

B32A (32 mm x 32 mm, Variable4, 5)

Notes:
1. Specification code definition:
Quad HPS: 2xA55 and 2xA76
Code HPS Transceiver Crypto
C No Yes No
D Quad HPS Yes Yes

2. The fabric-feeding IOPLL count inclusive of system PLL at transceiver bank, the System PLL can be repurposed for core fabric usage if not used for transceiver.
3. For more information about the device migration path, please refer to Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series.
4. VPBGA packaging is compatible with Type III PCBs, that use design rules equivalent to 0.8mm ball pitch packages and standard plated through hole (PTH) vias.
5. The ball pitch is variable, ranging from 0.65mm – 1.45mm in single package to ease signal routing. For more details about Variable Pitch BGA (VPBGA) technology, please refer to PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs.
6. The number of LVDS pairs is half of the HSIO count.
7. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

13 Altera Product Catalog Altera Product Catalog 14

Devices: Agilex FPGA Portfolio Devices: Agilex FPGA Portfolio

Device Group B FPGAs

Product Line
A5E 005B A5E 007B A5E 008B A5E 013B A5E 028B A5E 043B A5E 052B A5E 065B
Specification Options¹ A, G A, G A, B, C, D, E A, B, C, D, E A, B, C, D, E C, D C, D C, D
Logic elements (LEs) 50,445 69,030 85,196 138,060 282,256 434,240 523,920 656,080
Adaptive logic modules (ALMs) 17,100 23,400 28,880 46,800 95,680 147,200 177,600 222,400
ALM registers 68,400 93,600 115,520 187,200 382,720 588,800 710,400 889,600
M20K memory blocks 130 179 229 358 716 1,050 1,288 1,611
M20K memory size (Mb) 2.54 3.50 4.47 6.99 13.98 20.51 25.16 31.46
Resources

MLAB memory count 850 1,170 1,780 2,340 4,784 6,720 8,440 11,120
MLAB memory size (Mb) 0.52 0.71 1.09 1.43 2.92 4.10 5.13 6.79
I/O PLL 2 2 4 4 4 8 8 8
Fabric-feeding I/O PLL 2
5 5 8 8 10 13 13 13

Variable-precision digital signal processing (DSP) blocks 65 94 116 188 376 564 676 846

18 x 19 multipliers 130 188 232 376 752 1,128 1,352 1,692

Peak INT8 (TOPS) 1.7 2.46 3.05 4.93 9.85 14.78 17.72 22.17
LVDS pairs at 1,250 Mbps 48 48 96 96 96 192 192 192
DDR4 and LPDDR4/5 interfaces (x32) 1 1 2 2 2 4 4 4
Maximum Available Device Resources

MIPI D-PHY interface 7 7 14 14 14 28 28 28

Differential (RX or TX) pairs at 17 Gbps 0 0 4 4 12 16 24 24
PCIe 4.0 x4 instance 0 0 1 1 3 4 6 6
High-speed I/O (HSIO) 96 96 192 192 192 384 384 384
High-voltage I/O (HVIO) 160 160 200 200 200 120 120 120
Provides SHA-384 bitstream integrity, ECDSA 256/384 bitstream authentication, AES-256 bitstream encryption, physically unclonable function (PUF) protected key storage, side-channel attack resistance, SPDM attestation,
Secure device manager (SDM)
cryptographic services, physical anti-tamper support
Multi-core with 32-bit/64-bit dual-core Arm Cortex-A55 up to 1.25 GHz with 32 KB I/D cache and 128 KB L2 cache, and dual-core Arm Cortex-A76 up to 1.4 GHz with 64 KB I/D
Hard processor system (HPS) NA cache and 256 KB L2 cache, and up to 2 MB L3 shared cache, multi-channels direct memory access (DMA), 512 KB on-chip RAM, USB 3.1 x1, USB 2.0 OTG x2, TSN MAC x3,
UART x2, SPI M x2, SPI S x2, I3C x2, I2C x5, NAND x1, SDMMC x1, Osc timer x2, SP timer x2, watchdog x5, GPIO x2.
PCIe hard IP up to PCIe 4.0 x4 EP and RP
Transceiver NA Transceiver channel count: up to 24 channels at 17 Gbps (NRZ)
Ethernet IP: up to 6 x10 GbE hard IP (MAC, PCS, and FEC)

Package Options3 and I/O Pins

Package code ( Package size, ball pitch)​ HVIO/ HSIO7/HPSIO/Transceivers

B15A (15 mm x 15 mm, Variable4, 5) 80/72​/0/0 80/72/0/0​

M16A (16 mm x 16 mm, 0.5 mm6) 40/192/48/4​ 40/192/48/4​ 40/192/48/ 8

160/48/0/0 160/48/0/0
B18A (18mm x 18mm, Variable4, 5)

B23B (23 mm x 23 mm, Variable4, 5) 159/96/0/0​ 159/96/0/0​ 159/192​/48/0 159/192​/48/0 159/192​/48/0

120/96/48/4​ 120/96/48/4​ 120/96/48/12​ 120/96/48/12​ 120/96/48/12​ 120/96/48/12​

B23A (23 mm x 23 mm, Variable4, 5)

200/192/48/4​ 200/192/48/4​ 200/192/48/12​ 120/384/48/16​ 120/384/48/24​ 120/384/48/24​

B32A (32 mm x 32 mm, Variable4, 5)

Notes:
1. Specification code definition: 3. For more information about the device migration path, please refer to Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series.
Quad HPS: 2xA55 and 2xA76 4. VPBGA packaging is compatible with Type III PCBs, that use design rules equivalent to 0.8mm ball pitch packages and standard plated through hole (PTH) vias.
Code HPS Transceiver Crypto
Dual HPS: 2xA55 5. The ball pitch is variable, ranging from 0.65mm – 1.45mm in single package to ease signal routing. For more details about Variable Pitch BGA (VPBGA) technology, please refer to PCB Design
A No No No §
Enabled for B18A package only Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs.
B Quad HPS No Yes 6. 0.5mm Micro Fineline BGA (MBGA).
C No Yes No 7. The number of LVDS pairs is half of the HSIO count.
D Quad HPS Yes Yes 8. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.
E Dual HPS No Yes
G No No Yes§

2. The fabric-feeding IOPLL count inclusive of system PLL at transceiver bank, the System PLL can be repurposed for core fabric usage if not used for transceiver.

15 Altera Product Catalog Altera Product Catalog 16

Devices: Agilex FPGA Portfolio Devices: Agilex FPGA Portfolio

Agilex™ 5 FPGA and SoC D-Series Features View device ordering codes on page 53.

Product Line A5D 010 A5D 025 A5D 031 A5D 051 A5D 064
Specification Options¹ C, D C, D C, D C, D C, D
Logic elements (LEs) 103,250 254,054 318,600 515,070 644,280
Adaptive logic modules (ALMs) 35,000 86,120 108,000 174,600 218,400
ALM registers 140,000 344,480 432,000 698,400 873,600
M20K memory blocks 534 1,281 1602, 2,563 3,204
M20K memory size (Mb) 10.43 25.02 31.29 50.06 62.58
Resources

MLAB memory count 1780 3420 5,400 8,440 10,920

MLAB memory size (Mb) 1.09 2.09 3.30 5.15 6.67
I/O PLL 8 8 8 8 8
Fabric-feeding I/O PLL1 11 11 11 15 15
Variable-precision digital signal processing (DSP)
276 736 920 1,472 1,840
blocks
18 x 19 multipliers 552 1,472 1,840 2,944 3,680
Peak INT8 (TOPS) 8.48 22.61 28.26 45.22 56.22
LVDS pairs at 1.6 Gbps 192 192 192 192 192
DDR4 interface (x64) 2 2 2 2 2
DDR4/5 and LPDDR4/5 interfaces (x32) 4 4 4 4 4
Maximum Available Device Resources

MIPI D-PHY interface 28 28 28 28 28

Differential (RX or TX) pairs at 28 Gbps 16 16 16 24 32
PCIe 4.0 x4 instance 4 4 4 6 8
PCIe 4.0 x8 instance 2 2 2 3 4
High-speed I/O (HSIO) 384 384 384 384 384
High-voltage I/O (HVIO) 60 60 60 60 60
Provides SHA-384 bitstream integrity, ECDSA 256/384 bitstream authentication, AES-256 bitstream encryption, physically unclonable function (PUF) protected key storage, side-channel attack resistance, SPDM attestation, cryptographic
Secure device manager (SDM)
services, physical anti-tamper support

Multi-core with 32-bit/64-bit dual-core Arm Cortex*-A55 up to 1.5 GHz with 32 KB I/D cache and 128 KB L2 cache, and dual-core Arm Cortex-A76 up to 1.8 GHz with 64 KB I/D cache and 256 KB L2 cache, and up to 2 MB L3 shared cache,
Hard processor system (HPS)
multi-channels direct memory access (DMA), 512 KB on-chip RAM, USB3.1 x1, USB 2.0 OTG x2, TSN MAC x3, UART x2, SPI M x2, SPI S x2, I3C x2, I2C x5, NAND x1, SDMMC x1, Osc timer x2, SP timer x2, watchdog x5, GPIO x2.

PCI Express* (PCIe*) hard IP up to PCIe 4.0 x8 EP and RP

Transceiver Transceiver channel count: up to 32 channels at 28 Gbps (NRZ)
Ethernet IP: up to 16 x10/25 GbE hard IP (MAC, PCS, and FEC)

Package Options5 and I/O Pins

Package code ( Package size, ball pitch)​ HVIO/ HSIO6/HPSIO/Transceivers

60/192/48/8​ 60/192/48/8​ 60/192/48/8​

B23D (23 mm x 23 mm, Variable3, 4)

60/384/48/16​ 60/384/48/16​ 60/384/48/16​ 60/384/48/24​ 60/384/48/32​

B32B (32 mm x 32 mm, Variable3, 4)​

Notes:
1. Specification code definition:
Quad HPS: 2xA55 and 2xA76
Code HPS Transceiver Crypto
C No Yes No
D Quad HPS Yes Yes

2. The fabric-feeding IOPLL count inclusive of system PLL at transceiver bank, the System PLL can be repurposed for core fabric usage if not used for transceiver.
3. VPBGA packaging is compatible with Type III PCBs, that use design rules equivalent to 0.8mm ball pitch packages and standard plated through hole (PTH) vias.
4. The ball pitch is variable, ranging from 0.65mm – 1.45mm in single package to ease signal routing. For more details about Variable Pitch BGA (VPBGA) technology, please refer to PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs.
5. For more information about the device migration path, please refer to Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs D-Series
6. The number of LVDS pairs is half of the HSIO count.
7. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

17 Altera Product Catalog Altera Product Catalog 18

Devices: Agilex FPGA Portfolio Devices: Agilex FPGA Portfolio

Agilex™ 3 FPGA and SoC C-Series Features View device ordering codes on page 54.

Product Line A3C025 1 A3C050 A3C065 A3C100 A3C135

Specification Options² Y, Z Y, Z Y, Z W, Y, Z W, Y, Z
Logic elements (LEs) 25,075 47,200 65,490 100,300 135,110
Adaptive logic modules (ALMs) 8,500 16,000 22,200 34,000 45,800
ALM registers 34,000 64,000 88,800 136,000 183,200
M20K memory blocks 65 123 169 262 353
Resources

M20K memory size (Mb) 1.27 2.40 3.30 5.12 6.89

MLAB memory count 450 800 1,050 2,000 2,300
MLAB memory size (Mb) 0.27 0.49 0.64 1.22 1.40
I/O PLL 2 2 2 4 4
Fabric-feeding IOPLL 3
5 5 5 8 8
Variable-precision digital signal processing (DSP) blocks 34 65 88 138 184
18 x 19 multipliers 68 130 176 276 368
Peak INT8 (TOPS) 0.47 0.90 1.21 1.90 2.54
LVDS pairs at 1.25 Gbps 48 48 48 96 96
LPDDR4 interfaces (x32) 0 1 1 2 2
MIPI D-PHY interface 0 7 7 14 14
Maximum Available Device Resources

Differential (RX or TX) pairs at 12.5 Gbps 0 0 0 4 4

PCIe* 3.0 x4 instance 0 0 0 1 1
High-speed I/O (HSIO) 96 96 96 192 192
High-voltage I/O (HVIO) 160 160 160 200 200
Provides SHA-384 bitstream integrity, ECDSA 256/384 bitstream authentication, AES-256 bitstream encryption, physically unclonable function (PUF) protected key storage, side-channel attack resistance, SPDM attestation, cryptographic
Secure Device Manager (SDM)
services, and physical anti-tamper support

Multi-core with 32-bit/64-bit dual-core Arm Cortex*-A55 processor up to 800 MHz with 32 KB I/D cache and 128 KB L2 cache, and
Hard processor system NA up to 2 MB L3 cache, multi-channels direct memory access (DMA), 512 KB on-chip RAM, USB 3.1 x1, USB 2.0 OTG x2, TSN MAC x3,
UART x2, SPI M x2, SPI S x2, I3C x2, I2C x5, NAND x1, SDMMC x1, oscillator timer x2, SP timer x2, watchdog x5, and GPIO x2.

PCIe hard IP up to PCIe 3.0 x4 endpoint (EP) and root port (RP)
Transceiver NA Transceiver channel count: up to 4 channels at 12.5 Gbps (NRZ)
Ethernet IP: up to 4 x10 GbE hard IP (MAC, PCS, and FEC)

Package Options4 and I/O Pins

Package Size, Ball Pitch HVIO/HSIO9/HPSIO/Transceiver

M12A (12 mm x 12 mm, 0.5 mm5) 160/72/0/0 160/72/0/0 160/72/0/0

M16A (16 mm x 16 mm, 0.5 mm5) 40/192/48/4 40/192/48/4

B18A5 (18 mm x 18 mm, variable7, 8, 10) 160/48/0/0 160/48/0/0 160/48/0/0 160/48/0/0 160/48/0/0

B18B (18 mm x 18 mm, variable7, 8) 160/96/0/0 160/96/0/0 160/96/0/0

B23C (23 mm x 23 mm, variable7, 8) ​ 200/144/48/4 200/144/48/4

Notes: 3 The fabric-feeding IOPLL count including system PLL at the transceiver bank. The system PLL can be repurposed for core fabric usage if not used for the transceiver.
1. A3C025 does not support EMIF and MIPI. 4. For more information about the device migration path, please refer to Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs.
2. Specification code definition: 5. 0.5mm Micro Fineline BGA (MBGA).
EMIF: External Memory Interface 6. B18A only supports specification Y & Z.
Code HPS Crypto EMIF, MIPI, PUF, SPDM Attestation
MIPI: Mobile Industry Processor Interface 7. VPBGA packaging is compatible with Type III PCBs that use design rules equivalent to 0.8 mm ball pitch packages and standard plated through hole (PTH) vias.
W Yes Yes Yes PUF: Physical Unclonable Function 8. The ball pitch is variable and it helps to ease signal routing. Please contact your local sales representative for more details about Variable Pitch BGA (VPBGA) technology.
Y No No Yes SPDM: Security Protocal and Data Model 9. The number of LVDS pairs is half of the HSIO count.
Z No No No 10. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

19 Altera Product Catalog Altera Product Catalog 20

 Devices: Generation 10 Device Portfolio

Generation 10 FPGAs and SoCs

Altera's Generation 10 FPGAs and SoCs are optimized based on process technology and architecture to deliver the industry’s
highest performance and highest levels of system integration at the lowest power. Generation 10 device families include Stratix 10
FPGAs and SoCs, Arria 10 FPGAs and SoCs, Cyclone 10 FPGAs, and MAX 10 FPGAs.

1 GHz
High-End Performance... ...at Low Power

2X Arria® 10

+15%
gain n
age io
aver nerat 500 MHz
20% ach ge
e
wit
h Arria® 10
-40%

130 nm 90 nm 65 nm 40 nm 28 nm 14 nm

• 2X core performance with revolutionary Hyperflex® FPGA • 15% higher performance than the previous high-end devices†
Architecture †
• 40% lower midrange power†
• Up to 70% power savings †
• 1.5 GHz dual-core Arm Cortex-A9 processor
• Highest density FPGA with up to 10.2 M logic elements (LEs) • IP core support, including 100G Ethernet, 150G/300G
• 64 bit quad-core Arm Cortex-A53 processor system Interlaken, and PCI Express 3.0
• Up to 10 tera floating point operations per second (TFLOPS) • Built on TSMC’s 20 nm process technology
single-precision floating-point throughput
• Built on Intel’s 14 nm Tri-Gate process technology

Cyclone® 10 GX Cyclone® 10 LP
Half the PCB Space 25X the Logic Density
Twice the
Bandwidth
MAX® 10
Traditional
Volatile FPGAs
25X
Half the
Power

MAX® 10

-50%

Cyclone 10 GX
• Single-chip, dual-configuration non-volatile FPGA
• Optimized for high-bandwidth, high-performance
applications • Optimal system component integration for half the PCB
space of traditional volatile FPGAs
• The industry’s first low-cost FPGA with 12.5 Gbps
transceiver I/O support • Broad range of IP including analog-to-digital converters
(ADCs), DSP, and the Nios V embedded soft processor
• High-performance 1,866 Mbps external memory interface
• 1.434 Gbps LVDS I/Os
• The industry’s first low-cost FPGA with IEEE 754 compliant
hard floating-point DSP blocks

Cyclone 10 LP
• Optimized for cost and power-sensitive applications
• Chip-to-chip bridging
• I/O expansion
• Control applications

Altera Product Catalog 21

 Devices: Generation 10 Device Portfolio

Stratix® 10 FPGA and SoC Overview

intel.com/stratix10

Altera FPGAs and SoCs deliver breakthrough advantages in performance, power efficiency, density, and system integration that
are unmatched in the industry. Featuring the revolutionary Hyperflex FPGA Architecture and built on the Intel 14 nm Tri-Gate
process, Stratix 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs with up to 70%
lower power†.

Stratix® 10 Device Family Variants

58G 58G
Dual-Mode 58G PAM-4 29G NRZ Transceivers (XCVR) PAM-4 PAM-4
XCVR XCVR

Quad Quad Quad

Quad Core 64-bit Core Core Core
Arm* Cortex*-A53 HPS up to 1.5 GHz Arm Arm Arm
FPGA A53 A531 A531
Fabric
FPGA FPGA FPGA
Hyperflex FPGA Architecture Fabric Fabric Fabric
Up to 10 TFLOPS DSP
Secure Device Manager
Monolithic Fabric
28G 28G 28G PCIe
28G NRZ Transceivers (GX/SX/TX/MX)
XCVR XCVR XCVR 4.0,
PCIe* 4.0 or UPI (DX)
PCIe PCIe PCIe UPI
3.0 3.0 3.0

Note:
Stratix 10 GX
®
Stratix 10 SX
®
Stratix 10 TX
®
Stratix 10 DX
®

1. Not available in every device.

The figure above shows the core performance benchmarks Stratix 10 FPGA and SoC system integration breakthroughs
achieved by early access customers using the Stratix 10 include:
Hyperflex FPGA architecture. With the 2X performance • Heterogeneous 3D system in package (SiP) integration
increase, customers in multiple end markets can achieve • The highest density FPGA fabric with up to 10.2 million LEs
significant improvements in both throughput and area
• Up to 10 TFLOPS of IEEE 754 compliant single-precision
utilization, with up to 70% lower power†.
floating-point DSP throughput
• Secure Device Manager (SDM) with the most comprehen-
sive security capabilities
• Integrated quad-core 64 bit Arm Cortex-A53 hard processor
system up to 1.5 GHz
• Dual-mode 28.9 Gbps non-return-to-zero (NRZ) and
57.8 Gbps PAM-4 transceivers

Altera Product Catalog 22

 Devices: Generation 10 Device Portfolio

These unprecedented capabilities make Stratix 10 devices uniquely positioned to address the design challenges in
next-generation, high-performance systems in virtually all end markets including wireline and wireless communications,
computing, storage, military, broadcast, medical, and test and measurement.

Communications
• 400G/500G/1T optical transmission
• 200G/400G bridging and aggregation
• 982 MHz remote radio head
• Mobile backhaul
• 5G wireless communications

Computing and Storage

• Data center server acceleration
• High-performance computing (HPC)
• Oil and gas exploration
• Bioscience

Defense
• Next-generation radar
• Secure communications
• Avionics and guidance systems

Broadcast
• High-end broadcast studio
• High-end broadcast distribution
• Headend encoder or EdgeQAM or converged multiservice
access platform (CMAP)

Altera Product Catalog 23

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Stratix® 10 GX FPGA Features View device ordering codes on page 54.

Product Line GX 400 GX 650 GX 850 GX 1100 GX 1650 GX 2100 GX 2500 GX 2800 GX 1660 GX 2110 GX 10M

Logic elements (LEs)1 378,000 612,000 841,000 1,325,000 1,624,000 2,005,000 2,422,000 2,753,000 1,679,000 2,073,000 10,200,000

Adaptive logic modules (ALMs) 128,160 207,360 284,960 449,280 550,540 679,680 821,150 933,120 569,200 702,720 3,466,080

ALM registers 512,640 829,440 1,139,840 1,797,120 2,202,160 2,718,720 3,284,600 3,732,480 2,276,800 2,810,880 13,864,320

Hyper-Registers from Hyperflex FPGA Architecture Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric

Programmable clock trees synthesizable Hundreds of synthesizable clock trees

Resources

M20K memory blocks 1,537 2,489 3,477 5,461 5,851 6,501 9,963 11,721 6,162 6,847 12,950

M20K memory size (Mb) 30 49 68 107 114 127 195 229 120 134 253

MLAB memory size (Mb) 2 3 4 7 8 11 13 15 9 11 55

Variable-precision digital signal processing (DSP) blocks 648 1,152 2,016 2,592 3,145 3,744 5,011 5,760 3,326 3,960 3,456

18 x 19 multipliers 1,296 2,304 4,032 5,184 6,290 7,488 10,022 11,520 6,652 7,920 6,912

Peak fixed-point performance (TMACS)2 2.6 4.6 8.1 10.4 12.6 15.0 20.0 23.0 13.3 15.8 13.8

Peak floating-point performance (TFLOPS)3 1.0 1.8 3.2 4.1 5.0 6.0 8.0 9.2 5.3 6.3 5.5

Secure device manager AES-256/SHA-256 bitstream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side-channel attack protection –

Quad-core 64-bit Arm Cortex-A53 up to 1.5 GHz with 32KB I/D cache, Neon coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, cache
Hard processor system4 – – –
I/O and Architectural Features

coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general purpose timers x7, watchdog timer x4

Maximum user I/O pins 374 392 688 688 704 704 1160 1160 688 688 2,304

Maximum LVDS pairs 1.6 Gbps (RX or TX) 120 192 336 336 336 336 576 576 336 336 11525

Total full duplex transceiver count 24 24 48 48 96 96 96 96 48 48 48

GXT full duplex transceiver count (up to 28.3 Gbps) 16 16 32 32 64 64 64 64 32 32 –

GX full duplex transceiver count (up to 17.4 Gbps) 8 8 16 16 32 32 32 32 16 16 48

PCI Express hard intellectual property (IP) blocks (3.0 x16) 1 1 2 2 4 4 4 4 2 2 46

Memory devices supported DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, and Transceiver Count 7, 8

F1152 pin (35 mm x 35 mm, 1.0 mm pitch) 374,56,120,24 392,8,192,24 – – – – – – – –

688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48

F1760 pin (42.5 mm x 42.5 mm, 1.0 mm pitch) – –

704,32,336,96 704,32,336,96 704,32,336,96 704,32,336,96

F2397 pin (50 mm x 50 mm, 1.0 mm pitch) – – – – – –

1160,8,576,24 1160,8,576,24
F2912 pin (55 mm x 55 mm, 1.0 mm pitch) – – – – – – – –

F4938 pin (70 mm x 74 mm, 1.0 mm pitch) 2304, 32, 1152, 48

Notes:
1. LE counts valid in comparing across Altera FPGAs, and are conservative vs. competing FPGAs.
2. Fixed point performance assumes the use of pre-adder.
3. Floating point performance is IEEE-754 compliant single-precision.
4. Quad-core Arm Cortex-A53 hard processor system only available in Stratix 10 SX SoCs.
5. 1.4 Gbps LVDS maximum rate for GX 10M.
6. PCIe 3.0 x 8 support for GX 10M.
7. A subset of pins for each package are used for high-voltage 3.0 V and 2.5 V interfaces.
8. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

392,8,192,24 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, and transceiver count.

Indicates pin migration path.

24 Altera Product Catalog Altera Product Catalog 25

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Stratix® 10 TX FPGA Features View device ordering codes on page 54.

Product Line TX 400 TX 850 TX 850 TX 1100 TX 1100 TX 1650 TX 2100 TX 2500 TX 2500 TX 2800 TX 2800 Product Line Hard Processor System (HPS)
Logic elements (LEs)1 378,000 841,000 841,000 1,325,000 1,325,000 1,679,000 2,073,000 2,422,000 2,422,000 2,753,000 2,753,000 Quad-core 64 bit Arm Cortex-A53 MPCore
Processor
Adaptive logic modules (ALMs) 128,160 284,960 284,960 449,280 449,280 569,200 702,720 821,150 821,150 933,120 933,120 processor

ALM registers 512,640 1,139,840 1,139,840 1,797,120 1,797,120 2,276,800 2,810,880 3,284,600 3,284,600 3,732,480 3,732,480 Maximum processor
1.5 GHz1
frequency
Hyper-Registers from Hyperflex FPGA
Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric • L1 instruction cache (32 KB)
Architecture
Programmable clock trees synthesizable Hundreds of synthesizable clock trees • L1 data cache (32 KB) with error correction
code (ECC)
eSRAM memory blocks ‒ ‒ ‒ ‒ ‒ 2 2 ‒ ‒ ‒ ‒
• Level 2 cache (1 MB) with ECC
Resources

eSRAM memory size (Mb) ‒ ‒ ‒ ‒ ‒ 94.5 94.5 ‒ ‒ ‒ ‒

• Floating-point unit (FPU) single and double
M20K memory blocks 1,537 3,477 3,477 5,461 5,461 6,162 6,847 9,963 9,963 11,721 11,721 Processor cache and precision
M20K memory size (Mb) 30 68 68 107 107 120 134 195 195 229 229 co-processors • Arm Neon media engine
MLAB memory size (Mb) 2 4 4 7 7 9 11 13 13 15 15 • Arm CoreSight* debug and trace
technology
Variable-precision digital signal processing
648 2,016 2,016 2,592 2,592 3,326 3,960 5,011 5,011 5,760 5,760 • System Memory Management Unit
(DSP) blocks
(SMMU)
18 x 19 multipliers 1,296 4,032 4,032 5,184 5,184 6,652 7,920 10,022 10,022 11,520 11,520
• Cache Coherency Unit (CCU)
Peak fixed-point performance (TMACS)2 2.6 8.1 8.1 10.4 10.4 13.3 15.8 20.0 20.0 23.0 23.0
Scratch pad RAM 256 KB
Peak floating-point performance
1.0 3.2 3.2 4.1 4.1 5.3 6.3 8.0 8.0 9.2 9.2 HPS DDR memory DDR4 and DDR3 (Up to 64 bit with ECC)
(TFLOPS)3
Secure device manager AES-256/SHA-256 bitstream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side-channel attack protection DMA controller 8 channels

Quad-core 64-bit Arm Cortex-A53 up to 1.5 GHz with 32KB I/D cache, Neon coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, 3X 10/100/1000 Ethernet media access
EMAC
cache coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general purpose timers x7, watchdog timer x4 controller (EMAC) with integrated DMA
Hard processor system 4

Yes Yes Yes Yes Yes ‒ ‒ Yes Yes Yes Yes USB On-The-Go
2X USB OTG with integrated DMA
(OTG) controller
Maximum user I/O pins 384 440 440 440 440 440 440 440 296 440 296
UART controller 2X UART 16550 compatible
I/O and Architectural Features

Maximum LVDS pairs 1.6 Gbps (RX or TX) 144 216 216 216 216 216 216 216 144 216 144
Serial peripheral
Total full duplex transceiver count 24 48 72 48 72 96 96 96 144 96 144 interface (SPI) 4X SPI
GXE transceiver count - PAM4 12 PAM-4 12 PAM-4 24 PAM-4 12 PAM-4 24 PAM-4 36 PAM-4 36 PAM-4 36 PAM-4 60 PAM-4 36 PAM-4 60 PAM-4 controller
(up to 57.8 Gbps) or NRZ (up to 28.9 Gbps) 24 NRZ 24 NRZ 48 NRZ 24 NRZ 48 NRZ 72 NRZ 72 NRZ 72 NRZ 120 NRZ 72 NRZ 120 NRZ I2C controller 5X I2C
GXT transceiver count - NRZ Quad SPI flash
0 16 16 16 16 16 16 16 16 16 16 1X SIO, DIO, QIO SPI flash supported
(up to 28.3 Gbps) controller
GX transceiver count - NRZ SD/SDIO/MMC
0 8 8 8 8 8 8 8 8 8 8 1X eMMC 4.5 with DMA and CE-ATA support
(up to 17.4 Gbps) controller
PCI Express hard intellectual property (IP) NAND flash • 1X ONFI 1.0 or later
0 1 1 1 1 1 1 1 1 1 1
blocks (3.0 x16) controller • 8 and 16 bit support
100G Ethernet MAC (no FEC) hard IP
0 1 1 1 1 1 1 1 1 1 1 General-purpose
blocks 4X
timers
100G Ethernet MAC + FEC hard IP blocks 4 4 8 4 8 12 12 12 20 12 20
Software-
Memory devices supported DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys programmable
Maximum 48 GPIOs
general-purpose
Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, E-Tile Transceiver Count and H-Tile Transceiver Count5, 6
I/Os (GPIOs)
F1152 pin (35mm x 35mm, 1.0mm pitch) 384,0,144,24,0 HPS DDR Shared 3X 48 - May be assigned to HPS for HPS
I/Os DDR access
F1760 pin (42.5 mm x 42.5 mm, 1.0 mm pitch) 440,8,216,24,24 ‒ 440,8,216,24,24 ‒ ‒ ‒ ‒ ‒ ‒ ‒
48 I/Os to connect HPS peripherals directly
Direct I/Os
to I/O
F2397 pin (50 mm x 50 mm, 1.0 mm pitch) ‒ ‒ 440,8,216,48,24 ‒ 440,8,216,48,24 440,8,216,72,24 440,8,216,72,24 440,8,216,72,24 ‒ 440,8,216,72,24 ‒
Watchdog timers 4X
F2912 pin (55 mm x 55 mm, 1.0 mm pitch) ‒ ‒ ‒ ‒ ‒ ‒ ‒ ‒ 296,8,144,120,24 ‒ 296,8,144,120,24 Secure device manager, Advanced
Encryption Standard (AES) AES-256/
Notes: SHA-256 bitstream encryption/
Security
1. LE counts valid in comparing across Altera FPGAs, and are conservative vs. competing FPGAs. authentication, PUF, ECDSA 256/384 boot
2. Fixed point performance assumes the use of pre-adder. code authentication, side-channel attack
3. Floating point performance is IEEE-754 compliant single-precision. protection
4. Quad-core Arm Cortex-A53 hard processor system present in select Stratix 10 TX devices.
5. A subset of pins for each package are used for high-voltage 3.0 V and 2.5 V interfaces. Notes:
6. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga. 1. With overdrive feature.

296,8,144,120,24 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, GXE (E-Tile) transceiver count, and GXT+GX (H-Tile) transceiver count

Indicates pin migration path.

26 Altera Product Catalog Altera Product Catalog 27

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Stratix® 10 DX FPGA Features View device ordering codes on page 55.

Product Line DX 1100 DX 2800 Product Line Hard Processor System (HPS)

Logic elements (LEs)1 1,325,000 2,753,000 Quad-core 64 bit Arm Cortex-A53 MPCore
Processor
processor
Adaptive logic modules (ALMs) 449,280 933,120 Maximum processor
1.5 GHz1
frequency
ALM registers 1,797,120 3,732,480
• L1 instruction cache (32 KB)
Hyper-Registers from Hyperflex FPGA Architecture Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric • L1 data cache (32 KB) with error correction
code (ECC)
Programmable clock trees synthesizable Hundreds of synthesizable clock trees
• Level 2 cache (1 MB) with ECC
Resources

M20K memory blocks 5,461 11,721 • Floating-point unit (FPU) single and double
Processor cache and precision
M20K memory size (Mb) 107 229
co-processors • Arm Neon media engine
MLAB memory size (Mb) 7 15 • Arm CoreSight debug and trace
technology
Variable-precision digital signal processing (DSP) blocks 2,592 5,760
• System Memory Management Unit
18 x 19 multipliers 5,184 11,520 (SMMU)
• Cache Coherency Unit (CCU)
Peak fixed-point performance (TMACS)2 10.4 23.0
Scratch pad RAM 256 KB
Peak floating-point performance (TFLOPS)3 4.1 9.2
HPS DDR memory DDR4, DDR3 (Up to 64 bit with ECC)
AES-256/SHA-256 bitstream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication,
Secure device manager DMA controller 8 channels
side-channel attack protection
3X 10/100/1000 Ethernet media access
Quad-core 64-bit Arm Cortex-A53 up to 1.5 GHz with 32KB I/D cache, Neon coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory EMAC
controller (EMAC) with integrated DMA
management unit, cache coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general purpose timers x7, watchdog timer x4
Hard processor system4 USB On-The-Go
2X USB OTG with integrated DMA
Yes ‒ (OTG) controller

Maximum user I/O pins 528 816 UART controller 2X UART 16550 compatible
I/O and Architectural Features

Serial peripheral
Maximum LVDS pairs 1.6 Gbps (RX or TX) 264 408
interface (SPI) 4X SPI
controller
Total full duplex transceiver count - non return to zero (NRZ) 32 84
I2C controller 5X I2C
GXE transceiver count - PAM4 (up to 57.8 Gbps) or NRZ
8 PAM-4, or 16 NRZ 4 PAM-4, or 8 NRZ Quad SPI flash
(up to 28.9 Gbps) 1X SIO, DIO, QIO SPI flash supported
controller
GXP transceiver count - NRZ (up to 16 Gbps) 16 76 SD/SDIO/MMC
1X eMMC 4.5 with DMA and CE-ATA support
controller
UPI/PCI Express 4.0 x16 hard intellectual property (IP) blocks
- 3 • 1X ONFI 1.0 or later
(configurable for UPI or PCIe operation) NAND flash
controller • 8 and 16 bit support
PCI Express 4.0 x16 hard IP blocks (supports PCIe only) 1 1
General-purpose
4X
100G Ethernet media access control (MAC) + forward error timers
4 2
correction (FEC) hard IP blocks Software-
programmable
Memory devices supported DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3 Maximum 48 GPIOs
general-purpose
I/Os (GPIOs)
Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, P-Tile Transceiver Count and E-Tile Transceiver Count
HPS DDR Shared 3X 48 - May be assigned to HPS for HPS
F1760 pin (42.5 mm x 42.5 mm, 1.0 mm pitch) 528,0,264,16,16 ‒ I/Os DDR access
48 I/Os to connect HPS peripherals directly
F2912 pin (55 mm x 55 mm, 1.0 mm pitch) ‒ 816,0,408,76,8 Direct I/Os
to I/O
Watchdog timers 4X
Notes:
1. LE counts valid in comparing across Altera FPGAs, and are conservative vs. competing FPGAs. Secure device manager, Advanced
2. Fixed-point performance assumes the use of pre-adder. Encryption Standard (AES) AES-256/
3. Floating-point performance is IEEE-754 compliant single-precision.
SHA-256 bitstream encryption/
4. Quad-core Arm Cortex-A53 hard processor system present in select Stratix 10 DX devices. Security
authentication, PUF, ECDSA 256/384 boot
5. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.
code authentication, side-channel attack
816,0,408,76,8 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, P-Tile transceiver count, E-Tile transceiver count. protection
Notes:
1. With overdrive feature.

28 Altera Product Catalog Altera Product Catalog 29

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Stratix® 10 SX SoC Features View device ordering codes on page 54.

Product Line SX 400 SX 650 SX 850 SX 1100 SX 1650 SX 2100 SX 2500 SX 2800 Product Line Hard Processor System (HPS)

Logic elements (LEs) 1

378,000 612,000 841,000 1,325,000 1,624,000 2,005,000 2,422,000 2,753,000 Quad-core 64 bit Arm Cortex-A53 MPCore
Processor
processor
Adaptive logic modules (ALMs) 128,160 207,360 284,960 449,280 550,540 679,680 821,150 933,120
Maximum processor
1.5 GHz1
ALM registers 512,640 829,440 1,139,840 1,797,120 2,202,160 2,718,720 3,284,600 3,732,480 frequency
• L1 instruction cache (32 KB)
Hyper-Registers from Hyperflex FPGA Architecture Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric
• L1 data cache (32 KB) with error correction
code (ECC)
Programmable clock trees synthesizable Hundreds of synthesizable clock trees
Resources

• Level 2 cache (1 MB) with ECC

M20K memory blocks 1,537 2,489 3,477 5,461 5,851 6,501 9,963 11,721 • Floating-point unit (FPU) single and
M20K memory size (Mb) 30 49 68 107 114 127 195 229 Processor cache and double precision
co-processors • Arm Neon media engine
MLAB memory size (Mb) 2 3 4 7 8 11 13 15
• Arm CoreSight debug and trace
Variable-precision digital signal processing (DSP) blocks 648 1,152 2,016 2,592 3,145 3,744 5,011 5,760 technology
18 x 19 multipliers 1,296 2,304 4,032 5,184 6,290 7,488 10,022 11,520 • System Memory Management Unit
(SMMU)
Peak fixed-point performance (TMACS)2 2.6 4.6 8.1 10.4 12.6 15.0 20.0 23.0 • Cache Coherency Unit (CCU)
Peak floating-point performance (TFLOPS) 3
1.0 1.8 3.2 4.1 5.0 6.0 8.0 9.2 Scratch pad RAM 256 KB

AES-256/SHA-256 bitstream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, HPS DDR memory DDR4 and DDR3 (Up to 64 bit with ECC)
Secure device manager
side-channel attack protection Direct memory
access (DMA) 8 channels
Quad-core 64-bit Arm Cortex-A53 up to 1.5 GHz with 32KB I/D cache, Neon coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory controller
I/O and Architectural Features

Hard processor system 4

management unit, cache coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general purpose timers x7, watchdog
timer x4 3X 10/100/1000 Ethernet media access
EMAC
controller (EMAC) with integrated DMA
Maximum user I/O pins 374 392 688 688 704 704 1160 1160
USB On-The-Go
2X USB OTG with integrated DMA
Maximum LVDS pairs 1.6 Gbps (RX or TX) 120 192 336 336 336 336 576 576 (OTG) controller

Total full duplex transceiver count 24 24 48 48 96 96 96 96 UART controller 2X UART 16550 compatible
Serial peripheral
GXT full duplex transceiver count (up to 28.3 Gbps) 16 16 32 32 64 64 64 64
interface (SPI) 4X SPI
GX full duplex transceiver count (up to 17.4 Gbps) 8 8 16 16 32 32 32 32 controller
I2C controller 5X I2C
PCI Express hard intellectual property (IP) blocks (3.0 x16) 1 1 2 2 4 4 4 4
Quad SPI flash
1X SIO, DIO, QIO SPI flash supported
controller
Memory devices supported DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys
SD/SDIO/MMC
1X eMMC 4.5 with DMA and CE-ATA support
Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, and Transceiver Count5, 6 controller
NAND flash • 1X ONFI 1.0 or later
374,56,120,24 392,8,192,24
F1152 pin (35 mm x 35 mm, 1.0 mm pitch) – – – – – – controller • 8 and 16 bit support
General-purpose
688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 4X
F1760 pin (42.5 mm x 42.5 mm, 1.0 mm pitch) – – timers
Software-
704,32,336,96 704,32,336,96 704,32,336,96 704,32,336,96 programmable
F2397 pin (50 mm x 50 mm, 1.0 mm pitch) – – – – Maximum 48 GPIOs
general-purpose I/
Os (GPIOs)
1160,8,576,24 1160,8,576,24
F2912 pin (55 mm x 55 mm, 1.0 mm pitch) – – – – – – HPS DDR Shared 3X 48 - May be assigned to HPS for HPS
I/O DDR access
Notes: 48 I/Os to connect HPS peripherals directly
Direct I/Os
1. LE counts valid in comparing across Altera FPGAs, and are conservative vs. competing FPGAs. to I/O
2. Fixed point performance assumes the use of pre-adder.
3. Floating point performance is IEEE-754 compliant single-precision. Watchdog timers 4X
4. Quad-core Arm Cortex-A53 hard processor system only available in Stratix 10 SX SoCs. Secure device manager, Advanced
5. A subset of pins for each package are used for high-voltage 3.0 V and 2.5 V interfaces. Encryption Standard (AES) AES-256/
6. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.
SHA-256 bitstream encryption/
Security
392,8,192,24 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, and transceiver count. authentication, PUF, ECDSA 256/384 boot
Indicates pin migration path.
code authentication, side-channel attack
protection
Notes:
1. With overdrive feature.

30 Altera Product Catalog Altera Product Catalog 31

 Devices: Generation 10 Device Portfolio

Arria® 10 FPGA and SoC Overview

intel.com/arria10

Arria® 10 FPGAs and SoCs deliver the highest performance at 20 nm, offering a one speed-grade performance advantage over
competing devices. Arria 10 FPGAs and SoCs are up to 40% lower power than previous generation FPGAs and SoCs, and feature
the industry’s only hard floating-point DSP blocks with speeds up to 1,500 giga floating-point operations per second (GFLOPS)†.
The Arria 10 FPGAs and SoCs are ideal for the following end market applications.

Wireless
Applications

• Remote radio head

• Mobile backhaul
• Active antenna
• Base station
• 4G/Long Term Evolution (LTE) macro eNB
• Wideband Code Division Multiple Access (W-CDMA)

Cloud Service and Storage

Applications
• Flash cache
• Cloud
• Server
• Financial
• Bioscience
• Oil and gas
• Data center server acceleration

Broadcast
Applications
• Switcher
• Server
• Encoder/decoder
• Capture cards
• Editing
• Monitors
• Multiviewers

Altera Product Catalog 32

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Arria® 10 FPGA Features View device ordering codes on page 55.

Product Line GX 160 GX 220 GX 270 GX 320 GX 480 GX 570 GX 660 GX 900 GX 1150 GT 900 GT 1150
Part number reference 10AX016 10AX022 10AX027 10AX032 10AX048 10AX057 10AX066 10AX090 10AX115 10AT090 10AT115
LEs (K) 160 220 270 320 480 570 660 900 1,150 900 1,150
System logic elements (K) 210 288 354 419 629 747 865 1,180 1,506 1,180 1,506
Adaptive logic modules (ALMs) 61,510 83,730 101,620 118,730 181,790 217,080 250,540 339,620 427,200 339,620 427,200
Registers 246,040 334,920 406,480 474,920 727,160 868,320 1,002,160 1,358,480 1,708,800 1,358,480 1,708,800
Resources

M20K memory blocks 440 588 750 891 1,438 1,800 2,133 2,423 2,713 2,423 2,713
M20K memory (Mb) 9 11 15 17 28 35 42 47 53 47 53
MLAB memory (Mb) 1.0 1.8 2.4 2.8 4.3 5.0 5.7 9.2 12.7 9.2 12.7
Hardened single-precision floating-point multiplers/
156/156 192/192 830/830 985/985 1,368/1,368 1,523/1,523 1,687/1,687 1,518/1,518 1,518/1,518 1,518/1,518 1,518/1,518
adders
18 x 19 multipliers 312 384 1,660 1,970 2,736 3,046 3,374 3,036 3,036 3,036 3,036
Peak fixed-point performance (GMACS)1 343 420 1,826 2,167 3,010
3,351 3,714 3,340 3,340 3,340 3,340
Peak floating-point performance (GFLOPS) 140 172 747 887 1,231
1,371 1,519 1,366 1,366 1,366 1,366
Global clock networks 32 32 32 32 32 32 32 32 32 32 32
Regional clocks 8 8 8 8 8 8 16 16 16 16 16
I/O voltage levels supported (V) 1.2, 1.25, 1.35, 1.8, 2.5, 3.0
Clocks, Maximum I/O Pins, and

3 V I/O pins only: 3 V LVTTL, 2.5 V CMOS

DDR and LVDS I/O pins: POD12, PvOD10, Differential POD12, Differential POD10, LVDS, RSDS, mini-LVDS, LVPECL
Architectural Features

I/O standards supported

All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-135, SSTL-125, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-12, HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), HSUL-12, Differential SSTL-135, Differential SSTL-125, Differential
SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-12, Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12
Maximum LVDS channels (1.6 G) 120 120 168 168 222 324 270 384 384 312 312
Maximum user I/O pins 288 288 384 384 492 696 696 768 768 624 624
Transceiver count (17.4 Gbps) 12 12 24 24 36 48 48 96 96 72 72
Transceiver count (25.78 Gbps) – – – – – – – – – 6 6
PCI Express hardened IP blocks (3.0 x8) 1 1 2 2 2 2 2 4 4 4 4
Maximum 3 V I/O pins 48 48 48 48 48 48 48 – – – –
Memory devices supported DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3, LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II, HMC

Package Options2 and I/O Pins3: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs4, and Transceiver Count

U19 U484 pin (19 mm) 192, 48, 72, 6 192, 48, 72,6 – – – – – – – – –

F27 F672 pin (27 mm) 240, 48, 96, 12 240, 48, 96, 12 240, 48, 96, 12 240, 48, 96, 12 – – – – – – –

F29 F780 pin (29 mm) 288, 48, 120, 12 288, 48, 120, 12 360, 48, 156, 12 360, 48, 156, 12 360, 48, 156, 12 – – – – – –

F34 F1152 pin (35 mm) – – 384, 48, 168, 24 384, 48, 168, 24 492, 48, 222, 24 492, 48, 222, 24 492, 48, 222, 24 504, 0, 252, 24 504, 0, 252, 24 – –

F35 F1152 pin (35 mm) – – 384, 48, 168, 24 384, 48, 168, 24 396, 48, 174, 36 396, 48, 174, 36 396, 48, 174, 36 – – – –

KF40 F1517 pin (40 mm) – – – – – 696, 96, 324, 36 696, 96, 324, 36 – – – –
– – – – – 588, 48, 270, 48 588, 48, 270, 48 600, 0, 300, 48 600, 0, 300, 48 – –
NF40 F1517 pin (40 mm)

RF40 F1517 pin (40 mm) – – – – – – – 342, 0, 154, 66 342, 0, 154, 66 – –

– – – – – – – 768, 0, 384, 48 768, 0, 384, 48 – –

NF45 F1932 pin (45 mm)

SF45 F1932 pin (45 mm) – – – – – – – 624, 0, 312, 72 624, 0, 312, 72 624, 0, 312, 72 624, 0, 312, 72

UF45 F1932 pin (45 mm) – – – – – – – 480, 0, 240, 96 480, 0, 240, 96 – –

Notes:
192, 48, 72, 6 Numbers indicate GPIO count, high-voltage I/O count, LVDS pairs, and transceiver count.
1. Fixed-point performance assumes the use of pre-adders.
2. All packages are ball grid arrays with 1.0 mm pitch, except for U19 (U484), which is 0.8 mm pitch. Indicates pin migration.
3. A subset of pins for each package are used for 3.3 V and 2.5 V interfaces.
4. Each LVDS pair can be configured as either a differential input or a differential output.
5. Certain packages might not bond out all PCI Express hard IP blocks.
6. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

33 Altera Product Catalog Altera Product Catalog 34

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Arria® 10 SoC Features View device ordering codes on page 55.

Product Line SX 160 SX 220 SX 270 SX 320 SX 480 SX 570 SX 660 Product Line Hard Processor System (HPS)

Part number reference 10AS016 10AS022 10AS027 10AS032 10AS048 10AS057 10AS066 Dual-core Arm Cortex-A9 MPCore
Processor
LEs (K) 160 220 270 320 480 570 660 processor
System Logic Elements (K) 210 288 354 419 629 747 865
Maximum processor
1.2 -1.5 GHz1
ALMs 61,510 83,730 101,620 118,730 181,790 217,080 250,540 frequency
Registers 246,040 334,920 406,480 474,920 727,160 868,320 1,002,160 • L1 instruction cache (32 KB)
Resources

M20K memory blocks 440 588 750 891 1,438 1,800 2,133 • L1 data cache (32 KB)
M20K memory (Mb) 9 11 15 17 28 35 42 • Level 2 cache (512 KB) shared
MLAB memory (Mb) 1.0 1.8 2.4 2.8 4.3 5.0 5.7 • FPU single and double precision
Processor cache and
Hardened single-precision floating-point multiplers/ adders 156/156 192/192 830/830 985/985 1,368/1,368 1,523/1,523 1,687/1,687 co-processors • Arm Neon media engine
18 x 19 multipliers 312 1687/1687 1,660 1,970 2,736 3,046 3,374 • Arm CoreSight debug and trace
technology
Peak fixed-point performance (GMACS)1 343 420 1,826 2,167 3,010 3,351 3,714
• Snoop control unit (SCU)
Peak floating-point performance (GFLOPS) 140 172 747 887 1,231 1,371 1,519
• Acceleration coherency port (ACP)
Global clock networks 32 32 32 32 32 32 32
Regional clocks 8 8 8 8 8 8 16 Scratch pad RAM 256 KB
I/O voltage levels supported (V) 1.2, 1.25, 1.35, 1.8, 2.5, 3.0 DDR4 and DDR3
HPS DDR memory
Clocks, Maximum I/O Pins, and

3 V I/O pins only: 3 V LVTTL, 2.5 V CMOS (Up to 64 bit with ECC)
DDR and LVDS I/O pins: POD12, POD10, Differential POD12, Differential POD10, LVDS, RSDS, mini-LVDS, LVPECL
Architectural Features

DMA controller 8 channels

I/O standards supported All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-135, SSTL-125, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-12, HSTL-18 (I and II), HSTL-15 (I and II),
HSTL-12 (I and II), HSUL-12, Differential SSTL-135, Differential SSTL-125, Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-12, 3X 10/100/1000 EMAC with
Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 EMAC
integrated DMA
Maximum LVDS channels (1.6 G) 120 120 168 168 222 270 270
USB OTG controller 2X USB OTG with integrated DMA
Maximum user I/O pins 288 288 384 384 492 696 696
Transceiver count (17.4 Gbps) 12 12 24 24 36 48 48
UART controller 2X UART 16550 compatible
Transceiver count (25.78 Gbps) – – – – – – –
PCI Express hardened IP blocks (3.0 x8) 1 1 2 2 2 2 2 SPI controller 4X SPI
Maximum 3 V I/O pins 48 48 48 48 48 48 48
I2C controller 5X I2C
Memory devices supported DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3, LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II
Quad SPI flash controller 1X SIO, DIO, QIO SPI flash supported
Package Options2 and I/O Pins3: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs4, and Transceiver Count
1X eMMC 4.5 with DMA and CE-ATA
192, 48, 72, 6 192, 48, 72,6 – – – – – SD/SDIO/MMC controller
U19 U484 pin (19 mm) support

240, 48, 96, 12 240, 48, 96, 12 240, 48, 96, 12 240, 48, 96, 12 – – – • 1X ONFI 1.0 or later
F27 F672 pin (27 mm) NAND flash controller
• 8 and 16 bit support
288, 48, 120, 12 288, 48, 120, 12 360, 48, 156, 12 360, 48, 156, 12 360, 48, 156, 12 – –
F29 F780 pin (29 mm) General-purpose timers 7X
– – 384, 48, 168, 24 384, 48, 168, 24 492, 48, 222, 24 492, 48, 222, 24 492, 48, 222, 24 Software-programmable
F34 F1152 pin (35 mm) Maximum 54 GPIOs
GPIOs
– – 384, 48, 168, 24 384, 48, 168, 24 396, 48, 174, 36 396, 48, 174, 36 396, 48, 174, 36
F35 F1152 pin (35 mm) 48 I/Os to connect HPS peripherals
Direct shared I/Os
directly to I/O
– – – – – 696, 96, 324, 36 696, 96, 324, 36
KF40 F1517 pin (40 mm) Watchdog timers 4X
– – – – – 588, 48, 270, 48 588, 48, 270, 48 Secure boot, AES, and secure hash
NF40 F1517 pin (40 mm) Security
algorithm

Notes: Notes:
1. Fixed-point performance assumes the use of pre-adders. 1. With overdrive feature.
2. All packages are ball grid arrays with 1.0 mm pitch, except for U19 (U484), which is 0.8 mm pitch.
3. A subset of pins for each package are used for 3.3 V and 2.5 V interfaces.
4. Each LVDS pair can be configured as either a differential input or a differential output.
5. Certain packages might not bond out all PCI Express hard IP blocks.
6. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

192, 48, 72, 6 Numbers indicate GPIO count, high-voltage I/O count, LVDS pairs, and transceiver count.

Indicates pin migration.

35 Altera Product Catalog Altera Product Catalog 36

 Devices: Generation 10 Device Portfolio

Cyclone® 10 FPGA Overview intel.com/cyclone10

Cyclone® 10 FPGAs deliver cost and power savings over previous generations of Cyclone FPGAs. Cyclone 10 GX FPGAs pro-
vide high bandwidth via 12.5G transceiver-based functions, 1.4 Gbps LVDS, and 1,866 Mbps DDR3 SDRAM, and feature a hard
floating-point DSP block in a low-cost FPGA. Cyclone 10 LP devices offer low static power, cost-optimized functions.
• Cyclone 10 GX FPGAs are optimized for high bandwidth‡
• Cyclone 10 LP FPGAs are optimized for power and cost-sensitive applications

Cyclone 10 GX FPGA
• Low-cost 12.5 Gbps transceivers
• 1,866 Mbps 72 bit DDR3 SDRAM interface
• 1.4 Gbps LVDS
• The industry’s first low-cost FPGA with hard floating-point
blocks

GX Applications
• Embedded vision cameras
• Industrial robotics
• Machine vision
• Programmable logic controllers
• Pro-AV systems

Cyclone 10 LP FPGA
• Designed for power-sensitive applications
• Simplified core power supply requirements
• High I/O count to package density ratio
• Embedded Nios V processor support

LP Applications
• I/O expansion
• Interfacing
• Chip-to-chip bridging
• Sensor fusion
• Industrial motor control

‡
Compared to previous generation Cyclone FPGAs, cost comparisons are based on list price. Tests measure performance of components on a particular test, in specific systems. Differences in
hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information
about performance and benchmark results, visit www.intel.com/benchmarks.

Altera Product Catalog 37

 Devices: Generation 10 Device Portfolio

Cyclone® 10 GX FPGA Features

View device ordering codes on page 56.

Product Line 10CX085 10CX105 10CX150 10CX220

Logic elements (LEs) 1
85,000 104,000 150,000 220,000
Adaptive logic modules (ALMs) 31,000 38,000 54,770 80,330
ALM registers 124,000 152,000 219,080 321,320
M20K memory blocks 291 382 475 587
M20K memory size (Kb) 5,820 7,640 9,500 11,740
Resources

MLAB memory size (Kb) 653 799 1,152 1,690

Variable-precision digital signal processing
84 125 156 192
(DSP) blocks
18 x 19 multipliers 168 250 312 384
Peak fixed-point performance (GMACS)2 151 225 281 346
Peak floating-point performance
59 88 109 134
(GFLOPS)3
Global clock networks 32 32 32 32
I/O and Architectural Features

Regional clocks 8 8 8 8
Maximum user I/O pins 192 284 284 284
Maximum LVDS pairs 1.4 Gbps (RX or TX) 72 118 118 118
Maximum transceiver count (12.5 Gbps) 6 12 12 12
Maximum 3V I/O pins 48 48 48 48
PCI Express hard IP blocks (2.0 x4)4 1 1 1 1
Memory devices supported DDR3, DDR3L, LPDDR3

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, 3V I/O Count, LVDS Pairs, Total Transceiver count5

188, 48, 70, 6 188, 48, 70, 6 188, 48, 70, 6 188, 48, 70, 6
U484 pin (19 mm x 19 mm, 0.8 mm pitch)

192, 48, 72, 6 236, 48, 94, 10 236, 48, 94, 10 236, 48, 94, 10
F672 pin (27 mm x 27 mm, 1.0 mm pitch)

284, 48, 118, 12 284, 48, 118, 12 284, 48, 118, 12

F780 pin (29 mm x 29 mm, 1.0 mm pitch)

Notes:
1. LE counts valid in comparing across Altera FPGAs, and are conservative versus competing FPGAs.
2. Fixed-point performance assumes the use of pre-adders.
3. Floating-point performance is IEEE-754 compliant single-precision.
4. Hard PCI Express IP core x2 in U484 package
5. Each LVDS pair can be configured as either a differential input or differential output.
6. A subset of pins for each package are used for high-voltage 3.0 V and 2.5 V interfaces.
7. All data is correct at the time of printing and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

284,48,118,12 Numbers indicate GPIO count, 3V I/O count, LVDS pairs, total transceiver count.

Indicates pin migration path.

Altera Product Catalog 38

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Cyclone® 10 LP FPGA Features View device ordering codes on page 56.

Product Line 10CL006 10CL010 10CL016 10CL025 10CL040 10CL055 10CL080 10CL120

Logic elements (LEs)1 6,000 10,000 16,000 25,000 40,000 55,000 80,000 120,000

M9K memory blocks 30 46 56 66 126 260 305 432

Resources

M9K memory size (Kb) 270 414 504 594 1,134 2,340 2,745 3,888

DSP blocks (18 x 18 multipliers) 15 23 56 66 126 156 244 288

Phase-locked loops (PLL) 2 2 4 4 4 4 4 4

Global clock networks 10 10 20 20 20 20 20 20

Architectural
Features
I/O and

Maximum user I/O pins 176 176 340 150 325 321 423 525

Maximum LVDS channels 65 65 137 52 124 132 178 230

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, LVDS Pairs2

88, 22 88, 22 78, 19 76, 18

E144 pin (22 mm x 22mm, 0.5 mm pitch)

101,26 87, 22
M164 pin (8 mm x 8 mm, 0.5 mm pitch)

176, 65 176, 65 162, 53 150, 52

U256 pin (14 mm x 14 mm, 0.8 mm pitch)

340, 137 325, 124 321, 132 289, 110

U484 pin (19 mm x 19 mm, 0.8 mm pitch)

340, 137 325, 124 321, 132 289, 110 277, 103
F484 pin (23 mm x 23 mm, 1.0 mm pitch)

423, 178 525, 230

F780 pin (29 mm x 29 mm, 1.0 mm pitch)

Notes:
1. LE counts valid in comparing across Altera FPGAs, and are conservative versus competing FPGAs.
2. This includes both dedicated and emulated LVDS pairs
3. All data is correct at the time of printing and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

88, 22 Numbers indicate GPIO count, LVDS pairs.

Indicates pin migration path.

39 Altera Product Catalog Altera Product Catalog 40

 Devices: Generation 10 Device Portfolio

MAX® 10 FPGA Overview intel.com/max10

MAX® 10 FPGAs revolutionize non-volatile integration by delivering advanced processing capabilities in a low-cost, instant-on,
small form factor, programmable logic device.

MAX 10 FPGAs are built on TSMC’s 55 nm flash technology, enabling instant-on configuration so you can quickly control the
power-up or initialization of other components in the system. The devices also include full-featured FPGA capabilities, such as
DSP, analog functionality, Nios V processor, and memory controllers.

With a robust set of FPGA capabilities, MAX 10 FPGAs are optimized for a wide range of high-volume, cost-sensitive applications,
including:

Automotive
• Built on TSMC’s 55 nm high-volume flash process tailored
for the automotive industry’s rigorous safety and quality
requirements
• Integrated flash provides instant-on behavior for
applications requiring fast boot times such as rear-view
cameras in advanced driver assistance systems (ADAS) and
infotainment displays
• FPGA-class signal processing acceleration for electric
vehicle (EV) applications, such as motor control, battery
management, and power conversion

Industrial
• Reduced footprint, increased design security and reliability,
and lower system cost
• Accurate environmental condition sensing and efficient
real-time controls for motor control, I/O modules, and Internet
of Things (IoT) applications
• Single-chip support for multiple industrial Ethernet protocols
and machine-to-machine (M2M) communication

Communications
• Analog functionality for sensing board environment allows
integration of power-up sequencing and system-monitoring
circuitry in a single device
• High I/O count and software-based system management us-
ing the Nios V processor enable board management
integration in an advanced, reliable, single-chip system
controller

Altera Product Catalog 41

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

MAX® 10 FPGA Features View device ordering codes on page 57

Product Line 10M02 10M04 10M08 10M16 10M25 10M40 10M50

LEs (K) 2 4 8 16 25 40 50
Block memory (Kb) 108 189 378 549 675 1,260 1,638
User flash memory1 (KB) 12 16 – 156 32 – 172 32 – 296 32 – 400 64 – 736 64 – 736
18 x 18 multipliers 16 20 24 45 55 125 144
PLLs 2
1, 2 1, 2 1, 2 1, 4 1, 4 1, 4 1, 4
Internal configuration Single Dual Dual Dual Dual Dual Dual
Analog-to-digital converter (ADC), temperature sensing diode (TSD)3 - 1, 1 1, 1 1, 1 2, 1 2, 1 2, 1
External memory interface (EMIF) Yes 4
Yes 4
Yes 4
Yes 5
Yes 5
Yes 5
Yes5
Package Options6 and I/O Pins: Feature Set Options, GPIO, True LVDS Transmitter7/Receiver7
WLCSP
V36 (D) C, 27, 3/10 – – – – – –
(3 mm, 0.4 mm pitch)
WLCSP L, 58, 7/25
V81 (S)
(4 mm, 0.4 mm pitch)
WLCSP
V81 (D)8 – – C/F, 56, 7/25 – – – –
(4 mm, 0.4 mm pitch)
WLCSP L, 125, 10/53
Y180 (S)
(6x5 mm, 0.35 mm pitch)
EQFP C, 101, 7/45 C/A, 101, 10/41 C/A, 101, 10/41 C/A, 101, 10/41 C/A, 101, 10/41 C/A, 101, 10/42 C/A, 101, 10/42
E144 (S)
(22 mm, 0.5 mm pitch)
MBGA C, 112, 9/49 C/A, 112, 9/49 C/A, 112, 9/49 – – – –
M153 (S)
(8 mm, 0.5 mm pitch)
UBGA C, 130, 9/58 C/A, 130, 9/58 C/A, 130, 9/58 C/A, 130, 9/58 – – –
U169 (S)
(11 mm, 0.8 mm pitch)
UBGA C, 246, 15/114 C/A, 246, 15/114 C/A, 246, 15/114 C/A, 246, 15/114
U324 (S)
(15 mm, 0.8 mm pitch)
UBGA C, 160, 9/73 C/A, 246, 15/114 C/A, 246, 15/114 C/A, 246, 15/114 – – –
U324 (D)
(15 mm, 0.8 mm pitch)
FBGA – C/A, 178, 13/80 C/A, 178, 13/80 C/A, 178, 13/80 C/A, 178, 13/80 C/A/D, 178, 13/80 C/A/D, 178, 13/80
F256 (D)
(17 mm, 1.0 mm pitch)
FBGA – – C/A, 250, 15/116 C/A, 320, 22/151 C/A, 360, 24/171 C/A/D, 360, 24/171 C/A/D, 360, 24/171
F484 (D)
(23 mm, 1.0 mm pitch)
FBGA – – – – – C/A/D, 500, 30/241 C/A/D, 500, 30/241
F672 (D)
(27 mm, 1.0 mm pitch)
VPBGA – – – – – A, 485, 30/233 A, 485, 30/233
B610 (S)
(19mm, variable9, 10 pitch)
VPBGA – – – – – D, 485, 30/233 D, 485, 30/233
B610 (D)
(19mm, variable9, 10 pitch)

Notes:
1. Additional user flash may be available, depending on configuration options.
2. The number of PLLs available is dependent on the package option.
3. Availability of the ADC or TSD varies by package type. Smaller pin-count packages do not have access to the ADC hard IP.
4. SRAM only.
5. SRAM, DDR3 SDRAM, DDR2 SDRAM, or LPDDR2.
6. (D) = Dual power supply (1.2 V/2.5 V), (S) = Single power supply (3.3 V or 3.0 V).
7. Some LVDS channels at bottom bank can be configured as TX or RX, refer to the Intel MAX 10 High-Speed LVDS I/O User Guide for details.
8. V81 package does not support analog feature set. 10M08 V81 F devices support dual image with RSU.
9. VPBGA(Variable Pitch BGA) packaging is compatible with Type III PCBs that use design rules equivalent to 0.8 mm ball pitch packages and standard plated through hole (PTH) vias.
10. The ball pitch is variable, ranging from 0.5mm to 0.94mm in single package and it helps to ease signal routing. Please take note that the min pitch of 0.5mm is not meant for signal traces to go through. For more details, please refer to MAX® 10 FPGA Signal Integrity Design Guidelines.
11. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

C, 27, 3/10 Indicates feature set options, GPIO count, and LVDS transmitter or receiver count. Feature set options:
C = compact features, F = flash features with RSU option, A = analog and flash features with RSU option, D = analog and flash features with RSU option and flash access control. Each has added premiums.
Indicates pin migration.

42 Altera Product Catalog Altera Product Catalog 43

Devices: 28 nm Device Portfolio Devices: 28 nm Device Portfolio

Arria® V FPGA and SoC Features View device ordering codes on page 58.

Arria® V GX FPGAs1 Arria® V GT FPGAs1 Arria® V GZ FPGAs1 Arria® V SX SoCs1 Arria® V ST SoCs1
Product Line
5AGXA1 5AGXA3 5AGXA5 5AGXA7 5AGXB1 5AGXB3 5AGXB5 5AGXB7 5AGTC3 5AGTC7 5AGTD3 5AGTD7 5AGZE1 5AGZE3 5AGZE5 5AGZE7 5ASXB3 5ASXB5 5ASTD3 5ASTD5
LEs (K) 75 156 190 242 300 362 420 504 156 242 362 504 220 360 400 450 350 462 350 462
ALMs 28,302 58,900 71,698 91,680 113,208 136,880 158,491 190,240 58,900 91,680 136,880 190,240 83,020 135,840 150,960 169,800 132,075 174,340 132,075 174,340
Registers 113,208 235,600 286,792 366,720 452,832 547,520 633,964 760,960 235,600 366,720 547,520 760,960 332,080 543,360 603,840 679,200 528,300 697,360 528,300 697,360
M10K memory blocks 800 1,051 1,180 1,366 1,510 1,726 2,054 2,414 1,051 1,366 1,726 2,414 – – – – 1,729 2,282 1,729 2,282
Resources

M20K memory blocks – – – – – – – – – – – – 585 957 1,440 1,700 – – – –

M10K memory (Kb) 8,000 10,510 11,800 13,660 15,100 17,260 20,540 24,140 10,510 13,660 17,260 24,140 – – – – 17,290 22,820 17,290 22,820
M20K memory (Kb) – – – – – – – – – – – – 11,700 19,140 28,800 34,000 – – – –
MLAB memory (Kb) 463 961 1,173 1,448 1,852 2,098 2,532 2,906 961 1,448 2,098 2,906 2,594 4,245 4,718 5,306 2,014 2,658 2,014 2,658
Variable-precision DSP blocks 240 396 600 800 920 1,045 1,092 1,156 396 800 1,045 1,156 800 1,044 1,092 1,139 809 1,090 809 1,090
18 x 18 multipliers 480 792 1,200 1,600 1,840 2,090 2,184 2,312 792 1,600 2,090 2,312 1,600 2,088 2,184 2,278 1,618 2,180 1,618 2,180
Processor cores (Arm Cortex-A9) – – – – – – – – – – – – – – – – Dual Dual Dual Dual
Maximum CPU clock frequency (GHz) – – – – – – – – – – – – – – – – 1.052 1.052 1.052 1.052
Global clock networks 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
PLLs3 (FPGA) 10 10 12 12 12 12 16 16 10 12 12 16 20 20 24 24 14 14 14 14
Clocks, Maximum I/O Pins, and Architectural Features

PLLs (HPS) – – – – – – – – – – – – – – – – 3 3 3 3
I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.0, 3.34
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II),
I/O standards supported
Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12
Maximum LVDS pairs
80/67 80/67 136/120 136/120 176/160 176/160 176/160 176/160 80/68 136/120 176/160 176/160 108/99 108/99 168/166 168/166 136/120 136/120 136/120 136/120
(receiver/transmitter)
Transceiver count (6.5536 Gbps) 9 9 24 24 24 24 36 36 3 6 6 6 – – – – 30 30 30 30
Transceiver count (10.3125 Gbps)5 – – – – – – – – 4 12 12 20 – – – – – – 16 16
Transceiver count (12.5 Gbps) – – – – – – – – – – – – 24 24 36 36 – – – –
PCI Express hardened IP blocks
1 1 2 2 2 2 2 2 1 2 2 2 – – – – 2 2 2 2
(2.0 x4)
PCI Express hardened IP blocks
– – – – – – – – – – – – 1 1 1 1 – – – –
(2.0 x8, 3.0)
GPIOs (FPGA) – – – – – – – – – – – – – – – – 540 540 540 540
GPIOs (HPS) – – – – – – – – – – – – – – – – 208 208 208 208
Hard memory controllers6 (FPGA) 2 2 4 4 4 4 4 4 2 4 4 4 – – – – 3 3 3 3
Hard memory controllers (HPS) – – – – – – – – – – – – – – – – 1 1 1 1
Memory devices supported DDR3, DDR2, DDR II+7, QDR II, QDR II+, RLDRAM II, RLDRAM 38, LPDDR7, LPDDR27

Package Options and I/O Pins: GPIO Count, and Transceiver Count

F672 pin 336 336 336 336 – – – – 336 – – – – – – – – – – –

(27 mm, 1.0 mm pitch) 9,0 9,0 9,0 9,0 3,4

H780 pin – – – – – – – – – – – – 342 342 – – – – –

(29 mm, 1.0 mm pitch) 12 12

F896 pin 416 416 384 384 384 384 – – 416 384 384 – – – – – 250, 208 250, 208 250, 208 250, 208
(31 mm, 1.0 mm pitch) 9,0 9,0 18,0 18,0 18,0 18,0 3,4 6,8 6,8 12+0 12+0 12+6 12+6

F1152 pin – – 544 544 544 544 544 544 – 544 544 544 414 414 534 534 385, 208 385, 208 385, 208 385, 208
(35 mm, 1.0 mm pitch) 24,0 24,0 24,0 24,0 24,0 24,0 6,12 6,12 6,12 24 24 24 24 18+0 18+0 18+8 18+8

F1517 pin – – – – 704 704 704 704 – – 704 704 – – 674 674 540, 208 540, 208 540, 208 540, 208
(40 mm, 1.0 mm pitch) 24,0 24,0 36,0 36,0 6,12 6,20 36 36 30+0 30+0 30+16 30+16

Notes:
1. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga. 336 For Arria V GX and GT devices, values on top indicate available user I/O pins and values at the bottom indicate the 6.5536 Gbps and 10.3125 Gbps transceiver count. One pair of 10 Gbps
2. 1.15 V operation. transceiver channels can be configured as three 6 Gbps transceiver channels. For Arria V GZ devices, values on top indicate available user I/O pins and values at the bottom indicate the
9,0 12.5 Gbps transceiver count.
3. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs.
4. For Arria V GZ devices, the I/O voltage of 3.3 V compliant, requires a 3.0 V power supply. 250, 208
Values on top indicate available FPGA user I/O pins and HPS I/O pins; values at the bottom indicate the 6.5536 Gbps plus 10.3125 Gbps transceiver count.
5. One pair of 10 Gbps transceiver channels can be configured as three 6 Gbps transceiver channels. 12+0
6. With 16 and 32 bit ECC support. Pin migration (same Vcc, GND, ISP, and input pins). User I/O pins may be less than labeled for pin migration.
7. These memory interfaces are not available as Altera FPGA IP.
8. This memory interface is only available for Arria V GZ devices.

44 Altera Product Catalog Altera Product Catalog 45

Devices: 28 nm Device Portfolio Devices: 28 nm Device Portfolio

Cyclone® V FPGA Features View device ordering codes on page 59.

Cyclone® V E FPGAs1 Cyclone® V GX FPGAs1 Cyclone® V GT FPGAs1

Product Line
5CEA2 5CEA4 5CEA5 5CEA7 5CEA9 5CGXC3 5CGXC4 5CGXC5 5CGXC7 5CGXC9 5CGTD5 5CGTD7 5CGTD9
LEs (K) 25 49 77 150 301 36 50 77 150 301 77 150 301
ALMs 9,430 18,480 29,080 56,480 113,560 13,460 18,868 29,080 56,480 113,560 29,080 56,480 113,560
Registers 37,736 73,920 116,320 225,920 454,240 53,840 75,440 116,320 225,920 454,240 116,320 225,920 454,240
Resources

M10K memory blocks 176 308 446 686 1,220 135 250 446 686 1,220 446 686 1,220
M10K memory (Kb) 1,760 3,080 4,460 6,860 12,200 1,350 2,500 4,460 6,860 12,200 4,460 6,860 12,200
MLAB memory (Kb) 196 303 424 836 1,717 182 424 424 836 1,717 424 836 1,717
Variable-precision DSP blocks 25 66 150 156 342 57 70 150 156 342 150 156 342
18 x 18 multipliers 50 132 300 312 684 114 140 300 312 684 300 312 684
Global clock networks 16 16 16 16 16 16 16 16 16 16 16 16 16
PLLs2 (FPGA) 4 4 6 7 8 4 6 6 7 8 6 7 8
Clocks, Maximum I/O Pins, and

I/O voltage levels supported (V) 1.1, 1.2, 1.5, 1.8, 2.5,3.3
Architectural Features

LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II),
I/O standards supported
Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12, HiSpi, SLVS, Sub-LVDS
Maximum LVDS pairs (receiver/transmitter) 56/56 56/56 60/60 120/120 120/120 52/52 84/84 84/84 120/120 140/140 84/84 120/120 140/140
Transceiver count (3.125 Gbps) – – – – – 3 6 6 9 12 – – –
Transceiver count (6.144 Gbps)3 – – – – – – – – – – 64 94 124
PCI Express hardened IP blocks (1.0) 5
– – – – – 1 2 2 2 2 – – –
PCI Express hardened IP blocks (2.0) – – – – – – – – – – 2 2 2
Hard memory controllers6 (FPGA) 1 1 2 2 2 1 2 2 2 2 2 2 2
Memory devices supported DDR3, DDR2, LPDDR2

Package Options and I/O Pins: GPIO Count, and Transceiver Count

M301 pin 129 129 129

(11 mm, 0.5 mm pitch) 4 4 4

M383 pin 223 223 175 175 175 175

(13 mm, 0.5 mm pitch) 6 6 6

M484 pin 240 240 240

(15 mm, 0.5 mm pitch) 3 3

U324 pin 176 176 144

(15 mm, 0.8 mm pitch) 3

U484 pin 224 224 224 240 240 208 224 224 240 240 224 240 240
(19 mm, 0.8 mm pitch) 3 6 6 6 5 6 6 5

F256 pin 128 128

(17 mm, 1.0 mm pitch)

F484 pin 224 224 240 240 224 208 240 240 240 224 240 240 224
(23 mm, 1.0 mm pitch) 3 6 6 6 6 6 6 6

F672 pin 336 336 336 336 336 336 336 336 336
(27 mm, 1.0 mm pitch) 6 6 9 9 6 9 9

F896 pin 480 480 480 480 480 480

(31 mm, 1.0 mm pitch) 9 12 9 12

F1152 pin 560 560

(35 mm, 1.0 mm pitch) 12 12

Notes:
1. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga. 129 Values on top indicate available user I/O pins; values at the bottom indicate the 3.125 Gbps, 5 Gbps, or 6.144 Gbps transceiver count.
2. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 4
3. Automotive grade Cyclone V GT FPGAs include a 5 Gbps transceiver.
Pin migration (same Vcc, GND, ISP, and input pins). User I/O pins may be less than labeled for pin migration.
4. Transceiver counts shown are for ≤ 5 Gbps. The 6 Gbps channel count support depends on package and channel usage.
Refer to Cyclone V Device Handbook Volume 2: Transceivers for guidelines.
5. Only one PCIe hard IP block supported in M301, M484, and U324 packages. For FPGAs: Pin migration is only possible if you use only up to 175 GPIOs.
6. Includes 16 and 32 bit error correction code ECC support.

46 Altera Product Catalog Altera Product Catalog 47

Devices: 28 nm Device Portfolio Devices: 28 nm Device Portfolio

Cyclone® V SoC Features View device ordering codes on page 59.

Cyclone® V SE SoCs1 Cyclone® V SX SoCs1 Cyclone® V ST SoCs1

Product Line
5CSEA2 5CSEA4 5CSEA5 5CSEA6 5CSXC2 5CSXC4 5CSXC5 5CSXC6 5CSTD5 5CSTD6
LEs (K) 25 40 85 110 25 40 85 110 85 110
ALMs 9,430 15,880 32,070 41,910 9,430 15,880 32,070 41,910 32,070 41,910
Registers 37,736 60,376 128,300 166,036 37,736 60,376 128,300 166,036 128,300 166,036
Resources

M10K memory blocks 140 270 397 557 140 270 397 557 397 557
M10K memory (Kb) 1,400 2,700 3,970 5,570 1,400 2,700 3,970 5,570 3,970 5,570
MLAB memory (Kb) 138 231 480 621 138 231 480 621 480 621
Variable-precision DSP blocks 36 84 87 112 36 84 87 112 87 112
18 x 18 multipliers 72 168 174 224 72 168 174 224 174 224
Processor cores (Arm Cortex-A9) Single or dual Single or dual Single or dual Single or dual Dual Dual Dual Dual Dual Dual
Maximum CPU clock frequency (MHz) 925 925 925 925 925 925 925 925 925 925
Global clock networks 16 16 16 16 16 16 16 16 16 16
PLLs (FPGA)
2
5 5 6 6 5 5 6 6 6 6
Clocks, Maximum I/O Pins, and Architectural Features

PLLs (HPS) 3 3 3 3 3 3 3 3 3 3

I/O voltage levels supported (V) 1.1, 1.2, 1.5, 1.8, 2.5,3.3
VTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II),
I/O standards supported
Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12, HiSpi, SLVS, Sub-LVDS
Maximum LVDS pairs (receiver/transmitter) 37/32 37/32 72/72 72/72 37/32 37/32 72/72 72/72 72/72 72/72

Transceiver count (3.125 Gbps) – – – – 6 6 9 9 – –

Transceiver count (6.144 Gbps) – – – – – – – – 93 93

PCI Express hardened IP blocks (1.0) – – – – 2 2 24 24 – –

PCI Express hardened IP blocks (2.0) – – – – – – – – 2 2

GPIOs (FPGA) 145 145 288 288 145 145 288 288 288 288

GPIOs (HPS) 181 181 181 181 181 181 181 181 181 181

Hard memory controllers5 (FPGA) 1 1 1 1 1 1 1 1 1 1

Hard memory controllers5 (HPS) 1 1 1 1 1 1 1 1 1 1

Memory devices supported DDR3, DDR2, LPDDR2

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, and Transceiver Count

U484 pin 66, 151 66, 151 66, 151 66, 151
(19 mm, 0.8 mm pitch) 0 0 0 0

145, 181 145, 181 145, 181 145, 181 145, 181 145, 181 145, 181 145, 181
U672 pin 0 0 0 0 6 6 6 6
(23 mm, 0.8 mm pitch)

F896 pin 288, 181 288, 181 288, 181 288, 181 288, 181 288, 181
(31 mm, 1.0 mm pitch 0 0 9 9 9 9

Notes:
66, 151
1. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga. Values on top indicate available FPGA user I/O pins and HPS I/O pins; values at the bottom indicate the 3.125 Gbps or 5 Gbps transceiver count.
0
2. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs.
3. Transceiver counts shown are for ≤ 5 Gbps. The 6 Gbps channel count support depends on package and channel usage. Pin migration (same Vcc, GND, ISP, and input pins). User I/O pins may be less than labeled for pin migration.
Refer to Cyclone V Device Handbook Volume 2: Transceivers for guidelines.
4. One PCI Express hard IP block in U672 package. For SoCs: Pin migration is only possible if you use only up to 138 GPIOs.
5. With 16 and 32 bit ECC support.

48 Altera Product Catalog Altera Product Catalog 49

Devices: 60 nm Device Portfolio Devices: 60 nm Device Portfolio

Cyclone® IV FPGA Features View device ordering codes on page 60.

Cyclone® IV GX FPGAs1 Cyclone® IV E FPGAs1

Product Line
EP4CGX15 EP4CGX22 EP4CGX30 EP4CGX50 EP4CGX75 EP4CGX110 EP4CGX150 EP4CE6 EP4CE10 EP4CE15 EP4CE22 EP4CE30 EP4CE40 EP4CE55 EP4CE75 EP4CE115
LEs (K) 14 21 29 50 74 109 150 6 10 15 22 29 40 56 75 114
Resources

M9K memory blocks 60 84 120 278 462 666 720 30 46 56 66 66 126 260 305 432
Embedded memory (Kb) 540 756 1,080 2,502 4,158 5,490 6,480 270 414 504 594 594 1,134 2,340 2,745 3,888
18 x 18 multipliers 0 40 80 140 198 280 360 15 23 56 66 66 116 154 200 266
Clocks, Maximum I/O Pins, and Architectural Features

Global clock networks 20 20 20/30 30 30 30 30 10 10 20 20 20 20 20 20 20

PLLs 3 4 4/6 8 8 8 8 2 2 4 4 4 4 4 4 4

I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.0, 3.3

LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II),
I/O standards supported
Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12

Emulated LVDS channels 9 40 40 73 73 139 139 66 66 137 52 224 224 160 178 230

Maximum LVDS pairs, 840 Mbps

7/7 14/14 14/14 49/49 49/49 59/59 59/59 – – – – – – – – –
(receive/transmit)

Transceiver count2 (2.5 Gbps/3.124 Gbps) 2/0 2, 0 / 4, 0 4, 0 / 0, 43 0, 8 0, 8 0, 8 0, 8 – – – – – – – – –

PCI Express hardened IP blocks

1 1 1 1 1 1 1 – – – – – – – – –
(Base specification, Rev 1.1, 2.0, and so on)

Memory devices supported DDR2, DDR, SDR

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count and Transceiver Count

E144 pin4 – – – – – – – 91 91 81 79 – – – – –
(22 mm, 0.5 mm pitch)
M164 pin – – – – – – – – – 89 – – – – – –
(8 mm, 0.5 mm pitch)
M256 pin – – – – – – – – – 165 – – – – – –
(9 mm, 0.5 mm pitch)
U256 pin – – – – – – – 179 179 165 153 – – – – –
(14 mm, 0.8 mm pitch)
U484 pin – – – – – – – – – – – – 328 324 292 –
(19 mm, 0.8 mm pitch)
F169 pin 72 72 72 – – – – – – – – – – – – –
(14 mm, 1.0 mm pitch) 2 2 2

F256 pin – – – – – – – 179 179 165 153 – – – – –

(17 mm, 1.0 mm pitch)

F324 pin – 150 150 – – – – – – – – 193 193 – – –

(19 mm, 1.0 mm pitch) 4 4

F484 pin 290 290 290 270 270 – – 343 – 328 328 324 292 280
(23 mm, 1.0 mm pitch) 4 4 4 4 4

F672 pin – – – 310 310 393 393 – – – – – – – – –

(27 mm, 1.0 mm pitch) 8 8 8 8

F780 pin – – – – – – – – – – – 532 532 374 426 528

(29 mm, 1.0 mm pitch)
F896 pin – – – – – 475 475 – – – – – – – – –
(31 mm, 1.0 mm pitch) 8 8

Notes:
1. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga. 72 Values on top indicate available user I/O pins; values at the bottom indicate the 2.5 Gbps or 3.125 Gbps transceiver count.
2
2. Transceiver performance varies by product line and package offering.
3. EP4CGX30 supports 3.125 Gbps transceivers only in F484 package option. Pin migration (same Vcc, GND, ISP, and input pins). User I/Os may be less than labeled for pin migration.
4. Enhanced thin quad flat pack (EQFP).

50 Altera Product Catalog Altera Product Catalog 51

MAX CPLD Series MAX CPLD Series

MAX® V CPLD Features View device ordering codes on page 61.

MAX® V CPLDs1
Product Line
5M40Z 5M80Z 5M160Z 5M240Z 5M570Z 5M1270Z 5M2210Z
LEs 40 80 160 240 570 1,270 2,210
Resources

Equivalent macrocells2 32 64 128 192 440 980 1,700

Pin-to-pin delay (ns) 7.5 7.5 7.5 7.5 9.0 6.2 7.0
User flash memory (Kb) 8 8 8 8 8 8 8
Logic convertible to memory3 Yes Yes Yes Yes Yes Yes Yes
Internal oscillator       
Fast power-on reset       
Clocks, Maximum I/O Pins, and Architectural Features

Boundary-scan JTAG       
JTAG ISP       
Fast input registers       
Programmable register power-up       
JTAG translator       
Real-time ISP       
MultiVolt I/Os (V) 1.2, 1.5, 1.8, 2.5, 3.3 1.2, 1.5, 1.8, 2.5, 3.3, 5.04
I/O power banks 2 2 2 2 2 4 4
Maximum output enables 54 79 79 114 159 271 271
LVTTL/LVCMOS       
LVDS outputs       
32 bit, 66 MHz PCI compliant – – – – – 4 4
Schmitt triggers       
Programmable slew rate       
Programmable pull-up resistors       
Programmable GND pins       
Open-drain outputs       
Bus hold       
Package Options and I/O Pins5
E64 pin 54 54 54 – – – –
(9 mm, 0.4 mm pitch)
T100 pin6 – 79 79 79 74 – –
(16 mm, 0.5 mm pitch)
T144 pin6 – – – 114 114 114 –
(22 mm, 0.5 mm pitch)
M64 pin 30 30 – – – – –
(4.5 mm, 0.5 mm pitch)
M68 pin – 52 52 52 – – –
(5 mm, 0.5 mm pitch)
M100 pin – – 79 79 74 – –
(6 mm, 0.5 mm pitch)
M144 pin – – – – – – –
(7 mm, 0.5 mm pitch)
M256 pin – – – – – – –
(11 mm, 0.5 mm pitch)
U256 pin – – – – – – –
(14 mm, 0.8 mm pitch)
F100 pin – – – – – – –
(11 mm, 1.0 mm pitch)
F256 pin – – – – 159 211 203
(17 mm, 1.0 mm pitch)
F324 pin – – – – – 271 271
(19 mm, 1.0 mm pitch)

Notes:
1. All data is correct at the time of printing, and may be subject to change without prior notice. 4. An external resistor must be used for 5.0 V tolerance. 54 Number indicates available user I/O pins.
For the latest information, please visit www.intel.com/fpga. 5. For temperature grades of specific packages (commercial, industrial, or extended
2. Typical equivalent macrocells. temperatures), refer to Altera's online selector guide. Pin migration (same Vcc, GND, ISP, and input pins). User I/Os may be less than labeled for pin migration.
3. Unused LEs can be converted to memory. The total number of available LE RAM bits 6. Thin quad flat pack (TQFP).
depends on the memory mode, depth, and width configurations of the instantiated memory.

52 Altera Product Catalog Altera Product Catalog 53

 Ordering Codes

Ordering Codes
Ordering Information for Agilex™ 7 FPGAs F-Series, I-Series, and M-Series

Family Variant Transceiver Speed Grade Operating Temperature

1: Fastest E: Extended (TJ = 0 °C to 100 °C)

F: F-Series
2: Medium I: Industrial (TJ = -40 °C to 100 °C)
I: I-Series
M: M-Series 3: Slowest
Core Speed / Power

Speed: 1 Fastest − 4 Slowest

Power: V: Standard Power (VID)
E: Lower Power (VID)
X: Lowest Power (VID)
F: Fixed Voltage

Family Signature AG I C 040 R39A 2 E 2V ⱭⱭ Optional Suffix

AG: Agilex 7 FPGAs and SoCs Blank: Production build (RoHS 6)

B: Production build (RoHS 6),
supports 200/400 GbE Priority
Flow Control (F-Tile)
Specification Logic Density Package Code C: Production build (RoHS 6),
supports 200/400 GbE Priority
006: 573K logic elements F-Series Flow Control and 200G HIP block
Code HPS Crypto HBM2E Series R16A = 1546A F x2
008: 764K logic elements (F-Tile)
A No No None F, I, M 012: 1,178K logic elements R24B = 2486A P x1, E x1 R<n>: Engineering sample
B Yes No None F, I, M 014: 1,437K logic elements R24C = 2340A F x2 <n> identifies fabric/tile revision
019: 1,918K logic elements R24D = 2340A F x1 FP: FIPS compliance
C1 No Yes None F, I R25A = 2581A P x2, E x1 (AGF 019/023 package R25A only)
022: 2,208K logic elements
D1 Yes Yes None F, I 023: 2,308K logic elements R31C = 3184C F x4 ⱭⱭ: Custom (optional)
027: 2,692K logic elements I-Series
E Yes No 16 GB M
032: 3,245K logic elements R18A = 1805A R x1, F x1
F Yes No 32 GB M 035: 3,540K logic elements R29A = 2957A R x3, F x1
039: 3,851K logic elements R29D = 2957A R x3, F x1
G No No 16 GB M
040: 4,047K logic elements R31A = 3184A R x1, F x3
H No No 32 GB M 041: 4,000K logic elements R31B = 3184B F x4
R31E = 3184E R x2, Fx2
R39A = 3948A F x6
M-Series
R31B = 3184B F x4
R47A = 4700A F x3, R x1, HBM
1
Hard Crypto blocks supported in 019, 023, 035, 040, 041 logic density devices only R47B = 4700B F x4, HBM

Ordering Information for Agilex™ 5 FPGAs D-Series and E-Series

Family Variant Device Group Operating Temperature

D: D-Series A: 28G XCVR, with DDR5,VID E: Extended (TJ = 0 °C to 100 °C)

E: E-Series B: 17G XCVR, no DDR5, Fixed Voltage I: Industrial (TJ = -40 °C to 100 °C)

Core Speed

D-Series: 1 Fastest – 3 Slowest

E-Series: 1 Fastest – 6 Slowest

Power Grade

Family Signature A5 E A 005 A B15A E 2 V ⱭⱭ V: Standard Power (VID)

E: Lower Power (VID)
A5: Agilex 5 FPGAs and SoCs S: Standard Power (Fixed)
X: Lowest Power (Fixed)

Specification Logic Density Optional Suffix

αα: Special (optional)

Crypto 005: 50K logic elements
Code HPS Transceiver Series Rn: ES Device Revision number
Services 007: 69K logic elements Package Code Blank: Production build (RoHS6)
008: 85K logic elements
A No No No E
010: 103K logic elements
Quad 013: 138K logic elements Package Pins Pins Package
B No Yes E Code (D-Series) (E-Series) Size
HPS1 025: 252K logic elements
C No Yes No D, E 028: 282K logic elements B15A NA 351 pins 15 x 15 mm
031: 318K logic elements M16A NA 896 pins 16 x 16 mm
Quad 043: 434K logic elements
D Yes Yes D, E
HPS1 051: 515K logic elements B18A NA 474 pins 18 x 18 mm
Dual 052: 524K logic elements B23A NA 839 pins 23 x 23 mm
E No Yes E
HPS2 064: 644K logic elements
065: 656K logic elements B23B NA 795 pins 23 x 23 mm
G No No Yes3 E
B32A NA 1,591 pins 32 x 32 mm
1
Quad HPS = 2xA55 and 2xA76
2
Dual HPS = 2XA55 B23D 820 pins NA 23 x 23 mm
3
Enabled for B18A pkg only B32B 1,610 pins NA 32 x 32 mm
M = 0.5mm Micro Fineline BGA Package
B = Variable Pitch BGA Package

Altera Product Catalog 54

 Ordering Codes

Ordering Information for Agilex™ 3 FPGAs C-Series

Operating Temperature

E: Extended (TJ = 0 °C to 100 °C)

Family Variant Device Group I: Industrial (TJ = -40 °C to 100 °C)

C: C-Series B: Standard
Core Speed

C-Series: 6 Fastest – 7 Slowest

Power Grade

Family Signature A3 C W 100 B B23C I 6 S ⱭⱭ S: Standard Power

A3: Agilex 3 FPGAs and SoCs

Optional Suffix

Blank: Production build (RoHS6)

Specification Logic Density R<n>: Engineering sample
<n> identifies device revision
EMIF¹, MIPI², PUF³, 0255: 25K logic elements αα: Special (optional)
Code HPS Crypto 050: 50K logic elements
SPDM⁴ Attestation
065: 65K logic elements Package Code
W Yes Yes Yes 100: 100K logic elements
No 135: 135K logic elements
Y No Yes
Type Package Pins Package
Z No No No Code (C-Series) Size
M12A 484 pins 12 x 12 mm
MBGA6
1
External Memory Interface M16A9 896 pins 16 x 16 mm
2
Mobile Industry Processor Interface
B18A8 474 pins 18 x 18 mm
3
Physical Unclonable Function
4 Security Protocal and Data Model VPBGA7 B18B 538 pins 18 x 18 mm
5 A3C025 does not support EMIF and MIPI B23C9 931 pins 23 x 23 mm
6 0.5 mm Micro Fineline BGA Package
7 Variable Pitch BGA Package
8 B18A only supports specification Y and Z
9 Only M16A and B23C support transceiver

Ordering Information for Stratix® 10 (GX, SX, TX) Devices

SiP Tile Configuration

L: L-Tile
H: H-Tile Transceiver Speed Grade
E: E-Tile, or E-Tile + H-Tile
Fast Slow Operating Temperature
Logic Density
1 2 3
C: Commercial (TJ = 25 °C to 85 °C)
040 : 400K logic elements
E: Extended (TJ = 0 °C to 100 °C)
065 : 650K logic elements
I: Industrial (TJ = -40 °C to 100 °C)
085 : 850K logic elements
110 : 1,300K logic elements
165 : 1,650K logic elements
166 : 1,660K logic elements
210 : 2,100K logic elements Power Profile
211 : 2,110K logic elements
250 : 2,500K logic elements V: Standard Power (VID)
280 : 2,800K logic elements L: Low Power (Fixed voltage)
10M: 10,200K logic elements X: Extreme Low Power (Fixed voltage)

Family Signature 1S G 280 L N 2 F 43 I 2 V G S1 Optional Suffix

1S: Stratix 10 Engineering Sample S(n)

Advanced Security AS
Family Variant

G: GX FPGA Transceiver Count

X: SX SoC FPGA with Package Material
Arm Cortex-A53
T: TX FPGA H: 24 Package Type
G: RoHS 6
N: 48
S: 72 F: Fine line BGA
U: 96
Y: 144 Package Code FPGA Fabric Speed Grade

35: 1,152 Pins, 35x35 mm

43: 1,760 Pins, 42.5x42.5 mm Fast Slow
50: 2,397 Pins, 50x50 mm 1 2 3
55: 2,912 Pins, 55x55 mm
74: 4938 Pins, 70x74 mm

Altera Product Catalog 55

 Ordering Codes

Ordering Information for Stratix® 10 (DX) Devices

Transceiver Speed Grade

Fast Slow
Transceiver Tile SiP Configuration 1 2 3

P: P-Tile + E-Tile Operating Temperature

E: Extended (TJ = 0 °C to 100 °C)

I: Industrial (TJ = -40 °C to 100 °C)

Family Variant

D: DX FPGA Power Option

V: Standard Power (VID)

Family Signature 1S D 280 P T 2 F 55 E 1 V G S1 Optional Suffix

1S: Stratix 10 Engineering Sample S(n)

RoHS

G: RoHS 6
Logic Density + HBM2 Package Type

110 : 1,300K logic elements

F: Fine line BGA FPGA Fabric Speed Grade
280 : 2,800K logic elements

Transceiver Count Package Body Size Fast Slow

1 2 3
J: 32 43: 1,760 pins, 42.5x42.5 mm
T: 84 53: 2,597pins, 52.5x52.5 mm
55: 2,912pins, 55x55 mm

Ordering Information for Arria® 10 (GX, SX, GT) Devices

Package Type Power Profile

Transceiver Count
F: FineLine BGA H: High-Performance
U: Ultra Fineline BGA Power
C: 6
Operating Temperature S: Standard Power
E: 12
L: Low Power
H: 24
E: Extended (TJ = 0 °C to 100 °C) V: Smart Voltage ID
K: 36
I: Industrial (TJ = -40 °C to 100 °C) (Smart VID)
N: 48
R: 66 M: Military (Ta = -55 °C to TJ =125 °C)1
S: 72
U: 96

Family Signature 10A X 057 K 2 F 40 E 2 S G ⱭⱭ Optional Suffix

10A: Arria 10 ES: Engineering Sample

ⱭⱭ: Custom (optional)
Package Code
Family Variant
19: 484 pins Package Material
X: Up to 17.4 Gbps transceivers 27: 672 pins
S: SoC with up to 17.4 Gbps transceivers 29: 780 pins
P: Leaded
T: Up to 25.78125 Gbps transceivers 34: 1,152 pins
G: RoHS 6
35: 1,152 pins
40: 1,517 pins
Device Type 45: 1,932 pins
FPGA Fabric Speed Grade

10AX: 016, 022, 027, 032, 048, 057, 066, 090, 115 Transceiver
Fast Slow
10AS: 016, 022, 027, 032, 048, 057, 066 Speed Grade
10AT: 090, 115 1 2 3
Fast Slow
1 2 3 4

1
For details, refer to the Arria® 10 Military Temperature Range Support Technical Brief.

Altera Product Catalog 56

 Ordering Codes

Ordering Information for Cyclone® 10 Devices

Core Voltage Package Code

Y = Standard voltage 36: 36 pins

- GX = 0.9 V 81: 81 pins
Family Variant - LP = 1.2V 144: 144 pins
Z = Low Voltage1 153: 153 pins
X : GX - LP = 1.0V 169: 169 pins
L : LP 324: 324 pins
256: 256 pins
484: 484 pins
Family Signature 10C X 085 Y U 484 I 5 G ⱭⱭ 672: 672 pins

10C : Cyclone 10
Optional Suffix

ⱭⱭ: Custom (optional)

Device Type
G : RoHS 6
GX: 085, 105, 150, 220 Package Material
P : Leaded
LP: 006, 010, 016, 025, 040, 055, 080, 120

FPGA Fabric Speed Grade

Package Type Operating Temperature 5 : Fastest

8 : Slowest
E: Enhanced Quad Flat Pack (EQFP) C: Commercial (TJ = 0° C to 85° C)
M: Micro FineLine BGA (MBGA) E: Extended (TJ = 0° C to 100° C)
U: Ultra FineLine BGA (UBGA) I: Industrial (TJ = -40° C to 100° C)
F: FineLine BGA (FBGA) I: Extended Industrial1 (TJ = -40° C to 125° C)2
A: Automotive1 (TJ = -40° C to 125° C)

11
Only available
Only availableononIntel
Cyclone®
Cyclone1010
LP.
LP
22
For details,
For details,refer
refertotothe
theExtended
Extended Temperature
Temperature Device
Device Support
Support webweb page.
page.

Ordering Information for MAX® 10 Devices

Feature Options Package Type

SC: Single supply - compact features V, Y: Wafer-level chip scale package (WLCSP)
SA: Single supply - analog and flash features with E: Enhanced Quad Flat Pack (EQFP)
RSU option M: Micro FineLine BGA (MBGA)
SL: Single supply - flash features with RSU option U: Ultra FineLine BGA (UBGA)
DC: Dual supply - compact features F: FineLine BGA (FBGA)
DF: Dual supply - flash features with RSU option B: Variable Pitch BGA (VPBGA)
DA: Dual supply - analog and flash features with
RSU option
DD: Dual supply - analog and flash features with Operating Temperature
RSU option and flash access control1
C: Commercial (TJ = 0 ˚C to 85 ˚C)
I: Industrial (TJ = –40 ˚C to 100 ˚C)
Family Signature 10M 16 DA U 484 I 7 G ⱭⱭ A: Automotive (TJ = –40 ˚C to 125 ˚C)

10M: MAX 10
Optional Suffix

Logic Density ES: Engineering Sample

ⱭⱭ: Custom (optional)
02: 2K logic elements
04: 4K logic elements
08: 8K logic elements Package Code
Package Material
16: 16K logic elements
25: 25K logic elements 36: 36 pins
40: 40K logic elements 81: 81 pins G: RoHS 6
50: 50K logic elements 144: 144 pins FPGA Fabric Speed Grade P: Leaded
153: 153 pins
169: 169 pins 6 (fastest)
180: 180 pins 7
324: 324 pins 8
256: 256 pins
484: 484 pins
610 : 610 pins
672: 672 pins

1
DD OPN available only on 10M40 and 10M50 devices with F256, F484, B610 and F672 packages.

Altera Product Catalog 57

 Ordering Codes

Ordering Information for Arria® V (GT, GX, GZ) Devices

Transceiver Count

D: 9 (Arria V GX and GT devices only)

E: 12 (Arria V GZ devices only)
Package Type
G: 18 (Arria V GX and GT devices only)
H: 24
F: FineLine BGA
K: 36
H: Hybrid FineLine BGA

Embedded Hard IP Blocks Operating Temperature

5AGX: B, M, F C: Commercial (TJ = 0 °C to 85 °C)

5AGT: M, F I: Industrial (TJ = –40 °C to 100 °C for I5)
5AGZ: M (TJ = –40 °C to 100 °C for I3)

Family Signature 5A GZ M A5 K 2 F 40 I 3 LG Optional Suffix

5A : Arria V G: RoHS 6
P: Leaded
Family Variant L: Low-power device
Package Code
GX: 6-Gbps transceivers Member Code 27: 672 pins
GT: 10-Gbps transceivers 29: 780 pins
GZ: 12.5-Gbps transceivers GX GT GZ (Arria V GZ FPGAs only)
A1 C3 E1 Transceiver Speed Grade 31: 896 pins FPGA Fabric Speed Grade
A3 C7 E3 35: 1,152 pins
A5 D3 E5 40: 1,517 pins
For Arria V GX FPGAs only Fast Slow
A7 D7 E7 4: 6.5536 Gbps Devices 1 2 3 4 5 6 7 8
B1 6: 3.125 Gbps
B3 Arria V GX    
B5
For Arria V GT and GZ FPGAs only Arria V GT  
B7
3: 10.3125 Gbps  
Arria V GZ

For Arria V GZ FPGAs only

2: 12.5 Gbps
3: 10.3125 Gbps

Ordering Information for Arria® V (SX, ST) SoCs

Transceiver Count
Package Type
D: 9 (Arria V SX devices only)
E: 12 F: FineLine BGA
G: 18
H: 30 (Arria V SX devices only)
K: 30 (Arria V ST devices only) Operating Temperature

Embedded Hard IP Blocks C: Commercial (TJ = 0 ˚C to 85 ˚C)

I: Industrial (TJ = –40 ˚C to 100 ˚C)
5ASX: B, M, F
5AST: M, F
Family Signature 5A ST F D5 K 3 F 40 I 5 G Optional Suffix

5A : Arria V G: RoHS 6
Family Variant

SX: 6 Gbps transceivers Package Code

ST: 10 Gbps transceivers Member Code
FPGA Fabric Speed Grade
31: 896 pins
SX ST
Transceiver 35: 1,152 pins
B3 D3 40: 1,517 pins Fast Slow
Speed Grade
B5 D5 Devices 1 2 3 4 5 6 7 8
For Arria V SX FPGAs only Arria V SX    
6: 3.125 Gbps Arria V ST  
For Arria V SX FPGAs only
4: 6.5336 Gbps

For Arria V ST FPGAs only

3: 10.3125 Gbps

Altera Product Catalog 58

 Ordering Codes

Ordering Information for Cyclone® V (E, GX, GT) Devices

Package Type
Transceiver Count
F: FineLine BGA
U: Ultra FineLine BGA
B: 3
M: Micro FineLine BGA
F: 4
A: 5
C: 6
Embedded Hard IP Blocks D: 9 Operating Temperature
E: 12
A: Automotive (TJ = –40 ˚C to 125 ˚C)
5CE: B, F
C: Commercial (TJ = 0 °C to 85 ˚C)
5CGX: B, F
I: Industrial (TJ = –40 ˚C to 100 ˚C)
5CGT: F

Family Signature 5C GX B C3 B 6 F 23 C 7 N Optional Suffix

5C: Cyclone V N: Lead-free packaging

Family Variant

E: Enhanced logic/memory Package Code

GX: 3 Gbps transceivers Member Code
FPGA Fabric Speed Grade
GT: 6 Gbps transceivers
E GX GT 11: 301 pins
Transceiver 13: 383 pins
A2 C3 D5 Speed Grade 15 (M): 484 pins Fast Slow
A4 C4 D7 15 (U): 324 pins Devices 1 2 3 4 5 6 7 8
A5 C5 D9 17: 256 pins
A7 C7 For Cyclone V GX FPGAs only Cyclone V GT 
19: 484 pins
A9 C9 6: 3.125 Gbps Cyclone V GX   
23: 484 pins
7: 2.5 Gbps
27: 672 pins Cyclone V E   
31: 896 pins
For Cyclone V GT FPGAs only
35: 1,152 pins
5: 6.144 Gbps

Ordering Information for Cyclone® V (SE, SX, ST) SoCs

Package Type Operating Temperature

F: FineLine BGA C : Commercial (TJ = 0 °C to 85° C)

U: Ultra FineLine BGA I : Industrial (TJ = -40° C to 100° C)
A : Automotive (TJ = -40° C to 125° C)
Transceiver Count

C: 6
D: 9 Processor Cores

Embedded Hard IP Blocks For Cyclone V SE FPGAs only

S: Single-core
5CSE: B, M
5CSX: F
5CST: F

Family Signature 5C SX F C6 C 6 U 23 I 7 S L N TS TSN Enabled Device

5C: Cyclone® V
For Cyclone® V SE/SX FPGAs only
TS : TSN-enabled device

Family Variant Optional Suffix

SE: SoCs with enhance logic/memory Package Code N : Lead-free packaging

SX: SoCs with 3-Gbps transceivers SC : SEU scrubbing or partial
ST: SoCs with 6-Gbps transceivers 19: 484 pins reconfiguration support
23: 672 pins
31: 896 pins
Member Code
Power Option
SE SX ST Transceiver
Speed Grade FPGA Fabric Speed Grade For Cyclone® V SE/SX FPGAs only
A2 C2 D5 L : Low
A4 C4 D6
A5 C5 For Cyclone® V SX/ST FPGAs only Fast Slow
A6 C6 5: 6.144 Gbps
Devices 1 2 3 4 5 6 7 8
6: 3.125 Gbps
Cyclone® V SE   
Cyclone® V SX   
Cyclone® V ST 

Altera Product Catalog 59

 Ordering Codes

Ordering Information for Cyclone® IV GX Devices

Package Type
Member Code
F: FineLine BGA (FBGA)
15: 14,400 logic elements N: Quad Flat Pack No Lead (QFN)
22: 21,280 logic elements
30: 29,440 logic elements
50: 49,888 logic elements Operating Temperature
75: 73,920 logic elements
110: 109,424 logic elements C: Commercial (TJ = 0 °C to 85 ˚C)
150: 149,760 logic elements I: Industrial (TJ = –40 ˚C to 100 ˚C)

Family Signature EP4C GX 30 C F 19 C 7 N Optional Suffix

EP4C: Cyclone IV Indicates specific device

options or shipment method
N: Lead-free packaging
Family Variant

GX: 3 Gbps transceivers Package Code Speed Grade

FBGA Package Type 6 (fastest)

Transceiver Count 14: 169 pins 7
19: 324 pins 8
B: 2
23: 484 pins
C: 4
27: 672 pins
D: 8
31: 896 pins

Ordering Information for Cyclone® IV E Devices

Package Type

F: FineLine BGA (FBGA)

E: Enhanced Thin Quad Flat Pack (EQFP)
U: Ultra FineLine BGA (UBGA) Operating Temperature
M: Micro FineLine BGA (MBGA)
C: Commercial (TJ = 0 °C to 85 ˚C)
I: Industrial (TJ = –40 °C to 100 ˚C)
Family Variant Extended Industrial (TJ = –40 °C to 125 ˚C)1
A: Automotive (TJ = –40 °C to 125 ˚C)
E: Enhanced logic / memory

Family Signature EP4C E 40 F 29 C 8 LN Optional Suffix

EP4C: Cyclone IV Indicates specific device

Package Code options or shipment method
N: Lead-free packaging
Member Code
L: Low-voltage device
FBGA Package Type
6: 6,272 logic elements 17: 256 pins
10: 10,320 logic elements 19: 324 pins
15: 15,408 logic elements 23: 484 pins
22: 22,320 logic elements 29: 780 pins Speed Grade
30: 28,848 logic elements
EQFP Package Type 6 (fastest)
40: 39,600 logic elements
22: 144 pins 7
55: 55,856 logic elements
75: 75,408 logic elements UBGA Package Type 8
115: 114,480 logic elements 14: 256 pins 9
19: 484 pins
MBGA Package Type
8: 164 pins
9: 256 pins

1
For details, refer to the Extended Temperature Device Support web page.

Altera Product Catalog 60

 Ordering Codes

Ordering Information for MAX® V Devices

Package Type Operating Temperature

T: Thin quad flat pack (TQFP) C: Commercial (TJ = 0 °C to 85 ˚C)

F: FineLine BGA (FBGA) I: Industrial (TJ = –40˚C to 100 ˚C)
M: Micro FineLine BGA (MBGA) Extended Industrial (TJ = -40 to 125˚C)1
E: Plastic Enhanced Quad Flat Pack (EQFP) A: Automotive (TJ = –40˚C to 125 ˚C)

Family Signature 5M 40Z E 64 C 4 N Optional Suffix

5M: MAX V Indicates specific device

options or shipment method
Device Type N: Lead-free packaging

40Z: 40 Logic Elements Pin Count Speed Grade

80Z: 80 Logic Elements
160Z: 160 Logic Elements
Number of pins for a 4 or 5, with 4 being
240Z: 240 Logic Elements
particular package the fastest
570Z: 570 Logic Elements
1270Z: 1,270 Logic Elements
2210Z: 2,210 Logic Elements

1
For details, refer to the Extended Temperature Device Support web page.

Altera Product Catalog 61

 Acceleration Platform or Card Solutions

Acceleration Card Solutions

Accelerate your data center, cloud, or network infrastructure with a portfolio of Altera and partner infrastructure processing units
(IPUs) and SmartNICs. These acceleration solutions are enabled by Altera's latest FPGA technology, and designed then qualified
for large volume deployments. Altera, third-party, and proprietary cards, such as the Intel FPGA IPU F2000X-PL Platform, Intel
FPGA SmartNIC N6000-PL Platform, and Silicom FPGA SmartNIC N5010 Series, are supported by next-generation platform
software – Open FPGA Stack (OFS). Altera's wide portfolio of platforms, cards, and software solutions enable your workloads to
be efficiently developed, scaled, and deployed.

Intel FPGA SmartNIC and IPU Platforms

Intel FPGA SmartNIC and IPU platforms are delivered in two ways: as production-ready solutions and as platform designs.
Production-ready solutions can be purchased from Altera partners who offer commercial off-the-shelf production cards and
solutions. OFS and baseboard management controller (BMC) design files are available from partners to accelerate workload
development.
Customers who wish to accelerate their own custom board design can leverage an Intel FPGA SmartNIC or IPU Platform,
consisting of board design files, OFS, BMC design files, documentation, and a pre-production board. To get started, contact your
Iocal Altera sales representative to learn more.

DDR4x1CH
DDR4 4x16 DDR4 4x16 16GB
8GB 8GB

SFP28 2x25G

PCIe 3.0 x8

SFP28 2x25G

Stratix® 10 DX 1100 Intel® Xeon® D-1612

SATA 3.0

PCIe 4.0 x8 32GB

BGA SSD

FPGA IPU F2000X-PL Platform IPU Platform C5000X-PL is Intel FPGA SmartNIC N6000-PL
is an Agilex FPGA and Intel an Stratix 10 FPGA and Intel Platform is Intel's 3rd generation
Xeon processor-based platform Xeon processor-based cloud SmartNIC providing 2x100 Gbps
for high-performance cloud infrastructure acceleration platform Ethernet connectivity and 1588v2
acceleration. It offers 2x100 with 2x25GbE network interfaces. Precision Time Protocol (PTP)
GbE network interfaces and Production-ready solutions are synchronization for O-RAN/
accelerates cloud infrastructure available through Silicom and Broadcast in a FHHL PCIe form
workloads such as Open vSwitch Inventec. factor. Available workloads include
(OvS), Non-Volatile Memory 5G Virtualized Radio Access
Express over Fabrics (NVME- Network (vRAN), Accelerated
oF*), and Remote Direct Memory Virtual Cell Site Router (vCSR),
Access (RDMA) over Converged 5G User Plane Function (UPF),
Ethernet v2. Leverage FPGA and SMTE ST2110 Offload with
programmability through OFS JPEG-XS.
with Infrastructure Programmer
Development Kit (IPDK), Data
Plane Development Kit (DPDK), or
Storage Performance Development
Kit (SPDK). Production-ready
solutions are currently available
from Napatech.

Altera Product Catalog 62

 Acceleration Platform or Card Solutions

Partner FPGA SmartNIC and IPU Production Ready Solutions

Based on the FPGA IPU F2000X-PL Platform Based on the FPGA IPU C5000X-PL Platform

Napatech FPGA IPU F2070X adapter is an IPU Silicom FPGA IPU C5010X and Inventec FPGA IPU
based on the Agilex and Intel Xeon D processor, C5020X adapters are Intel Xeon D processor, SoC +
offering both software and hardware programmable FPGA cards offering a hardware programmable data
data path with 2x100 GbE support and PCIe 4.0 x path with 50G connectivity. With these IPUs, cloud
16 host interface. With these IPUs, cloud service service providers can improve server core utilization
providers can improve server core utilziation by by offloading vSwitch and storage using IA-optimized
offloading vSwitch and storage functions using IA- DPDK and SPDK.
optimzied DPDK and SPDK.

Based on the FPGA SmartNIC N6000-PL Platform Silicom FPGA SmartNIC N5010 is the first hardware
programmable 4x100 GbE FPGA SmartNIC enabling
next-generation IA-based servers to meet the
Artiza Networks Griffin N6060/N6061, Silicom performance needs of the 4/5G Core User Plane
FPGA SmartNIC N6010/N6011, and WNC FPGA Function/Access Gateway Function. Its
SmartNIC WSN6050 series are high-performance re-programmability can support Virtual Broadband
Agilex 7 FPGA F-Series based SmartNICs. These Network Gateway, Virtualized Evolved Packet Core,
platforms provide 2x100 GbE connectivity and Internet Protocol Security, vFirewall, Segment Routing
1588v2 PTP synchronization for acceleration of Version, and Vector Packet Processing workload
communication workloads such as 5G vRAN, vCSR, capability.
UPF, and ST2110 Offload.

Product descriptions and datasheets for partner SmartNIC and IPU Acceleration Platforms can be found in the Intel® Solution Marketplace or on the Artiza Networks,
Silicom, Inventec, and WNC websites, and are not in this catalog.

Altera Product Catalog 63

 Acceleration Platform or Card Solutions

Platform Software
OFS is the first complete hardware and software infrastructure that is fully open sourced and comprises composable hardware
code and upstreamed kernel code to kernel.org to enable a collaborative community of FPGA developers. OFS provides an
efficient approach to customize your own unique acceleration platform solutions using an Altera, 3rd party, or custom board.

All source code and technical documentation is open source in the OFS GitHub and enables development using the Stratix 10
FPGA and Agilex FPGA. To get started, access the OFS GitHub Repositories at www.github.com/OFS or browse our Board
Catalog to view all OFS-enabled boards.

Why Choose Altera FPGAs for Acceleration Applications?

Ease of Deployment Standardization Wide-range of Solutions

Find validated and qualified Intel Help eliminate complexity and Discover what FPGAs can do for your
FPGA SmartNIC and IPU platforms enable application portability by business with the broad portfolio
through several leading original leveraging the standard hardware of acceleration solutions from
equipment manufacturers (OEMs). and software interfaces provided by technology experts.
the Altera platform or card software.

Faster Time to
Customization Deployment Portability

Create customer platform or Experience faster time to deployment Achieve greater design portability
card solutions using source- with native support for OFS by leading through industry-standard interface
accessible OFS hardware and open-source software distribution support and reusable OFS Standard
software code. vendors. APIs.

Altera Product Catalog 64

 Acceleration Platform or Card Solutions

Open FPGA Stack

Open FPGA Stack (OFS) is an open-source hardware and software infrastructure delivered
through git repositories that enables you to customize your own unique acceleration platform
or workload solutions. OFS provides a starting point and reference infrastructure for custom
design by delivering a framework of synthesizable code, a simulation environment, and scripts
that can be taken as-is or modified. All OFS source code and technical documentation is open
source on GitHub at github.com/OFS. Hardware developers can try out OFS on one of the reference platforms including the
Agilex 7 FPGA F-Series Development Kit, Agilex 7 FPGA I-Series Development Kit, Intel FPGA IPU F2000X Platform, or Intel
FPGA SmartNIC N6000 Platform before porting to their own boards. Application developers can choose between OFS reference
platforms or use the OFS Board Catalog to browse OFS-enabled boards from our ecosystem partners.

OFS provides multiple benefits to hardware, software, and application design engineers:

OFS Feature Board Developer Software Developer Application Developer

Inherit an ecosystem of Open FPGA Stack-based boards,

  
workloads, and OS distributors

Accelerate software development by leveraging software

drivers upstreamed to the Linux* kernel and Open Programmable  
Acceleration Engine (OPAE) software and libraries

Accelerate workload development with industry-standard

Arm AMBA AXI and Avalon compliant bus interfaces, workload  
examples, and simulation

Accelerate your verification and validation with automated build

scripts, a United Verification Methodology (UVM) environment, 
and a suite of unit test cases

Customize your FPGA design (FIM) with modular and


composable source code

Get Started Today with OFS

Two Routes of Development

Using an OFS reference platform OR Using a custom or 3rd party board

Agilex™ FPGA
Agilex™ 7 FPGA I-Series Development Kit
Agilex™ 7 FPGA F-Series Development Kit
Step 1: Choose a board Intel IPU F2000X-PL Platform Browse the OFS Board Catalog at www.intel.com/OFS
Intel FPGA SmartNIC N6001PL-Platform

Stratix® 10 FPGA

Step 2: Evaluate OFS Technical documentation can be referenced on GitHub Board vendor will provide a corresponding version of
open-source resources pages www.ofs.github.io OFS technical documentation

Step 3: Access open-source Modify or use the provided OFS software or hardware Board vendor will provide corresponding OFS software
hardware and software code code available at www.github.com/OFS or hardware code

Follow the OFS RTL flow

Step 4: Develop workload
OR
using RTL or C/C++
Utilize the oneAPI development flow and build FPGA workloads in C/C++

Altera Product Catalog 65

 Acceleration Platform or Card Solutions

FPGA IPU F2000X-PL

The FPGA IPU F2000X-PL is a high-performance Agilex and Intel Xeon D processor based IPU platform providing networking
and storage acceleration for cloud and communication service providers. The F2000X-PL offers 2x100GbE network interface and
accelerates cloud workloads such as Open vSwitch, NVMe over Fabrics, and RDMA over Converged Ethernet, and has hardware
crypto blocks to enhance security. It offers FPGA re-programmability through IPDK, DPDK, SPDK, and OFS.

Targeted Workloads
• Open vSwitch (OvS)
• NVMe-oF
• RDMA over Converged Ethernet v2 (RoCEv2)
• Packet processing
• Cryptographic acceleration
• Security

Hardware Power management

Agilex 7 FPGAs F-Series • Intelligent system power management with real-time
• 2,300K logic elements telemetry and health monitoring
• 222 Mb on-chip memory
• 3,200 DSP blocks Software
Intel Xeon D processor • IPDK
• 8 core Processor • DPDK
• 15 MB cache • SPDK
• Up to 3.4 GHz • OFS1
Onboard memory 1
An open-source OFS-based FIM is available. For more
• 16 GB DDR4 (to FPGA and processor) information, visit the OFS GitHub.
Interfaces
• PCIe 4.0 x16 host interface
• 2X QSFP with up to 2x100 GbE configuration
Ordering Information
Form factor
• ¾ length, full height; single slot Please visit the FPGA IPU F2000X-PL product page to see
Board management the list of partners with production ready solutions.
• Cyclone 10 LP FPGA Board Management Controller
(BMC)
- Temperature and voltage readout Platform Level Data
Model (PLDM)
• Full security implementation using MAX 10 FPGA as RoT
• Remote update capabilities for FPGA flash memory and
BMC

Altera Product Catalog 66

 Acceleration Platform or Card Solutions

FPGA IPU C5000X-PL

The FPGA IPU C5000X-PL Platform is a high-performance, Intel Xeon D processor and Stratix 10 FPGA-based, cloud
infrastructure accelerator. It supports up to 50G network connectivity and accelerates cloud and telco cloud infrastructure
workloads such as Open vSwitch, NVMe over Fabrics, and RDMA over Converged Ethernet v2. Cloud service providers can
take advantage of a large software ecosystem including software tools such as Virtio-net and DPDK or SPDK. Workloads can be
optimized in bare metal, virtualized cloud, and bare metal virtualization deployments. The development platform is available from
Altera, and production ready partner solutions are available from Silicom and Inventec.

DDR4x1CH
DDR4 4x16 DDR4 4x16 16GB
8GB 8GB

SFP28 2x25G

PCIe 3.0 x8

SFP28 2x25G

Stratix® 10 DX 1100 Intel® Xeon® D-1612

SATA 3.0

PCIe 4.0 x8 32GB

BGA SSD

Targeted Workloads
• Open vSwitch
• NVMe-oF
• RDMA over Converged Ethernet v2 (RoCEv2)
• Security

Hardware Software
Stratix 10 DX FPGA • DPDK/BBDev
• 1,325K logic elements • SPDK
• 114 Mb on-chip memory • OPAE
• 5,184 DSP blocks
Intel Xeon D-1612 processor Design Entry Tools
• 4 core • Quartus Prime Pro Edition Software
• 6 MB cache
• Up to 2.5 GHz Ordering Information
Onboard memory
Buy now from:
• 20 GB DDR4
• 1.25 Gb flash • Inventec, Silicom
Interfaces
• PCIe 3.0 x8 or 4.0 x8 host interface
• 4-8 core Intel Xeon D processor
• Up to 2x25 GbE configuration
Form factor/thermal/power
• ½ length, full height
• 75 W for key applications
Board management
• Full security implementation using BMC as RoT
• Remote update capabilities for FPGA flash memory and
BMC
Power management
• Intelligent system power management with real-time
telemetry and system health monitoring
Altera Product Catalog 67
 Acceleration Platform or Card Solutions

Intel FPGA SmartNIC N6000-PL Platform

The Intel FPGA SmartNIC N6000-PL Platform is the 3rd generation Agilex 7 FPGA family-based SmartNIC for network
acceleration. It supports 2x100 Gbps Ethernet connectivity and 1588v2 PTP synchronization, boasting higher performance, TCO
optimization, and scalability compared to previous generations. Agilex 7 FPGAs are built with Intel's advanced 10 nm SuperFin
technology and a second-generation Hyperflex FPGA Architecture. Agilex 7 devices deliver ~2X better fabric performance per
watt compared to competing 7 nm FPGAs.
The Intel FPGA SmartNIC N6000-PL Platform is delivered in two ways:
As Production-ready Solutions: Customer who wish to deploy commercial off-the-shelf N6000 based-SmartNIC as-is, can buy
N6000-based production cards and solutions from Intel's partners. Open FPGA Stack (OFS) and BMC design files are available
from partners to accelerate the workload development
As Platform Design: Customers who wish to accelerate their own custom board design by leveraging the N6000 board design and
customizing to add their own differentiation can use the Intel FPGA SmartNIC N6000-PL Platform, consisting of board design
files, OFS stack, BMC design files, documentation, and a pre-production board. Contact your local Altera sales representative to
learn more.
Workloads Available: 4G/5G Virtualized Radio Access Network (vRAN), Virtual Cell Site Router (vCSR), 5G User Plane Function
(UPF), SMPTE ST2110 Professional Media over Managed IP Networks, and more. Contact Altera sales representative or Altera's
partners for the workloads.

Targeted Workloads
• vRAN/Open RAN (O-RAN)
• 5G UPF
• vCSR
• SMPTE ST2110 Professional Media over Managed IP Networks

Altera Product Catalog 68

 Acceleration Platform or Card Solutions

Hardware Software
Agilex 7 FPGAs F-Series • DPDK
• High-performance F-Series, multi-gigabit SERDES • FlexRAN/BBDEV(pf-bb-config) - only for vRAN
transceivers up to 58 Gbps • OPAE
• 1,437K logic elements • OFS
• 190 Mb on-chip memory
• 4,510 DSP blocks Design Entry Tools
Onboard memory • Quartus Prime Pro Edition Software
• 16 GB DDR4 to FPGA
• 1 GB DDR4 to HPS Ordering Information
Interfaces Production card (ready-to-deploy COTS board): Available now
• PCIe 4.0 bifurcated x8/x8 (N6000) Buy now from:
• PCIe 4.0 x16 (N6001) • Artiza Networks
• Intel® Ethernet Controller E810-CAM2 (N6000) • Silicom
• 2X QSFP with up to 2x100 GbE support • Winston NeWeb Corp (WNC)
(2x1x100G, 2x2x50G, 2x4x25G, 2x4x10G)
For Intel FPGA SmartNIC N6000-PL Platform Design
• Supports SyncE, CPRI, eCPRI
(customizing board design)
• Front panel SMA for IEEE1588 1pps/10 MHz and master
• Contact Altera sales representative
clocking
• O-RAN LLS-C1, -C2, -C3 support
Form factor/thermal/power
• FHHL, single slot; passively cooled
• N6000 < 100W, N6001 < 75W
• NEBS Class 1 compliance support
Board management
• MAX 10 FPGA BMC
• Full security implementation using MAX 10 FPGA as
RoT
• Remote update capabilities for FPGA flash memory and
BMC
• Full card BMC solution host communication via SMBus
and PCIe VDM
Power management
• Intelligent system power management with real-time
telemetry and system health monitoring
Timing Synchronization
• IEEE 1588v2 support for PRTC/T-GM, T-BC, T-TSC,
T-TC
• O-RAN S-Plane PTP support (G.8275.1) for LLS-C1, -C2,
-C3, -C4
• Support for Synchronous Ethernet (SyncE)
• Class B frequency and phase timing accuracy
• Integrated OCXO for holdover performance
• Timing interface for local PRTC support for ToD with
1 PPS/10MHz SMA connectors

Altera Product Catalog 69

 Acceleration Platform or Card Solutions

Accelerated Workload Solutions

Altera’s broad ecosystem enables leading providers to offer a variety of accelerator functions best suited for FPGA acceleration.
A number of these providers have complete solutions enabled for Altera FPGA-based PACs, IPUs, and SmartNICs, ranging from
NFV, network security and monitoring, data analytics, AI, and more.

Networking and Wireless Application Workloads

Virtualized Radio 5G User Plane

Virtualized Data Plane Virtual Cell-site
Access Network Function (5G UPF)
Acceleration Router (vCSR)
(vRAN)

Enterprise and Cloud Application Workloads

Packet Monitoring Storage

Data Analytics Artificial Intelligence
and Cyber Security

Media Processing Financial Services Genomics

(FSI)

Browse Intel Partner Showcase

Or visit the following website for various partner acceleration solutions:

www.intel.com/content/www/us/en/products/details/fpga/platforms.html

Altera Product Catalog 70

 Acceleration Platform or Card Solutions

Acceleration Card Comparison

Silicom FPGA SmartNIC IPU C5000X-PL FPGA SmartNIC FPGA IPU
Features
N5010 Platform N6000-PL Platform F2000X-PL Platform
SmartNIC for SmartNIC for
Category
Product

Target Market IPU for CSP IPU for CSP

Communications Communications
Intel SmartNIC
Type Partner card Partner card Intel FPGA IPU
Platform
Agilex™ 7 FPGA Agilex™ 7 FPGA
FPGA Stratix 10 DX Stratix 10 DX
F-Series F-Series
Resources
FPGA

Logic Elements 2,073K 1,325K 1,437K 2,300K

On-chip Memory 240 Mb 114 Mb 190 Mb 222 Mb
DSP Blocks 7,920 5,184 4,510 3,200
Processor

Intel Xeon D-1612 Quad-core 64-bit Arm

Type - 8-core Intel Xeon-D SoC
Processor Cortex-A53 Processor

16 GB FPGA, 16 GB FPGA,
DDR4 32 GB 20 GB
1 GB Processor 16 GB SoC
Memory

SRAM 144 Mb QDR IV - - -

Flash 2 Gb 1.25 Gb - 2 Gb
4.0 x8 FPGA & 4.0
4.0 x16 edge connector x8 to E810 Ethernet
PCI Express 3.0 x8, 4.0 x8 (Option) controller (N6000) 4.0 x16
Interfaces and Modules

4.0 x16 over cable 4.0 x16 to FPGA

(N5000) (N6001)
4 x100 Gbps
Network Interface Dual Intel Ethernet 2 x25 Gbps 2 x 100 Gbps 2x 100 Gbps
Controller E810
(N5000)
MAX 10 FPGA Board F2000 has an option for
Yes Option Yes
Management Controller MAX 10 BMC
FPGA Interface Manager Yes - Yes Yes
Full Height, ⅔Length
Full Height, ¾ Length
Single slot
Mechanical, Thermal,

Form Factor Full height, full length Full Height, ½ Length Full Height, ½ Length
(N5000) Optional:
and Power

Full Height, ½ Length

Dual slot
Single slot (active
Width Single slot Single slot Single slot
cooling)
36 W (FPGA) + 22/30 W
Maximum Power Consumption 100 W (N6000),
194 W (Intel Xeon D processor 150 W
(TDP) 75 W (N6001)
4C/8C)
Open FPGA Stack (OFS) Yes No Yes Yes
Quartus® Prime Software Yes Yes Yes Yes
Data Plane Developer Kit
Yes Yes Yes Yes
(DPDK)
Tools Support

Infrastructure Programmer
No No No Yes
Development Kit (IPDK)
Storage Performance
No Yes No Yes
Development Kit (SPDK)
P4 Programmable No No Yes Yes
Intel Distribution of
No No No No
OpenVINO™ Toolkit
Artiza Networks,
How to

Silicom, Winston
buy

Contact Silicom Inventec, Silicom Napatech

NeWeb Corporation
(WNC)

Altera Product Catalog 71

 Accelerator Cards That Fit Your
Performance Needs
Altera® FPGA-based acceleration solutions make it possible to move, process, and store data faster and more efficiently. Altera
and partner Infrastructure Processing Units (IPUs), SmartNICs, and acceleration platforms offer hardware programmability on
production-qualified cards, which enable the quick design and deployment of workloads in networking, wireless, cloud, and data
center applications.

Artiza Networks Griffin SmartNIC CAES APD Vortex Prodesign FALCON

N6060/N6061
EmbedWay PA8921 Ruijie C5040X
BittWare IA-220-U2
Flyslice FA728Q Silicom FPGA IPU C5010X
BittWare IA-420F
Flyslice FA927S Silicom FPGA SmartNIC N5013/
BittWare IA-840F N5014
Flyslice FA925E
BittWare IA-440i Silicom FPGA SmartNIC N6010/N6011
Hitek HiPrAcc CS200D
BittWare IA-780i Terasic DE10-Agilex
Hitek HiPrAcc NC100
BittWare IA-820i WNC FPGA SmartNIC
Hitek HiPrAcc NC200 WSN6050/6051
BittWare IA-821i
Hitek HiPrAcc NCS200
BittWare IA-860m
Inventec FPGA IPU C5020X
BittWare IA-865m
Napatech F2070X IPU

For more information, please visit:

www.intel.com/content/www/us/en/products/details/fpga/platforms.html
 Design Tools, OS Support, and Processors

Quartus® Prime Design Software

intel.com/quartus

The Quartus® Prime Software is revolutionary in performance and productivity for FPGA, CPLD, and SoC designs, providing
a fast path to convert your concept into reality. The Quartus Prime Software also supports many third-party tools for synthesis,
static timing analysis, board-level simulation, signal integrity analysis, and formal verification.

Availability
Pro Edition Standard Edition Lite Edition
Quartus® Prime Design Software
($) ($) (Free)
Agilex™ FPGAs 
IV, V 
Stratix® series
10 
II 1
Arria® series II, V 
Device Support
10  
IV, V  
Cyclone® series 10 LP  
10 GX 2
MAX® series  
Partial reconfiguration  3
Design Flow Block-based design 
Incremental optimization 
Available for
IP Base Suite  
purchase
Intel® HLS Compiler   
Platform Designer (Standard)  
Platform Designer (Pro) 
Design Partition Planner  
Design Entry/Planning Chip Planner   
Interface Planner 
Logic Lock regions  
VHDL   
Verilog   
SystemVerilog  4 4
VHDL-2008  4
Questa*-Intel FPGA Starter Edition software   
Functional Simulation
Questa-Intel FPGA Edition software 5 5 5
Fitter (Place and Route)   
Compilation Register retiming  
(Synthesis & Place and Route) Fractal synthesis 
Multiprocessor support  
Timing Analyzer   
Design Space Explorer II   
Timing and Power Verification
Power Analyzer   
Power and Thermal Calculator 6
Signal Tap Logic Analyzer   
In-System Debug Transceiver toolkit  
Intel Advanced Link Analyzer  
Operating System (OS) Support Windows/Linux 64 bit support   

Notes:
1. The only Arria II FPGA supported is the EP2AGX45 device.
2. The Cyclone 10 GX device support is available for free in the Pro Edition software.
3. Available for Cyclone V and Stratix V devices only and requires a partial reconfiguration license.
4. For language support, refer to the Verilog and SystemVerilog Synthesis Support section of the Quartus Prime Standard Edition User Guide.
5. Requires an additional license.
6. Integrated in the Quartus Prime Software and available as a stand-alone tool. Only supports Agilex and Stratix 10 devices.

Altera Product Catalog 73

 Design Tools, OS Support, and Processors

Additional Development Tools

Tools Description
• No additional license required.
Intelt HLS Compiler • Now available as a separate download.
• Supported with the Quartus® Prime Pro Edition Software.

• Additional licenses are required.

DSP Builder • DSP Builder (Advanced Blockset only) is supported with the Quartus® Prime Pro Edition Software for Agilex™ 7,
Stratix® 10, Arria® 10, and Cyclone® 10 GX devices.

• No additional licenses are required.

Ashling RiscFree IDE for
• Supported with all editions of the Quartus® Prime Software.
Intel FPGAs
• Includes Nios® V software development tools and libraries.

Intel SoC FPGA • Requires additional licenses for Arm* Development Studio for Intel SoC FPGA (Arm* DS for Intel SoC FPGA).
Embedded Development • The SoC EDS Standard Edition is supported with the Quartus® Prime Lite/Standard Edition Software and the SoC
Suite (SoC EDS) EDS Pro Edition is supported with the Quartus® Prime Pro Edition Software.

Quartus® Prime Design Software Features Summary

Interface Planner Enables you to quickly create your I/O design using real time legality checks.
Pin planner Eases the process of assigning and managing pin assignments for high-density and high-pin-count designs.
Accelerates system development by integrating IP functions and subsystems (collection of IP functions) using a
Platform Designer
hierarchical approach and a high-performance interconnect based on a network-on-a-chip architecture.
Off-the-shelf IP cores Lets you construct your system-level design using IP cores from Altera and from Altera’s third-party IP partners.
Synthesis Provides expanded language support for System Verilog and VHDL 2008.
Scripting support Supports command-line operation and Tcl scripting.
Offers a faster methodology to converge to design sign-off. The traditional fitter stage is divided into finer
Incremental optimization
stages for more control over the design flow.
Creates a physical region on the FPGA that can be reconfigured to execute different functions. Synthesize,
Partial reconfiguration
place, route, close timing, and generate configuration bitstreams for the functions implemented in the region.
Block-based design flows Provides flexibility of reusing timing-closed modules or design blocks across projects and teams.
Hyperflex FPGA Architecture Provides increased core performance and power efficiency for Stratix® 10 devices.
Physical synthesis Uses post placement and routing delay knowledge of a design to improve performance.
Increases performance by automatically iterating through combinations of Quartus® Prime Software settings to
Design space explorer (DSE)
find optimal results.
Extensive cross-probing Provides support for cross-probing between verification tools and design source files.
Optimization advisors Provides design-specific advice to improve performance, resource usage, and power consumption.
Reduces verification time while maintaining timing closure by enabling small, post-placement and routing de-
Chip planner
sign changes to be implemented in minutes.
Provides native Synopsys Design Constraint (SDC) support and allows you to create, manage, and analyze
Timing Analyzer
complex timing constraints and quickly perform advanced timing verification.
Supports the most channels, fastest clock speeds, largest sample depths, and most advanced triggering
Signal Tap logic analyzer
capabilities available in an embedded logic analyzer.
Enables you to easily debug your FPGA in real time using read and write transactions. It also enables you to
System Console
quickly create a GUI to help monitor and send data into your FPGA.
Power Analyzer Enables you to analyze and optimize both dynamic and static power consumption accurately.
A design rules checking tool that allows you to get to design closure faster by reducing the number of iterations
Design Assistant needed and by enabling faster iterations with targeted guidance provided by the tool at various stages of
compilation.
Enables the Quartus® Prime Software to efficiently pack arithmetic operations in the FPGA's logic resources
Fractal synthesis
resulting in significantly improved performance.
Offers EDA software support for synthesis, functional and timing simulation, static timing analysis, board-level
EDA partners simulation, signal integrity analysis, and formal verification. To see a complete list of partners, visit
intel.com/fpgaedapartners.

Altera Product Catalog 74

 Design Tools, OS Support, and Processors

Getting Started Steps

Step 1: Download the free Quartus Prime Lite Edition Software
intel.com/quartus
Step 2: Get oriented with the Quartus Prime Software interactive tutorial.
After installation, open the interactive tutorial on the welcome screen.
Step 3: Sign up for training
intel.com/fpgatraining

Purchase the Quartus Prime Software and increase your productivity today.

Quartus® Prime Software

Quartus® Prime Software (Standard and Pro Edition) and Questa-Intel FPGA Edition software are bundled together into one single ordering
part number effective October 15, 2021.

SW-ONE-QUARTUS Price: $3,645

The purchase can be applied for Fixed or Floating or Renewal licenses.

Refer to the following product advisories for more information:

• ADV 2127 Single Ordering Part Number for Quartus® Prime Software

Questa-Intel FPGA Edition Software Questa-Intel FPGA Starter Edition Software

SW-QUESTA-PLUS SW-QUESTA

$1,995 Free

Questa-Intel FPGA Starter Edition is available for free, but requires a

Questa-Intel FPGA Edition software is available for $1,995 license that can be generated at the Self-Service Licensing Center. It
is 40% the performance of the Questa-Altera FPGA Edition software.

Refer to the following product advisories for more information:

• ADV 2122 Replacement of ModelSim*-Intel FPGA Edition Software

Altera Product Catalog 75

 Design Tools, OS Support, and Processors

FPGA AI Suite
intel.com/aisuite

FPGA AI Suite provides complete software solution to quickly convert and optimize trained AI model to custom AI inference
accelerator for deployment on Altera FPGAs. It enables seamless collaboration between data scientists and FPGA engineers with
intuitive and easy-to-use tools

Why Choose FPGA AI Suite?

•  upport popular AI frameworks: The front-end of FPGA AI Suite is OpenVINO Toolkit. The Toolkit seamlessly converts trained
S
(inference) models from most standard frameworks like Pytorch, TensorFlow to intermediate representation that FPGA AI
Suite uses
Hardware-less early model validation: Data scientists can do quick check on trained model’s performance, model accuracy(1)(2),
• 
power, area in FPGA without hardware. FPGA AI Suite’s model optimizer auto optimizes the IP parameters for target area or
performance.
Access to free pre-trained AI models: Jump start your solution development by picking the best suited model. Supports most
• 
of the deep learning models on Open Model Zoo for OpenVINO™ toolkit.
Ease of Use: Push-button AI inference IP generation
• 
Easy Integration of AI inference IP: Add AI inference IP to FPGA design with best-in-class standard Quartus® Prime Design
• 
Software FPGA flows
Lower TCO (total cost of ownership) with easy system integration: Integrate AI IP with other system level components to
• 
achieve smaller footprint, lower power, low latency and system costs.

FPGA AI Suite Inference Deployment Flow

1. Supported for Agilex 5 devices only.

2. Minor rounding differences between software emulation and hardware will typically result in differences of less than two units of least precision (ULPs)

Altera Product Catalog 76

 Design Tools, OS Support, and Processors

Getting Started with FPGA AI Suite – Example Designs,

Applications Documentation
Segment Application Example design Device Development Kit
Image Classification, Terasic DE10-Agilex™ Dev Board
Object Detection, Semantic (DE10-Agilex-B2E2)
Computer Vision Segmentation, Pose Estimation,
PCIe Attach Agilex™ 7 FPGA I-Series Dev Kit
Anomaly Detection, Predictive Agilex™ 7
Design ES2 (DK-DEV-AGI027RBES)
Maintenance
Intel FPGA SmartNIC
Endoscopy, Ultrasound, CT/PET/
Medical Imaging & Diagnosis N6001-PL Platform
MR/X-Ray
Hostless DDR- Agilex™ 7 FPGA I-Series Dev Kit
Predictive Maintenance, Quality Agilex™ 7
Industrial free Design ES2 (DK-DEV-AGI027RBES)
Inspection and assurance
Hostless JTAG- Agilex™ 5 FPGA E-Series 065B
Adaptive beamforming, Agilex™ 5
attach Design Modular Dev Kit
Channel Estimation, Network
Telecom optimization, FrontHaul traffic Agilex™ 7 FPGA I-Series
reduction, Network Security, Agilex™ 7 Transceiver-SoC Dev Kit
Packet inspection (DK-SIAGI027FC)
Target Detection (e.g. Missile), SOC Design Arria® 10 SX SoC FPGA Dev Kit
Arria® 10
Military RF Sensing for Surveillance, (DK-SOC-10AS066S)
Unmanned Aerial Vehicles Agilex™ 5 FPGA E-Series 065B
Agilex™ 5
Broadcast Video Conferencing Modular Dev Kit

Key Components Documentation Description

Segment Application Interactive step-by-step

guidance for developing and
Automatically generates FPGA AI Suite Guided Journey
deploying FPGA AI Suite
optimized FPGA IP from AI Inference IP designs
FPGA AI Suite Compiler models, provides resource
(dla_compiler) estimation, performance analysis, Guidance for installation,
and creates compiled binaries for Getting Started Guide initial setup, and running first
deployment inference tests

Push-button IP generation tool Comprehensive details on

that helps customized Inference Compiler Reference Manual compiler usage, commands, and
FPGA AI Suite IP Generation Tool IP based on the FPGA AI input options
architecture config file that can Information on IP customization,
be imported into FPGA design IP Reference Manual supported models, and
Imports trained models integration techniques
seamlessly from various Step-by-step walkthroughs
frameworks (TensorFlow*, Design Examples Guide for deploying FPGA AI Suite
OpenVINO Toolkit PyTorch*, PaddlePaddle*, inference IP
Keras*, and more) and converts
them to a unified intermediate
representation.
System Requirements
API for controlling and
configuring AI inference • Agilex™ 3
IP allowing heterogeneous • Agilex™ 5
execution of layers across • Agilex™ 7
Supported FPGA Families
OpenVINO Runtime hardware targets (Eg., CPU, • Arria® 10
FPGA). It supports C, C++, • Stratix® 10
and Python* interfaces with • Cyclone® 10 GX
dynamic plugin loading for each • Ubuntu 22.04 LTS,
hardware type Supported Operating System • Ubuntu 20.04 LTS,
Runtime application to estimate • Red Hat Enterprise Linux 8.10
inference performance on FPGA Software Dependencies OpenVINO Toolkit
dla_benchmark
devices through emulation or
direct hardware execution FPGA Design Implementation
Quartus®® Prime Pro Software
& FPGA Programming
Standalone best-in-class
FPGA design implementation
Quartus® Prime Pro Software software tool to help integrate AI
inference IP and generate FPGA Pricing
Programming file
$2,995 Primary Subscription
SW-FPGAAISuite $2,995 Renewal Subscription
(1 year)

Altera Product Catalog 77

 Design Tools, OS Support, and Processors

DSP Builder
The DSP Builder is a DSP development tool that allows push- intel.com/dspbuilder
button HDL generation of DSP algorithms directly from the
MathWorks Simulink environment. This tool adds additional
libraries alongside existing Simulink libraries with the DSP Getting Started with the DSP Builder
Builder (Advanced Blockset) and DSP Builder (Standard
Blockset). Altera recommends using the DSP Builder Step 1: Download the Quartus Prime Pro or Standard
(Advanced Blockset) for new designs. The DSP Builder Edition Software (intel.com/quartus):
(Standard Blockset) is not recommended for new designs • Pro Edition to target the latest Agilex 7, Stratix 10,
except as a wrapper for the DSP Builder (Advanced Blockset). Arria® 10, and Cyclone 10 GX devices.
• Standard Edition to target Arria® 10, Cyclone 10 LP,
MAX 10, Stratix V, and Cyclone V devices.
DSP Builder Features
The DSP Builder (Advanced Blockset) offers the following features: Step 2: Purchase additional DSP Builder and MATLAB
• Arithmetic logic unit (ALU) folding to build custom ALU software licenses:
processor architectures from a flat data-rate design • DSP Builder software license
• High-level synthesis optimizations, auto-pipeline insertion and • MATLAB software license
balancing, and targeted hardware mapping
• High-performance fixed- and floating-point DSP with vector
processing
Step 3: Follow the following required order of installation:
• Auto memory mapping a. Quartus Prime Software
• Single system clock datapath b. MathWorks MATLAB software
• Flexible ‘white-box’ fast Fourier transform (FFT) toolkit with an c. DSP Builder
open hierarchy of libraries and blocks for users to build custom
FFTs Step 4: To view the DSP Builder version history and software
requirements, visit the
Generate resource utilization tables for all designs without the
Quartus® Prime Software compile.
DSP Builder Version History and Software
Requirements web page.
Automatically generate projects or scripts for the Quartus® Prime
Software, the Questa*-Intel FPGA software, Timing Analyzer, and Step 5 : To learn how to add your DSP Builder license to your
Platform Designer. MATLAB installation, refer to the
Installing and Licensing DSP Builder web page.

DSP Builder DSP Builder

Features
(Standard Blockset) (Advanced Blockset)
High-level optimization 
Auto pipeline insertion 
Floating-point blocks 
Resource sharing 
IP-level blocks  
Low-level blocks  
System integration  
Hardware co-simulation  

Purchase the DSP Builder to meet high-performance DSP

design needs today.

Pricing Operating System

$1,995 Primary
$1,995 Renewal Windows/ Linux
Subscription for one year

Altera Product Catalog 78

 Design Tools, OS Support, and Processors

Embedded Software and Tools for Altera

SoC FPGAs intel.com/soceds

The Intel SoC FPGA Embedded Development Suite (SoC EDS) is a comprehensive tool suite for embedded software
development on Intel SoC FPGAs. It comprises development tools, utility programs, and design examples to jump-start firmware
and application software development. The SoC EDS is available in Standard and Pro Editions. The Standard Edition includes
extensive support for 28 nm SoC FPGA families, whereas the Pro Edition is optimized to support the advanced features in the
next-generation SoC FPGA families. In addition, the SoC EDS works in conjunction with the Arm Development Studio for Altera
SoC FPGA (Arm DS for Altera SoC FPGA). This toolkit enables embedded developers to code, build, debug, and optimize in a
single Eclipse-based IDE. The Arm DS for Intel SoC FPGA licenses are available in two options: a 30-day evaluation license and
a paid Arm DS for Intel SoC FPGA license. The Arm DS for Intel SoC FPGA license is included at no cost with Intel SoC FPGA
Development Kits.

Intel SoC FPGA Embedded Development Suite

Availability
Standard Pro
Evaluation Evaluation
Key Features Paid License Paid License
License License
Cyclone® V SoC  
Arria® V SoC  
Supported
Arria® 10 SoC    
Device Families
Stratix® 10 SoC  
Agilex™ SoC  
Linaro Compiler1    
Compiler Tools Arm Compiler 5 (included in the Arm DS for Intel SoC FPGA) 
Arm Compiler 6 (included in the Arm DS for Intel SoC FPGA)  
Libraries Hardware Libraries (HWLIBs)    
Quartus® Prime Programmer    
Signal Tap Logic Analyzer    
Other Tools
Intel FPGA Boot Disk Utility    
Device Tree Generator    
Golden Hardware Reference Design (GHRD) for SoC
   
development kits
Design Triple-Speed Ethernet (TSE) with Modular
   
Examples Scatter-Gather Direct Memory Access (mSG-DMA)2
PCI Express Root Port with Message Signal Interrupts (MSI)2    
Partial Reconfiguration design example3  
Windows 7 64 bit    
Host OS Windows 10 64 bit    
Support 32 bit libraries 32 bit libraries 32 bit libraries 32 bit libraries
Red Hat Linux 6 64 bit
are required are required are required are required
Ubuntu 18    

Arm DS for Intel SoC FPGA

Linux application debugging over Ethernet    
Debugging over Altera FPGA Download Cable II
• Board bring-up
• Device driver development
 
• Operating system (OS) porting
• Bare-metal programming
• Arm CoreSight trace support
Debugging over DSTREAM
• Board bring-up
Arm DS for Intel
• Device driver development
SoC FPGA  
• OS porting
• Bare-metal programming
• Arm CoreSight trace support
FPGA-adaptive debugging
• Auto peripheral register discovery
• Cross-triggering between CPU and FPGA domains  
• Arm CoreSight trace support
• Access to System Trace Module (STM) events
Streamline Performance Analyzer support Limited  Limited 
Notes:
1. You have to download the Linaro Compiler.
2. These design examples are only available through Rocketboards.org.
3. For Arria 10 SoC only.
4. Individual components of SoC EDS can now be downloaded from GitHub.
5. Altera has migrated to Arm DS for Intel SoC FPGA. Arm DS for Intel SoC FPGA is no longer a part of SoC EDS and is a separate download from intel.com.

Altera Product Catalog 79

 Design Tools, OS Support, and Processors

SoC FPGA Operating System Support

Altera and our ecosystem partners offer comprehensive operating system support for Altera SoC FPGA development boards that
support the Arm Cortex-A9 processor.

Operating System Company Operating System Company

Abassi Code Time Technologies OSE Enea

Android MRA Digital

PikeOS Sysgo
AUTOSAR MCAL Altera
QNX Neutrino QNX
Bare-Metal/Hardware
Altera
Libraries
RTEMS RTEMS.org
Carrier Grade Edition 7
MontaVista
(CGE7)
RTXC Quadros System
DEOS DDC-I
ThreadX Express Logic
eCosPro eCosCentric
uC/OS-II, uC/OS-III Micrium
eT-Kernel eSOL

uC3 (Japanese) eForce

FreeRTOS FreeRTOS.org

INTEGRITY RTOS Green Hills Software VxWorks Wind River

Open Source Wind River Linux Wind River

Linux
(rocketboards.org)

Nucleus Mentor Graphics Windows Embedded Compact 7 Microsoft (Witekio)

More Information

For the latest on OS support for Altera SoCs, visit

intel.com/socecosystem

Altera Product Catalog 80

 Design Tools, OS Support, and Processors

Nios® V Processor
The Nios® V processor is the next-generation soft processor Hardware development
for Altera FPGAs based on the open-source industry standard • Quartus Prime Pro Edition Software
RISC-V instruction set architecture (ISA). This processor is • Platform Designer
available in the Quartus Prime Pro Edition Software starting • Signal Tap logic analyzer
with version 21.3. There are three variants of the Nios V • System Console for low-level debugging of Platform
processor IP. The Nios V/c compact microcontroller which Designer systems
is the smallest processor in the Nios V family of processors,
Nios V/m microcontroller which is balanced for size and Software development
performance and the Nios V/g General-Purpose processor
• Software development and debug is supported using
which is the high performance Nios V processor. You can the RiscFree* IDE for Altera FPGAs. This integrated
use the Nios V processor together with the Arm processor in development environment (IDE) includes the full
Altera SoCs to create effective multi-processor systems. toolchain, IDE, compiler, debugger, and trace support.
With the Nios V processor you can: • You can also use third party tools of your choice from
• Lower overall system cost and complexity by integrating the open-source ecosystem that work with RISC-V
external processors into the FPGA. processors
• Target the Agilex, Stratix, Arria, Cyclone, or MAX 10
FPGA, or the FPGA portion of the Agilex, Stratix 10, Arria Licensing
10, Arria V, or Cyclone V SoC. A license is required for Nios V processors. The Nios V
• Leverage the community-maintained ecosystem to embedded processor license is available at no cost in the
get your designs to market faster by choosing from the Self-Service Licensing Center.
most up-to-date and modern toolchains, debuggers, and
real-time operating system (RTOS) for your software Getting started
development
To learn more about the Nios V processor, visit www.intel.com/
• Take advantage of the free license for the Nios V content/www/us/en/products/details/fpga/nios-processor/v.
processors core to get started today html.

Summary of Soft Processors

Category Processor Vendor Description

Nios® V processors give you the ultimate flexibility to achieve the exact
Performance and
performance required for your embedded design, without overpaying for high
size balanced Nios® V microcontroller
Altera clock frequency, power-hungry off-the-shelf processors. Due to architectural
optimized core
improvements, the Nios® V processor has performance benefits over the
processing
Nios® II processor.

With unique, real-time hardware features such as custom instructions, ability

to use FPGA hardware to accelerate a function, instruction and data caches
Nios® V General-
Real-time processing Altera and tightly coupled memory, as well as support for industry-leading RTOSs, the
Purpose Processor
Nios® V processor meets both your hard and soft real-time requirements, and
offers a versatile solution for real-time processing.

Size-Optimized Nios® V Compact

Altera Small area footprint for area constrained microcontroller applications.
processing Microcontroller

Altera Product Catalog 81

 Design Tools, OS Support, and Processors

RiscFree* IDE for Intel FPGAs

The RiscFree IDE for Intel FPGAs is developed by Ashling for Intel FPGAs. This integrated development environment (IDE)
provides software development and debug support for Nios® V processors that are based on the RISC-V ISA. It includes the full
toolchain, IDE, compiler, and debugger.

What you get with RiscFree* IDE with Quartus Hardware Development Tools
Prime Software • Quartus Prime Pro Edition Software
• Single-shot free stand-alone installer that works out-of-the- • Platform Designer
box or integrated with the Quartus Prime Software
• Signal Tap logic analyzer
• Support for Agilex, Stratix, Arria, Cyclone,or MAX 10 FPGA,
• System Console for low-level debugging of Platform
or the FPGA portion of the Agilex, Stratix 10, Arria 10, Arria
Designer systems
V, or Cyclone V SoC.
• Project Manager and Build Manager including Make and
CMake support with rapid import, build, and debug of Get Started
Quartus software-created applications
The RiscFree IDE for Intel FPGAs can be downloaded at
• Targeted Nios V GCC compiler toolchain fully integrated FPGA Software Download Center as a stand-alone installer or
into the RiscFree* IDE with support for newlib and picolibc as part of the Quartus Prime Pro Edition Software download.
runtime libraries using the Nios V Hardware Abstraction To learn more about the Nios V processor and the RiscFree
Layer (HAL) application programming interface (API) for IDE for Intel FPGAs, visit intel.com/content/www/us/en/
hardware access products/details/fpga/nios-processor/v.html.
• Runtime debug with support for the Intel FPGA Download
Cable II
• Homogeneous and heterogeneous simultaneous multi-
core debug support for Nios V and Arm processor cores
• Register visualization for Arm processor cores
• uC/OS-II, Zephyr, and FreeRTOS real time operating
system debug awareness
• Support for Visual Studio Code (VSCode) extension

Altera Product Catalog 82

 Intellectual Property

Altera and Intel Partner Alliance IP Functions

For a complete list of IP functions from Altera and Intel Partner Alliance, please visit intel.com/fpgaip.

Product Name Vendor Name Product Name Vendor Name

Arithmetic Hard/Soft Processors

Processors and
Floating Point Altera FPGA IP Altera Nios® V Embedded Processors Altera

Peripherals
Fixed Point Altera FPGA IP Altera Arm Cortex-A9 MPCore Processor in Altera
Altera
SoC
Error Detection/Correction
Arm Cortex-A53 MPCore Processor in Altera
POLAR Encoder / Decoder Altera Altera
SoC
Reed-Solomon Encoder/Decoder II Altera
Communication
Turbo Encoder/Decoder Altera
Optical Transport Network (OTN)
Altera
High-Speed Reed Solomon Encoder/ Framers/Deframers
Altera
Decoder
SFI-5.1 Altera
BCH Encoder/Decoder Altera
Ethernet
Low-Density Parity Check Encoder/Decoder Altera Low-Latency 10 Gbps Ethernet Media
Altera
Zip-Accel-C: GZIP/ZLIB/Deflate Data Access Controller (MAC) with 1588
CAST, Inc.
Compression Core Triple-Speed Ethernet (10/100/1000 Mbps)
Altera
Zip-Accel-D: GUNZIP/ZLIP/Inflate Data MAC and PHY with 1588 Option
CAST, Inc.
Decompression Core
1 / 2.5 / 5 / 10G Multi-Rate PHY Altera
Filters and Transforms 10G Base-X (XAUI) PHY Altera
Fast Fourier Transform (FFT)/ 25G MAC and PHY with RS-FEC option Altera
Altera
Inverse FFT (IFFT)
40G MAC and PHY with 1588 and Backplane
Cascaded Integrator Comb (CIC) Compiler Altera Altera
Options
Finite Impulse Response (FIR) Compiler II Altera 50G MAC and PHY Altera
Unified FFT IP for Altera FPGA Altera 100G MAC and PHY with 1588 and RS-FEC
Altera
SHA-3 CAST, Inc. options

SHA-256 CAST, Inc. 1/10G PHY Altera

DSP

AES CODECs CAST, Inc. Low-Latency 40- and 100G Ethernet MAC
Interface and Protocols

Altera
and PHY with 1588
Modulation/Demodulation
GTS Ethernet Altera
Numerically Controlled Oscillator Compiler Altera 10G Base-R PHY Altera
ATSC and Multi-Channel ATSC 8-VSB Backplane Ethernet 10G Base-KR PHY Altera
Commsonic
Modulators
Agilex™ 7 F-Tile Ethernet MAC and PHY
DVB-T Modulator Commsonic (10G/25/40/50/100/200/400G) Altera
DVB-S2 Modulator Commsonic with KR- and RS-FEC Options

Video and Image Processing Agilex™ 7 and Stratix® 10 E-Tile Ethernet

Altera
(10/25/100G) with Backplane Options
Video and Image Processing Suite Altera
Stratix® 10 H-Tile Ethernet Altera
Fujisoft
Stereo Vision IP Suite Low-Latency 25/50G Ethernet MAC and PHY Altera
Incorporated
Agilex™ 7 F-Tile Ethernet (400/800G) Hitek Systems
Infinivision Gidel
High-Performance Gigabit Ethernet MAC IFI
HD JPEG 2000 Encoders/Decoders IntoPIX
High Speed
TICO Lightweight Video Compression IntoPIX
eCPRI Altera
Multi-Channel JPEG 2000 Encoder and
Silex Insight O-RAN Altera
Decoder Cores
JESD204B Altera
VC-2 High Quality Video Decoder Silex Insight
JESD204C Altera
VC-2 High Quality Video Encoder Silex Insight Common Public Radio Interface (CPRI) Altera
JPEG Encoders CAST, Inc. Interlaken Altera
Ultra-fast, 4K-compatible, AVC/ H.264 Interlaken Look-Aside Altera
CAST, Inc.
Baseline Profile Encoder SerialLite II/III/IV Altera
Low-Power AVC / H.264 Baseline Profile SATA 1.0/SATA 2.0 Intelliprop, Inc.
CAST, Inc.
Encoder RapidIO Gen3 Mobiveil
H.265 Main Profile Video Decoder CAST, Inc. QDR Infiniband Target Channel Adapter Polybus

Altera Product Catalog 83

 Intellectual Property

Product Name Vendor Name Product Name Vendor Name

PCI Express / PCI Serial (CONTINUED)

PCI Express Hard IP Controller Embedded USB 3.0 / 3.1 Gen 1 Host
SLS
(up to PCIe 5.0 x16) with SR-IOV on Altera and Device Controllers
Agilex™ 7 FPGAs USB 3.0 SuperSpeed Device
SLS
PCI Express Hard IP Controller Controller
(up to PCIe 4.0 x8) with SR-IOV on Altera Audio and Video
Agilex™ 5 FPGAs

Interface and Protocols (Continued)

Character LCD Altera
PCI Express Hard IP Controller
(up to PCIe 4.0 x16) with SR-IOV on Altera Pixel Converter (BGR0 to BGR) Altera
Stratix® 10 FPGAs Video Sync Generator Altera
Scalable Switch (up to PCIe 5.0 x16) SD/HD/3G-HD Serial Digital
with 1 Upstream / 96 Downstream ports Altera Altera
Interface (SDI)
for Agilex™ 7 and Stratix® 10 FPGAs
DisplayPort 1.1 and 1.2 Altera
Multichannel DMA (MCDMA)
for Agilex™ 7 (up to PCIe 5.0 x16), HDMI 1.4 and 2.0 Altera
Altera
Agilex™ 5 (up to PCIe 4.0 x8), and
Bitec HDMI 2.0a IP core Bitec
Stratix® 10 (up to PCIe 4.0 x16) FPGAs
Multichannel DMA (MCDMA) for DisplayPort 1.3 IP Core Bitec
Agilex™ 7 (up to PCIe 5.0 x16), Agilex™ HDCP IP Core Bitec
Altera
5 (up to PCIe 4.0 x8), and Stratix® 10
Rambus
(up to PCIe 4.0 x16) FPGAs MIPI CSI-2 Controller Core
(Northwest Logic)
PCI Express 6.1 Controller (up to x16)
Rambus (PLDA) Rambus
with AXI MIPI DSI-2 Controller Core
(Northwest Logic)
Compute Express Link (CXL)
AC'97 Controller SLS
Compute Express Link (CXL) IP
supporting device Types 1, 2, and 3 for Altera Flash
Interface and Protocols (Continued)

Agilex™ 7 FPGAs (R-Tile) CompactFlash (True IDE) Altera

CXL 2.0 Controller with AXI Rambus (PLDA) EPCS Serial Flash Controller Altera
Serial Flash Memory Altera
Generic QUAD SPI Controller Altera NAND Flash Controller Eureka Technology, Inc.
Avalon® I2C (Master) Altera Universal NVM Express Controller
Mobiveil, Inc.
I2C Slave to Avalon-MM Master Bridge Altera (UNEX)
Serial Peripheral Interface (SPI)/Avalon ONFI Controller SLS
Altera
Master Bridge Enhanced ClearNAND Controller SLS
UART Altera
SDRAM
JTAG UART Altera
DDR/DDR2 and DDR3/DDR4
16550 UART Altera Altera
SDRAM Controllers
JTAG/Avalon Master Bridge Altera
LPDDR2 SDRAM Controller Altera
CAN 2.0/FD CAST, Inc.
RLDRAM 2 Controller Altera
Local Interconnect Network (LIN)
CAST, Inc. Streaming Multi-Port SDRAM
Controller Microtronix, Inc.
Memory Controller
H16550S UART CAST, Inc.
HyperDrive Multi-Port DDR2
MD5 Message-Digest CAST, Inc. Microtronix, Inc.
Memory Controller
Smart Card Reader CAST, Inc.
Avalon Multi-Port SDRAM
DI2CM I2C Bus Interface-Master Digital Core Design Microtronix, Inc.
Memory Controller
DI2CSB I C Bus Interface-Slave
2
Digital Core Design
SRAM
D16550 UART with 16-Byte FIFO Digital Core Design
SSRAM (Cypress CY7C1380C) Altera
DSPI Serial Peripheral Interface Master/
Digital Core Design QDR II/II+/II+Xtreme/IV SRAM
Slave Altera
Controller
Secure Digital (SD)/MMC SPI El Camino GmbH
Security
Secure Digital I/O (SDIO)/SD Memory/ Eureka Technology,
Slave Controller Inc. 200G MACsec Altera
SDIO/SD Memory/ MMC Host Eureka Technology, 200G Symmetric Cryptographic
Controller Inc. Altera
(AES)
I2C Master/Slave/PIO Controller Microtronix, Inc.
I C Master and Slave
2
SLS
USB High-Speed Function Controller SLS
USB Full-/Low-Speed Function Controller SLS

Altera Product Catalog 84

 Intellectual Property

Design Store fpgacloud.intel.com/devstore

The Design Store contains Altera and partner FPGA design examples to assist you in designing with Altera FPGAs and
associated development tools. Design examples can be filtered by device family, development kit, Quartus software versions, and
IP for easy search. These design examples showcase a wide range of interface IP, core function IP, configuration, embedded, and
end applications. New content is continuously added and updated for all product families.

Check out the Design Store now.

Design Example Search

Altera Product Catalog 85

 Development Kits

Altera and Partner Development Kits

intel.com/devkits

Altera development kits provide a complete, high-quality design environment for engineers. These kits help simplify the design
process and reduce time to market. Development kits include software, reference designs, cables, and programming hardware.
Altera and partner development kits are listed below. For more details about these development kits or other older development
kits that are available, check out our online development kits page at intel.com/devkits.

Product and Vendor Name Description

Agilex™ FPGA Kits

This kit allows you to design and develop your Agilex™ 7 FPGA F-Series design, and includes all hardware and
Agilex™ 7 FPGA F-Series software needed to take advantage of the performance and capabilities of the Agilex™ 7 FPGA F-Series with
Development Kit E-Tile and P-Tile. This PCIe form factor board can be used to develop and test PCI Express 4.0 designs, and
Altera external memory subsystems consisting of DDR4 and QDR IV memories. The kit also includes two QSFPDD
connectors supporting both optical and electrical interfaces.

The Agilex™ 7 FPGA I-Series development kit delivers a complete prototyping and reference platform for
Agilex™ 7 FPGA I-Series
designs needing PCIe 5.0 (32 GT/s), CXL v1.1, or 400G Ethernet connectivity. The Agilex™ 7 FPGA I-Series
Development Kit
Transceiver SoC development kit delivers a complete design environment that includes both hardware and
Altera
software for developing with Agilex™ 7 FPGA I-Series that contain 4x F-Tiles and 6 x F -Tiles.

Stratix® 10 FPGA Kits

This kit provides a complete design environment including all hardware and software needed to take
Stratix® 10 GX FPGA
advantage of the performance and capabilities of the Stratix® 10 GX FPGA. This kit can be used to develop
Development Kit
and test PCI Express 3.0 designs, memory subsystem consisting of DDR4, DDR3, QDR IV, and RLDRAM III
Altera
memories, and develop modular and scalable designs using FPGA mezzanine card (FMC) connectors.

This kit provides a complete design environment including all hardware and software needed to take
Stratix® 10 GX Transceiver Signal
advantage of the performance and capabilities of the Stratix® 10 GX FPGA. This kit can be used to evaluate
Integrity Development Kit
transceiver channel performance, generate and verify pseudo-random binary sequence (PRBS), and
Altera
dynamically change the channel’s differential output voltage (VoD), pre-emphasis, and equalization settings.

The kit offers a quick and simple approach for developing custom Arm processor-based SoC designs. It
Stratix® 10 SX SoC
offers memory options, such as HiLo DDR4 and DDR4 SODIMM. There are also two FMC+ low-pin-count
Development Kit
connectors and two quad small form factor pluggable (QSFP) connectors for transceiver channel
Altera
performance. More notably, the kit offers two HPS peripheral daughtercards to expand the capabilities.

This kit offers a complete design environment for developing on the Stratix® 10 TX FPGA. It can evaluate
Stratix® 10 TX Signal Integrity E-Tile transceiver channel performance up to 58 Gbps PAM4 and 30 Gbps NRZ. The board has different
Development Kit QSFP-DD, FMC+, MXP, and SMA connectors for networking applications. It can also be used for jitter
Altera analysis and to verify physical medium attachment (PMA) compliance for 10/25/50G/100G/200G/400G
Ethernet and other major standards.

Stratix® 10 MX FPGA This kit can be used to test and develop designs using the Stratix® 10 MX FPGA. PCIe 3.0 designs can be
Development Kit developed as the board contains a PCIe end point connector and a PCIe root port connector. The board also
Altera contains a DIMM socket and HiLO connector for expanded memory capability.

MAX® 10 FPGA Kits

This kit offers a comprehensive general-purpose development platform for many markets and applications,
MAX® 10 FPGA Development Kit such as industrial and automotive. This fully featured development kit includes a 10M50DAF484C6G
Altera device, DDR3 memory, 2X 1 GbE, high-speed mezzanine card (HSMC) connector, quad serial peripheral
interface, 16 bit digital-to-analog converter (DAC), flash memory, and 2X Digilent Pmod Compatible headers.

The 10M08 evaluation board provides a cost-effective entry point to MAX 10 FPGA design. The card comes
MAX® 10 FPGA Evaluation Kit complete with an Arduino header socket, which lets you connect a wide variety of daughtercards. Other
Altera features include an MAX® 10 10M08SAE144C8G device, Arduino shield expansion, access to 80 I/O through-
holes, and a prototyping area.

Altera Product Catalog 86

 Development Kits

Product and Vendor Name Description

Stratix® V FPGA Kits

This kit is a complete systems design environment that includes both the hardware and software needed to
Stratix® V Advanced Systems begin architecture development and system design using Stratix® V FPGAs. The PCI Express-based form
Development Kit factor utilizes a x16 edge connector, and includes high memory bandwidth to DDR3, QDR II+, and serial
Altera memory. Multiple high-speed protocols are accessible through FMC and HSMC connections. A one year
license for the Quartus® Prime Software is available with this kit.

This kit provides a full-featured hardware development platform for prototyping and testing high-speed serial
interfaces to a Stratix® V GX FPGA. This kit includes the PCI Express x8 form factor, two HSMC connectors
Stratix® V GX FPGA for expandability, and Ethernet, USB, and SDI interfaces. Memory includes one x72 DDR3 SDRAM, one
Development Kit RLDRAM II x18 QDR II+ SRAM, and flash memory. This kit also includes two SMA connectors for a differential
Altera transceiver output. Several programmable oscillators are available and other user interfaces include three
user push buttons, one 8-position DIP switch, 16 user LEDs, an LCD display, and power and temperature
measurement circuitry.

This kit enables a thorough evaluation of transceiver signal integrity and device interoperability. Features
Transceiver Signal
include seven full-duplex transceiver channels with SMA connectors, two 14G backplane connectors (from
Integrity Development Kit,
Amphenol and Molex), four programmable clock oscillators, four user push buttons, one 8-position DIP
Stratix® V GX Edition
switch, eight user LEDs, a 7-segment LCD display, power and temperature measurement circuitry, and
Altera
Ethernet, an embedded Intel FPGA Download Cable, and JTAG interfaces.

The Stratix® V GT Transceiver Signal Integrity Development Kit provides a platform for electrical compliance
testing and interoperability analysis. The accessibility to multiple channels allows for real-world analysis as
implemented in the system with transceiver channels available through SMA and popular backplane
Transceiver Signal Integrity connectors. This development kit can be used for evaluation of transceiver link performance up to 25.7 Gbps,
Development Kit, generation and checking pseudo-random binary sequence (PRBS) patterns via an easy-to-use GUI that does
Stratix® V GT Edition not require the Quartus® Prime Software, access advanced equalization to fine-tune link settings for optimal
Altera bit error ratio (BER), jitter analysis, and verifying physical media attachment (PMA) interoperability with
Stratix® V GT FPGAs for targeted protocols, such as CEI-25/28G, CEI-11G, PCI Express 3.0, 10GBASE-KR, 10
Gigabit Ethernet, XAUI, CEI-6G, Serial RapidIO, HD-SDI, and others. You can use the built-in high speed
backplane connectors to evaluate custom backplane performance and evaluate link BER.

This kit enables a thorough evaluation of 100G designs. It supports 10G/40G line interfaces through optical
modules, and applications requiring external memory interfaces through one x18 QDR II and six x32 DDR3
100G Development Kit,
memory banks. With this kit, you can evaluate transceiver performance up to 12.5 Gbps, and verify PMA
Stratix® V GX Edition
compliance to standards, such as 10G/40G/100G Ethernet, Interlaken, CEI-6G/11G, Serial RapidIO, PCI
Altera
Express (1.0, 2.0, and 3.0), and other major standards. This kit can also validate interoperability between
optical modules, such as SFP, SFP+, QSFP, and CFP.

The DSP Development Kit, Stratix® V Edition provides a complete design environment that includes all the
hardware and software you need to begin developing DSP intensive FPGA designs immediately. The
DSP Development Kit,
development kit is RoHS-compliant. You can use this development kit to develop and test PCI Express
Stratix® V Edition
designs at data rates up to 3.0, develop and test memory subsystems for DDR3 SDRAM or QDR II SRAM
Altera
memories, and use the HSMC connectors to interface to one of over 35 different HSMCs provided by Altera
partners, supporting protocols such as Serial RapidIO, 10 Gbps Ethernet, SONET, CPRI, OBSAI, and others.

Altera Product Catalog 87

 Development Kits

Product and Vendor Name Description

Arria® 10 FPGA Kits

This kit provides a complete design environment including hardware and software for prototyping and
testing high-speed serial interfaces to an Arria® 10 GX FPGA. This kit includes the PCI Express x8 form
factor, two FMC connectors for expandability, Ethernet, USB, and SDIs. The board includes one HiLo
connector for plugging in DRAM and SRAM daughtercards. Supported daughtercard formats include
Arria® 10 FPGA Development Kit
DDR4 x72 SDRAM, DDR3 x72 SDRAM, RLDRAM 3 x36, and QDR IV x36 SRAM. The board includes SMA
Altera
connectors for transceiver output, clock output, and clock input. Several programmable oscillators are
available and other user interfaces include user push buttons, dual in-line package (DIP) switches, bi-color
user LEDs, an LCD display, power, and temperature measurement circuitry. This development kit comes with
a one-year license for the Quartus® Prime Software.

This kit enables a thorough evaluation of transceiver signal integrity and device interoperability. Features
include six full-duplex transceiver channels with 2.4 mm SMA connectors, four full-duplex transceiver
channels to Amphenol Xcede+ backplane connector, four full-duplex transceiver channels to C form factor
Arria® 10 FPGA pluggable (CFP2) optical interface, four full-duplex transceiver channel to QSFP+ optical interface, one
Signal Integrity Kit transceiver channel to SFP+ optical interface, and ten full-duplex transceiver channels to Samtec BullsEye
Altera high-density connector. This board also includes several programmable clock oscillators, user push buttons,
DIP switches, user LEDs, a 7-segment LCD display, power and temperature measurement circuitry, Ethernet,
an embedded Intel FPGA Download Cable II, and JTAG interfaces. This development kit comes with a one-
year license for the Quartus® Prime Software.

This kit offers a quick and simple approach for developing custom Arm processor-based SoC designs.
The Arria® 10 SoCs offers full software compatibility with previous generation SoCs, a broad ecosystem
of Arm software and tools, and an enhanced FPGA and DSP hardware design flow. This kit includes an
Arria® 10 SoC Development Kit
Arria® 10 10AS066N3F40I2SG SoC, PCI Express 3.0 protocol support, a dual FMC expansion headers, two
Altera
10/100/1000 SGMII Ethernet ports, one 10/100/1000 RGMII Ethernet port, two 10GbE small form factor
pluggable (SFP) cages, two 1GB DDR4 HPS HiLo memory card, DDR4 SDRAM, NAND, quad SPI, SD/
MICRO boot flash cards, character LCD, display port, and SDI port.

Cyclone® 10 FPGA Kits

This kit provides an easy-to-use platform for evaluating Cyclone® 10 LP FPGA technology and Enpirion
Cyclone® 10 LP Evaluation Kit regulators. This evaluation board enables you to develop designs for Cyclone® 10 LP FPGAs via Arduino
Altera UNO R3 shields, Digilent Pmod Compatible cards, GPIOs, or Ethernet connector. This kit also measures key
Cyclone® 10 LP FPGA power supplies and reuse the kit's PCB schematic as a model for your design.

Cyclone® 10 GX FPGA This kit is an ideal starting point for developing applications, such as embedded vision, factory automation,
Development Kit and surveillance. With this development kit, you can develop Cyclone® 10 GX FPGA-based designs with
Altera expansion through PCIe 2.0, USB 3.1, SFP+, and RJ-45.

Arria® V FPGA and SoC Kits

This kit provides a low-cost platform for developing transceiver I/O-based Arria® V GX FPGA designs. This kit
Arria® V GX Starter Kit,
includes the PCI Express x8 form factor, one HSMC connector, a 32 bit DDR3 SDRAM device, one-channel
Arria® V GX Edition
high-speed transceiver input and output connected to SMAs, HDMI output, SDI input and output, 16x2 LCD
Altera
display, and flash memory.

The Arria® V SoC Development Kit offers a quick and simple approach to develop custom Arm processor-
based SoC designs. Altera’s midrange, transceiver-based Arria® V FPGA fabric provides the highest
Arria® V SoC Development Kit
bandwidth with the lowest total power for midrange applications such as remote radio units, 10G/40G line
and SoC Embedded Design
cards, medical imaging, broadcast studio equipment, and the acceleration of image- and video-processing
Suite
applications. This development kit includes the SoC Embedded Design Suite software development tools.
Altera
The development board has PCI Express 2.0 x4 lanes (endpoint or rootport), two FMC expansion headers,
dual Ethernet PHYs, and various DRAM and flash memories.

Altera Product Catalog 88

 Development Kits

Product and Vendor Name Description

Cyclone® V FPGA and SoC Kits

The Cyclone® V E Development Kit offers a comprehensive general-purpose development platform for many
markets and applications, including industrial, networking, military, and medical applications. The kit features
Cyclone® V E FPGA
an Cyclone® V device and a multitude of onboard resources including multiple banks of DDR3 and LPDDR2
Development Kits
memory, LCD character display, LEDs, user switches, USB, and RJ-45 connectors. The
Altera
Cyclone® V E FPGA Development Kit gives industrial equipment designers greater flexibility in implementing
real-time Ethernet communications with industrial Ethernet IP cores.

This kit can be used to prototype Cyclone® V GT FPGA or Cyclone® V GX FPGA applications. It offers a quick
Cyclone® V GT FPGA
and simple way to develop low-cost and low-power system-level designs and achieve rapid results. This kit
Development Kit
supports a myriad of functionalities, such as FPGA prototyping, FPGA power measurement, transceiver I/O
Altera
performance up to 5 Gbps, PCI Express 2.0 x4 (at 5 Gbps per lane), endpoint or rootport support.

The Cyclone® V SoC Development Kit offers a quick and simple approach to develop custom Arm processor-
Cyclone® V SoC based SoC designs accompanied by Altera's low-power, low-cost Cyclone® V FPGA fabric. This kit supports
Development Kit a wide range of functions, such as processor and FPGA prototyping and power measurement, industrial
Altera networking protocols, motor control applications, acceleration of image- and video-processing applications,
PCI Express x4 lane with ~1,000 MBps transfer rate (endpoint or rootport).

The Cyclone® V GX Starter Kit offers a robust hardware design platform based on Cyclone® V GX FPGA. This
kit is optimized for the lowest cost and power requirement for transceiver applications with industry-leading
Cyclone® V GX
programmable logic for ultimate design flexibility. The Cyclone® V Starter Kit development board includes
Starter Kit
hardware, such as Arduino Header, onboard Intel FPGA Download Cable circuit, audio and video capabilities,
Terasic Technologies
and an onboard HSMC connector with high-speed transceivers that allows for an even greater array of
hardware setups.

The DE0-Nano-SoC Kit combines a robust, Cyclone® V SoC-based development board and interactive
reference designs into a powerful development platform. This low-cost kit is an interactive, web-based guided
DE10-Nano Kit tour that lets you quickly learn the basics of SoC development and provides an excellent platform on which
Terasic Technologies to develop your own design. The board includes a Gigabit Ethernet port, USB 2.0 OTG port, SD card flash, 1
GB DDR3 SDRAM, an Arduino header, two 40-pin expansion headers, onboard Intel FPGA Download Cable
circuit, 8-channel A/D converter, accelerometer, and much more.

MAX® V CPLD Kits

This low-cost platform will help you quickly begin developing low-cost, low-power CPLD designs. Use this kit
MAX® V CPLD Development Kit
as a stand-alone board or combined with a wide variety of daughtercards that are available from third parties.
Altera
With this platform, you can develop designs for the 5M570Z CPLD and build upon example designs provided.

Stratix® IV FPGA Kits

This kit enables a thorough evaluation of 100G designs. It supports 10G/40G line interfaces through optical
modules, and applications requiring external memory interfaces through four x18 QDR II and four x32 DDR3
100G Development Kit,
memory banks. With this kit, you can evaluate transceiver performance up to 11.3 Gbps, verify PMA compliance
Stratix® IV GT Edition
to standards, such as 10G/40G/100G Ethernet, Interlaken, CEI-6G/11G, Serial RapidIO, PCI Express (1.0, 2.0,
Altera
and 3.0), and other major standards. This kit can also validate interoperability between optical modules, such
as SFP, SFP+, QSFP, and CFP.

Cyclone® IV FPGA Kits

This kit provides a comprehensive design environment that allows you to quickly develop low-cost and
Cyclone® IV GX FPGA low-power FPGA system-level designs. This kit includes the PCI Express short card form factor, two HSMC
Development Kit connectors, and a 10/100/1000 Mbps Ethernet interface. Onboard memory includes 128 MB DDR2 SDRAM, 64
Altera MB flash, and 4 MB SSRAM. This kit also includes SMA connectors, and 50 MHz, 100 MHz, and 125 MHz clock
oscillators, as well as user interfaces including push buttons, LEDs, and a 7-segment LCD display.

The DE0-Nano Development Board is a compact-sized FPGA development platform suited for prototyping
circuit designs such as robots and "portable" projects. The board is designed to be used in the simplest possible
implementation targeting the Cyclone® IV device up to 22,320 LEs. This kit allows you to extend designs
DEO-Nano Development Board beyond the DE0-Nano board with two external general-purpose I/O (GPIO) headers and allows you to handle
Terasic Technologies larger data storage and frame buffering with onboard memory devices including SDRAM and EEPROM. This
kit is lightweight, reconfigurable, and suitable for mobile designs without excessive hardware. This kit provides
enhanced user peripheral with LEDs and push buttons and three power scheme options including a USB Mini-
AB port, 2-pin external power header, and two DC 5-V pins.

This board is part of the DE2 educational development board series and features the Cyclone® IV E EP4CE115
DE2-115 Development and
FPGA. The DE2-115 offers an optimal balance of low cost, low power, and a rich supply of logic, memory and
Education Board
DSP capabilities, as well as interfaces to support mainstream protocols including GbE. A HSMC connector is
Terasic Technologies
provided to support additional functionality and connectivity via HSMC daughtercards and cables.

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 Development Kits

FPGA-Based SoM Partner Ecosystem

intel.com/som

System on modules (SoMs) provide a compact, pre-configured solution with FPGA, memory, and software which is perfect for
prototyping, proof-of-concept, and initial system development and production. SoMs enable you to focus on development of your
IP, algorithms, and human/mechanical interfaces rather than spending time on the fundamentals of the processor and electrical
system and software bring-up. In many cases, SoMs can also make sense for full system production.

Customer Benefits
• Faster time to market by off-loading complex board design
• Production-ready hardware for immediate deployment
• Versatile product design and application fit from various partners
• Minimize component supplier management

Target Application
• General embedded applications
• Industrial PC, factory automation, and control applications
• Machine vision, surveillance camera, and retail applications
• Networking and security applications
• Test and measurement equipment

Related Links
• Browse FPGA-based SoMs on Intel Partner Showcase
• Read the Agilex 5 SoM Solution Brief

Learn More
Our partners now offer SoMs powered by the Agilex 5 FPGA E-Series, which extends the innovations of the Agilex™ FPGA
portfolio to mid-range FPGAs.

Altera Product Catalog 90

 Partner Programs

Altera Solution Acceleration

Partner (ASAP) Program
The ASAP program is an initiative designed to help companies accelerate innovation, get to market faster and grow their
businesses more efficiently with support from Altera and its partners. The ASAP program delivers the resources and support
to ensure companies have the necessary tools to solve their complex design challenges and compete in today’s rapidly evolving
marketing being driven by artificial intelligence.

Join the ASAP Program

Altera’s partner program brings together hardware and software subject matter experts that span a wide range of end markets,
including data center, communications, and embedded systems. The program provides a range of offerings, listed below.
Browse the selection of Altera FPGA offerings from our partners in Altera Partner Showcase.

Visit the Altera Partner Showcase

Trusted Partner Program Offerings

Boards, SoMs & Dev Kits Intellectual Property Software Design Services &
Manufacturing
Development Kits, A wide variety of horizontal Design tools, simulators,
Production-Ready and vertical market operating systems (OS), Hardware design,
Boards, System on Chip, Intellectual Property (IP) hypervisors, and other Software development,
Programmable Automation solutions related software solutions PCB, Simulation, Debug,
Controllers, Daughter Cards Verification, Manufacturing,
Certification

Education & Training System Integrators/Providers EDA Tools/IDE Acceleration/AI/Cloud

Customer training for Chip integration, board Design, simulation, Data training/inference,
Altera FPGA, design tools, integration, software verification, protocol scale in/out, computer
and software integration, chassis analysis, embedded tools vision, model optimizing &
construction performance, production
transition

Altera Product Catalog 91

 Training

Training Overview Altera FPGA Technical Training

Altera FPGA technical training offers many ways to learn. Sharpen your FPGA design skills today! All public training is free to attend.

On-Demand Training Learn FPGA Design from Expert Instructors Webinars, Workshops and Quick Videos

Learn at your convenience with our on-demand

eLearning, all for FREE! The duration of each
Webinars and workshops are shorter events
eLearning session typically ranges from Learn FPGA design from expert instructors that offer an overview of the subject being
approximately 30 minutes to one hour. A and earn badges for your achievements, all taught. Join us and learn something new in
convenient player makes it easy to skip to the for FREE! Classes are taught as either one or these informative sessions.
sections that interest you most. a series of two half-day sessions. The virtual
classroom allows you to attend from work or These short how-to YouTube videos teach
Please click to view our learning plans,
home. During class, access to a remote lab specific skills to help solve your issues.
designed to guide you through a set of
environment is provided – which means no Check out the Altera FPGA Quick Videos
e-learning modules, each offering a well-
setup is required to attend. page or the Engineer to Engineer: How-To
structured learning path.
YouTube Channel.
(Note: It requires logging in to the learning.
intel.com website first)

Instructor-Led Trainings
Instructor-Led and Virtual Classes (Note: It requires logging in to the learning.intel.com website first)

Course Description

This course introduces the FPGA device in an easy-to understand manner for people who are completely
Beginner Workshop for Altera new to the world of FPGAs such as FPGA. It uses the Quartus® Prime software tool to provide a practical
FPGAs approach towards utilizing' FPGAs for design in the world of hardware. It introduces FPGAs, their
architecture, the basic tools in Quartus® Prime software that is used for FPGA design.

This class is a general introduction to the Verilog language and its use in programmable logic design,
covering the basic constructs used in both the simulation and synthesis environments. By the end of this
course, you will have a basic understanding of the Verilog module, data types, operators and assignment
Verilog HDL Basics statements needed to begin creating your own designs, using both behavioral and structural approaches.
In the hands-on laboratory sessions, you will get to practice the knowledge you have gained by writing
simple but practical designs. You will check your designs by compiling in the Quartus® Prime software and
simulating in the Questa-Intel FPGA Edition software.

You will learn efficient coding techniques for writing synthesizable Verilog for Altera FPGAs and CPLDs.
You will gain experience in behavioral and structural coding while learning how to effectively write common
Verilog HDL Advanced logic functions including registers, memory, and arithmetic functions. You will learn how to parameterize
your Verilog design, increasing flexibility and reusability. You will be introduced to testbenches and the
constructs used when building them.

You will learn how to use the Quartus® Prime Pro Edition software & correlate these steps to the general
flow of an FPGA design process. You'll create a new project, input new or existing design files, and compile
Using Quartus® Software your project. Learn how to search for compilation information, use settings and assignments to adjust
the results of compilation, and go through an overview to migrate another vendor’s design to an Quartus®
Prime Pro design.

Intel Simics Simulator for Intel FPGAs is used to test your software early on in the development process.
Intel® Simics® Simulator for Intel
This training covers the functionalities for the simulator that include hardware and software inspection,
FPGAs
dynamic system configuration, hardware modeling tools, scripting, and a rich set of other features.

Altera Product Catalog 92

 Training

Course Description

This class will teach you how to design with Stratix 10 and Agilex 7 SoC FPGAs using the Quartus® Prime
software and how to develop software for these devices. You will get an an overview of the Arm Cortex-A53
and the peripherals present in the hard processor system. You will learn to add and configure the processor
Stratix 10 and Agilex™ 7 SoC
component in a Platform Designer system. You will then learn to implement and configure the first-stage
FPGA Basics
and second-stage bootloaders (based on U-Boot), including how to append the first-stage bootloader and
how to build the Linux OS. You will learn the boot stages of each SoC FPGA family and how to gather all the
pieces for the implementation.

Nios® V processor is the next generation soft core processor based on the open-source RISC-V instruction
set, designed for Altera FPGA devices. One or more soft processors can be instantiated in a device’s
Introduction to the Nios® V
programmable fabric allowing designers to add a microcontroller or microprocessor core to a solution,
Processor
Nios® V processor IP can be added through the device’s programmable fabric using Quartus® Software
and Ashling* RISCFree IDE for Intel FPGAs.

This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug
tools included in the Quartus® Prime software. You’ll learn how including the logic analyzer in your
Quartus® Prime Software Debug
FPGA design makes it easy to debug your design quickly by triggering on internal hardware events and
Tools: Signal Tap
monitoring tapped signals, decreasing your overall design development time. You’ll gain experience with
using Signal Tap through hands-on lab exercises utilizing the tool in a real design.

This class will teach you the basics of how to build embedded system designs quickly for Altera FPGA
devices using the Platform Designer system-level integration tool, part of the Quartus® Prime software.
Introduction to Platform Designer: Platform Designer can be used as a design entry method for any FPGA design, though its use is required
Building Systems if you are implementing a Nios® processor or the Hard Process System (HPS) in an SoC device. You will
become proficient with using Platform Designer and learn how to quickly integrate “off-the-shelf” IP into a
system.

You will learn how to constrain and analyze a design for timing using the Timing Analyzer in the Quartus®
Prime Pro software v.22.1. This includes writing Synopsys Design Constraint (SDC) files, generating
Altera FPGA Timing Analysis:
various timing reports in the Timing Analyzer, and applying this knowledge to an FPGA design. Besides
Lecture
learning the basic requirements to ensure that your design meets timing, you will see how the Timing
Analyzer makes it easy to create timing constraints to help you meet those requirements.

Altera FPGA Timing Analysis: This workshop is a follow on to the Altera FPGA Timing Analysis: Lecture class. There will be a brief review
Hands-On Labs of the SDC constraints learned in the previous class before starting the labs.

This class teaches the techniques used by design specialists to close timing on designs that “push the
Altera FPGA Timing Closure: envelope” of performance. Example techniques include thoroughly analyzing the design for common
Lecture timing failures, adjusting settings and assignments according to tool recommendations, selecting the
correct clock resources, and adjusting HDL code for optimal performance.

This workshop is a follow on to the Altera FPGA Timing Closure: Lecture class. Your time during this
Altera FPGA Timing Closure: workshop will mostly be spent using the Quartus® Prime Software to practice timing closure techniques.
Hands-On Lab There will be a brief review of the timing closure techniques and reports learned in the previous class
before starting the labs.

Altera Product Catalog 93

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration
will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more
complete information about performance and benchmark results, visit www.intel.com/benchmarks.

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera Corporation. *Other names and
brands may be claimed as the property of others.

SG-PRDCT-25.1