Computer Architecture

Lecture 11.
. Instruction Sets:
Addressing modes.

Instructors

Elena Boldyreva, Associate Professor [email protected]

E-mail for questions [email protected]

GOALS OF THIS LECTURE: PLAN:
1. get more details about 1. Addressing Modes
instruction set architecture 2. Issues in design of ISAs

©. Stallings, William. Computer organization and architecture : designing for performance

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 What is an Instruction Set?

• The complete collection of instructions that are understood by a CPU

• Machine Code
• Binary
• Usually represented by assembly codes

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 Elements of a Machine Instruction

Operation code (opcode)

• Specifies the operation to be performed. The operation is specified
by a binary code, known as the operation code, or opcode

Source operand reference

• The operation may involve one or more source operands, that is,
operands that are inputs for the operation

Result operand reference

• The operation may produce a result

Next instruction reference

• This tells the processor where to fetch the next instruction after the
execution of this instruction is complete

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Instruction Cycle State Diagram

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 Instruction Representation

• Within the computer each instruction is represented by a sequence

of bits
• The instruction is divided into fields, corresponding to the
constituent elements of the instruction

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 Addressing Modes

• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack

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 Immediate Addressing

• Operand is part of instruction

• Operand = address field
• e.g. ADD 5
• Add 5 to contents of accumulator
• 5 is operand
• No memory reference to fetch data
• Fast
• Limited range

Instruction
Opcode Operand

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 Direct Addressing

• Address field contains address of operand

• Effective address (EA) = address field (A)
• e.g. ADD A
• Add contents of cell A to accumulator
• Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective
address
• Limited address space

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 Indirect Addressing (1)

• Memory cell pointed to by address field contains the address of (pointer to) the operand
• EA = (A)
• Look in A, find address (A) and look there for operand
• e.g. ADD (A)
• Add contents of cell pointed to by contents of A to accumulator

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 Indirect Addressing (2)

Instruction
Opcode Address A
Memory
• Large address space Pointer to operand
• 2n where n = word length
• May be nested, multilevel, cascaded
• e.g. EA = (((A)))
• Draw the diagram yourself Operand
• Multiple memory accesses to find operand
• Hence slower

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 Register Addressing

• Operand is held in register named in • No memory access

address filed
• Very fast execution
• EA = R
• Very limited address space
• Limited number of registers
• Multiple registers helps performance
• Very small address field needed • Requires good assembly programming or
• Shorter instructions compiler writing
• Faster instruction fetch • N.B. C programming
• register int a;
• c.f. Direct addressing

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 Register Addressing Diagram

Instruction
Opcode Register Address R
Registers

Operand

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 Register Indirect Addressing

• C.f. indirect addressing

• EA = (R)
• Operand is in memory cell pointed to by
contents of register R
• Large address space (2n)
• One fewer memory access than indirect
addressing

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 Register Indirect Addressing Diagram

Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

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 Displacement Addressing

• EA = A + (R)
• Address field hold two values
• A = base value
• R = register that holds displacement
• or vice versa

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 Relative Addressing

• A version of displacement addressing

• R = Program counter, PC
• EA = A + (PC)
• i.e. get operand from A cells from current
location pointed to by PC
• c.f locality of reference & cache usage

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 Base-Register Addressing

• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
• e.g. segment registers in 80x86

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 Indexed Addressing

• A = base
• R = displacement
• EA = A + R
• Good for accessing arrays
• EA = A + R
• R++

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 Stack Addressing

• Operand is (implicitly) on
top of stack
• e.g.
• ADD Pop top two
items from stack and
add

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 x86 Addressing Modes

• Virtual or effective address is offset into segment

• Starting address plus offset gives linear
address
• This goes through page translation if paging
enabled
• 12 addressing modes available
• Immediate
• Register operand
• Displacement
• Base
• Base with displacement
• Scaled index with displacement
• Base with index and displacement
• Base scaled index with displacement
• Relative

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 ARM Addressing Modes
Load/Store
• Only instructions that reference memory
• Indirectly through base register plus offset
• Offset
• Offset added to or subtracted from base register contents to
form the memory address
• Preindex
• Memory address is formed as for offset addressing
• Memory address also written back to base register
• So base register value incremented or decremented by offset
value
• Postindex
• Memory address is base register value
• Offset added or subtracted
Result written back to base register
• Base register acts as index register for preindex and
postindex addressing
• Offset either immediate value in instruction or another
register
• If register scaled register addressing available
• Offset register value scaled by shift operator
• Instruction specifies shift size

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 Instruction Formats

• Layout of bits in an instruction

• Includes opcode
• Includes (implicit or explicit) operand(s)
• Usually more than one instruction format in an instruction set

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 Instruction Length

• Affected by and affects:

• Memory size
• Memory organization
• Bus structure
• CPU complexity
• CPU speed
• Trade off between powerful instruction repertoire and saving space

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 Allocation of Bits

• Number of addressing modes

• Number of operands
• Register versus memory
• Number of register sets
• Address range
• Address granularity

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PDP-8 Instruction Format

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PDP-10 Instruction Format

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PDP-11 Instruction Format

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x86 Instruction Format

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 ARM Instruction Formats

• S = For data processing instructions, updates condition codes

• S = For load/store multiple instructions, execution restricted to supervisor mode
• P, U, W = distinguish between different types of addressing_mode
• B = Unsigned byte (B==1) or word (B==0) access
• L = For load/store instructions, Load (L==1) or Store (L==0)
• L = For branch instructions, is return address stored in link register 30
 Thumb Instruction Set

• Re-encoded subset of ARM instruction set

• Increases performance in 16-bit or less data bus
• Unconditional (4 bits saved)
• Always update conditional flags
• Update flag not used (1 bit saved)
• Subset of instructions
• 2 bit opcode, 3 bit type field (1 bit saved)
• Reduced operand specifications (9 bits saved)

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Expanding Thumb ADD Instruction to ARM
Equivalent

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 Assembler

• Machines store and understand binary instructions

• E.g. N= I + J + K initialize I=2, J=3, K=4
• Program starts in location 101
• Data starting 201
• Code:
• Load contents of 201 into AC
• Add contents of 202 to AC
• Add contents of 203 to AC
• Store contents of AC to 204
• Tedious and error prone

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 Improvements

• Use hexadecimal rather than binary

• Code as series of lines
• Hex address and memory address
• Need to translate automatically using program
• Add symbolic names or mnemonics for instructions
• Three fields per line
• Location address
• Three letter opcode
• If memory reference: address
• Need more complex translation program

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 Program in:
Binary Hexadecimal
Address Contents Address Contents

101 0010 0010 101 2201 101 2201

102 0001 0010 102 1202 102 1202

103 0001 0010 103 1203 103 1203

104 0011 0010 104 3204 104 3204

201 0000 0000 201 0002 201 0002

202 0000 0000 202 0003 202 0003

203 0000 0000 203 0004 203 0004

204 0000 0000 204 0000 204 0000

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 Symbolic Addresses

• First field (address) now symbolic

• Memory references in third field now symbolic
• Now have assembly language and need an assembler to translate
• Assembler used for some systems programming
• Compliers
• I/O routines

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 Programs

Symbolic Program Assembler Program

Address Instruction Label Operation Operand
101 LDA 201 FORMUL LDA I

102 ADD 202 ADD J

103 ADD 203 ADD K

104 STA 204
STA N

201 DAT 2
I DATA 2
202 DAT 3
J DATA 3
203 DAT 4
K DATA 4
204 DAT 0 N DATA 0

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 Issues in design of ISAs
• Characterization of application programs
• What are typical programs like
• What mix of instructions (ALU, Branch, ..)
• Size of instruction word
• Length of program
• Number of instructions
• Number of bytes
• Number of instructions needed to code the same program may
be different depending on the ISA
• Clock period
• Needs to be long enough to do one cycle of instruction
• Single cycle instruction or multi-cycle instruction
• Multi-cycle instructions: (we are skipping this)
• Hardwired control vs micro-programmed control
• Pipelined instructions
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 Number of operands

• Another way to classify instruction sets is according to the number of operands that each data
manipulation instruction can have.
• Our example instruction set had three-address instructions, because each one had up to three
operands—two sources and one destination.

operation operands
Register transfer instruction:
ADD R0, R1, R2
R0  R1 + R2
destination sources

• This provides the most flexibility, but it’s also possible to have fewer than three operands.

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 Two-address instructions

• In a two-address instruction, the first operand serves as both the destination and one of the source registers.

operation operands
Register transfer instruction:
ADD R0, R1

destination source 2 R0  R0 + R1
and source 1

• Some other examples and the corresponding C code:

ADD R3, #1 R3  R3 + 1 R3++;

MUL R1, #5 R1  R1 * 5 R1 *= 5;
NOT R1 R1  R1’ R1 = ~R1;

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 One-address instructions

• Some computers, like this old Apple II, have one-address instructions.
• The CPU has a special register called an accumulator, which implicitly serves as the destination
and one of the sources.

operation source Register transfer instruction:

ADD R0 ACC  ACC + R0

• Here is an example sequence which increments M[R0]:

LD (R0) ACC  M[R0]

ADD #1 ACC  ACC + 1
ST (R0) M[R0]  ACC

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 The ultimate: zero addresses

• If the destination and sources are all implicit, then you don’t have to specify any
operands at all!
• For the ALU instructions
• This is possible with processors that use a stack architecture.
• HP calculators and their “reverse Polish notation” use a stack.
• The Java Virtual Machine is also stack-based.
• How can you do calculations with a stack?
• Operands are pushed onto a stack. The most recently pushed element is at the
“top” of the stack (TOS).
• Operations use the topmost stack elements as their operands. Those values are
then replaced with the operation’s result.

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 Stack architecture example

• From left to right, here are three stack instructions, and what the stack looks like after each example
instruction is executed.

(Top)
PUSH R1 PUSH R2 ADD

R1 R2 R1 + R2
(Bottom)
… stuff 1 … R1 … stuff 1 …
… stuff 2 … … stuff 1 … … stuff 2 …
… stuff 2 …

• This sequence of stack operations corresponds to one register transfer instruction:

TOS  R1 + R2

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 Data movement instructions

• Finally, the types of operands allowed in data manipulation instructions is another

way of characterizing instruction sets.
• So far, we’ve assumed that ALU operations can have only register and constant
operands.
• Many real instruction sets allow memory-based operands as well.
• We’ll use the book’s example and illustrate how the following operation can be
translated into some different assembly languages.

X = (A + B)(C + D)

• Assume that A, B, C, D and X are really memory addresses.

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 Register-to-register architectures

• Our programs so far assume a register-to-register, or load/store, architecture, which matches our
datapath from last week nicely.
• Operands in data manipulation instructions must be registers.
• Other instructions are needed to move data between memory and the register file.
• With a register-to-register, three-address instruction set, we might translate X = (A + B)(C + D)
into:
LD R1, A R1  M[A] // Use direct addressing
LD R2, B R2  M[B]
ADD R3, R1, R2 R3  R1 + R2 // R3 = M[A] + M[B]

LD R1, C R1  M[C]
LD R2, D R2  M[D]
ADD R1, R1, R2 R1  R1 + R2 // R1 = M[C] + M[D]

MUL R1, R1, R3 R1  R1 * R3 // R1 has the result

ST X, R1 M[X]  R1 // Store that into M[X]

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 Memory-to-memory architectures
• In memory-to-memory architectures, all data manipulation instructions use memory addresses
as operands.
• With a memory-to-memory, three-address instruction set, we might translate X = (A + B)(C + D)
into simply:
ADD X, A, B M[X]  M[A] + M[B]
ADD T, C, D M[T]  M[C] + M[D] // T is temporary
storage
MUL X, X, T M[X]  M[X] * M[T]

• How about with a two-address instruction set?

MOVE X, A M[X]  M[A] // Copy M[A] to M[X] first

ADD X, B M[X]  M[X] + M[B] // Add M[B]
MOVE T, C M[T]  M[C] // Copy M[C] to M[T]
ADD T, D M[T]  M[T] + M[D] // Add M[D]
MUL X, T M[X]  M[X] * M[T] // Multiply

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 Register-to-memory architectures

LD R1, A R1  M[A] // Load M[A] into R1 first

ADD R1, B R1  R1 + M[B] // Add M[B]
LD R2, C R2  M[C] // Load M[C] into R2
ADD R2, D R2  R2 + M[D] // Add M[D]
MUL R1, R2 R1  R1 * R2// Multiply
ST X, R1 M[X]  R1 // Store

• Finally, register-to-memory architectures let the data manipulation instructions access both
registers and memory.
• With two-address instructions, we might do the following:

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 Size and speed

• There are lots of tradeoffs in deciding how many and what kind of operands and addressing
modes to support in a processor.
• These decisions can affect the size of machine language programs.
• Memory addresses are long compared to register file addresses, so instructions with
memory-based operands are typically longer than those with register operands.
• Permitting more operands also leads to longer instructions.
• There is also an impact on the speed of the program.
• Memory accesses are much slower than register accesses.
• Longer programs require more memory accesses, just for loading the instructions!

• Most newer processors use register-to-register designs.

• Reading from registers is faster than reading from RAM.
• Using register operands also leads to shorter instructions.

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 Summary

• Instruction sets can be classified along several lines.

• Addressing modes let instructions access memory in various ways.
• Data manipulation instructions can have from 0 to 3 operands.
• Those operands may be registers, memory addresses, or both.
• Instruction set design is intimately tied to processor datapath design.

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