UNIT II

Combinational Logic Design-II

CO2:Build modular combinational circuits with MUX/DEMUX, Decoder, and Comparator

etc.
CONTENTS
Multiplexers and their use in combinational logic designs,
Multiplexer trees,
De-multiplexers and their use in combinational logic designs,
Decoders,
Demultiplexer trees,
Design Examples
Arithmetic Circuits.
BCD - to – 7 segment decoder,
Code converters.
4-bit Binary Adder,
4-bit BCD adder ,
Digital Comparator,
Parity generators/checkers
Multiplexers and their use in combinational logic designs
Multiplexer (Data Selectors)

The term Multiplexer means many into one.

Multiplexing is the process of transmitting a large number of information over a
single line.
A Digital Multiplexer (MUX) is a combinational Circuit that select one digital
information from several sources and transmits the selected information on a
single output line.
A Multiplexer is also called a Data Selector.
The Multiplexer has several data input line and a single output line.
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-Multiplexers-and-Demultiplexer
Multiplexers and their use in combinational logic designs

A multiplexer is a combinational circuit that has 2n input lines and a single output line.
Simply, the multiplexer is a multi-input and single-output combinational circuit. The
binary information is received from the input lines and directed to the output line. On
the basis of the values of the selection lines, one of these data inputs will be connected
to the output.
Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is a
total of 2N possible combinations of inputs. A multiplexer is also treated as Mux.
 Cont.
MUX directs one of the inputs to its output line by using a control bit word
(selection line) to its select lines.
Multiplexer contains the followings:
❖ data inputs
❖ selection inputs
❖ a single output
❖Strobe/Enable
Selection input determines the input that should be connected to the output.
The multiplexer acts like an electronic switch that selects one from different.
2:1 Multiplexer
 4×1 Multiplexer:

In the 4×1 multiplexer, there is a total of four

inputs, i.e., A0, A1, A2, and A3, 2 selection lines,
i.e., S0 and S1 and single output, i.e., Y. On the
basis of the combination of inputs that are
present at the selection lines S0 and S1, one of
these 4 inputs are connected to the output. The
block diagram and the truth table of the 4×1
multiplexer are given below.
 Truth Table: Logical circuit of the above expression is given
below:

The logical expression of the term Y is

as follows:
Y=S1'S0'A0+S1'S0A1+S1S0'A2+S1 S0 A3
 8×1 Multiplexer:

In the 8 to 1 multiplexer, there are total eight

inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7,
3 selection lines, i.e., S0, S1and S2 and single
output, i.e., Y. On the basis of the combination
of inputs that are present at the selection lines
S0, S1, and S2, one of these 8 inputs are
connected to the output. The block diagram
and the truth table of the 8×1 multiplexer are
given below.
 Truth Table: Logical circuit of the above expression is given below:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2’.A2
+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5
+S0'.S1.S2 .A6+S0.S1.S3.A7
Multiplexer ICs
Multiplexer Tree: A number of m-to-1 multiplexers can be arranged in a tree topology to
obtain a bigger n-to-1 multiplexer is called Multiplexer Tree
16:1 mux are the largest available ICs therefore meet the larger input needs there should
be a provision for expansion. This can be achieve with the help of Strobe/Enable inputs and
Multiplexer Trees.
 8 ×1 multiplexer using 4×1 and 2×1 multiplexer
We can implement the 8×1 multiplexer using a lower order multiplexer. To implement the
8×1 multiplexer, we need two 4×1 multiplexers and one 2×1 multiplexer. The 4×1
multiplexer has 2 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1
selection line.
For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1 multiplexer produces
one output. So, in order to get the final output, we need a 2×1 multiplexer. The block
diagram of 8×1 multiplexer using 4×1 and 2×1 multiplexer is given below.
8 ×1 multiplexer using 4×1. (Special Case)

Let us implement 8x1 MUX by using 4x1 MUX. This is a special case in MUX tree. We
require 8x1 MUX which has 8 data lines. Let number of inputs be n1= 8, but the available
MUX is 4x1 which has 4 inputs so n2=4
The next step is to divide 8/4 = 2,
let us take this 2 again and divide by 4 i.e 2/4 = 0.5
It is clear from the above calculation that we have to use 2.5 MUX! How are we going to
use 2.5 MUX is the obvious question now.
We have 4x1 MUX i.e two select lines, but we need 3 select lines in order to design 8x1
MUX. This means that all of the inputs of the third 4x1 are not used. This is a problem, so
we cannot use this method to implement this case.
We can use enable input to implement this. Let us see how we use this enable. The most
important and helpful part in this procedure is the truth table. This table gives all the ideas
to implement the higher order MUX by using lower order MUX.
Here we have two 4X1 multiplexers which have inputs as D0,D1,D2,D3,D4,D5,D6
andD7 as shown in the circuit diagram below. We can see from the below diagram that
enable input is given to the second 4X1 MUX and its complemented input to first 4X1
MUX. Let us see what is the advantage of doing this.

Look at the first four cases of the truth table; S2 = 0. Note that Enable is considered as S2
here. In this case, Second MUX will not work because the enable is low and when enable is
zero, the output is always zero. But for the first MUX enable is 1 and this MUX works.
Now the output depends upon the select line. The working is same as 4X1 multiplexer.
Boolean function implementation Using MUX
1. Any Boolean function with variable can be implemented with MUX.
2. Any Boolean function with variable can be implemented with MUX and a NOT gate.

Example 1: Implement the given Boolean function using 8:1 Mux

Example : Implement the Boolean function using 4:1 MUX.
Example: Implement the Boolean function using 8:1 MUX.
MSB Reduction Technique:
For Implementing any Boolean function of n-variable with a MUX, we require some
general procedure.
1)Express the function in its Standard SOP form.
2)In the ordered sequence of variable, connect variable to to the select input and the single
variable to the input line with complement or uncomplemented form including 0 and 1.
3)List the inputs of MUX (all the minterms) in two rows. The row list all those minterms
where single variable is complemented and row with uncomplemented form.
4)Circle all the minterms of function and inspect each column separately.
5)If two minterms in a column are not circled, apply to the corresponding MUX input.
6)If two minterms are circled, apply to the corresponding MUX input.
7)If one minterm is circled (either upper or lower row), then its front value is the
corresponding MUX input.

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De-Multiplexers and their use in combinational logic designs
The De-Multiplexer is a combinational logic circuit that performs the reverse operation of
multiplexer (Several output lines, one input line).
De -Multiplexer means one to many. A De-Multiplexer is a circuit with one input and many
output. By applying control signal, we can steer input to the any output. Few types of
De -Multiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16 De -Multiplexer
A DE multiplexer(DEMUX) is a device that allows digital information from one source to be
routed onto a multiple lines for transmission over different destinations.
In other words, A DEMUX is a combinational circuit that receives information on a single
line And transmits this on to possible output lines.
The selection of a specific output line is controlled by the bit values of selection line.
A demultiplexer can also known as a‘distributor’,since it transmits the same data to different
destination.
The circuit can be used as a Binary to Decimal Decoder.
Applications of Demux
•Demultiplexers are used for the reconstruction
of parallel data and ALU circuits.
•The demultiplexer receives the output signals
of the multiplexer and converts back to the
original form of the data at the receiving
end. MUX and DEMUX work together to
carry out the process of communication.
•Demultiplexer helps to store the output of the
ALU in multiple registers and storage units in
an ALU circuit.
•A serial to parallel converter is used for
reconstructing the parallel data from the
incoming serial data stream.
 DeMultiplexer
Tree
2x4 Decoder
Another View
3x8 Decoder

34
Example
4x16 Decoder
Inputs
Output
E A B C D

0 X X X X 0

1 0 0 0 0 Y0

1 0 0 0 1 Y1

1 0 0 1 0 Y2

1 0 0 1 1 Y3

1 0 1 0 0 Y4

1 0 1 0 1 Y5

1 0 1 1 0 Y6

1 0 1 1 1 Y7

1 1 0 0 0 Y8

1 1 0 0 1 Y9

1 1 0 1 0 Y10

1 1 0 1 1 Y11

1 1 1 0 0 Y12

1 1 1 0 1 Y13

1 1 1 1 0 Y14

1 1 1 1 1 Y15

36
37
Full Adder with Decoder
 Arithmetic Circuits
1-Digit BCD ADDER/4-Bit BCD ADDER

The digital systems handles the decimal number in the form of binary coded decimal
numbers (BCD). A BCD Adder Circuit that adds two BCD digits and produces a sum digit
also in BCD. BCD numbers use 10 digits, 0 to 9 which are represented in the binary form 0
0 0 0 to 1 0 0 1, i.e. each BCD digit is represented as a 4-bit binary number. When we write
BCD number say 526, it can be represented as

Here, we should note that BCD cannot be greater than 9.

The addition of two BCD numbers can be best understood by considering the three cases
that occur when two BCD digits are added.
✔ Sum Equals 9 or less with carry 0
Let us consider additions of 3 and 6 in BCD.

The addition is carried out as in normal binary addition and the sum is 1 0 0 1,
which is BCD code for 9.

✔ Sum greater than 9 with carry 0

Let us consider addition of 6 and 8 in BCD
The sum 1 1 1 0 is an invalid BCD number. This has occurred because the sum of the
two digits exceeds 9. Whenever this occurs the sum has to be corrected by the addition
of six (0110) in the invalid BCD number, as shown below

After addition of 6 carry is produced into the second decimal position.

✔ Sum equals 9 or less with carry 1
Let us consider addition of 8 and 9 in BCD

In this, case, result (0001 0001) is valid BCD number, but it is incorrect. To get the correct
BCD result correction factor of 6 has to be added to the least significant digit sum, as
shown below
 Going through these three cases of BCD addition we can summarize the BCD addition
procedure as follows :
1.Add two BCD numbers using ordinary binary addition.
2.If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper
BCD form.
3.If the four-bit sum is greater than 9 or if a carry is generated from the four-bit sum, the
sum is invalid.
4.To correct the invalid sum, add 01102 to the four-bit sum. If a carry results from this
addition, add it to the next higher-order BCD digit.
Thus to implement BCD Adder Circuit we require :
•4-bit binary adder for initial addition
•Logic circuit to detect sum greater than 9 and
•One more 4-bit adder to add 01102 in the sum if sum is greater than 9 or carry is 1.
The logic circuit to detect sum greater than 9 can be determined by simplifying the
boolean expression of given BCD Adder Truth Table.
As shown in the Fig. the two BCD numbers, together with input carry, are first added in
the top 4-bit binary adder to produce a binary sum. When the output carry is equal to zero
(i.e. when sum ≤ 9 and Cout = 0) nothing (zero) is added to the binary sum. When it
is equal to one (i.e. when sum > 9 or Cout = 1), binary 0110 is added to the binary sum
through the bottom 4-bit binary adder. The output carry generated from the bottom binary
adder can be ignored, since it supplies information already available at the output-carry
terminal.

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4-bit Parallel Adder using Full Adders.

Recap

• What is a half adder?

• A Half-Adder is a logic circuit that adds 2-binary bits.

• What is full adder?

• A Full-Adder is a logic circuit that adds 3-binary bits.

• For both Full-Adder and Half-Adders there are two outputs Known as Sum
and Carry.
Truth Table of full adder
 4-bit parallel adder
• A binary adder is a logic circuit that can add two binary numbers.
• The binary operation performed by the 4-bit parallel adder can be explained with
the help of below example.
Example:
Let the two binary numbers that are to be added are
C3 C2 C1 C0 Ci
A3 A2 A1 A0 Ai
B3 B2 B1 B0 Bi Here,
S3 S2 S1 S0 Si
• A3 A2 A1 A0 = Ai is known as Augend.
CS CR Cq CP Ci+1
• Bi = B3 B2 B1 B0 is known as Addend.
• Si = S3 S2 S1 S0 is known as sum.
• Ci = C0 C1 C2 C3 is known as input carry.
• Ci+1 = Cp Cq Cr Cs is known as output carry.
4-bit parallel Adder using Full Adders:

Fig. 1

Fig 1 shows the inter connection of four full adders (FA) to implement a 4-bit parallel
binary adder.
An n bit adder requires n Full Adders with each output carry connected to the input
carry of the next higher order Full Adder.
• The working can be explained with two binary numbers
that are to be added are
A = 1 0 1 1 , B = 0 0 1 1 And
input carry Ci = 0 1 1 0
• For the Full Adder (0) inputs are A0=1, B0=1 and C0=0.
• It produces S0=sum=0; carry C1=1
• For the Full Adder(1) inputs are A1 = 1, B1= 1 and the carry from the Full
Adder 1 is C1=1.
• It produces S1= sum = 1, carry C2=1.
• For the third Full Adder(2) inputs are A2=0,B2=0,C2=1.
• It produces S2= sum =1 and carry C3= 0.
• Similarly for the fourth Full Adder (3)inputs are A3=1 , B3=0 and C3=0.
• It produces sum = S3=1 and carry = C4 =0
The above operation of 4-bit parallel Adder is shown in Table 1.

If input carry = 0 1 1 0 = Ci

Augend = 1 0 1 1 = Ai

Addend = 0 0 1 1 = Bi

Sum = 1 1 1 0 = Si

Output carry = 0 0 1 1 = Ci+1

Table 1
✔ Advantage of Binary Adder and Subtractor
•Low Design Complexity: Both binary adder and subtractor circuits are easy to design
using logic gates like XOR, AND, and OR.
•High-Speed Operations: Binary adders such as parallel adders-and subtractors can do
their operations at a high speed.
•Versatility: It allows the same hardware : to add ,to subtract. Saving on redundancy of
separate components and designs for different functions.
✔ Disadvantages of Binary Adder and Subtractor
•Carry Propagation Delay: In a simple ripple carry adder, the carry has to ripple through
all stages of the adder; this increases the computation time as more bits are added. This
will be more for a larger number of bits in binary.
•Hardware Complexity: The more the number of bits, the more complicated the circuit
gets due to more gates. To eliminate the problem of delays, higher versions of adders such
as carry lookahead adders are included which increases complexity.
https://www.geeksforgeeks.org/4-bit-binary-adder-subtractor/

n-bit Binary adder using n-full adders

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Block diagram of n-bit Binary adder communications/second-year/sem-1/digital-circuits/unit-3-co
mbinational-circuits-5
Parity generator and checker

Parity bit:
A parity bit is an extra bit that is added to the message bits or data-word bits on the
sender side. Data-word bits along with parity bits is called a code word. The parity bit is
added to the message bits on the sender side, to help in error detection at the receiver
side. The additional bit added to the information bits is called parity bit. The number of
1’s in the new word decides the even or odd parity.
Even Parity : If the total number of 1’s in the binary word, including the parity bit are
even then it is called even parity.

Ex: 1 1 1 1 0
Odd Parity : If the total number of 1’s in the binary word, including the parity bit are
odd then it is called odd parity.
Ex: 1 1 1 0

3-bit Even Parity Generator:

The K-map simplification for 3-bit message even parity generator is
From the above parity checker truth table, the simplified expression of the parity bit can be
written as

The above expression can be implemented by using two Ex-OR gates. The logic diagram
of even parity generator with two Ex – OR gates is shown below. The three bit message
along with the parity generated by this circuit which is transmitted to the receiving end
where parity checker circuit checks whether any error is present or not.
3-bit Odd Parity Generator:
The three inputs- A, B and C produces P - the output parity bit, so as to make the total
number of 1’s (including P) odd.
3-bit Even Parity Checker:
Consider that three input message along with even parity bit is generated at the transmitting
end. These 4 bits are applied as input to the parity checker circuit, which checks the
possibility of error on the data. Since the data is transmitted with even parity, four bits
received at circuit must have an even number of 1s. If any error occurs, the received message
consists of odd number of 1s.
The table shows the truth table
for the Even Parity Checker in
which PEC = 1 if the error
occurs, i.e., the four bits
received have odd number of
1s and PEC = 0 if no error
occurs, i.e., if the 4-bit message
has even number of 1s.
The above logic expression for the even parity checker can
be implemented by using three Ex-OR gates as shown in
figure. If the received message consists of five bits, then
one more Ex-OR gate is required for the even parity
checking.
3-bit Odd Parity Checker:
Consider that a three bit message along with odd parity bit is transmitted at the transmitting
end. Odd parity checker circuit receives these 4 bits and checks whether any error are present
in the data.
If the total number of 1s in the data is odd, then it indicates no error, whereas if the total
number of 1s is even then it indicates the error since the data is transmitted with odd parity at
transmitting end.
The figure shows the truth table for odd parity
generator where PEC =1 if the 4-bit message
received consists of even number of 1s (hence
the error occurred) and PEC= 0 if the message
contains odd number of 1s (that means no
error).
 Applications and Limitations of Parity Generator
•The parity bit is used in applications where a simple error detector is needed and the
transmission can be repeated if an error occurs.
•This method needs only a single bit to detect errors, which can increase the number of
transmissions within a period.
•The most important application is in serial data transmission.
•Other applications of parity bits are SCSI buses, PCI buses, and many microprocessor
instructions caches.
This simple parity code suffers from two limitations:
•Firstly, the addition of a single parity bit cannot be used to detect two-bit errors.
•Secondly, the single-bit parity code cannot be used to localize or identify the error bit even if
one bit is in error. If a binary stream with errors is received, the receiver must discard it.
Parity Generator/Checker ICs
There are different types of parity generator
/checker ICs are available with different input
configurations such as 5-bit, 4-bit, 9-bit, 12-bit,
etc. One of the most commonly used and standard
type of parity generator/checker IC is 74180.
It is a 9-bit parity generator or checker used to
detect errors in high speed data transmission or
data retrieval systems.
This IC can be used to generate a 9-bit odd or
even parity code or it can be used to check for
odd or even parity in a 9-bit code (8 data bits and
one parity bit).
This IC consists of eight parity inputs
from A through H and two cascading
inputs. There are two outputs even sum
and odd sum. In implementing generator
or checker circuits, unused parity bits
must be tied to logic zero and the
cascading inputs must not be equal.
If this IC is used as an Even Parity
Checker and when a parity error occurs,
the ‘sum even’ output goes low and ‘sum
odd’ output goes high. If this IC is used as
an Odd Parity Checker, the number of
input bits should be odd, but if an error
occurs the ‘sum odd’ output goes low and
‘sum even’ output goes high