Unit IV – Logic
Families
Logic Families:
TTL NAND gate,
Specifications, Noise margin, Propagation delay,
fan-in, fan-out,
TTL,
ECL,
CMOS families.
Programmable logic devices: Concept of
Programmable logic devices,
Study of PROM, ROM, DRAM, SRAM, PAL, PLA,
Introduction to FPGA and CPLD
Merits & Demerits of Digital ICs
Merits
✔ It reduces the overall size of the system.
✔ It reduces the overall Cost of the system.
✔ It improves the reliability of the system by reducing wiring
interconnections.
✔ It reduces the power consumption of the system.
Demerits
✔ It can not handle large power
✔ Electrical components like R,L, transformers and large
Capacitors can not be implemented wit great precision.
1. Propagation Delay and Threshold voltage.
Propagation delay justifies the speed of operation of digital IC. It is
a delay of signal transition from input to output.
It is the average transition time of signal from input to output.
It is measured in terms of nano seconds.
Threshold voltage explains the voltage at which transition is
happening
2. Power Dissipation
Power Dissipation per Logic gate:
Pdn = Pd/n
4A. Fan Out
4B. Fan In
5. Voltage Parameters
6.Current Parameters
7.Noise Immunity
8. Operating Temperature
9.Power Supply Requirements
Case-I :If any one input is logic ‘0’
Then BE junction of T1 will be forward biased and CB junction
will be reverse biased, Hence T1 operates in active region. As CB
region is reverse biased T2 will remain cut-off and hence T3,
So output will be logic high.
Case-II :If all inputs are logic ‘1’
Then BE junction of T1 will be reverse biased and CB junction
will be forward biased, As CB region is forward biased T2 will
turned ON and hence T3, So output will be logic low.
As this NAND gate can be connected to any other gate then there
will be load capacitance connected in the output so there are two
cases that will happen
1. If T3 is OFF then capacitor will charge through R4, in that cae
RC time constant will be decide speed of operation. To have
low time constant value ,R4 should be low.
2. When T3 is ON, High current will flow through R4 as value is
small. It will increase the Power dissipation.
We need High speed with low power dissipation hence
When T3 is OFF, R4 should be low and When T3 is ON, R4
should be High.
But R4 is a passive element offering fixed resistance.
This variable resistance is implemented using Totempole output
TTL.
TTL NAND Gate with Totempole output.
Figure illustrates a basic two-input
TTL NAND gate schematic. Transistor
Q1 is the input transistor. Inputs, such
as A and B, feed the emitter of Q1.
Transistor Q2 serves as a phase splitter,
and transistors Q3 and Q4 create a
totem pole output that provides high
stability and a high fan-out capability
for the output.
When inputs A and B are on -- logic 1
or high -- transistors Q2 and Q3 turn on
and act as amplifiers, while transistor
Q4 turns on to create a logic 0 or low
logic output. When either or both
inputs A and B are off -- logic 0 or low
-- transistors Q2 and Q4 turn off to
create a logic 1 or high logic output.
P-MOS
CMOS Inverter
Working of CMOS Inverter:
When input is low or logic ‘0’, then VSG > VT for this
PMOS transistor and that’s why PMOS will be ON.
On the other end, for NMOS transistor, VGS < VT.
that means when input is logic ‘0’, PMOS transistor
will be ON and NMOS transistor will be OFF.
And that’s why the output will be connected to 5V.
Moreover, since PMOS passes strong logic ‘1’ , the
output will be very close to supply voltage.That means
when Vin is logic ‘0’ then output is logic ‘1’.
On the other end, when Vin is logic ‘1’, then PMOS
will be OFF and NMOS will ON.
So, in that case, the NMOS transistor will pull-down
the output voltage to logic ‘0’. And since NMOS
passes strong ‘0’, so output will be very close to 0V.
https://www.allaboutelectronics.org/cmos-logic-gates-ex
plained/
https://www.tutorialspoint.com/digital-electronics/implementation-of-nand-nor
-gate-using-cmos.htm
https://www.youtube.com/watch?v=za5ZvFLfg0c
Comparison of Logic Families
Advantages of Programmable Logic Devices
Programmable Logic Devices (PLDs) have numerous advantages that make
them vital tools in the field of digital system design. Some of the important
benefits of programmable logic devices are listed here −
•Programmable logic devices (PLDs) are easy to program and reprogram.
Hence, they provide significant flexibility in terms of designing and
implementation of a variety of logic functions.
•PLDs allow for designing custom logic circuits to fulfil the specific
requirements of applications. This can be done by programming the internal
logic circuits of the device.
•PLDs can be used in prototyping and testing of digital circuits which help in
new product development at a faster rate. By speeding up the product
development process, PLDs help to reduce the time and cost involved in
hardware design.
•PLDs provide a fast and cost-effective way of developing medium to complex
digital logic circuits and systems. PLDs help to develop simple, less expensive,
and compact digital systems by integrating a large number of logic functions
and components into a single device.
•PLDs also support modern processing techniques like parallel processing,
pipeline processing, etc. This feature helps to achieve high performance by
simultaneous execution of logic functions.
Programmable Read Only Memory (PROM)
Read Only Memory (ROM) is a memory device, which stores the
binary information permanently. That means, we cant change that
stored information by any means later. If the ROM has
programmable feature, then it is called as Programmable ROM
(PROM). The user has the flexibility to program the binary
information electrically once by using PROM programmer.
PROM is a programmable logic device that has fixed AND array
& Programmable OR array. The block diagram of PROM is
shown in the following figure.
Here, the inputs of AND gates are not of programmable type. So,
we have to generate 2n product terms by using 2n AND gates
having n inputs each. We can implement these product terms by
using nx2n decoder. So, this decoder generates n min terms.
Here, the inputs of OR gates are programmable. That means, we
can program any number of required product terms, since all the
outputs of AND gates are applied as inputs to each OR gate.
Therefore, the outputs of PROM will be in the form of sum of
min terms.
https://www.youtube.com/watch?v=Cd19ohX0770&list=
PLAuW6sm6dy0yRMXL47Kz4nfhB7tURK88p&index=3
Example
Let us implement the following Boolean functions using PROM.
A(X,Y,Z)=∑m(5,6,7)
B(X,Y,Z)=∑m(3,5,6,7)
The given two functions are in sum of min terms form and each
function is having three variables X, Y & Z. So, we require a 3 to 8
decoder and two programmable OR gates for producing these two
functions. The corresponding PROM is shown in the following
figure.
Here, 3 to 8 decoder generates eight min terms. The two
programmable OR gates have the access of all these min terms.
But, only the required min terms are programmed in order to
produce the respective Boolean functions by each OR gate. The
symbol X is used for programmable connections.
Example: Design a combinational circuit using a ROM. The circuit
accepts a 3 bit number and produces a Binary output equal to
square of input number.
1.Input: A 3-bit number can represent the decimal numbers 0 to 7
(i.e., 000 to 111).
Example: Implement Full Adder using PROM.
Solution
Block Diagram of a Full Adder can be represented as:
Logic Diagram: There are three input variables
= A, B, C, therefore we will be using a 3:8
decoder.
Example :Implement the following Boolean functions using
PROM.
Random Access Memory (RAM)
Random Access Memory (RAM) is a type of computer memory
that stores data temporarily. When you turn off your computer, the
data in RAM disappears. It is a volatile memory.
RAM is much faster than secondary storage, allowing quick access
to data.
Types of RAM:
Static RAM (SRAM)
Faster
Expensive
Used in cache memory
Dynamic RAM (DRAM)
Slower, needs refreshing
Cheaper
Used in main memory of computers
Static RAM: The SRAM bitcell is the basic building block of
SRAM memory. A cell holds a single bit value for as long as
there is power.
The two access points to the cell are known as bitlines (BL). The
bitlines comprise of the stored bit value and its complement
(BL’)
Two access transistors sit on the bitlines in order to enable and
disable access to the stored data for reading and writing
operations. The signal that controls the access transistors is
referred to as a wordline (WL).
Dynamic RAM:
DRAM stores data by “writing a charge to the capacitor by way of
an access transistor” DRAM looks at the state of charge in a
transistor-capacitor circuit. A charged state is a 1 bit; the low
charge is seen as a 0 bit.
DRAM uses capacitors that lose charge over time due to leakage,
even if the supply voltage is maintained. Since the charge on a
capacitor decays when a voltage is removed,
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PLAuW6sm6dy0yRMXL47Kz4nfhB7tURK88p&index=1
Programmable Array Logic
It is most commonly used PLD.
It has Programmable AND gates and Fixed OR gates.
Structure is simple but less flexibility compared to PLA
PLA Architecture
Example:
Implement the following Boolean expression with the help
of programmable array logic (PAL)
X=AB+AC’
Y= AB’ + BC’
The above given two Boolean functions are in the form of SOP
(sum of products). The product terms present in the Boolean
expressions are X & Y. So, the total required logic gates for
generating the above two equations is AND gates-4 OR
programmable gates-2. The equivalent PAL logic diagram is
shown below.
The AND gates which are programmable have the right of entry for normal as
well as complemented variable inputs. In the above logic diagram, the available
inputs for each AND gate are A, A’, B, B’, C, C’. All the product terms are
obtainable at the inputs of an each OR gate. Here, the programmable
connections on the logic gate can be denoted with the symbol ‘X’.
Here, the OR gate inputs are fixed. Thus, the required product terms are
associated with each OR gate inputs. As a result, these gates will generate
particular Boolean equations.
Example: Realize the given function by using PAL: Any form
from sum of product (SOP) form or product of sum (POS) can be
used for realization of a Boolean function.
There are three inputs A, B, C and three functions X, Y, Z. Using
sum of product (SOP) terms to express the given function as
follows:-
X(A,B,C)=∑(2,3,5,7)
Y(A,B,C)=∑(0,1,5)
Z(A,B,C)=∑(0,2,3,5)
Following Truth table will be helpful in understanding function on
number of inputs:
Here ,place 1 as we take in part of the question( for example there
is given that X=2,3,5,7 place 1 in the column of X for this values)
Example :Realize the given function by using PAL
X(A,B,C)=∑(2,3,6,7)
Y(A,B,C)=∑(0,2,3,5)
Z(A,B,C)=∑(1,6,7)
Programmable Logic Array
The definition of term PLA presents the Boolean function in the
form of a sum of product (SOP). In the programmable logic
array, the connections of logic gates like AND & OR are
programmable. In this kind of method, every connection can be
done using a fuse on each intersection point wherever the
unnecessary connections can be detached by the fuse blowing.
Steps to Program PLA:
Step 1: Find Boolean function from the truth table.
Step 2: Identify number of buffers.
Step 3: Implement Boolean function using PLA
Example: Implement the following function using PLA
F1 = AB’C’ + ABC’ + ABC
on simplifying we get : F1 = AB + AC’
F2 = A’BC + AB’C + ABC
on simplifying we get: F2 = BC + AC
Example: Implement the following Boolean expression with the
help of programmable logic array (PLA)
X=AB+AC’
Y = AB’ +BC + AC’
The above given two Boolean functions are in the form of SOP
(sum of products). The product terms present in the Boolean
expressions are X & Y, and one product term that is AC’ is
common in every equation. So, the total required logic gates for
generating the above two equations is AND gates-4, OR
programmable OR gates-2. The equivalent PLA logic diagram is
shown below.
X=AB+AC’
Y = AB’ +BC + AC’
Difference between PAL and PLA
Introduction to FPGA and CPLD
https://www.youtube.com/watch?v=SJyyD2KJyrE
https://www.elprocus.com/what-are-pal-and-pla-design-
and-differences/
https://studytronics.weebly.com/programmable-logic-de
vices.html https://www.youtube.com/watch?v=lAqERUtAsqk
https://www.slideshare.net/slideshow/programmable-log
ic-devices-234332283/234332283 1
https://www.slideshare.net/slideshow/programmable-log
ic-devices-plds/56506628 2
https://www.scribd.com/presentation/250034325/Progra
mmable-Logic-Devices-Ppt 3
https://www.slideshare.net/slideshow/unit-5-programma
ble-logic-devicespdf/261014977 4
