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-- Company:
-- Engineer:
--
-- Create Date: 07.05.2024 13:32:50
-- Design Name:
-- Module Name: Point_add - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Point_add is
GENERIC (
wid : INTEGER := 256
);
PORT(
Px : IN STD_LOGIC_VECTOR(wid - 1 DOWNTO 0);
Py : IN STD_LOGIC_VECTOR(wid - 1 DOWNTO 0);
Qx : IN STD_LOGIC_VECTOR(wid - 1 DOWNTO 0);
Qy : IN STD_LOGIC_VECTOR(wid - 1 DOWNTO 0);
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
start : IN STD_LOGIC;
Rx : OUT STD_LOGIC_VECTOR(wid - 1 downto 0);
Ry : OUT STD_LOGIC_VECTOR(wid - 1 downto 0);
done : OUT STD_LOGIC
);
end Point_add;

architecture Behavioral of Point_add is

component Multmod is
GENERIC (
wid : INTEGER := 256
);
PORT(
m : IN STD_LOGIC_VECTOR(wid - 1 DOWNTO 0);
 r : IN STD_LOGIC_VECTOR(wid - 1 DOWNTO 0);
p : IN STD_LOGIC_VECTOR(wid - 1 DOWNTO 0);
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
start : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(wid - 1 downto 0);
done : OUT STD_LOGIC
);
end component;

component Powmod is
GENERIC (
wid : INTEGER := 256
);
PORT(
a : IN STD_LOGIC_VECTOR(wid - 1 DOWNTO 0);
e : IN STD_LOGIC_VECTOR(wid - 1 DOWNTO 0);
m : IN STD_LOGIC_VECTOR(wid - 1 DOWNTO 0);
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
start : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(wid - 1 downto 0);
done : OUT STD_LOGIC
);
end component;

component c_addsub_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
CLK : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(255 DOWNTO 0)
);
END component;

component c_addsub_0t IS
PORT (
A : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
CLK : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(255 DOWNTO 0)
);
END component;

component c_addsub_0a IS
PORT (
A : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
CLK : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(255 DOWNTO 0)
);
END component;

constant p : std_logic_vector(255 downto 0) :=

x"fffffffffffffffffffffffffffffffffffffffffffffffffffffffefffffc2f";
constant pm1 : std_logic_vector(255 downto 0) :=
x"fffffffffffffffffffffffffffffffffffffffffffffffffffffffefffffc2e";
constant pm2 : std_logic_vector(255 downto 0) :=
x"fffffffffffffffffffffffffffffffffffffffffffffffffffffffefffffc2d";
signal Qxsub : std_logic_vector(wid - 1 downto 0);
signal Qysub : std_logic_vector(wid - 1 downto 0);
signal Qsub_doneL : std_logic_vector(5 downto 0);
signal QxMod : std_logic_vector(wid - 1 downto 0);
signal QxMod_done : std_logic;
signal QxMod_doneL : std_logic_vector(5 downto 0);
signal QxMods : std_logic_vector(wid - 1 downto 0);
signal s : std_logic_vector(wid -1 downto 0);
signal s_done : std_logic;
signal sSq : std_logic_vector(wid -1 downto 0);
signal sSq_done : std_logic;
signal sSq_doneL : std_logic_vector(9 downto 0);
signal Rxt : std_logic_vector(wid - 1 downto 0);
signal Rxreg : std_logic_vector(wid - 1 downto 0);
signal Qxsub2 : std_logic_vector(wid - 1 downto 0);
signal QxS : std_logic_vector(wid -1 downto 0);
signal QxS_done : std_logic;
signal QxS_doneL : std_logic_vector(5 downto 0);

begin

Qxsub_b: c_addsub_0a
PORT map(
A => Qx,
B => Px,
CLK => clk,
S => Qxsub
);

Qysub_b: c_addsub_0a
PORT map(
A => Qy,
B => Py,
CLK => clk,
S => Qysub
);

process(clk, rst)
begin
if (rst='1') then
Qsub_doneL <= ( others=>'0' );
elsif (clk'event and clk='1') then
Qsub_doneL <= Qsub_doneL(Qsub_doneL'high - 1 downto 0) & start;
end if;
end process;

Qxmod_b: Powmod
GENERIC map(
wid => wid
)
Port map(
a => Qxsub,
e => pm2,
m => p,
clk => clk,
rst => rst,
start => Qsub_doneL(Qsub_doneL'high),
result => QxMod,
 done => QxMod_done
);

process(clk, rst)
begin
if (rst='1') then
QxMod_doneL <= ( others=>'0' );
elsif (clk'event and clk='1') then
QxMod_doneL <= QxMod_doneL(QxMod_doneL'high - 1 downto 0) & QxMod_done;
end if;
end process;

Qxmodsub_b: c_addsub_0a
PORT map(
A => p,
B => QxMod,
CLK => clk,
S => QxMods
);

Scalc_b: Multmod
generic map(
wid => wid
)
port map(
m => Qysub,
r => QxMods,
p => p,
clk => clk,
rst => rst,
start => QxMod_doneL(QxMod_doneL'high),
result=> s,
done => s_done
);

SSq_b: Multmod
generic map(
wid => wid
)
port map(
m => s,
r => s,
p => p,
clk => clk,
rst => rst,
start => s_done,
result=> sSq,
done => sSq_done
);

Rxsub_b: c_addsub_0t
PORT map(
A => sSq,
B => Qx,
CLK => clk,
S => Rxt
);

Rxsub2_b: c_addsub_0
 PORT map(
A => Rxt,
B => Px,
CLK => clk,
S => Rxreg
);

Rx <= Rxreg;

Qxsub3_b: c_addsub_0t
PORT map(
A => Qx,
B => Rxreg,
CLK => clk,
S => Qxsub2
);

process(clk, rst)
begin
if (rst='1') then
sSq_doneL <= ( others=>'0' );
elsif (clk'event and clk='1') then
sSq_doneL <= sSq_doneL(sSq_doneL'high - 1 downto 0) & sSq_done;
end if;
end process;

QxS_b: Multmod
generic map(
wid => wid
)
port map(
m => s,
r => Qxsub2,
p => p,
clk => clk,
rst => rst,
start => sSq_doneL(sSq_doneL'high),
result=> QxS,
done => QxS_done
);

Qysub3_b: c_addsub_0t
PORT map(
A => QxS,
B => Qy,
CLK => clk,
S => Ry
);

process(clk, rst)
begin
if (rst='1') then
QxS_doneL <= ( others=>'0' );
elsif (clk'event and clk='1') then
QxS_doneL <= QxS_doneL(QxS_doneL'high - 1 downto 0) & QxS_done;
end if;
end process;

done <= QxS_doneL(QxS_doneL'high);

end Behavioral;