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A New Simplified Space Vector PWM Scheme for Two-Level Voltage Source
Inverter

Conference Paper · May 2015

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 PCIM Europe 2015, 19 – 21 May 2015, Nuremberg, Germany

A New Simplified Space Vector PWM Scheme for Two-Level

Voltage Source Inverter
Hani Muhsen, Sebastian Hiller, Technische Universität Chemnitz, Germany,
[email protected]

Abstract
This paper proposes and analyzes a new structure for generating a space vector pulse width
modulation in the linear zone, and it is dedicated to the two-level voltage source inverter. The
study aims to produce three reference signals that can be used later to generate SVPWM
signals. Unlike, the classical SVPWM, the proposed method will depend on extracting voltage
signals based on the pulse width calculations during the rotation of the reference vector instead
of calculating the turn-on and off times. The generated reference signals will be compared then
with a carrier signal in order to retrieve the switching pulses; the scheme has been investigated
by simulation and implemented in FPGA to confirm the experimental validation of the approach.

1. Introduction

Space vector pulse modulation (SVPWM) is a favored topology that can control power
converters due to its remarkable profits over the conventional PWM in terms of harmonics
reduction, better utilization of the DC bus voltage and its suitability for variable frequency
applications. For instance, in variable frequency applications; SVPWM is essential in order to
simplify the control of the induction motors, which considers a non-straight forward issue;
thereby the usage of the SVPWM will ease their control. SVPWM differs from the classical
sinusoidal-width modulations in the complexity of switching times computations; it begins
mainly by minimizing three-phase representation to a two-phase system, which is known as
alpha-beta transformation in order to estimate the switching times by creating a rotated
reference vector. Aforementioned vector usually rotates with a speed corresponds to the
switching speed in the new plane, which is divided equally into six sectors such that each
sector contains two boundary vectors that have been used to calculate the projection of the
rotated reference vector on the sector’s borders. Hence, the turn-on and off times will be
calculated [1-4]. In this work; the proposed strategy will generate referential voltage signals
that will be compared with a carrier like the SPWM in order to generate the SVPWM pulse
sequences; the extracted reference signals will be formed based on the summation of the
pulse widths during the rotation of the reference vector and they will be multiplied with the
duration of the consistent sectors within alpha-beta plane. Therefore, pulse widths formulae in
the initial phase will be extracted as an alternative to turn-on and off times and then the
produced reference signals will be compared with a carrier signal in the final phase in order to
recover the required pulse widths on the output as in the classical SVPWM. This paper is
divided into four sections; the first section that has been presented discussed the introduction,
and section II will discuss the mathematical background of the simplified scheme. Simulation
and the experimental results are presented in section III and conclusion will be given in section
IV.

2. Simplified Two Levels CB-SVPWM

Classical SVPWM relies on generating a rotating field vector that represent the output voltage
in order to generate the switching pulses; by calculating the turn-on and off times within the
different sectors time. Therefore, this mission begins by simplifying the three-phase

ISBN 978-3-8007-3924-0 472 © VDE VERLAG GMBH · Berlin · Offenbach

 PCIM Europe 2015, 19 – 21 May 2015, Nuremberg, Germany

representation into two-phase system by the Clarke transformation; where, the normalized
three-phase voltages to the dc input voltage can be expressed by

= (1 ⁄ √3) ∙ ( ) (1)
= (1 ⁄ √3) ∙ ( + 2 /3) (2)
= (1 ⁄ √3) ∙ ( + 4 /3) (3)

Assuming balanced three-phase loads; the transformation can be simplified and expressed by
(4) and (5). Well known that the power circuit of two-level three-phase inverter is consisted of
six switches that are distributed equally to three legs of the inverter so that each one will contain
two complementary switches. Consequently, eight switching vectors (states) will divide the
alpha-beta plane to six equally sectors with 60° angle, some of these sectors are in the same
quadrant. Whereas, the six active vectors to form a regular Hexagon and the zero
switching vectors , lie on the zero as depicted in figure 1.a.

= (3/2) ∙ = 0.866 ∙ ( ) (4)

= (√3/2) ∙ ( − ) = 0.5 ∙ ( + 2 /3) − 0.5 ∙ ( + 4 /3) (5)

(1.a) (1.b)
Figure 1: (1.a) Sectors and switching sequence in d-q plane. (1.b) Turn-on and off times definitions
within switching period.
Accordingly, the pulse width of each phase leg = , , in all sectors have been calculated
using equations (6) and (7), where the turn-on and off times have a special definition in the
proposed method as shown in figure 1.b. The formulae of the turn-on and off times in the
different sectors have been extracted from [5] and based on these equations; the pulse widths
formula have been placed.
, = , − , (6)
= , + , (7)
In order to simplify the representation of the pulse widths in the complete alpha-beta plane;
four groups of vectors have been defined, where each group consists of three different vectors
that cover the corresponding quadrant and they will be used to form the pulse widths equations.
Although the preliminary derivation showed the requirement of four different groups but the
simplified version proved the ability to represent all of the groups using the elements of group
1 due to the relation among the different groups as listed in table 1.

ISBN 978-3-8007-3924-0 473 © VDE VERLAG GMBH · Berlin · Offenbach

 PCIM Europe 2015, 19 – 21 May 2015, Nuremberg, Germany

As a result, the final pulse widths in different sectors have been summarized in table 2; where
“sec” represents the sector and “Quad” represents the quadrant. The next phase was to
produce the reference voltage signals; which have been done by summing the multiplication
of the pulse widths with the corresponding sector time periods for each phase as in (8).
, = ∙[ ∙ +( + )∙ ∙ −( + )∙ ∙
− ∙ − ∙ −( + )∙ ∙ (8)
+( + )∙ ∙ + ∙ ]

Quad 1 Quad 2 Quad 3 Quad 4

=| | + (1/√3) ∙ = ( + /6) =− =− =
=| | − (1/√3) ∙ = ( − /6) =− =− =
= (2/√3) ∙ = ( + /2) = =− =−
Table 1: Vectors groups in the different quadrants.

Seeing that (8) is not in the simplest form; the formula can be oversimplified by substituting the
sinusoidal values of A1,B1 as in table 2 and the same procedure still valid for the other phases.
Hence the reference voltage signals can be given by
, = ∙[ ∙ + ∙ ] (9)
, = ∙ [− ∙ + ∙ ] (10)
, = ∙ [− ∙ − ∙ ] (11)
Where X, Y, and Z represent the effective sectors after constructing the reference waveforms
and they are given as the following
=[ + + + ] (12)

=[ + + + ] (13)

=[ + + + ] (14)
The same way as the sinusoidal PWM, the reference signals will be compared with a carrier
signal with a switching frequency , which represents the sampling frequency and equals to
the switching frequency. The carrier signal will have a peak value equals to 2 ∙ to ensure
the modulation in linear zone. The previous contrasting will result in generating the SVPWM
switching pulses, which will be applied later to control the inverter’s switches.

Sector , , ,
1 ∙ ∙ (− + ) ∙ (− )
2 Quad1 ∙( + ) ∙( ) ∙ (− )
2 Quad2 ∙ (− − ) ∙( ) ∙ (− )
3 ∙ (− ) ∙( ) ∙( − )
4 ∙ (− ) ∙( − ) ∙( )
5 Quad3 ∙ (− − ) ∙ (− ), ∙( )
5 Quad4 ∙( + ) ∙ (− ) ∙( )
6 ∙( ) ∙ (− ) ∙ (− + )
Table 2: Calculations of the pulses width for each sector.

ISBN 978-3-8007-3924-0 474 © VDE VERLAG GMBH · Berlin · Offenbach

 PCIM Europe 2015, 19 – 21 May 2015, Nuremberg, Germany

Finally, the complete steps for generating proposed SVPWM structure have been summarized
in an algorithm, which starts from the desired output voltages and ends up with the pulses
sequence for each phase.

Figure 2: Proposed SVPWM generation algorithm

3. Simulations and Experimental Results

In the initial phase; an open source simulation software called GeckoCIRCUITS, which has the
capabilities to perform a fast simulation, has verified the validation of the proposed topology.
So, the reference signal for each phase was implemented based on the formulae in (9-11),
where A1, B1, and C1 have been represented by sinusoidal signals. On other hand X, Y, and Z
have been represented by digital pulses with a unit amplitude. According to the appropriate
sectors that are included within X; the duty cycle of has been set to 66.6% and frequency
to 100 Hz in order to cover the required ones, while the duty cycle of Y was set to 33.3% with
the same frequency of X, but the output has been inverted. The last signal Z, which has been
implemented by a NAND logic gate and its inputs were X and inverted Y.
The final step is to generate the switching pulses, which can be done by comparing the
modulating signal (reference signal) with a triangular or a sinusoidal carrier signal as shown in
figure 3.a, which has an identical frequency equals to the switching frequency. The positive
and negative amplitude of the carrier signal is equal in magnitude to the double of the switching
period magnitude (2 ∙ ) to confirm the operation in the linear zone, in other words the
modulation index must be less than one. The comparison with the positive part of the carrier
will generate the switching sequence of the top switches in each leg, and the negative one is
used with the bottom side switches. Based on the previous steps, the generated pulses out of
the comparison have been applied on the switches’ control inputs. Hence, the output
waveforms were formed on the load side as shown in Figure 3.a.
Similarly, the topology has been implemented in FPGA using LabVIEW 2014; the same
procedures, which has been clarified previously in the simulation stage has been applied to
FPGA.

ISBN 978-3-8007-3924-0 475 © VDE VERLAG GMBH · Berlin · Offenbach

 PCIM Europe 2015, 19 – 21 May 2015, Nuremberg, Germany

In addition to the simplicity of implementation of the proposed technique; it offers a high speed
execution and low memory size requirement, where implementation has been done in the
FPGA within a single cycle time loop (SCTL), which means the execution speed is 25 ns owing
to the clock speed, which was 40 in the used FPGA. Proceeding from the necessity to
validate the implemented code; FPGA output control signals have been applied on a three
phase inverter that consisted of six IGBTs as the main element. Hence, the switching frequency
has been set to 10 and the fundamental frequency was set to 50 .

(3.a) (3.b)

(3.c) (3.d)
Figure 3: (3.a) Modulation signals and output waveforms by (simulation) and (3.b) by (experiment).
(3.c) Harmonic Analysis of phase current and (3.d) of line-to-line voltage.

Figure 3.b depicted the experimental three-phase voltages, line to line voltage and three-phase
currents, which agreed with simulation results in terms of the smooth output current, dc usage
and the total harmonics distortion. Dc utility can be controlled by changing the modulation index,
which is defined as the ratio between the carrier and the reference signal like the SPWM but
the difference here in the real value of the modulation index. In the proposed method; the
modulation index with a unit magnitude corresponds to 0.866 in the classical SVPWM; in other
words, the maximum output phase voltage will be 2/3 and in case of the line-to-line
voltage.
The effective output voltage of each phase is given by /√8, while the effective line to line
voltage is √3 /√8 , which means better utilization of the dc input voltage and hence reducing
the currents in the switches at the same power rating and this will lead to enhance the inverter’s
efficiency. The next step was to analyze the harmonic distortion in the generated waveforms

ISBN 978-3-8007-3924-0 476 © VDE VERLAG GMBH · Berlin · Offenbach

 PCIM Europe 2015, 19 – 21 May 2015, Nuremberg, Germany

by applying fast Fourier transform on the phase current and line-to-line voltage. The results of
harmonics analysis is depicted in figure 3.c and 3.d, where THD in the phase current was 1.2%
and in case of line-to-line voltage was found to be 5%. The analysis outcomes showed a low
distortion in the output waveforms.

Figure 4: Normalized three-phase currents trajectory in 0 space. Normalized three-phase voltages

trajectory in 0 space (right).

Moreover, the extracted results showed a reduction in the magnitudes of the third, fifth and
the seventh harmonics, which gives the proposed method one more advantage in variable
frequency applications due to the reduction of undesirable effects of the odd harmonics on
the loads. Particularly, in induction motor the odd harmonics consider the responsible of
generating extra heat in the motor, which may destroy the isolation of the coils’ conductors.
Therefore, the SVPWM, third harmonic injection and other control topologies have been
proposed previously to work on reducing the effects of these harmful harmonics.
The study is going further in analyzing the normalized trajectories of the output currents and
voltages to show the accuracy of the output waveforms using the proposed structure. Figure
4 depicts three-phase currents trajectory in 0 space and it shows a circular behavior in
the − plane due to the smooth sinusoidal currents behavior in the time domain. Likewise,
the three-phase voltages points should be scattered within the hexagon in the plane, but
the results showed few dispersed points outside the hexagon that resulted from the voltage
peaks and oscillations during the switching time and they are not related to the planned
switching strategy.

4. Conclusions
In this paper, a new methodology to generate the SVPWM pulses has been proposed and
analyzed. The task was accomplished by extracting three referential voltages out of pulse
widths calculations during the rotation of the reference vector in the alpha-beta plane.
Consequently, the created reference signals will be compared with a carrier in order to
recover the required switching times instead of calculating the turn-on and off times to avoid
computations complexity and more memory size requirement. The proposed structure has
been investigated in simulation and practically in FPGA and it was applied on a three-phase
inverter. Thus, the results showed a good performance in terms of low total harmonic
distortion, enhanced quality of the output currents and the simplicity of the implementation
in FPGA.

ISBN 978-3-8007-3924-0 477 © VDE VERLAG GMBH · Berlin · Offenbach

 PCIM Europe 2015, 19 – 21 May 2015, Nuremberg, Germany

5. References
[1] Zhou, Keliang, and Danwei Wang. "Relationship between space-vector modulation and
three-phase carrier-based PWM: a comprehensive analysis [three-phase inverters]." Industrial
Electronics, IEEE Transactions on 49.1 (2002): 186-196.
[2] Iqbal, Atif, and Shaikh Moinuddin. "Comprehensive relationship between carrier-based
PWM and space vector PWM in a five-phase VSI." Power Electronics, IEEE Transactions on
24.10 (2009): 2379-2390.
[3] Rathnakumar, D., J. LakshmanaPerumal, and T. Srinivasan. "A new software
implementation of space vector PWM." SoutheastCon, 2005. Proceedings. IEEE. IEEE, 2005.
[4] Seo, Jae Hyeong, Chang Ho Choi, and Dong-Seok Hyun. "A new simplified space-vector
PWM method for three-level inverters." Power Electronics, IEEE Transactions on 16.4 (2001):
545-550.
[5] Quang, Nguyen Phung, and Jörg-Andreas Dittrich. "Vector control of three-phase AC
machines". Berlin, Heidelberg: Springer, 2008.

ISBN 978-3-8007-3924-0 478 © VDE VERLAG GMBH · Berlin · Offenbach

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