ISSN 2278-3091

International Journal of Advanced Trends in Computer Science and Engineering, Vol. 3 , No.1, Pages : 322 – 325 (2014)
Special Issue of ICETETS 2014 - Held on 24-25 February, 2014 in Malla Reddy Institute of Engineering and Technology, Secunderabad– 14, AP, India

DESIGN OF LOW POWER DIGITAL I/O CELL WITH ESD CIRCUIT PROTECTION

P.Sai Kumar S Pedda Krishna M.Girsih Kumar

Dept of Electronics and Dept of Electronics and Dept of Electronics and
Communication Engineering, Communication Engineering, Communication Engineering,
Malla Reddy institute of Malla Reddy institute of National Institute of Technology
engineering & technology engineering & technology Hamirpur,
Hyderabad,A.P, India. Hyderabad,A.P, India. Hamirpur, H.P, India.
E-mail1: [email protected] E-mail1: [email protected] E-mail 2:[email protected]

Abstract— A novel low-power I/O cell is proposed in this work. regular structure. The I/O cell provides the functional
The new input/output (I/O) cell is found to reduce the I/O power building blocks used for synthesis and a layout
consumption, which has been considered as the major power representation of the cells for place-and-route. This
dissipation of the whole chip. The maximum operating clock is guarantees that a physical or layout representation of the
500 MHz given a 10-pF off chip load. Physical measurements of
cells exists when the design is implemented using place-and
the proposed I/O cells show that the delays of the transmitter and
the receiver are 2.7ns and 1.6 ns, respectively. The largest route tools. Standard Cell- Based Design refers to a design
power/bandwidth of the proposed design is 38.9 W/MHz when approach that uses a library of basic building blocks called
transmitting. This work also facilitates ESD circuit that prevents standard cells. This flow requires an I/O cell of predefined
the circuit from high voltage spikes. logic circuits implementing a selected range of logic
Keywords- ESD protection, i/o cells,trnsmitter, receiver. functions, characterized for power, area and timing.
I. INTRODUCTION [1] presents low-power and small-area digital I/O
cell. The new input/output (I/O) cell drastically reduces the
In the digital transmission of chips through longs wires on I/O power consumption, which has been considered as the
the printed circuit board (PCB) is the input/output (I/O) major power dissipation of the whole chip. In [2] the authors
cells which are responsible for voltage level shifting and have employed three circuit techniques to reduce the power
electrostatic discharge (ESD) protection. Besides, long and area of I/O circuits. Input multiplexed transmitter
wires mean huge and loads to the I/O cells. The I/O cells, architecture with reduced voltage swing allows a small
namely I/O pads, are asked to supply sufficient current to transmitter to be used while still providing most of the speed
drive these large loads. Hence, not only is the pad area advantage of an output-multiplexed architecture. [4]
large, but also the power consumption occupied a great Presents new CAD tools for CMOS I/O circuit design. To
portion of the overall power. Most of prior CMOS I/O cells our knowledge, this is the first layout extractor developed
utilized very large area to accommodate large driving for CMOS I/O circuit reliability. Unlike normal extractors,
transistors as well as large passive elements. As the supply the circuit schematic is extracted based on the specified
voltage of the chip is dropped, the switching speed of the ESD conditions. In addition, parasitic BJTs are extracted for
I/O pads is reduced proportionally which in turn neutralize circuit simulation. J. G. Hansen [6] presents the design of
the high-speed performance of any CMOS digital core cell library for minimal leakage currents. The advantages of
design. The output voltage swing in the transmitter of our having library are faster time-to-market and reuse of often
new cell is reduced to about half of the supply voltage. In complex logic functions. The design methodology and
the mean time, the high-speed and high-throughput digital requirement has been described. It is obvious that a very
core design is not affected by using a feedback loop careful procedure and format has to be followed in order to
containing transistors with different threshold voltages. The produce a good cell library for ASIC design. Asral [5],
power dissipation is also drastically reduced. The receiver of explains the standard cell design requirements, standard cell
the proposed I/O cell, on the other way around, restores the design and the characterization process. The
signal level such that it can be faithfully decoded to be the characterization process in this paper is much easier then the
original data. Neither reference bias nor passive element is complexed one or the industrial flow that was given in the
required in the proposed design. above TSMC data book.

The I/O cell is typically called a “Standard I/O The paper is organized as follows. Section II deals with the
Cell” because of its common interface implementation and back ground knowledge about input/output cell design.

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 ISSN 2278-3091
International Journal of Advanced Trends in Computer Science and Engineering, Vol. 3 , No.1, Pages : 322 – 325 (2014)
Special Issue of ICETETS 2014 - Held on 24-25 February, 2014 in Malla Reddy Institute of Engineering and Technology, Secunderabad– 14, AP, India

Section III presents the proposed methodology to reduce huge static charges gets induced into the chip through
power dissipations at transmitter and receiver end of a human body/machine/second IC, which results in failure of
digital I/O cell. Section IV is devoted to results and chip.ESD results in
discussion and paper is concluded in section V. • Dielectric Failure resulting in gate oxide breakdown when
the gate of the input buffer is connected to the input pad [9].
• Thermal failure results in melting of the device [9].
II INPUT/OUTPUT CELL • Latent failure which is a typical failure which increases
A typical IO cell design in digital data transmission is shown in leakage current/reduces gate oxide integrity without any
Figure1 change in functionality. This problem cannot be identified
immediately.
These problems can be overcome by proper
handling of IC’s or by using packaged IC’s or by
introducing a ESD protection circuit to the IC pins which
diverts huge voltages/high current from the internal circuitry
thus protecting the IC.
This figure shows the Low voltage trigger
ggNMOS circuit designed to clamp the high rise time ESD
signal. Here the resistor and capacitor pair acts as high pass
Fig.1.Basic I/O cell design. filter [2] to filter the signal of rise time more than 400pS. As
we know the TR =2.2RC [8] Assume R=1K therefore
The pre-driver, when C=18.18pF.
enabled, supplies the gate drive to the driver composed of a pair
of huge pMOS and nMOS transistors to steer a large current to
or from the long wire. This traditional design cannot directly
be voltage scaled so as to achieve the power saving by
P=f.C.V2, where f is the switching frequency, C is the load,
and V is the supplied voltage. The reason is obvious: if the
supplied voltage of the driver is shifted from VDD (supply
voltage) to 1/2 VDD, the drain current of M11 becomes
Fig.2.ESD circuit.

ID  VSG  Vthp 2 1   VSF  VSD,sat  During the normal operation NMOS is in cut-off as the gate
2 is connected to ground through 1K resistor. But the
Where, VSG is the voltage drop between the occurrence of ESD event will trigger the gate and make the
source and the gate of is M11; VSF is that between the transistor to conduct hence clamp the over voltage stress due
source and the drain of M11.The decrease of VSF caused to ESD event. The ESD current can go up to 1A the size
by the shrinkage of the supplied voltage results in the NMOS is designed to sink this current. By using linear
decrease of ID. Thus, the driving capability as well as the current equation of NMOS [Appendix] it was found that
speed is deteriorated. Adding a reference 1/2 VDD bias WN=180nm LN=180nm.
to the driver pair might be considered as a good idea.
Regardless of using a band gap bias or a second voltage
supply, the area penalty is highly unacceptable since the B) DESIGN OF TRANSMITTER AND RECEIVER:
load is large. On top of this drawback, the reference 1/2
VDD bias usually has a poor driving capability which
severely affects the supplied voltage of the driver pair.
The consequence could be malfunction and large power
dissipation [6]-[7].

III PROPOSED METHODOLOGY

a) ESD PROTECTION CIRCUIT:

ESD failure is one of the major IC reliability issue
in the field. Most of the customer complaints in the field due
Fig.3. proposed methodology of transmitter design.
to chip failures are due to ESD issues. This occurs when

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 ISSN 2278-3091
International Journal of Advanced Trends in Computer Science and Engineering, Vol. 3 , No.1, Pages : 322 – 325 (2014)
Special Issue of ICETETS 2014 - Held on 24-25 February, 2014 in Malla Reddy Institute of Engineering and Technology, Secunderabad– 14, AP, India

Referring to Fig.3, which is the proposed transmitter, Data m 1P5M process and better processes.) The function of the
and Enable are signals generated by the digital core. ESD is receiver is described as follows.
the electrostatic discharging circuitry for the purpose of R1) When the gate drive of M43 is low to turn off M43,
protection [11]–[13]. The model of the pad as well as the node A is charged to VDD. Hence, the To_Chip signal is
bonding wire and package is shown in Fig.3. The operation low. The weak feedback latch composed of INV2 and M42
of the transmitter is described as follows. stabilizes the signal to the digital core.
T1) When Data is low and Enable is high, inverter INV1 R2) If the gate drive of M43 turns high, M43 will be turned
turns on M23 and M24 which in turn pull down node C and on to discharge node A. To_Chip signal, thus, is pulled
A, respectively, to ground. Then, the low voltage at node A high. As long as the voltage of the gate drive of M43, which
turns on M26 via INV0. is the received signal via the pad and ESD, is higher than the
T2) As soon as Data turns high, a wide M26 turns on M21 pre-determined 0.4 V, the voltage level of the signal sent to
right away. Node C, thus, will be charged to around 0.1V the internal digital core can be restored to VDD.
very shortly which turns on the zero- nMOS, M22. The
voltage at node A then is boosted to VDD. Thus, M26 is off IV RESULTS AND DISCUSSION
and M25 is turned on to ground node B which in turn shuts
down M21. The charging operation to node C is then
terminated. The final voltage level of node C after the
mentioned procedure will be kept around. Since neither
reference bias nor passive element is used in the design, the
transmitter size is extremely small. Notably, in order to
avoid the racing problem which might occur in the
procedure of shutting down M21.We have to ensure that
M26 is turned off before M25 is on. Otherwise, a large dc
current will be induced. The design of inverter INV0 is
different from the rest of the inverters. The pull down
transistor in INV0 is a zero- nMOS, as shown in Fig. 4. The
threshold voltage of the zero- nMOS, which provides a high
sensitivity to the variation of the voltage at node A, is 0.2 V
[14]. Hence, the gate drive at M26 will be discharged very
quickly. The final voltage level at node C does not have to
be very precisely a, which is the “high” of the output of the
transmitter. It will drift due to the temperature, process Fig.5. waveforms of transmitter design.
variation, or loading. As long as the a logic “1” sent by the
proposed transmitter is above 0.8 V for all process corners, The proposed methodology implemented on 180nm
it can be recovered correctly by the sophisticated receiver technology with a Vdd of 1.8v and with enable(en),
design which will be illustrated in the following section. enable(enb), input(din) taken as 1.8v .Fig. shows the
simulation results of transmitter it can be observed when
enable is set to 1, enb is set to 0, input(din) set to 1 the
output becomes high with voltage of 1.8v.

Fig.4. proposed methodology of receiver design.

The signal delivered by the transmitter will be contaminated

seriously by the noise and crosstalk of the transmission
lines. The quality of the signal present at the receiver is
expected to be poor. Referring to Fig. 5, the received signal
appears at the gate of M43 via pad and ESD circuitry. The
threshold voltage of M43 is chosen to be a medium V.
(Note: The medium- transistors are available in TSMC 0.25- Fig.6. waveforms of receiver design.

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 ISSN 2278-3091
International Journal of Advanced Trends in Computer Science and Engineering, Vol. 3 , No.1, Pages : 322 – 325 (2014)
Special Issue of ICETETS 2014 - Held on 24-25 February, 2014 in Malla Reddy Institute of Engineering and Technology, Secunderabad– 14, AP, India

The proposed methodology implemented on 180nm [7] Phillip E.Allen, Douglas R. Holerg, “CMOS Analog Circuit
technology with a Vdd of 1.8v and with input(dout) as 1.8v. Design", Second edition, Oxford university press, 2003.
Fig. shows the simulation results of receiver it can be
observed when input (dout) set to 1 the output becomes high [8] Jacob Baker, Boyce “CMOS circuit design, layout and
simulation", Prentice Hall India Ltd.
with voltage of 1.8v.
[9] Ming-Dou Ker, Kuo-Chun Hsu, “Overview of On-Chip
TABLE I Electrostatic Discharge Protection Design With SCR-Based
Devices in CMOS Integrated Circuits”, Device and Materials
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[10] H.Sarbishaei, O.Semenov, M.Sachdev, “Optimizing Circuit
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Power 1.8v 1.8v 1.8v
[11] M.-D. Ker and C.-H. Chuang, “Stacked-nMOS triggered
supply
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V CONCULSION pp.1046–1055, Aug. 2002.

[13] M. M. Lee, “Secondary protection scheme for CMOS I/O

In this paper presented a novel design of digital input/output buffers and core circuits and their ESD sensitivity,” in Proc. 6th
cell with ESD protection cell. The design presented Int. Physical &Failure Analysis of Integrated Circuits Symp., 1997,
satisfactory results regarding circuit safety without affecting pp. 109–114.
the logic naturality. The present work reduces the power
dissipation and propagation delay compared to the work [14] “TSMC 0.25–_mMixed-Signal 2P5M PIP or 1P5M+MIM
with basic I/O cells. Salicide 2.5V/5.0 V or 2.5 V/3.3 V Design Guideline,” TSMC,
Hsin-Chu, Taiwan,R.O.C., Data sheet: 2000.

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