Alfaisal University

College of Engineering
Department of Software and Electrical Engineering

EE 210/SE223
Digital Design

Chapter 3
Gate Level Minimization

1
 Outline
• 2, 3 and 4 variables K-map
• K-map simplification rules
• Don’t care conditions

Analyze and construct Boolean

functions, minimization, and
implementation with truth tables
and Karnaugh-maps.

Outcome 2 2
 Gate-Level Minimization
• Gate-Level Minimization refers to the design task
of finding an optimal gate-level implementation
of the Boolean functions describing a digital
circuit.
• This task is difficult to implement when the logic
has more than a few inputs.
• Computer-based logic synthesis tools minimize a
large set of Boolean equations efficiently and
quickly
• It is very important that the designer understand
the underlying mathematical description and
solution of the problem

3
 Gate-Level Minimization
• The complexity of the digital logic gates that
implement a Boolean function is directly related to the
complexity of the algebraic expression from which the
function is implemented

• Although the truth table representation of a function is

unique, when it is expressed algebraically it can appear
in many different, but equivalent, forms.

• The map method presented in this chapter provides a

simple, straightforward procedure for minimizing
Boolean functions.
– It is known as Karnaugh map or K-map

4
 Karnaugh Map
• It is a pictorial form of Truth Table
– Diagram made up of squares; each square represents a
minterm
• A method for simplifying Boolean functions into
– Sum of Products (SOP)
– Product of Sums (POS)
• The simplest algebraic expression should have
– Minimum # of terms
– With smallest possible # of literals (variables in
complemented or ordinary form) in each term
• This produces a logic circuit with a minimum # of
gates and gate inputs (minimum cost)
5
SOPE +
-- --

-
-
-
We'd Like
Each one means a

to recture the
dedicated AND gate ,
number of >
--
-

Herms that
we have
and
/or a dedicates
connection into the

final OR gate .
SOP = -
+ - +
-

t
-
-.
upi gl z

In each term, we'd also like to reduce

the number of Eal Ci .

e
.,
variables /

To reces the wiring in the

=>
into the first AND
stape
 Two-Variable Karnaugh Map (n=2)
Truth table Karnaugh map
x y y
x 0 1
0 0 m0
0 1 m1 0 m0 m1
1 0 m2 1 m2 m3
1 1 m3

• Each square (cell) à a minterm

– Represented by an AND term with n=2 variables
• Variable x appears primed in row 0 and unprimed in row 1
• Variable y appears primed in column 0 and unprimed in
column 1
6
Ephe
i ne
al
ay'+hy ,
Example for OR

· f 3 +x
= .
 I
F
I
As
f
we
=
By find larger
Legitimate
groupings for

= e
, the "1" ,
reche the
number

Literals
of
we

in

of A expression
the

=
 Two-Variable Maps: Examples
AND
x y xy y y

0 0 0 x 0 1
0 1 0 0 0 0
1 0 0
x 1 0 1
1 1 1

• A cellà a minterm and represented with n=2 literal

• Two adjacent cells
– in the same row or column (not diagonal)
– differ in only one literal
– represent a term with n-1=1 literal
7
 Two-Variable Maps: Examples
OR
x y y y
x+y 0 1
x
0 0 0
0 1
0 1
1
1 0 1 1 1 1
x
1 1 1
x+y
m1+m2+m3=x’y+xy’+xy
=(xy’+xy)+(xy+x’y)

= x+y
8
 Three-Variable Map (n=3)

• 2-bit Gray code is used for columns

• Only 1-bit changes between two adjacent cells
• Diagonal cells are not adjacent
• One cell represents a minterm with n=3 literals

9
Why use Gray code ?

·1 "X
i

i
 Gray Code
• Only one bit changes
during any transition
between two numbers
• Used in position
encoders

10
 Three-Variable Map (n=3)
• Two adjacent cells differ in only one literal
– in the same row or column (not diagonal)
– represent a term with n-1=2 literals
– “wrap around” cells are adjacent
• Example:
f (x,y,z) = Σ (2,3,4,5)

11
Three-Variable Map (n=3): Example 2
f (x,y,z) = Σ (1,3,4,6) =
x+
=
xz .

siz

⑭
D E
I

It t
12
Three-Variable Map (n=3): Example 3
• Four adjacent cells represent a term with n-2=1
literal

i
f (x,y,z) = Σ (0,1,2, 3,6,7) =

·
e
JE as
of

f a
= +
y .

13
 I
Reducing Literals in

"
of

-A-map
a 3-variable

z
37

·"I
6
%
a

o
of of 11 e

nyz it I ,

37

k
of 11 16 37

Fi
a
of of of 11 16
a

%,
O

f
Nz
= 1 .
Example
-

37

l
of o 1 ↓ 6

ziy
O
a

1⑧
O I 3
I
s
O

y'z
f = y + az + hy
Function Minimization using K-map (SOP)
• Find the K-map for a given function
• Find maximum size groups that cover all 1s
in the map
– Note: a group should not be a subset of another group
– Example: 3 literal K-map
• 1 cell group à 0 literals can be removed
• 2 cell group à 1 literal can be removed
• 4 cell group à 2 literals can be removed
• 8 cell group à Entire map; produces a function that is
always equal to 1
• To cover all 1s, you should choose:
– Fewer groups à fewer AND gates, and fewer inputs to
the OR gate
– Fewer literals within a group (larger group) àfewer
inputs to an AND gate
• This will result in Cost Minimization:
– Fewest # of gates and # of gate inputs 14
 Example 4:
• The truth table of the Boolean function g(x,y,z) is given below,
find the minimal SOP expression for g.
x y z

·
0 0 0 1
0 0 1 1 O
n

0 1 0 0
0 1 1 0 I

1 0 0 1

y
1 0 1 1
+ Dz
1 1 0 0
1 1 1 1

15
 Example 5
• Express the Boolean function
f(x,y,z)=x’z+x’y+xy’z+yz
(a) Sum of minterms, (b) minimal SOP

· O

a) [C , 213 , 3 , 7) ; b) E +my -

16
*
Four-Variable Map (n=4)
• 2-bit Gray code is used for both rows & columns
• One cell represents a minterm with n=4 literals
• For each cell, the minterm is obtained by
concatenation of the row # with the column #

17
 Four-Variable Map (n=4)
• 2 adjacent cells à a term with n-1=3 literals
• 4 adjacent cells à a term with n-2=2 literals
• 8 adjacent cells à a term with n-3=1 literal
• For adjacent cells
– Assume the right edge is connected to the left edge and top
to the bottom

18
The K-Map Torus

- 19
 Examples

• Minimize the following K-maps

x2 x2 x1 x2 x 2 x1 x2
x2 x1
x4 x3 x4 x3

I
x4 x3

o
00 01 11 10 00 01 11 10 00 01 11 10
Mo Mu un My MI
m, My ML Me my m

00 0 0 0 0 00 0 0 0 0 00 1 0 0 1

④
O
M4 W5 My ME
MH ms unt kn ws net m6

01 0 0 1 1 01 0 0 1 1 01 0 0 0 0
x x3 x3
⑧
3 C O I
3 Miz us Mis M14
min Was ms
mir M/s Mis MIL mak

11 1 0 0 1 11 1 1 1 1 11 1 1 1 0
x4 x4 x4

C
M8 ma MIL urlo
M8 my WH mo me wa m M10

10 1 0 0 1 10 1 1 1 1 10 1 1 0 1

x1 x1
.

A
24 23 · 2
24 / : +
xk + k4
+ Rise 2 + Rudy & .:
20
 Examples

• Minimize the following K-maps

x2 x2 x1 x2 x 2 x1 x2
x2 x1
x4 x3 x4 x3 x4 x3
00 01 11 10 00 01 11 10 00 01 11 10

00 0 0 0 0 00 0 0 0 0 00 1 0 0 1

01 0 0 1 1 01 0 0 1 1 01 0 0 0 0
x3 x3 x3
11 1 0 0 1 11 1 1 1 1 11 1 1 1 0
x4 x4 x4
10 1 0 0 1 10 1 1 1 1 10 1 1 0 1

x1 x1 x1

f 1 = x'1 x 4 + x 2 x'4 x 3 f 2 = x4 + x2 x3 f 3 = x'1x’3 + x'2 x 4 + x 1x 3 x 4

21
 Example
• Sometimes the minimum representation is not
unique.
• Example: Use a Karnaugh map to minimize
f(w,x,y,z)= S (1, 2, 5, 6, 7, 9, 10, 13, 14).
y z y y z y
wx wx

Gif gif
00 01 11 10 00 01 11 10

·
00 00

01 01
x x
11 11
w 8
w
10 10

z z

y'E + yet willz y't + ye't way 22

 Example
• Represent the logic function f(w,x,y,z)=w’xz+wxy+y’z on a
karnaugh map and then obtain the minimal SOP
representation.
y
y z
wx
00 01 11 10

yz
00 I
KE
⑪
01
+ Wxy +
x
.

11
w
10 (

23
23
 3

·all
is
o

e e
i e
 Five-Variable Map (n=5)
• Maps for more than 4 variables are not easy to use. *
-

• Five-variable maps require 32 cells.

• Use two 4-variable maps to make a 5-variable one
– Minterms 0 to 15 in one map. 16 to 31 in the other
one.

24
 Five-Variable Map (cont.)
• Each square in the A=0 map is adjacent to the
corresponding one in the A=1 map.

25
 Example
• f(A,B,C,D, E)= S(2, 6, 8, 9, 10, 14, 18, 22, 24, 25)

A=0 A=1

26
 Definitions
- -

• Implicant - a single minterm or group

of minterms that can be combined
together on the K-map. For example AB
the implicants in the example on the 00 01 11 10
right are A'B'C', A'BC', A'BC, ABC, C
A'C', A'B, and BC. 1 0
1 1 3 2

• Prime Implicant - Implicant that can 0

not be combined with another one to 6
remove a literal. For example: A'C', 1
4
1 5
1 7

A'B, BC.
• Each product term in the minimum
Sum of Products (SOP) expression is a
prime implicant.
• Essential Prime Implicant - A prime
imlpicant that includes a minterm not
covered by any other prime implicant.
• Essential prime implicants are found
by looking at each square marked with
a 1 and checking the number of prime 27
implicants that cover it.
 Selection Rule
1. Select all essential prime implicants
2. From the remaining prime implicants select
in such a way to minimize the overlap among
the prime implicants and every minterm is
included in some prime imiplicant

28
 Implicants
YZ
00 01 11 10
WX
0 1 1 1 3 2
00
4 5 7 6
01 1 1 1 1
12 13 15
11 1 1 14
8 9 11 10
10

WZ, WX, XZ are prime implicants

WZ, XZ are essential

29
 Examples
YZ
00 01 11 10
WX
1 0 1 3 2
00
Essential 4 5 7 6
01 1 1
12 13 15 14
11 1 1 1 Essential
8 9 11 10
10 1

Essential

F = YZ + XY + WXZ
30
 Examples
YZ
00 01 11 10
WX
00 1 0 1 3 1 2

4 5 7 6
Not 01 1 1
essential 12
11 1 13 15 14

8 9 11 10
10 1 1

Essential

Essential
WYZ
F = XZ + XYZ + or
WXY 31
 Examples

YZ
00 01 11 10
WX
0 1 1 3 2
00
4 5 7 6
01 1 1 1 1 All prime implicants
12 13 are essential
11 1 15 1 14
8 9 11 10
10 1

F = WX + YZ + XY

32
 Examples

YZ
00 01 11 10
WX
0 1 1 3 1 2
00
4 5 7 6
01 1 1
All prime implicants
12 13 15
11 1 1 1 14 are not essential
8 9 11 10
10 1

F = WXY + WXZ + WXY + WYZ

33
 Product of Sums Simplification
• Find the minimal SOP expression for the
complement of the function
– It can be done by combining 0s in the K-map of
the function
• Complement the resulting minimal SOP
expression using DeMorgan’s theorem to find
the minimal expression of the function in
product of sums (POS).

34
 Example
Simplify the following Boolean function F(A,B,C,D)=Σ(0,1,2,5,8,9,10) in
(a) sum of products (b) product of sums
C
F CD F’ C

-C
CD

D
AB 00 01 11 10 00 01 11 10

:
gi
AB
00 114 00 ·..
3

...
6

>
40s I 7 6
01 01 O O
B B
12 B 18 14 13 18 14
11 O
.

11
.

l
of "
A
10 , 10
10

↑
D

& 1) B') (B
I

B'D' A'CD + AB'C (i + (A + + D)

+
B'j
35
 Example (cont.)

• Cost (SOP) =4 (gates)+ 2+2+3+3 (gate inputs)=14

• Cost (POS) =4 (gates)+ 2+2+2+3 (gate inputs)=13
• The POS implementation has lower cost, so (b) is cheaper
to implement than the SOP implementation, (a)
36
 “Don’t Care” conditions
• Some logic circuits can be designed so that there
are certain input conditions for which there are no
specified output levels
• This is the case because these input conditions will
never occur
• Therefore, we “don’t care” whether the output is
HIGH or LOW
• Hence, we choose the don’t care as either 1 or 0
depending on which helps the K-map
minimization
37
 Even

:i
ABC D
-

Pompeii
G
ooo

e
o 0 O I

0
0 1 0

0 0 11

O 100

① 10/
of
!
10

ol 1 I

e
O G
o

0
O

1 0
I

X
A'D' + B'c'D'
01/
100
*

t with don't cames , D .

10/ X

I 10 ↓
1 1 1
 Elevator control
• We need to design a logic circuit to control an elevator
door in a three-story building. The circuit has four inputs.
M is a logic signal that indicates when the elevator is
moving (M=1) or stopped (M=0). F1, F2, and F3 are floor
indicator signals that are normally LOW, and they go
HIGH only when the elevator is positioned at the level of
that particular floor. For example, when the elevator is
lined up level with the second floor, F2=1 and F1 = F3 =
0. The circuit output is the OPEN signal which is
normally LOW and is to go HIGH when the elevator door
is to be opened.

38
 Elevator control
Truth Table M F1F2 F3 OPEN
0 0 0 0 0 M F1 F2 F3
0 0 0 1 1
0 0 1 0 1
0 0 1 1 x Elevator
0 1 0 0 1 control
0 1 0 1 x
0 1 1 0 x
0 1 1 1 x OPEN DOOR
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 x
1 1 0 0 0
1 1 0 1 x
1 1 1 0 x
39
1 1 1 1 x
 Elevator control
F2 F3
00 01 11 10
OPEN = M F2 + M F3 + M F1 M F1
0 1 1 x 3 1 2
F 00
4 5 7 6
01 1 x x x
12
11 x 13 x 15 x 14
8 9 11 10
10 x
M
F1
OPEN
F2

F3 40
 Designing using Product of Sum (POS)

F2 F3
Elevator control problem 00 01 11 10
M F1
POS for OPEN = M (F1+F2+F3) 0 0 1 x 3 2
00
4 5 7 6
01 x x x
12
M 11 0 x 13 x 15 x 14
8 9 11 10
F1 OPEN
10 0 0 x 0
F2 DOOR
F3

K-map showing 0’s

Note that this one is simpler than And don’t cares
the one we got from SOP!
41
 Summary of K-map process
• The K-map process has several advantages over
the algebraic method
– K mapping is a more orderly process
– Usually requires less steps
– Always produces a minimum expression (need to try
both SOP and POS)
• There are other techniques that designers use to
minimize logic circuits with more than four inputs.
Most of these techniques can be translated into a
computer program that will perform the
minimization
42
Exercise
B'D' + As + AB' + C'D
C

+ AC .

CD->

⑳O
AB 00 01 11 10
I
00 1 1 0
C
1
01 X 1 X 0
11 1 0 1 1

&
I
10
E 1 1 1 1

43
Exercise A 'B + A 'D + B'D .

~
CD->
AB 00 01 11 10
00
01 -
11
O
0
1
0
1
1
0
X
X
0
X
1
X
10
M
X 1 X X

44
Exercise A 'B
-
I
+ A 'D + B' D .

not needed !
-

~
CD->
AB 00 01 11 10
00
01 -
11
O
0
1
0
1
1
0
X
X
0
X
1
X
10
M
X 1 X X

44
Exercise

CD->

00 S
AB 00 01 11 10
0 1 X X L
01 1 1 X 1
11 -0 0 0 X

Y
10
-
X 1 X X

(A B) + B + D
44
Please note
all
-

you have
an obligation to cover

the Is .

(In the case of Pos , your obligation

is to cover
all the Os) .

each to
associate
-
In
covering , you want
1 with a
prime implicant
You do not have an
obligation to

cover all don't cares

This is worth repeating ,
so I will write

it again
- You do not have an
obligation to cover

all don't cares

covered
- A don't care should only be

if it helps making
a 1
part of
cant than the
a
bigger prime impli
it
One cover ,
'y .

-
-
 Universality of NAND and NOR Gates
-

• All Boolean expressions consist of various combinations

of the basic operations of OR, AND, and invert (NOT)
• Any expression can be implemented using combinations
of OR gates, AND gates, and NOT gates
• It is possible to implement any logic expression using
only NAND gates and no other type of gate
• It is also possible to implement any logic expression using
only NOR gates and no other type of gate
45
 Practical Motivation
• Digital circuits are more frequently
constructed with NAND or NOR gates rather
than with AND and OR gates.
• NAND and NOR gates are easier to fabricate
with electronic components
• They are the basic gates used in all IC
(Integrated Circuit) digital logic families

46
 Universality of NAND gates

NOT
A A
x = A×A = A

A×B AND
A A
B
1 2 1

x = A ×B
B

A A OR
x = A×B = A + B A
B
B
B 47
 Exercise

Generate the basic Boolean functions (AND,

OR, NOT) using only NOR gates.
-

Useful Exercise !
how the NAND
Also try
,
to understand
AND, OR, NOT
implementations for
came

about
-
48
 Implementing Basic gates Using
NAND/NOR
Basic gates à Inverter AND OR
using
NAND
1 (x·1)’=x’
Equivalent to x
Invert-OR
OR
x
(x·x)’=x’
NOR x
Equivalent to 0 x’
Invert-AND
x
(x+x)’=x’
49
 Two-level NAND-NAND
Implementation
1. Simplify the function and express it in SOP to find the AND-OR
implementation.
Example: F=AB+CD+E
2. Draw a NAND gate for each product term of the function that has at least
two literals.
3. Draw a single NAND gate (Invert-OR) in the 2nd level
4. A term with a single literal is complemented and applied as an input to the
second-level NAND gate.

A A
B B
C C
D F
D
E E E’
50
 Two-level NOR-NOR
Implementation
1. Simplify the function and express it in POS to find the OR-AND
implementation.
Example: G=(A+B)(C+D)E
2. Draw a NOR gate for each sum term of the function that has at least two
literals.
3. Draw a single NOR gate (Invert-AND) in the 2nd level
4. A term with a single literal is complemented and applied as an input to the
second-level NOR gate.

A A A
B B B
C G C C G
D D G D
E E’ E’
51
 Multi-Level NAND Circuits
• SOP and POS result in two level designs
• Not all designs are two-level, e.g. F=A(CD+B)+BC’
(without changing to SOP)
• How many levels does the function F have?
• How do we convert multilevel circuits to NAND
circuits?

52
 Multi-Level NAND Circuits &

• SOP and POS result in two level designs

• Not all designs are two-level, e.g. F=A(CD+B)+BC’
M

(without changing to SOP)

• How many levels does the function F have?
• How do we convert multilevel circuits to NAND
circuits?
~ o
②
⑳ ⑳
vo
O -
②
~ O

52
 NOR
-
Multi-Level NAND Circuits
,

• SOP and POS result in two level designs

• Not all designs are two-level, e.g. F=A(CD+B)+BC’
(without changing to SOP)
• How many levels does the function F have?
• How do we convert multilevel circuits to NAND
circuits?
% 8
O
⑳

② O
O o
o
8
52
 Multi-Level NAND Circuits (Rules)
1.Convert all ANDs to NAND gates
2.Convert all ORs to NAND gates with invert-OR
symbols
3.Check the bubbles, insert inverter if not compensated

53
 Multi-Level NAND Circuits (Example)
• Sometimes an inverter is required at the output.
• This increases the level of the NAND circuit.

G
C’
D
54
 Multi-Level NOR Circuits (Rules)
1. Convert all ORs to NOR gates
2. Convert all ANDs to NOR gates with invert-AND
3. Check the bubbles and insert inverter if not compensated

% %
O
O

④ O
o O
o O

O O

55
 Other 2-level Implementation
using AND-OR-Invert
• F=(AB+CD+E)’
– The complement of function should be expressed as
SOP
• It results in AND-NOR & NAND-AND
implementations

56
 Other 2-level Implementation
using OR-AND-Invert
• F=((A+B)(C+D)E)’
– The complement of function should be expressed as
POS
• It results in OR-NAND & NOR-OR
implementations

57
Other Two-Level Implementations

58
 (ky + xz + yz)

noot
· ②z
-> > -
O

-
L

:TODO NOR
AND-OR into
Example of converting
Alfaisal University
College of Engineering
Department of Software and Electrical Engineering

EE 210/SE223
Digital Design

Chapter 3
Gate Level Minimization

1
Exercise

CD->
AB 00 01 11 10
00 1 1 0 1
01 X 1 X 0
11 1 0 1 1
10 1 1 1 1

Expression becomes A’C’ + AC + AB’ + C’D’ + B’D’

2
Exercise

CD->
AB 00 01 11 10
00 0 1 X X
01 1 1 X 1
11 0 0 0 X
10 X 1 X X

Expression becomes A’D + CD’ + A’B + AB’

3
 Exercise

Generate the basic Boolean functions (AND,

OR, NOT) using only NOR gates.

(A+A)’ = A’A’ = A’
A

Two methods of
implementing NOT
using NOR gates

A (A+0)’ = (A)’ = A’
0

4
 Method of
implementing AND
A’ using NOR gates
A

(A’+B’)’ = (A’)’.(B’)’ = (A.B)

B B’

--------------------------------------------------------------------------------------------------------------------------------
Method of
implementing OR
using NOR gates
(A+B)’ = A’.B’
A
B ( (A’B’)+(A’B’) )’ =
(A’B’)’.(A’B’)’ =
(A+B).(A+B) =
(A+B)
5