Pipelining Concepts

Overview
Why Pipelining?
▪ Speed of execution of programs is influenced by many factors
▪ To improve performance – faster circuit technology to build processor and main memory
– Arrange the hardware so that more than one operation can be
performed at the same time
Pipelining is an implementation technique in which multiple instructions are overlapped in execution
• Pipelining is widely used in modern processors.
• Pipelining improves system performance in terms of throughput.
• Pipelined organization requires sophisticated compilation techniques.
Making the Execution of Programs Faster

• Use faster circuit technology to build the processor and the main memory.
• Arrange the hardware so that more than one operation can be performed at the same time.
• In the latter way, the number of operations performed per second is increased even though the
elapsed time needed to perform any one operation is not changed.
 Use the Idea of Pipelining in a Computer
Fetch + Execution
F : Fetch
E : Execute T ime
I1 I2 I3
T ime
Clock cycle 1 2 3 4
F E F E F E
1 1 2 2 3 3 Instruction

I1 F1 E 1
(a) Sequential execution

I2 F2 E 2
Interstage buffer
B1
I3 F3 E 3

Instruction Ex ecution
fetch unit (c) Pipelined execution
unit

Figure 8.1. Basic idea of instruction pipelining (2 stage).

(b) Hardware organization
 Use the Idea of Pipelining in a Computer
Time
Clock cy cle 1 2 3 4 5 6 7

Instruction

I1 F1 D1 E1 W1

I2 F2 D2 E2 W2

I3 F3 D3 E3 W3

I4 F4 D4 E4 W4

(a) Instruction execution div ided into f our steps

Interstageuff
b ers

D : Decode
F : Fetch instruction E: Execute W : Write
instruction and f etch operation results
operands
B1 B2 B3

(b) Hardware organization

Fi gure 8.2. A 4-stage pi pel i ne.

Fetch + Decode
+ Execution + Write

F Fetch : read the instruction from the memory

D Decode: decode the instruction and fetch operands
E Execute: perform the operation in the instruction
W Write : store the result in destination location
Role of Cache Memory

• Each pipeline stage is expected to complete in one clock cycle.

• The clock period should be long enough to let the slowest pipeline stage
to complete.
• Faster stages can only wait for the slowest one to complete.
• Since access time of main memory is very slow compared to the execution,
if each instruction needs to be fetched from main memory, pipeline is
almost useless.
• Fortunately, we have cache. Frequently accessed data is stored here to
reduce execution time.
Pipeline Performance

• The potential increase in performance resulting from pipelining is

proportional to the number of pipeline stages.
• However, this increase would be achieved only if all pipeline stages
require the same time to complete, and there is no interruption
throughout program execution.
• Unfortunately, this is not true.
 Time
Clock c
y cle 1 2 3 4 5 6 7 8 9

Instruction

I1 F1 D1 E1 W1

Pipeline Performance
I2 F2 D2 E2 W2

I3 F3 D3 E3 W3

I4 F4 D4 E4 W4

I5 F5 D5 E5

Fi gure 8.3. Effect of an xecuti

e on operati on taki ng more than one ycl
cl ock
e. c
Pipeline Performance

• The previous pipeline is said to have been stalled for two clock cycles.
• Any condition that causes a pipeline to stall is called a hazard.
• Data hazard – any condition in which either the source or the destination operands of an
instruction are not available at the time expected in the pipeline. So some operation has to
be delayed, and the pipeline stalls.
• Instruction (control) hazard – a delay in the availability of an instruction causes the pipeline
to stall.
• Structural hazard – the situation when two instructions require the use of a given hardware
resource at the same time.
Pipeline Performance

• Again, pipelining does not result in individual instructions being executed

faster; rather, it is the throughput that increases.
• Throughput is measured by the rate at which instruction execution is
completed.
• Pipeline stall causes degradation in pipeline performance.
• We need to identify all hazards that may cause the pipeline to stall and to
find ways to minimize their impact.
Quiz

• Four instructions, the I2 takes two clock cycles for execution. Pls draw the figure for 4-stage
pipeline, and figure out the total cycles needed for the four instructions to complete.
Pipelining Problems
Pipeline Parameters
• Twp = n. 𝑘.tc n-No. of instruction, k - No of Pipeline stages
• Tp = ( n+ 𝑘 -1) tc

• Speed Up, S= Twp = n.𝑘.tc = n.𝑘

Tp ( n+𝑘−1)tc ( n+𝑘−1)

• Throughput = n 1 (ideal condition, if n not given)

( n+𝑘−1)tc = tc

• Utilization or Efficiency, η = n.𝑘

( n+𝑘−1)𝑘

• η= n
( n+𝑘−1)

• S= 𝑘.η
 Question 1

Consider a 5-stage pipeline with cycle time of 5ns. Calculate the

execution time of 100 instructions and speed up due to pipeline. Also
find the utilization.
 Question 2
Consider a 5 stage pipeline. Delay of each stage is given as per 10ns, 16ns, 12ns,
11ns and 14ns, respectively. Calculate execution time of 100 instruction and
speed up due to pipeline.
Question:3
Question 4

Consider a pipeline having 5 stages with duration 10ns,

30ns,45ns,80ns and 35ns. If the buffer delay is 20ns,
calculate the speedup of pipelined processor.
Question 5
Question 6