Chapter 4

The Processor – Pipelining

 Exceptions and Interrupts
Exceptions and Interrupts
§ “Unexpected” events requiring change in flow of control
§ Different Instruction Set Architectures (ISAs) use the terms differently
§ Exception
§ Arises within the CPU
§ An unscheduled event that disrupts program execution; used to detect overflow.

§ Interrupt
§ An exception that comes from outside of the processor.
§ Some architectures use the term interrupt for all exceptions.

§ Dealing with them without sacrificing performance is hard

Exceptions and Interrupts: Events

Type of event From where? RISC-V terminology

I/O device request External Interrupt
Invoke the operating system
Internal Exception
from user program
Arithmetic overflow Internal Exception
Using an undefined
Internal Exception
instruction
Hardware malfunctions Either Exception or interrupt
Handling Exceptions
§ Two types of exceptions:
§ Undefined instruction and arithmetic overflow
§ The basic action that the processor must perform when an exception occurs
is to save the address of the of the offending instruction in the supervisor
exception program counter (SEPC) and then transfer control to the
operating system at some specified address.
§ SEPC: A 64-bit register used to hold the address of the affected instruction.
§ SCause: A 64-bit register used to record the cause/reason of the exception
Handling Exceptions Cont.
§ Vector Interrupts
§ the address to which control is transferred is determined by the cause of the
exception. For example, to accommodate two exception types, we might
define the following two exception vector addresses:
Exception type Exception vector address
Undefined instruction 00 0100 0000
System Error (hardware malfunction) 01 1000 0000

§ The addresses are separated by 32 bytes or eight instructions, and the OS must record
the reason for the exception and may perform some limited processing in this
sequence.
Pipeline with Exceptions
Pipeline with Exceptions
The key additions include a new input
with the value 0000 0000 1C09
0000hex in the multiplexor that
supplies the new PC value; a SCAUSE
register to record the cause of the
exception; and an SEPC register to
save the address of the instruction
that caused the exception.

The 0000 0000 1C09 0000hex input to

the multiplexor is the initial address
to begin fetching instructions in the
event of an exception. Although not
shown, the ALU overflow signal is an
input to the control unit.
Exception Example
§ Exception on add in
40 sub x11, x2, x4
44 and x12, x2, x5
48 or x13, x2, x6
4c add x1, x2, x1
50 sub x15, x6, x7
54 ld x16, 100(x7)
…
§ Handler
1C090000hex sd x26, 1000(x10)
1c090004hex sd x27, 1008(x10)
…
Exception Example
Exception Example
Assume the hardware malfunction is
detected during the EX stage and 0000
0000 1C09 0000hex is forced into the
PC. CC7 shows that the add and
following instructions are flushed, and
the first instruction of the exception-
handling code is fetched. The address
of the add instruction is saved: 4Chex.

Note. Although not shown, the ALU

overflow signal is an input to the
control unit.
Multiple Exceptions
§ Pipelining overlaps multiple instructions
§ Could have multiple exceptions at once
§ Simple approach: deal with exception from earliest
instruction
§ In complex pipelines
§ Multiple instructions issued per cycle
§ Out-of-order completion
§ Maintaining precise exceptions is difficult!
Precise & Imprecise Interrupt
§ Precise Interrupt, also called precise exception.
§ An interrupt or exception that is always associated with the
correct instruction in pipelined computers.

§ Imprecise Interrupt
§ Interrupts or exceptions in pipelined computers that are not
associated with the exact instruction that was the cause of
the interrupt or exception.
Multiple Issue
§ A scheme where multiple instructions are launched in one clock cycle.
§ Static multiple issue
§ An approach to implementing multiple-issue processor where many
decisions are made by the compiler before execution.
§ Compiler groups instructions to be issued together
§ Packages them into “issue slots” – instructions could be issued in a given CC
§ Compiler detects and avoids hazards
§ Dynamic multiple issue
§ An approach to implementing a multiple-issue processor where many
decisions are made during execution by the processor.
§ CPU examines instruction stream and chooses instructions to issue each cycle
§ Compiler can help by reordering instructions
§ CPU resolves hazards using advanced techniques at runtime
Speculation
§ An approach where the compiler or processor guesses the outcome of
an instruction to remove it as a dependence in executing other
instructions.
§ “Guess” what to do with an instruction
§ Start operation as soon as possible
§ Check whether guess was right
§ If so, complete the operation
§ If not, roll-back and do the right thing

§ Common to static and dynamic multiple issue

§ Examples
§ Speculate on branch outcome
§ Roll back if path taken is different
§ Speculate on load
§ Roll back if location is updated
Compiler/Hardware Speculation
§ Compiler can reorder instructions
§ e.g., move load before branch
§ Can include “fix-up” instructions to recover from incorrect guess

§ Hardware can look ahead for instructions to execute

§ Buffer results until it determines they are needed
§ Flush buffers on incorrect speculation
Speculation and Exceptions
§ What if exception occurs on a speculatively executed instruction?
§ e.g., speculative load before null-pointer check

§ Static speculation
§ Can add ISA support for deferring exceptions

§ Dynamic speculation
§ Can buffer exceptions until instruction completion (which may not occur)
 Static Multiple Issue
§ Issue Packet:
§ Compiler groups instructions into “issue packets”
§ Set of instructions that
§ Group of instructions that can be issued on a single cycle issues together in one
§ Determined by pipeline resources required clock cycle, the packet
may be determined
statically by the compiler
or dynamically by the
§ Think of an issue packet as a very long instruction processor.
§ Specifies multiple concurrent operations
§ Þ Very Long Instruction Word (VLIW)
§ A style of ISA that launches many operations that are
defined to be independent in a single-wide instruction,
typically with many separate opcode fields.
Scheduling Static Multiple Issue
§ Compiler must remove some/all hazards
§ Reorder instructions into issue packets
§ No dependencies with a packet
§ Possibly some dependencies between packets
§ Varies between ISAs; compiler must know!
§ Pad with nop if necessary
Static Two-Issue Pipeline in Operation Example
§ The ALU and data transfer instructions
are issued at the same time. Here we
have assumed the same five-stage
structure as used for the single-issue
pipeline.
§ Although, this is not strictly necessary, it
does have some advantages. In keeping
the register writes at the end of the
pipeline, it simplifies the handling of
exceptions and the maintenance of a
precise exception model, which become
more difficult in multiple-issue
processors
RISC-V with Static Dual Issue