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Assignment#7

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4 views

Assignment#7

Uploaded by

Rishabh pandey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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S24CSEU0667,KESHAV SHRINGI

1 How does a 4-to-2 Encoder function? Provide a truth table and explain.

Solution: The combinational circuits that change the binary information


into N output lines are known as Encoders. 4-to-2-line Encoder: In 4-to-2-
line encoder, there are total of four inputs, i.e., Y0, Y1, Y2, and Y3, and two
outputs, i.e., A0 and A1. In 4-input lines, one input-line is set to true at a
time to get the respective binary code in the output side. Below are the
block diagram and the truth table of the 4-to-2-line encoder.

Block diagram:

INPUTS OUTPUTS

Y3 Y2 Y1 Y0 A1 A0

1 0 0 0 0 0

0 1 0 0 0 1

0 0 1 0 1 0

0 0 0 1 1 1

The logical expression of the term A0 and A1 is as follows:

A1=Y3+Y2

A0=Y3+Y1
S24CSEU0667,KESHAV SHRINGI
2. What is the difference between Decoder and Demultiplexer?

Solution:

3. Implement a 2-to-4 decoder using Verilog.

Solution:
Verilog code for 2 to 4 line Decoder

module decoder_2_4(a,b,w,x,y,z);
output w,x,y,z;

input a,b;

assign w = (~a) & (~b);

assign x = (~a) & b;

assign y = a & (~b);

assign z = a & b;

endmodule

TEST BENCH
module decoder_2_4_test;
reg a,b;

wire w,x,y,z;

decoder_2_4 decoder_2_4_test(a,b,w,x,y,z);

initial

begin

#000 a=0; b=0;

#100 a=0; b=1;

#100 a=1; b=0;


#100 a=1; b=1;

end

initial

begin

$monitor($time,"a=%b,b=%b,w=%b,x=%b,y=%b,z=%b",a,b,w,x,y,z);

End

Endmodule

4. What is priority encoder? Write Verilog code for an 8-to-3 priority encoder.

Solution:

Priority Encoder

The priority encoder is a combinational logic circuit that contains 2^n input
lines and n output line and represents the highest priority input among all the
input lines. When multiple input lines are active high at the same time, then the
input that has the highest priority is considered first to generate the output. It
is used to solve the issues in binary encoders, which generate wrong output
when more than one input line is active high. If more than one input line is
active high (1) at the same time, then this encoder prioritizes every input level
and allocates the priority level to each input.
Verilog code for 8-to-3 Priority Encoder

module priority_encoder_8to3 (

input [7:0] in, // 8-bit input

output reg [2:0] out // 3-bit output

);

always @(*) begin

casez (in) // 'z' allows don't-care conditions for priority encoding

8'b10000000: out = 3'b111;


8'b01000000: out = 3'b110;

8'b00100000: out = 3'b101;

8'b00010000: out = 3'b100;


8'b00001000: out = 3'b011;

8'b00000100: out = 3'b010;

8'b00000010: out = 3'b001;

8'b00000001: out = 3'b000;

default: out = 3'b000; // Default case (no input active)

endcase

end

endmodule

TEST BENCH
module testbench;

reg [7:0] in;

wire [2:0] out;

priority_encoder_8to3 uut (.in(in), .out(out)); // Instantiate module

initial begin

$monitor("Time=%0t | Input=%b | Output=%b", $time, in, out);

in = 8'b00000001; #10; // Expect 000

in = 8'b00000010; #10; // Expect 001


in = 8'b00000100; #10; // Expect 010

in = 8'b00001000; #10; // Expect 011

in = 8'b00010000; #10; // Expect 100

in = 8'b00100000; #10; // Expect 101

in = 8'b01000000; #10; // Expect 110

in = 8'b10000000; #10; // Expect 111

in = 8'b00011000; #10; // Expect 011 (Highest priority: bit 4)

in = 8'b00000000; #10; // Expect 000 (Default case)

$stop;

End

Endmodule

5. Write a Verilog code to implement the following Boolean function using a


decoder. F(A,B,C)=Σm(1,2,5,7)F(A,B,C)=Σm(1,2,5,7)

Solution:

Verilog code
module decoder_3to8 (
input [2:0] in,

output reg [7:0] out

);

always @(*) begin

out = 8'b00000000; // Default all outputs to 0

case (in)

3'b000: out = 8'b00000001; // minterm 0

3'b001: out = 8'b00000010; // minterm 1


3'b010: out = 8'b00000100; // minterm 2

3'b011: out = 8'b00001000; // minterm 3

3'b100: out = 8'b00010000; // minterm 4

3'b101: out = 8'b00100000; // minterm 5

3'b110: out = 8'b01000000; // minterm 6

3'b111: out = 8'b10000000; // minterm 7

Endcase

End

Endmodule

// Implement Boolean function using decoder output

module boolean_function (

input [2:0] in,

output F
);

wire [7:0] decoder_out;


// Instantiate 3-to-8 decoder

decoder_3to8 decoder (.in(in), .out(decoder_out));0

// OR gate to combine selected minterms: 1, 2, 5, 7

assign F = decoder_out[1] | decoder_out[2] | decoder_out[5] | decoder_out[7];


endmodule
TEST BENCH
module testbench;

reg [2:0] in;

wire F;

boolean_function uut (.in(in), .F(F)); // Instantiate module

initial begin

$monitor("Time=%0t | Input=%b | Output F=%b", $time, in, F);

in = 3'b000; #10; // 0 -> Expect 0

in = 3'b001; #10; // 1 -> Expect 1


in = 3'b010; #10; // 2 -> Expect 1

in = 3'b011; #10; // 3 -> Expect 0

in = 3'b100; #10; // 4 -> Expect 0

in = 3'b101; #10; // 5 -> Expect 1

in = 3'b110; #10; // 6 -> Expect 0

in = 3'b111; #10; // 7 -> Expect 1

$stop;

end

endmodule

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