Computer Organization and Architecture

Designing for Performance

11th Edition

Chapter 3
A Top-Level View
of Computer
Function and
Interconnection

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 Computer Components
• Contemporary computer designs are based on concepts
developed by John von Neumann at the Institute for
Advanced Studies, Princeton
• Referred to as the von Neumann architecture and is
based on three key concepts:
– Data and instructions are stored in a single read-write memory
– The contents of this memory are addressable by location, without
regard to the type of data contained there
– Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next

• Hardwired program
– The result of the process of connecting the various components in the
desired configuration

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Figure 3.1
Hardware and
Software
Approaches

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 Software and I/O Components
Software
• A sequence of codes or instructions
• Part of the hardware interprets each instruction and generates
control signals
• Provide a new sequence of codes for each new program instead of
rewiring the hardware
Major components:
• CPU
• Instruction interpreter
• Module of general-purpose arithmetic and logic functions
• I/O Components
• Input module
• Contains basic components for accepting data and instructions
and converting them into an internal form of signals usable by the
system
• Output module
• Means of reporting results
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 Computer Function
• The basic function performed by a computer is execution of a program.
The processor does the actual work by executing instructions specified in
the program. Two main components are:
• Central Processing Unit (CPU) / Processor
• Memory it is about 4096 word
– 4096 = 212 : require 12 bits to select a word in memory
▪ Each word: 16 bits long

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 Overview of Key elements
• Program
– A sequence of (machine) instructions (fetch & execution)
• (Machine) Instruction Processing
– A group of bits that tell the computer to perform a specific
operation (a sequence of microoperation)
• Steps:
– The CPU reads (fetches) instructions from memory one at a
time and executes each instruction.
– The CPU reads the next instruction from memory and
places it in an Instruction Register (IR)
– The control unit translates the binary code of the instruction
and proceeds to execute it by issuing a sequence of
microoperations
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Memory, MAR, and MBR
Memory Memory buffer
address register register (MBR)
(MAR) • Contains the data to
• Specifies the be written into
address in memory memory or
for the next read or receives the data
write read from memory

I/O address I/O buffer

register (I/OAR) register (I/OBR)
• Specifies a • Used for the
particular I/O exchange of data
device between an I/O
module and the
CPU

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 CPU Main Memory
0
Figure 3.2: System
Bus
1
2
PC MAR
Computer Instruction
Instruction
Instruction
Components: IR MBR

Top-Level Execution
I/O AR
Data
Data
View unit I/O BR
Data
Data

I/O Module n–2

n–1

PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register

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Figure 3.2 Computer Components: Top-Level View
BC Registers

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Common Bus System - 1

Fig. 5-4
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Figure 3.3

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 Fetch Cycle

• At the beginning of each instruction cycle the processor fetches

an instruction from memory.

• The program counter (PC) holds the address of the instruction to

be fetched next.

• The processor increments the PC after each instruction fetch so

that it will fetch the next instruction in sequence.
• The fetched instruction is loaded into the instruction register (IR).

• The processor interprets the instruction and performs the

required action.

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 Action Categories
• Data • Data transferred to
transferred or from a
from processor peripheral device
by transferring
to memory or between the
from memory to processor and an
processor I/O module

Processor- Processor-
memory I/O

Data
Control
processing

• An instruction may • The processor

specify that the may perform
sequence of some arithmetic or
execution be logic operation on
altered data

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Figure 3.4: Characteristics of a Hypothetical Machine

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Instruction Format

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Address Modes

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Figure 3.5: Example of Program Execution
(contents of memory and registers in hexadecimal)

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 Figure 3.6

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 Table 3.1: Classes of Interrupts
Program Generated by some condition that occurs as a result
of an instruction execution, such as arithmetic
overflow, division by zero, attempt to execute an
illegal machine instruction, or reference outside a
user’s allowed memory space.
Timer Generated by a timer within the processor. This
allows the operating system to perform certain
functions on a regular basis.
I/O Generated by an I/O controller, to signal normal
completion of an operation, request service from the
processor, or to signal a variety of error conditions.
Hardware Failure Generated by a failure such as power failure or
memory parity error.

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 Figure 3.9

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Figure 3.12: Instruction Cycle State Diagram,
with Interrupts

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 I/O Function
• I/O module can exchange data directly with the processor
• Processor can read data from or write data to an I/O module
– Processor identifies a specific device that is controlled by a particular I/O
module
– I/O instructions rather than memory referencing instructions

• In some cases it is desirable to allow I/O exchanges to occur

directly with memory
– The processor grants to an I/O module the authority to read from or write
to memory so that the I/O memory transfer can occur without tying up the
processor
– The I/O module issues read or write commands to memory relieving the
processor of responsibility for the exchange
– This operation is known as direct memory access (DMA)

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Figure 3.15: Computer Modules

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Memory Stack Organization
• Memory stack: a portion of memory is used as a stack, With a
processor register as a stack pointer
• Memory partitioned into three types of segments:
– Program, Data, Stack segments
 Push-Pop

 Overflow/underflowa
Most computers do not provide HW to check stack overflow (full stack)
or stack underflow (empty stack) --> must be done in SW
(Two registers are used to hold the upper(3000)/lower (4001) limits:
After push/pop operation, SP is compared with the upper/lower limit)

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The interconnection structure must support the
following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
Processor data
Processor directly
reads an Processor
reads data Processor with
instructio writes a
from an sends data memory
n or a unit unit of
I/O device to the I/O without
of data data to going
via an I/O device
from memory through the
module
memory processor
using
direct
memory
access

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A communication pathway Signals transmitted by any
connecting two or more one device are available for
devices reception by all other
• Key characteristic is that it is a devices attached to the bus
shared transmission medium • If two devices transmit during the
same time period their signals
will overlap and become garbled

Bus
Interconnection
Typically consists of
multiple communication Computer systems contain a
lines number of different buses
that provide pathways
• Each line is capable of between components at
transmitting signals representing
binary 1 and binary 0 various levels of the
computer system hierarchy

System bus
• A bus that connects major The most common computer
computer components (processor,
memory, I/O) interconnection structures
are based on the use of one
or more system buses

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 Data Bus

• Data lines that provide a path for moving data among system
modules
• May consist of 32, 64, 128, or more separate lines
• The number of lines is referred to the width of the data bus
• The number of lines determines how many bits can be
transferred at a time
• The width of the data bus is a key factor in determining overall
system performance

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Address Bus Control Bus
• Used to designate the source or • Used to control the access and the
destination of the data on the use of the data and address lines
data bus
– If the processor wishes to • Because the data and address lines
read a word of data from are shared by all components there
memory it puts the address must be a means of controlling their
of the desired word on the use
address lines
• Control signals transmit both
• Width determines the maximum command and timing information
possible memory capacity of the
among system modules
system
• Also used to address I/O ports • Timing signals indicate the validity
– The higher order bits are of data and address information
used to select a particular • Command signals specify
module on the bus and the operations to be performed
lower order bits select a
memory location or I/O port
within the module

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 Components of CPU
•Storage Components
–Registers
–Flags
•Processing Components
–Arithmetic Logic Unit (ALU): Arithmetic/Logical
computations, Shifts/Rotates
•Transfer Components
– Bus

•Control Components
–Control Unit

31

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 Registers

•In BC,
– Only one general purpose register, the Accumulator (AC)

•In modern CPUs,

– Many general purpose registers

•Many registers --> advantageous because :

– Transfer between registers within the processor are relatively fast,
– Going off the processor to access memory is much slower.

32

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 General Register Organization

33

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 Operation of Control Unit

• The Control Unit : Direct the info flow through ALU by :

– selecting various Components in the system
– selecting the Function of ALU
• Example: R1 ← R2 + R3
– [1] MUX A selector (SELA): BUS A ← R2
– [2] MUX B selector (SELB): BUS B ← R3
– [3] ALU operation selector (OPR): ALU to ADD
– [4] Decoder destination selector (SELD): R1 ← Out Bus
• Control Word (14 bits)

• Encoding of register selection fields:

34
Table 8.1
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 ALU Control
• Encoding of ALU operations:

 Examples of ALU Microoperations: Table 8.2

Table 8.3
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 Figure 3.16

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 Point-to-Point Interconnect

Principal reason for change At higher and higher data

was the electrical rates it becomes
constraints encountered increasingly difficult to
with increasing the perform the synchronization
frequency of wide and arbitration functions in a
synchronous buses timely fashion

A conventional shared bus

on the same chip magnified
Has lower latency, higher
the difficulties of increasing
data rate, and better
bus data rate and reducing
scalability
bus latency to keep up with
the processors

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Intel’s Quick Path Interconnect (QPI)
• Introduced in 2008
• Multiple direct connections
– Direct pairwise connections to other components eliminating the need for
arbitration found in shared transmission systems

• Layered protocol architecture

– These processor level interconnects use a layered protocol architecture
rather than the simple use of control signals found in shared bus
arrangements

• Packetized data transfer

– Data are sent as a sequence of packets each of which includes control
headers and error control codes

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 Figure 3.18

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 Figure 3.22

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 A Top-Level View of
Summary Computer Function and
Interconnection
Chapter 3
• Point-to-point interconnect
• Computer components
– QPI physical layer
• Computer function
– QPI link layer
– Instruction fetch and execute
– QPI routing layer
– Interrupts
– QPI protocol layer
– I/O function
• PCI express
• Interconnection structures
– PCI physical and logical
• Bus interconnection
architecture
– PCIe physical layer
– PCIe transaction layer
– PCIe data link layer

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