1. a) Explain VLSI design flow.

System specifications:
• The objective of the desired final product is written in this step.
• The designated cost of the system, its performance, architecture, and how the system will
communicate with the external world are to be determined.
• The design specification should be provided by the users or clients.
Architectural design:
• The basic architecture of the desired design must meet the system specifications of the
desired design.
• Architectural design includes the integration of analog and mixed-signal blocks, memory
management, internal and external communication, power requirements, and choice of
process technology and layer stacks.
Functional design or Behavioural design:
• The main objective of this is to generate design a high-performance architectural design
within the cost requirements posed by the specifications.
Logic Design:
• The structure of the desired design is added to the behavioral representation of the desired
design.
• The main specifications to be considered for logic design are logic minimization,
performance enhancement, and testability.
• Logic design must also consider the problems associated with test vector generation, error
detection, and error correction.
Circuit Design:
• The logic blocks of the desired design are replaced by resistors, capacitors, and transistors.
• Circuit simulation of the desired design is done at this stage, in order to verify the timing
behavior of the desired system.
Physical Design:
• The actual layout of the desired system is done.
• Actual layout of the desired system can affect the area, correctness, and performance of the
final desired product.
• Errors such as short circuits, open circuits, open channels, etc may result if the design rules
are not respected.
Y-chart:
• Introduced by D. Gajski
• Design flow for most logic chips, using design activities on the three different axes
(domains).
Behavioral domain Structural domain Geometrical layout domain
 2. b) What are the steps involved in the nMOS/pMOS fabrication? Explain with
neat sketches?
Fabrication of NMOS transistor:

NMOS structure: NMOS symbol:

1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high
purity into which the required p-impurities are introduced as the crystal is grown.
2. A layer of silicon dioxide (SiO2 ), typically 1 μm thick, is grown all over the surface of
the wafer to protect the surface, act as a barrier to dopants during processing, and
provide a generally insulating substrate on to which other layers may be deposited and
patterned.

3. The surface is now covered with a photoresist which is deposited onto the wafer and
spun to achieve an even distribution of the required thickness.

4. The photoresist layer is then exposed to ultraviolet light through a mask which defines
those regions into which diffusion is to take place together with transistor channels.
 Those areas exposed to ultraviolet radiation are polymerized (hardened), but that the
areas required for diffusion are shielded by the mask and remain unaffected.
5. These areas are subsequently readily etched away together with the underlying silicon
dioxide so that the wafer surface is exposed in the window defined by the mask.

6. The remaining photoresist is removed and a thin layer of SiO2 (0.1 μm typical) is grown
over the entire chip surface and then polysilicon is deposited on top of this to form the
gate structure. The polysilicon layer consists of heavily doped polysilicon deposited by
chemical vapor deposition (CVD). In the fabrication of fine pattern devices, precise
control of thickness, impurity concentration, and resistivity is necessary.
7. Further photoresist coating and masking allows the polysilicon to be patterned (as
shown in Step 6).
8. Then the thin oxide is removed to expose areas into which n-type impurities are to be
diffused to form the source and drain as shown. Diffusion is achieved by heating the
wafer to a high temperature and passing a gas containing the desired n-type impurity
(for example, phosphorus) over the surface as indicated in Figure 1.8. Note that the
polysilicon with underlying thin oxide act as masks during diffusion--the process is
self-aligning. 8.

9. Oxide (Si02) is grown over all again and is then masked with photoresist and etched to
expose selected areas of the polysilicon gate and the drain and source areas where
connections (i.e. contact cuts) are to be made.

10. The whole chip then has metal (aluminum) deposited over its surface to a thickness
typically of 1μm. This metal layer is then masked and etched to form the required
interconnection pattern.
 2. a) Derive the relationship between drain to source current Ids verses drain to
source voltage Vds in non-saturated and saturated region.
Ids : Drain to source current:
L - Channel length of the transistor
W- Width of the transistor.
D – Thickness of the oxide layer.
ε - Permittivity of the oxide layer.
IDS -Dr ain to source current
VDS -Drain to source voltage
Q - Charge induced in the channel
τ - Electron transit time

• The voltage on Gate induces a charge in the channel between Source and Drain.
• This charge is then moved from source to drain under the influence of electric field
created by voltage applied between Drain and Source VDS .
Hence the current IDS is given by
𝐶ℎ𝑎𝑟𝑔𝑒 𝑖𝑛𝑑𝑢𝑐𝑒𝑑 𝑖𝑛 𝑡ℎ𝑒 𝑐ℎ𝑎𝑛𝑛𝑒𝑙
𝐼𝑑𝑠 =
𝐸𝑙𝑒𝑐𝑡𝑟𝑜𝑛 𝑡𝑟𝑎𝑛𝑠𝑖𝑡 𝑡𝑖𝑚𝑒
𝑄𝑐
𝐼𝑑𝑠 = 𝜏
𝐿𝑒𝑛𝑔𝑡ℎ 𝑜𝑓 𝑡ℎ𝑒 𝑐ℎ𝑎𝑛𝑛𝑒𝑙 𝐿
Where, 𝜏= =
𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 𝜗
𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 𝑜𝑓 𝑡ℎ𝑒 𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛 𝜗 = 𝜇𝐸𝑑𝑠
Where,
𝜇 = Mobility of the electron or hole
μn – 1250 cm2 /V sec, μp– 480 cm2 /V sec
𝐸𝑑𝑠 = 𝐸𝑙𝑒𝑐𝑡𝑟𝑖𝑐 𝑓𝑖𝑒𝑙𝑑
𝑉𝑑𝑠
𝐸𝑑𝑠 =
𝐿
𝑉𝑑𝑠
𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 𝑜𝑓 𝑡ℎ𝑒 𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛 𝜗 = 𝜇
𝐿
Substituting in 𝜏,
𝐿2
𝜏=
𝜇𝑉𝑑𝑠
Case i: Non saturated region
Let the charge induced in the channel due to gate voltage is given by
𝑸𝒄 = 𝑬𝒈 𝜺𝒐 𝜺𝒊𝒏𝒔 𝑾𝑳
Where,
Eg εins ε0 -- Charge / unit area
Eg - Avg. electric field gate to channel
εins - Relative permittivity of insulation between gate
and channel – 4 for SiO2
ε0 - Permittivity of free space - 8.854 x 10-4 F/cm
Since the voltage along the channel varies linearly with distance X from source due to IR
drop in the channel, hence the average VDS is Vds / 2
The effective gate voltage Vg = Vgs – Vt
V
[(Vgs − Vt ) − DS ]
Eg = 2
D
D = Oxide thickness
Substituting in the charge expression
∈𝑖𝑛𝑠 ∈0 𝑊𝐿 𝑉𝐷𝑆
𝑄𝐶 = [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ]
𝐷 2
Substituting Qc & 𝜏 in Ids expression,
𝜇. 𝑉𝐷𝑆 ∈𝑖𝑛𝑠 ∈0 𝑊𝐿 𝑉𝐷𝑆
𝐼𝐷𝑆 = 2 [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ]
𝐿 𝐷 2
𝜇 ∈𝑖𝑛𝑠 ∈0 𝑊 𝑉𝐷𝑆
𝐼𝐷𝑆 = [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ]𝑉
𝐷 𝐿 2 𝐷𝑆
𝑊 𝑉𝐷𝑆
𝐼𝐷𝑆 = 𝐾 [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ]𝑉
𝐿 2 𝐷𝑆

Where,
𝜇 ∈𝑖𝑛𝑠 ∈0
𝐾=
𝐷
Case ii : Saturation region
In saturation region V ds = Vgs - Vt
Substituting in Ids
W V
IDS = K L [(Vgs − Vt ) − 2DS] VDS
W VDS.VDS
IDS = K [(Vgs − Vt )VDS − ]
L 2
 2
W 2 (Vgs − Vt )
IDS = K [((Vgs − Vt ) ) − ]
L 2
2
W (Vgs − Vt )
IDS =K
L 2

2. b) Compare CMOS, Bipolar, BiCMOS technologies.

CMOS BiPolar

1. Low static power dissipation High power dissipation

2. High input impedance Low input impedance

3. Scalable Threshold voltage

4.High noise margin Low voltage swing logic

5. High package density Low package density

6. Low output drive current High output drive current

7. Bidirectional capability Unidirectional

(Source & drain are
interchangeable)
8. Low gm High gm
(gm α Vin ) (gm α eVin )

9. High delay sensitivity to load Low delay sensitivity

(Fan out limitations)

3. a) Derive the pull up to pull down ratio for an NMOS inverter driven by another
NMOS inverter through a pass transistor.
An nMOS Inverter Driven Through Pass Transistors
An nMOS inverter is driven through one or more pass transistors as shown in Fig. As
we have seen a pass transistor passes a weak high level. If Vdd is applied to the input
of a pass transistor, at the output, we get ( Vdd–Vtp), where Vtp is the threshold voltage
of the pass transistor. Therefore, instead of Vdd, a degraded high level ( Vdd–Vtp) is
applied to the second inverter. We have to ensure that the same voltage levels are
produced at the outputs of the two Inverters in spite of different input voltage levels.

For Vin = Vdd ,

Pull up – Saturation- Current source
Pull down – linear – resistor
For pull down transistor
𝑊𝑝𝑑1 𝑉𝑑𝑠1 2
𝑰𝒅𝒔 = 𝐾 [(𝑉𝑑𝑑 − 𝑉𝑡𝑛 ) 𝑉𝑑𝑠1 − ]
𝐿𝑝𝑑1 2

𝑉𝑠𝑑1 1 𝐿𝑝𝑑1 1
𝑅1 = =
𝐼𝑑𝑠1 𝐾 𝑊𝑝𝑑1 (𝑉 − 𝑉 − 𝑉𝑑𝑠1 )
𝑑𝑑 𝑡𝑛 2
𝑉𝑑𝑠1 𝑍𝑝𝑑1 1
𝑓𝑎𝑐𝑡𝑜𝑟, 𝑅1 =
2 𝐾 (𝑉𝑑𝑑 − 𝑉𝑡𝑛 )
2
𝑊𝑝𝑢1 (−𝑉𝑡𝑑𝑝 )
𝐼1 = 𝐼𝑑𝑠 = 𝐾
𝐿𝑝𝑢1 2
For depletion pull up transistor, Vgs = 0
2
𝑍𝑝𝑑1 1 (− 𝑉𝑡𝑑𝑝 )
𝐼1 𝑅1 = 𝑉𝑜𝑢𝑡1 = ( )
𝑍𝑝𝑢1 𝑉𝑑𝑑 − 𝑉𝑡𝑛 2
Similarly, for the second inverter
𝑍𝑝𝑑2 1
𝑅2 ≈
𝐾 [(𝑉𝑑𝑑 − 𝑉𝑡𝑝 ) − 𝑉𝑡𝑛 ]
1 (−𝑉𝑡𝑑 )2
𝐼2 = 𝐾
𝑍𝑝𝑢2 2
𝑍𝑝𝑑2 1 (−𝑉𝑡𝑑 )2
𝑉𝑜𝑢𝑡2 = 𝐼2 𝑅2 =
𝑍𝑝𝑢2 (𝑉𝑑𝑑 − 𝑉𝑡𝑝 − 𝑉𝑡𝑛 ) 2
𝑉𝑜𝑢𝑡1 = 𝑉𝑜𝑢𝑡2 𝑡ℎ𝑒𝑛, 𝐼1 𝑅1 = 𝐼2 𝑅2
𝑍𝑝𝑢2 𝑍𝑝𝑢1 (𝑉𝑑𝑑 − 𝑉𝑡𝑛 )
=
𝑍𝑝𝑑2 𝑍𝑝𝑑1 (𝑉𝑑𝑑 − 𝑉𝑡𝑝 − 𝑉𝑡𝑛 )
Substituting Vtn = 0.2 Vdd & Vtp = 0.3 Vdd
 𝑍𝑝𝑢2 4.0 𝑍𝑝𝑢1 𝑍𝑝𝑢2 𝑍𝑝𝑢1 8
= 𝑜𝑟 ≈ 2. =
𝑍𝑝𝑑2 2.5 𝑍𝑝𝑑1 𝑍𝑝𝑑2 𝑍𝑝𝑑1 1
Zpu / Zpd = 8/1

If an inverter is driven through one or more pass transistors, it should have inverter
ratio Zpu / Zpd = 8/1

3. b) Draw and explain about BICMOS inverter.

In BiCMOS technology, MOS switches are used to perform the logic function and
bipolar transistors to drive the output loads.
BiCMOS inverter:

Vin T1 T2 T3 T4 Vout

0V OFF ON OFF ON VDD - VBE

VDD ON OFF ON OFF VCESAT

Advantages:
• The output logic levels will be good .
• The inverter has a high input impedance.
• The inverter has a low output impedance.
• Has high current drive capability
• Has relatively small area.
• The inverter has high noise margins.
Disadvantages:
• DC path through VDD and VSS through T3 & T1 Hence static power dissipation.
• No discharge path for current.
 Modified circuit for no static current flow:

Vin T1 T2 T3 T4 Vout

0V OFF ON OFF ON VDD - VBE

VDD ON OFF ON OFF VBE

Advantage:
• DC path is eliminated.
Limitation:
• Voltage swing is reduced.

Improved version for better voltage levels:

 Vin T1 T2 T3 T4 Vout

0V OFF ON OFF ON VDD – IR1

VDD ON OFF ON OFF IR2

Advantages:
• Provides the improved swing of output voltage.
• Provides discharge paths for base current during turn-off.
Limitation:
• On chip resistors of suitable value is not always convenient.
• Resistors are space-consuming.

Improved version for base current discharge:

Vin T1 T2 T3 T4 T5 T6 Vout

0V OFF ON OFF ON OFF ON VDD - VBE

VDD ON OFF ON OFF ON OFF VBE

4. a) Explain the operation of CMOS inverter with voltage and current

characteristics.
 CMOS inverter:

The operation of CMOS inverter can be explained in 5 regions.

Region 1: (0 ≤ Vin < Vtn)

Vin = logic 0, p-transistor is fully turned on while the n-transistor is fully turned off.
Thus no current flows through the inverter and the output is directly connected to V DD
through the p-transistor. A good logic 1 output voltage is thus present at the output.
Region 5: (Vdd - Vtp ≤ Vin < Vdd )
Vin = logic 1, the n-transistor is fully on while the p-transistor is fully off. Again, no
current flows and a good logic 0 appears at the output.
Region 2: (Vtn < Vin < Vinv )
The input voltage has increased to a level which just exceeds the threshold voltage of
the n-transistor. The n-transistor conducts and has a large voltage between source and
drain; so it is in saturation. The p-transistor is also conducting but with only a small
voltage across it, it operates in the unsaturated resistive region. A small current now
flows through the inverter from VDD to VSS. As currents voltage drops at the output.
Region 4: (Vinv < Vin < Vdd - Vtp)
Similar to region 2 but with the roles of the p- and n-transistors reversed. However, the
current magnitudes in regions 2 and 4 are small and most of the energy consumed in
switching from one state to the other is due to the larger current which flows in region
3.
Region 3: (Vin = Vinv )
For the input which is equal to the threshold voltage of the inverter. The region in which
the inverter exhibits gain and in which both transistors are in saturation.

The currents in each device must be the same since the transistors are in series
𝑝𝑑
𝑉𝑔𝑠 = 𝑉𝑖𝑛𝑣
𝑝𝑢
𝑉𝑔𝑠 = 𝑉𝑖𝑛 − 𝑉𝑑𝑑 = 𝑉𝑖𝑛𝑣 − 𝑉𝑑𝑑
1 𝑊𝑛
𝐼𝑑𝑠𝑛 = 𝐾𝑛 (𝑉 − 𝑉𝑡𝑛 )2
2 𝐿𝑛 𝑖𝑛𝑣
2
1 𝑊𝑝
𝐼𝑑𝑠𝑝 = − 𝐾𝑝 (𝑉 − 𝑉𝑑𝑑 − 𝑉𝑡𝑝 )
2 𝐿𝑝 𝑖𝑛𝑣
Equating the currents,
Idsp =- Idsn

𝛽𝑛 𝛽𝑝 2
𝑜𝑟 (𝑉𝑖𝑛𝑣 − 𝑉𝑡𝑛 )2 = − (𝑉𝑖𝑛𝑣 − 𝑉𝑑𝑑 − 𝑉𝑡𝑝 )
2 2
2
(𝑉𝑖𝑛𝑣 − 𝑉𝑑𝑑 − 𝑉𝑡𝑝 ) 𝛽𝑛
2
=−
(𝑉𝑖𝑛𝑣 − 𝑉𝑡𝑛 ) 𝛽𝑝
𝑉𝑖𝑛𝑣 − 𝑉𝑑𝑑 − 𝑉𝑡𝑝 𝛽𝑛
𝑜𝑟 = −√
𝑉𝑖𝑛𝑣 − 𝑉𝑡𝑛 𝛽𝑝
𝛽 𝛽
𝑜𝑟 𝑉𝑖𝑛𝑣 (1 + √𝛽𝑛 ) = 𝑉𝑑𝑑 + 𝑉𝑡𝑝 + 𝑉𝑡𝑛 √𝛽𝑛
𝑝 𝑝

𝛽
𝑉𝑑𝑑 + 𝑉𝑡𝑝 + 𝑉𝑡𝑛 √𝛽𝑛
𝑝
𝑉𝑖𝑛𝑣 =
𝛽
1 + √𝛽𝑛
𝑝

𝛽𝑛 = 𝛽𝑝 and 𝑉𝑡𝑛 = - 𝑉𝑡𝑝

𝑉𝑖𝑛𝑣 = 𝑉𝑑𝑑 / 2
𝐾𝑛 𝜇𝑛
= ≈ 2.5
𝐾𝑝 𝜇𝑝
To make 𝛽𝑛 = 𝛽𝑝 ,
𝑊 𝑊
[
] = 2.5 [ ]
𝐿 𝑝 𝐿 𝑛
Voltage and Current characteristics:
 b) What is latch–up explain the condition with remedial measures?
Latch up in CMOS:
• A condition in which the parasitic components give rise to the establishment of low-
resistance conducting paths between VDD and VSS with disastrous results.
• Occurs in the p-well and n-well CMOS processes.
• Due to the relatively large number of junctions which are formed in these structures, the
consequent presence of parasitic transistors and diodes.
• Latch-up may be induced by glitches on the supply rails or by incident radiation.

Consider a P-Well process, the key parasitic components associated with a p-well structure
are

• There are two transistors and two resistances (associated with the p-well and with regions
of the substrate) which form a path between VDD and VSS.
• If sufficient substrate current flows to generate enough voltage across R s to turn on
transistor T1, this will then draw current through Rp and, if the voltage developed is
sufficient, T2 will also turn on, establishing a_self-sustaining low-resistance path between
the supply rails.
• If the current gains of the two transistors are such that β1 x β2 > 1, latch-up may occur.

• With no injected current, the parasitic transistors will exhibit high resistance, but sufficient
substrate current flow will cause switching to the low-resistance state.
 Once latched-up, this condition will be maintained until the latch-up current drops below
Il.

Remedies for the latch-up problem:

• Increase in substrate doping levels with a consequent drop in the value of R s
• Reducing Rp by control of fabrication parameters and by ensuring a low contact
resistance to Vss
• Introduction of guard rings.

5. a) Design a stick diagram for two input nMOS NAND and NOR gates.

NMOS NOR gate:

NMOS NAND gate:
 b) Derive the expressions for trans conductance, output conductance and figure of
merit.
Transconductance (gm):Non saturation
Trans conductance is defined as
𝜕𝐼
𝑔𝑚 = 𝜕𝑉𝑑𝑠 |𝑉𝑑𝑠 = 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
𝑔𝑠
Transconductance in terms of transistor parameters:
𝑄
𝐼=
𝑡
𝜕𝑄
𝜕𝐼𝑑𝑠 = 𝜏
𝑑𝑠
Since,
𝐿2
𝜏𝑑𝑠 =
𝜇𝑉𝑑𝑠
Substituting in Ids
𝑉𝑑𝑠. 𝜇𝜕𝑄
𝜕𝐼𝑑𝑠 =
𝐿2
Since
𝜕𝑄𝑐 = 𝐶𝑔 𝜕𝑉𝑔𝑠
𝐶𝑔 𝜇𝑉𝑑𝑠 𝜕𝑉𝑔𝑠
𝜕𝐼𝑑𝑠 =
𝐿2
𝜕𝐼𝑑𝑠 𝐶𝑔 𝜇𝑉𝑑𝑠
=
𝜕𝑉𝑔𝑠 𝐿2
𝜕𝐼𝑑𝑠 𝐶𝑔 𝜇𝑉𝑑𝑠
𝑔𝑚 = =
𝜕𝑉𝑔𝑠 𝐿2
In saturation,
𝜈𝐷𝑆 = 𝑉𝑔𝑠 − 𝑉𝑡
𝐶𝑔 𝜇
𝑔𝑚 = 2 (𝑉𝑔𝑠 − 𝑉𝑡 )
𝐿
𝜇 ∈𝑖𝑛𝑠 ∈𝑜 𝑊 ∈𝑖𝑛𝑠 ∈𝑜 𝑊𝐿
∴ 𝑔𝑚 = (𝑉𝑔𝑠 − 𝑉𝑡 ) ∵ 𝐶𝑔 =
𝐷𝐿 𝐷
∴ g m = β(Vgs − Vt )
• Since gm is proportional to width ( W ), it can be increased by increasing width but it
increases input capacitance and area occupied.
Output conductance(gds):
𝜕𝐼𝑑𝑠
𝑔𝑑𝑠 =
𝜕𝑉𝑑𝑠

𝜕𝐼𝑑𝑠 (𝐶𝑔 𝜇𝑉𝑔𝑠 )

𝑔𝑑𝑠 = =
𝜕𝑉𝑑𝑠 𝐿2
Figure of merit(wo): Signifies about the frequency response of the device.
𝑔𝑚
𝑊𝑜 =
𝐶𝑔
𝜇∈𝑖𝑛𝑠 ∈𝑜 𝑊
(𝑉𝑔𝑠 −𝑉𝑡 )
𝐷𝐿
= ∈ 𝑖𝑛𝑠 ∈𝑜 𝑊𝐿
𝐷

𝜇
= 𝐿2 (𝑉𝑔𝑠 − 𝑉𝑡 )

• Higher gate voltage and higher electron mobility provide better frequency response.

μn – 1250 cm2 /V sec, μp– 480 cm2 /V sec

6. a) Derive the pull up to pull down ratio for an NMOS inverter driven by another NMOS
inverter.
Different inverter ratios will be necessary for correct and satisfactory operation of the inverters.
An nMOS Inverter Driven by Another Inverter

An nMOS inverter driven by another inverter;

b inverter with Vin = Vdd; and
c inverter with Vin = Vdd – Vt. nMOS n-type metal–oxide–semiconductor, Vin voltage input to the
inverter, Vdd positive supply rail, Vt inverter threshold voltage

Let us consider an nMOS inverter with depletion-type transistor as an active load is driving a
similar type of inverter as shown in Fig. In order to cascade two or more inverters without any
degradation of voltage levels, we have to meet the condition Vin = Vout = Vinv; and for equal
margins, let us set Vinv = 0.5 Vdd. This condition is satisfied when both the transistors are in
saturation, and the drain current is given by

Cascading inverters without degradation

Vin = Vout =Vinv = 0.5Vdd
Both the transistors are in saturation
2
𝑊 (𝑉𝑔𝑠 − 𝑉𝑡 )
𝐼𝑑𝑠 =𝐾
𝐿 2
For depletion mode transistor,
2
𝑝𝑢 𝑊 (−𝑉𝑡𝑑𝑝 )
𝐼𝑑𝑠 = 𝐾 𝐿 𝑝𝑢 , Vgs = 0V
𝑝𝑢 2

For enhancement mode transistor

𝑊𝑝𝑑 (𝑉𝑖𝑛𝑣 − 𝑉𝑡𝑛 )2
𝐼𝑑𝑠 = 𝐾
2𝐿𝑝𝑑

Equating currents,
𝑊𝑝𝑑 𝑊𝑝𝑢 2
(𝑉𝑖𝑛𝑣 − 𝑉𝑡𝑛 )2 = (−𝑉𝑡𝑑𝑝 )
𝐿𝑝𝑑 𝐿𝑝𝑢

Zpd = Lpd / Wpd & Zpu = Lpu / Wpu

Z = aspect ratio
1 1 2
(𝑉𝑖𝑛𝑣 − 𝑉𝑡𝑛 )2 = (−𝑉𝑡𝑑𝑝 )
𝑍𝑝𝑑 𝑍𝑝𝑢

𝑍𝑝𝑢
√ (𝑉 − 𝑉𝑡𝑛 ) = −𝑉𝑡𝑑𝑝
𝑍𝑝𝑑 𝑖𝑛𝑣

𝑉𝑡𝑑𝑝
𝑉𝑖𝑛𝑣 = 𝑉𝑡𝑛 −
𝑍𝑝𝑢
√
𝑍𝑝𝑑
Substituting Vtn = 0.2Vdd, Vtdp = -0.6Vdd , Vinv = 0.5Vdd
Zpu / Zpd = 4/1

b) Draw the stick diagram and layout for a CMOS inverter indicating the design rules.
CMOS inverter: CMOS stick diagram:

Layout:
7. Explain the operation of NMOS inverter and compare the characteristics with various
pull up loads.
8. What are the steps involved in the CMOS fabrication? Explain with neat sketches.

Stick diagrams:

CMOS NAND GATE:

CMOS NOR GATE:

Layouts:
 Alternate forms of Pull ups:

• Load resistance RL
• NMOS Depletion-mode transistor pull up
• NMOS Enhancement mode transistor pull up
• Complementary transistor pull up (CMOS)

Load resistor RL as pull up:

Vin NMOS Vout

<Vtn OFF Vdd

>Vtn ON >0

Limitations of resistive pull up:

• Asymmetrical switching times.
• Rc & RL should be low.
Rc – Large area of transistor.
Increased power dissipation.
• Large chip area.
• Resistance cannot be controlled.

NMOS depletion mode transistor pull up:

Vin NMOS Vout

<Vtn OFF Vdd

>Vtn ON >0
• High power dissipation – for logic 1 – rail to rail current
• Switching from logic 1 to logic 0 begins when Vin exceeds Vt of PD transistor.
• When switching the output from 1 to 0, the p.u. device is non-saturated initially and this
presents lower resistance through which to charge capacitive loads .
• It produces strong high output level, but weak low output level.

nMOS Enhancement-Mode Transistor as Pull up:

Vin Vout NMOS

0 VDD - Vth OFF

1 >0V ON
 Limitations of Enhancement NMOS:
• High power dissipation – for logic 1 – rail to rail current
• The output is not ratioless, which leads to asymmetry in switching characteristics.
• It produces weak low and high output levels.
• VGG may be derived from a switching source, one phase of a clock, so that dissipation can be
greatly reduced.
• If VGG is higher than VDD then an extra supply rail is required

Complementary Transistor Pull Up (Pseudo NMOS):

Vin NMOS Vout

0 OFF VDD

1 ON >0V

Limitations of Pseudo NMOS:

• The pull-up transistor always remains ON
• DC current flows when the pull-down device is ON.
• The low-level output is also not zero and is dependent on the β n / βp
 Complementary Transistor Pull Up (CMOS):

Vin NMOS PMOS Vout

0 OFF ON VDD

1 ON OFF 0

• No current flow either for logical 0 or for logical 1 inputs.

• Full logical 1 and 0 levels are presented at the output.
• For devices of similar dimensions the p-channel is slower than the n-channel device.