MPMC 2019 IT Final
MPMC 2019 IT Final
DEPARTMENT
OF
INFORMATION TECHNOLGYENGINEERING
LECTURE NOTES
EC8691 – MICROPROCESSOR AND MICROCONTROLLER
(2017 Regulation)
Year/Semester: III/VI
Prepared by
T.VENKATESH KANNA,.AsstProf/ECE.
SKR Engineering College EC8691 – Microprocessor &
Microcontroller
OUTCOMES:
At the end of the course, the student should be able to:
Design and implement programs on 8086 microprocessor.
Design I/O circuits.
Design Memory Interfacing circuits.
Design and implement 8051 microcontroller based systems.
TEXT BOOKS:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family Architecture, Programming and Design”, Second Edition, Prentice
Hall of India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The 8051
Microcontroller and Embedded Systems: Using Assembly and C”, Second
Edition, Pearson Education, 2011
REFERENCE:
1. DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware: TMH, 2012
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SKR Engineering College EC8691 – Microprocessor &
Microcontroller
INDEX
EC8691 – MICROPROCESSOR AND MICROCONTROLLER
S.NO TOPICS PAG
E
NO
UNIT I – THE 8086 MICROPROCESSOR
1 Introduction to 8086 7
2 Microprocessor architecture 7
3 Addressing modes 13
4 Instruction set 18
5 Assembler directives 38
6 Assembly language programming 42
7 Modular Programming 47
8 Linking and Relocation 48
9 Stacks 51
10 Procedures 52
11 Macros 54
12 Interrupts and interrupt service routines 56
13 Byte and String Manipulation. 59
14 2 Marks Questions & Answers 63
15 16 Marks Questions 67
UNIT 2 – 8086 SYSTEM BUS STRUCTURE
1 8086 signals 69
2 Basic configurations 72
3 System bus timing 75
4 System design using 8086 76
5 I/O Programming 77
6 Introduction to Multiprogramming 81
7 System Bus Structure 85
8 Multiprocessor configurations 86
9 Coprocessor, Closely coupled and loosely Coupled 86
configurations
10 Introduction to advanced processors 99
11 2 Marks Questions & Answers 109
12 16 Marks Questions 111
UNIT 3 – I/0 INTERFACING
1 Memory Interfacing and I/O interfacing 113
2 Parallel communication interface 117
3 Serial communication interface 120
4 D/A and A/D interface 123
5 Timer 127
6 Keyboard /display controller 130
7 Interrupt controller 133
8 DMA controller 136
9 Programming and applications 140
10 Case studies: 140
Traffic Light
control
11 LED display 143
12 LCD display 146
13 Keyboard display interface 149
IT/ IIIYR / VSEM / VENKATESH KANNA.T Page 3
UNIT 1
THE 8086 MICROPROCESSOR
REFERRED BOOK:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family
- Architecture, Programming and Design”, Second Edition, Prentice Hall of
India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly
and C”, Second
1. DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH,2012
Table 1.2 8086 default 16 bit segment and offset address combination
Fig: 1.25 Instruction formats for short, near and far jumps instructions
Near and far jumps are further described as
1) Direct
2) Indirect.
If the destination address for the jump is specified directly within the
instruction, then the jump is described as direct.
If the destination address for the jump is contained in a register or memory
location, the jump is referred us indirect.
Example: (Unconditional jump)
JMP NEXT ; Fetch next instruction from address at label NEXT.
J Cond - Conditional Jump:
Conditional jumps are always short jumps in the 8086.
These instructions will cause a jump to a label given in the instruction if
the desired condition(s) occurs in the program before the execution of the
instruction.
The destination must be in the range of -128 bytes to +127 bytes from the
address of the instruction after the conditional transfer instruction.
1f the Jump is not taken execution simply goes on to the next instruction.
bits.
Fig: 1.32 Addressing Modes
Z-bit:
It is used for string primitives such as REP for comparison with ZF Flag.
1f it is 1, the instruction with REP prefix is executed until the zero flag
matches the Z-hit.
MASM.
Fig: 1.37 Steps in program development and execution
The linker program is invoked using the following options.
C> LINK
Or
C>LINK MS.OBJ
The .OBJ extension is a must for a file to be accepted by the LINK as a valid
object file.
The first object may generate a display asking for the object file, list file and
libraries as inputs and an expected name of the .EXE file to be generated.
The output of the link program is an executable file with the entered filename
and .EXE extension.
This executable filename can further be entered at the DOS prompt to execute
the file.
In the advanced version of the MASM, the complete procedure of assembling
and linking is combined under a single menu invokable compile function.
A linker links the machine codes with the other required assembled codes.
The linked file in binary for run on a computer is commonly known as
executable file or simply ‘.exe.’ file.
The DOS linking program links the different object modules of a source
program and function library routines to generate an integrated executable
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SKR Engineering EC8691 – Microprocessor &
Collegecode of the source program. Microcontroller
1.9 STACKS
The information is written on the stack, the operation is called PUSH. The
information is read from the stack, the operation is called POP.
1.9.1 Stack Structure of 8086/88
The 8086/88 has a special 16-bit register, SP to work as a stack pointer.
The stack pointer (SP) register contains the 16-bit offset from the start of the
segment to the top of stack.
Physical address is produced by adding the contents of stack pointer
register to the segment base address in SS.
The contents of the stack segment register are shifted four bits left and the
contents of SP are added to the shifted result.
If the contents of SP are 9F20H and SS are 4000Hthen the physical
address. SS = 4000H after shifting four bits left SS = 40000H
Now
SS 40000H
+ SP 9F20H
Physical address
1.10 PROCEDURES
The procedure is a group of instructions stored as a separate program in
the memory and it is called from the main program.
The type of procedure depends on where the procedure is stored in the
memory.
Two types of procedures:
1) Near Procedure
2) Far procedure
Near Procedure and Far Procedure:
If it is in the same code segment where the main program is stored then it is
called near procedure otherwise it is referred to as far procedure.
For near procedure CALL instruction pushes only the IP register contents on the
stack
For far procedures CALL instruction pushes both IP and CS on the stack.
1.10.1 Reentrant Procedure.
Procedure 1 is called from main program, procedure2 is called from
procedure1 and procedure 1 is again called from procedure2.
Program execution flow reenters in the procedure 1. This type of
procedures is called reentrant procedures.
The flow of program execution for reentrant procedure is shown in Fig.1.40
Fig: 1.40 Flow Diagram and Pseudo code for Reentrant procedure
1.10.2 Recursive Procedure
A recursive procedure is a procedure which calls itself.
Recursive procedures are used to work with complex data structures called
Fig: 1.41 Flow Diagram and Pseudo code for recursive procedure
1.10.3 Passing parameters:
There are four ways to pass parameters to and from the procedure
1) Using registers
2) Using general memory
3) Using pointers
4) Using stack
1.10.3.1. Passing Parameters Using Registers
The data, to be passed is stored in the registers and these registers are
accessed in the procedure to process the data.
Example:
Passing Parameters Using Registers
; Main program
CODE SEGMENT
MOV AL, DATA ; Data to be passed is loaded in the AL register
…..
CALL PRO1
....
; Procedure
PRO1 PROC NEAR
MOV INPUT, AL ; Procedure access the data from AL register
…. RET
PRO1. ENDP CODE
ENDS
1.10.3.2. Passing Parameters Using Memory
To pass few parameters to and from a procedure, registers are a
convenient way to do it.
To pass a large number of parameters to procedure we use memory.
This memory may be a dedicated section of general memory or a part of stack.
Example:
Passing using general memory
; Main program
DATA SEGMENT
BCD_INPUT DB 42 ; Storage for BCD
value HEX_VALUE DB ? ; Storage for HEX
value DATA ENDS
CODE SEGMENT
CALL PRO1
; Procedure
PRO1 PROC NEAR MOV
AL, BCD_INPUT MOV
HEX_VALUE, AL
1.11 MACROS
Macro is a group of instructions. The macro assembler generates the
code in the program each time where the macro is ‘called’.
Macros can be defined by MACRO and ENDM assembler directives.
Example:
Macro definition for initialization of segment registers.
INIT MACRO; Define macro
MOV AX, data;
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SKR Engineering EC8691 – Microprocessor &
CollegeMOV DS; Body of macro definition Microcontroller
MOV ES AX;
1.42).
Fig: 1.42 8086 interrupt Response
1. It decrements stack pointer by 2 and pushes the flag register on the stack.
2. It disables the LNTR interrupt input by clearing the interrupt flag in the flag register.
3. It resets the trap flag in the flag register.
4. It decrements stack pointer by 2 and pushes the current code segment
register contents on the stack.
5. It decrements stack pointer by 2 and pushes the current instruction pointer
contents on the stack.
6. It does an indirect far Jump at the start of the procedure by loading the CS and
IP values for the start of the interrupt service routine (ISR).
The block of memory is often called the interrupt vector table or the interrupt
pointer
table.
A a Y
0 0 0
0 1 1
1 0 1
1 1 0
Table 1.15 Truth Table for XOR gate
This instruction logically XORs each bit of the source byte or
word with the corresponding bit in the destination and stores
result in the destination.
The source may be an immediate number, a register or a memory
location. The destination may be a register or a memory location.
The source and destination both cannot be memory locations in the same
instruction.
The CF and OF are both 0 after XOR. The PF, SF and ZF are affected. AF is
undefined.
Example:
; AL = 1010 1111 = AFH
; BL = 1111 0000 = F0H
XOR BL, AL ; XOR byte in AL with byte in BL
; BL = 0101 1111 = 5FH
The XOR instruction is used if some bits of a register or memory
location must be inverted. This instruction allows part of a number to
be inverted or complemented.
23. What is the use of addressing modes, mention the different types (May/June’14)
The various formats of specifying the operands are called addressing modes,
it is used to access the operands or data. The different types are as follows
1) Immediate addressing
2) Register addressing
3) Direct addressing
4) Indirect addressing
5) Implicit addressing
30. What is the function of LOCK and RQ/GT signals? (May/June’13) (Nov/Dec 2017)
LOCK: This signal indicates that an instruction with a LOCK prefix is being
executed and the bus is not to be used by another processor.
RQ/GT1 and RQ/GT0: In the maximum mode, HOLD and HLDA pins are
replaced by RQ (Bus request)/GT0 (Bus Grant), and RQ/GT1 signals.
Procedure Macro
Accessed by CALL and RET Accessed during assembly with
instruction during name given to macro when
program defined
execution.
Machine code for instructions is Machine code is generated
put only once in the memory. for instructions each time
when macro is called.
With procedures less memory With macros more memory is
is required. required.
Parameters can be Parameters passed as part
passed in registers, of statement which calls
memory locations, macro.
or
stack.
37. What is the maximum memory size that can be addressed by 8086?
UNIT 2
8086 SYSTEM BUS STRUCTURE
REFERRED BOOK:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family
- Architecture, Programming and Design”, Second Edition, Prentice Hall of
India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly
and C”, Second
1. DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH,2012
BHE / S7-Bus High Enable/Status The bus high enable signal is used to indicate the
transfer of data over the higher order (D15—D8) data bus as shown in Table 1.2. It
goes low for the data transfers over D 15—D8 and is used to derive chip selects of
odd address memory bank or peripherals. BHE is low during T 1 for read, write and
interrupt acknowledge cycles, whenever a byte is to be transferred on the higher
byte of the data bus. The status information is available during T2, T3 andT4. The
signal is active low and is tristated during ‘hold’. It is low during T 1 for the first pulse
of the interrupt acknowledges cycle.
BHE A0 Indications
0 0 Whole Word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 None
Table 2.2 Bus High Enable/Status
RD-Read Read signal, when low, indicates the peripherals that the processor is
performing a memory or I/O read operation. RD is active low and shows the state
for T2, T3, Tw of any read cycle. The signal remains tristated during the ‘hold
acknowledge’.
READY This is the acknowledgement from the slow devices or memory that they
have completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the 8086. The
signal is active high.
INTR- Interrupt Request This is a level triggered input. This is sampled during the last
clock cycle of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters the interrupt acknowledge cycle.
This can be internally masked by resetting the interrupt enable flag. This signal is
active high and internally synchronized.
TEST This input is examined by a ‘WAIT’ instruction. If the TEST input goes low,
execution will continue, else, the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.
RQ / GT0 , RQ / GT1 -Request/GrantThese pins are used by other local bus masters,
in maximum mode, to force the processor to release the local bus at the end of the
processor’s current bus cycle. Each of the pins is bidirectional with RQ / GT0 having
higher priority than
RQ / GT1 . RQ / GT pins have internal pull-up resistors and may be left unconnected.
The request/grant sequence is as follows:
1. A pulse one clock wide from another bus master requests the bus access to
8086.
2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from 8086
to the requesting master, indicates that the 8086 has allowed the local bus to
float and that it will enter the “hold acknowledge” state at next clock cycle.
The CPU’s bus interface unit is likely to be disconnected from the local bus of
the system.
3. A one clock wide pulse from another master indicates to 8086 that the ‘hold’
request is about to end and the 8086 may regain control of the local bus at
the next clock cycle.
Thus each master to master exchange of the local bus is a sequence of 3
pulses. There must be at least one dead clock cycle after each bus exchange. The
request and grant pulses are active low. For the bus requests those are received
while 8086 is performing memory or I/O cycle, the granting of the bus is governed
by the rules as discussed in case of HOLD and HLDA in minimum mode.
M/ IO RD WR Indications
0 0 1 I/O Read
0 1 0 I/O Write
1 0 1 Memory
Read
1 1 0 Memory
Write
The MRDC , MWTC are memory read command and memory write command
signals respectively and may be used as memory read and write signals. All these
command signals instruct the memory to accept or send data from or to the bus.
For both of these write command
signals, the advanced signals namely AMWC and AIOWC are available. They also
serve the same purpose, but are activated one clock cycle earlier than the IOWC
and MWTC signals, respectively. The maximum mode system is shown in Fig.
1.10.The maximum mode system
timing diagrams are also divided in two portions as read (input) and write
(output) timing
diagrams. The address/data and address/status timings are similar to the minimum
mode. ALE is asserted in T1, just like minimum mode.
S0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will
output a pulse as on the ALE and apply a required signal to its DT / R pin during T1.
In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will
activate MRDC or IORC. These signals are activated until T4. For an output, the
AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3
to T4.
The status bit S0 to S2 remains active until T3 and become passive during
T3 and T4. If reader input is not activated before T3, wait state will be
inserted between T3 and T4.
Table 2.5 Comparison between Programmed I/O and Interrupt Driven I/O
2.5.6 Direct Memory Access (DMA) Transfer
In software control data transfer, processor executes a series of instructions
to carry out data transfer.
For each instruction execution fetch, decode arid execute phases are required.
Fig. 2.11 gives the flowchart to transfer data from memory to I/O device.
So this method of data transfer is not suitable for large data transfers.
1.
Fig: 2.27 Bit definition of control register
Bits 5-0 of the control registers contain individuals masks for each
of the six exceptions
Bit 7 contains a general mask bit for all 8087 interrupts.
The high order byte of the control register configures the 8087
operating mode including precision, rounding, and infinity controls.
After reset or initialization of the 8087, these bits are PC = 11, RC= 00, IC =0, IEM = 0
and all error mask bits are
Tag Register: TAG register holds the status of the contents of data
register. This includes
0 0– Data Valid
0 1 - Zero
1 0 – A special value
1 1 - Empty
2.9.3.4 Data Formats and Conversions of 8087:
The 8087 can operate on memory operands of seven different data types:
1) Word integer
2) Short integer
3) Long integer
4) Packed BCD
5) Short real
6) Long real
A real format is divided into three fields:
Sign
Exponent
Mantissa.
Real number n = sign x mantissa.
To convert any number to real format, we have to move the decimal point
to the right of the most significant, non zero digit.
This process of moving the decimal point to the right of the most
significant, nonzero digit is referred to as Normalization.
The 8087 recognizes three real data types:
1) Short real (32-bit)
2) Long real (64-bit)
3) Temporary real (80-bits)
Format has field:sign, exponent and mantissa.
Fig: 2.34 Bit Patterns of 80286 status word and flag register
NT (Nested flag): This flag is set when one system task invokes another
task.
IOPL (110 Privilege level) : The two bits in the IOPL are used by the
processor and the operating system to determine your application’s
access to I/Facilities.
*****
3. Write some advantages of loosely coupled systems over tightly coupled systems
More number of CPUs can be added in loosely coupled systems to improve the
system performance. The system structure is modular and hence easy to maintain and
troubleshoot.
A fault in a single module does not lead to a complete system breakdown.
Due to the independent processing modules used in the system, it is more fault
tolerant, more suitable to parallel applications due to its modular organizations.
18. How does CPU differentiate the 8087 instructions from its own instructions
(May/June’12)
The 8087 instructions can be distinguished from 8086 instructions by letter F
which stands for floating point number. All mnemonics in 8087 begins with the
letter F.
21. In what ways are the standard microprocessor and coprocessor differ from each
other (Nov/Dec’13)
A processor provides auxiliary functions or features that the main processor
does not have. These might include floating point support or hardware encryption. A
coprocessor is generally not usable without its main processor, whereas a processor
may function in a crippled or less powerful form without a coprocessor.
UNIT 3
I/O INTERFACING
REFERRED BOOK:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family
- Architecture, Programming and Design”, Second Edition, Prentice Hall of
India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly
and C”, Second
1. DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH,2012
Fig: 3.1 Memory components illustrating the address, data and control connections
ROM
It read only memory permanently stores programs and data and data was
always
present, even when power is disconnected. It is also called as nonvolatile memory.
RAM
RAM memory device has either one or two control inputs. If there is one
control input it is often called R/W.
This pin selects a read operation or a write operation only if the device is
selected by the selection input (CS).
If the RAM has two control inputs, they are usually labeled WE or W and
OE or G. (WE) write enable must be active to perform a memory write
operation and OE must be active to perform a memory read operation.
When these two controls WE and OE are present, they must never be active
at the same time.
EPROM
Erasable Programmable Read Only Memory is also erasable if exposed to
high intensity ultraviolet light for about 20 minutes or less, depending upon
the type of EPROM as shown in figure 3.2.
We have PROM (Programmable Read Only Memory)
RMM
Read Mostly Memory is also called the flash memory.
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SKR Engineering EC8691 – Microprocessor &
College Microcontroller
The flash memory is also called as an EEPROM (Electrically Erasable
Programmable ROM), EAROM (Electrically Alterable ROM), or a NOVROM
(Nonvolatile ROM).
These memory devices are electrically erasable in the system, but require
more time to erase than a normal RAM.
A0 –A10 ADDRESSES
PD/PGM POWER DOWN PROGRAM/
CS CHIP SELECT
O0-O7 OUT PUTS
Table 3.1
Static Random access memory (SARAM)
Static RAM memory device retain data for as long as DC power is applied.
Because no special action is required to retain stored data, these devices are
called as static memory.
They are also called volatile memory because they will not retain data without
power.
The main difference between a ROM and RAM is that a RAM is written
under normal operation, while ROM is programmed outside the computer and
is only normally read.
The SRAM stores temporary data and is used when the size of read/write
memory is relatively small.
The control inputs of this RAM are slightly different from those presented earlier.
The OE pin is labeled G, the CS pin S and the WE pin W. This 4016 SRAM
device has 11 address inputs and 8 data input/output connections
A 0 –A 10 ADDRESSES
_
WRITE ENABLE
W
_
CHIP SELECT
S
Table 3.2
Dynamic RAM
Whenever a large capacity memory is required in a microcomputer system,
the memory subsystem is generally designed using dynamic RAM because
there are various advantages of dynamic RAM is shown in figure 3.5.
The basic dynamic RAM cell uses a capacitor to store the charge as a
representation of data.
This capacitor is manufactured as a diode that is reverse biased so that the
storage capacitance comes into the picture.
This storage capacitance is utilized for storing the charge representation of
data but the reverse-biased diode has leakage current that tends to
discharge the capacitor giving rise to the possibility of data loss. To avoid this
possible data loss, the data stored in a dynamic RAM cell must be refreshed
after a fixed time interval regularly.
The process of refreshing the data in RAM is called as Refresh cycle.
The refresh activity is similar to reading the data from each and every cell of
memory, independent of the requirement of microprocessor.
During this refresh period all other operations related to the memory
subsystem are suspended.
Hence the refresh activity causes loss of time, resulting in reduces system
performance.
However keeping in view the advantages of dynamic RAM, like low power
consumption, high packaging density and low cost, most of the advanced
computing system are designed using dynamic RAM, at the cost of operating
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following aspects.
Table 3.3
CS A1 A0 Function
RD WR
X X 1 X X Data bus tristated
Receiver Buffer
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College Microcontroller
The Receiver Buffer and Control accept serial data, convert it to parallel
format, check for parity, framing, overrun, and break.
In the above program, port A is initialized as the output port for sending the
digital data as input to DAC. The ramp starts from the 0V (analog), hence AL
starts with 00H.
To increment the ramp, the content of AL is increased during each execution
of loop till it reaches F2H. After that the saw tooth wave again starts from
00H, i.e. 0V(analog) and the procedure is repeated.
The ramp period given by this program is precisely 1.000625 ms. Here the
count F2H has been calculated by dividing the required delay of 1ms by the
time required for the execution of the loop once.
The ramp slope can be controlled by calling a controllable delay after the
OUT instruction.
This single output line is the signal that is the final programmed output of the
device. Actual operation of the outline depends on how the device has been
programmed. This input can act as a gate for the clock input line, or it can act as a
start pulse, depending on the programmed mode of the counter.
Counter #0, #1, #2 Each counter is identical, and each consists of a 16-bit, pre-
settable, down counter. Each is fully independent and can be easily read by the
CPU. When the counter is read, the data within the counter will not be disturbed.
This allows the system or your own program to monitor the counter's value at any
time, without disrupting the overall function of the 8253.
Control Word Register This internal register is used to write information to,
prior to using the device. This register is addressed when A0 and A1 inputs are
logical 1's. The data in the register controls the operation mode and the
selection of either binary or BCD (binary coded decimal) counting format
3.6.6 Modes
The following text describes all possible modes. The modes used in the MZ-
700 and set by the monitor's startup are mode 0, mode 2, and mode 3.
Priority Resolver
This unit determines the priorities of the interrupt requests appearing
simultaneously.
The highest priority is selected and stored into the corresponding bit of ISR
during INTA pulse.
The IR0 has the highest priority while the IR7 has the lowest one,
normally in fixed priority mode.
The priorities however may be altered by programming the 8259A in
rotating priority mode.
3.8.3 Interrupt Control Logic
This block manages the interrupt and interrupt acknowledge signals to be
sent to the CPU for serving one of the eight interrupt requests.
This also accepts the interrupt acknowledge (INTA) signal from CPU that
causes the 8259A to release vector address on to the data bus.
Data Bus Buffer
This tristate bidirectional buffer interfaces internal 8259A bus to the
microprocessor system data bus.
Control words, status and vector information pass through data buffer
during read or write operations.
Read/Write Control Logic
This circuit accepts and decodes commands from the CPU.
This block also allows the status of the 8259A to be transferred on to the data
bus.
Cascade Buffer/Comparator
This block stores and compares the ID’s all the 8259A used in system.
The three I/O pins CASO-2 are outputs when the 8259A is used as a master.
The same pins act as inputs when the 8259A is in slave mode.
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College Microcontroller
The 8259A in master mode sends the ID of the interrupting slave device on
these lines. The slave thus selected, will send its preprogrammed vector
address on the data bus during the next INTA pulse.
INT:
This pin goes high whenever a valid interrupt request is asserted. This is used
to interrupt the CPU and is connected to the interrupt input of CPU.
IR0 – IR7 (Interrupt requests):
These pins act as inputs to accept interrupt request to the CPU. In edge
triggered mode.
An interrupt service is requested by raising an IR pin from a low to a high
state and holding it high until it is acknowledged, and just by latching it to
high level, if used in level triggered mode.
INTA (Interrupt acknowledge):
This pin is an input used to strobe-in 8259A interrupt vector data on to the data
bus.
In conjunction with CS, WR and RD pins, this selects the different operations
like, writing command words, reading status word, etc.
3.8.4 Interrupt Sequence in an 8086-8259A system
One or more IR lines are raised high that set corresponding IRR bits.
8259A resolves priority and sends an INT signal to CPU.
The CPU acknowledge with INTA pulse.
Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set
and the corresponding IRR bit is reset. The 8259A does not drive data during
this period.
The 8086 will initiate a second INTA pulse. During this period 8259A releases
an 8-bit pointer on to a data bus from where it is read by the CPU.
This completes the interrupt cycle. The ISR bit is reset at the end of the
second INTA pulse if automatic end of interrupt (AEOI) mode is programmed.
Otherwise ISR bit remains set until an appropriate EOI command is issued at
the end of interrupt subroutine.
Command Words of 8259A
The command words of 8259A are classified in two groups
Initialization command words (ICW) and
Operation command words (OCW).
Initialization Command Words (ICW)
Before it starts functioning, the 8259A must be initialized by writing two to
four command words into the respective command word registers.
These are called as initialized command words.ICW1 and ICW2 are
compulsory command words in initialization sequence of 8259A while ICW3
and ICW4 are optional.
Operation Command Words:
Once 8259A is initialized it is ready for its normal function, i.e. for accepting
the interrupts but 8259A has its own way of handling the received interrupts
called as modes of operation. These modes of operations can be selected by
programming, i.e. writing three internal registers called as operation
command words registers.
The data written into them is called as operational
command words. There are three operation command
words
OCW1
OCW2
OCW3
Every bit corresponds to some operational feature of the mode selected,
except for a few bits those are either 1 or0.
Priority Resolver:
This block assigns the priorities to the DMA channels of DMAC based on mode
of operation.
First/Last Flip Flop (FF):
8257 have 8bit data line and 16 bit address line.8086 it is getting 8-bit data
in simultaneously.8086 cannot access 16-bit address in simultaneously.A0-A3 lines
are used to distinguish between registers, but they are not distinguishing lower and
higher address. It is reset by external RESET signal. It is also reset by whenever
mode set register is loaded. So program initialization with a dummy (00 H).
i. FF=1=Higher byte of address
ii. FF=0=Lower byte of address.
Fig. 3.26 The interfacing diagram for traffic light control system
I/O Map
Software:
Source program:
Seven-Segment display
Seven segment displays are generally used as numerical indicators
It consists of a number of LEDs arranged in seven segments shown
in the Fig. 3.27.
Fig: 3.31 Circuit for driving single seven segment LED display
The value of the resistor in series with the segment can be calculated as follows:
Vcc — drop across LED segment — IR = O.
Drop across LED segment is nearly
1.5 V. IR = Vcc. - 1.5 V
= 5 — 1.5 V
= 3.5 V
Each LED segment requires a current of between 5 and 30 mA to light.
Let’s assume that current through LED segment is 15 mA and R=35V/15mA = 233ohm
The voltage drop across the LED and the output of 7447 are not exactly
predictable.
A standard value 220 Q can be used.
The static display circuits work well for driving just one or two LED digits.
When there is more number of digits, the first problem is power consumption.
For worst-case calculations, assume that all eight digits with all segments are lit.
Therefore, worst case current required is
I = 8 (digits) x 7 (segment) x 15 mA (current per segment)
=84OmA
A second problem of the static approach is that each display digit requires a
separate BCD to 7 segment decoder.
Multiplexed Display
To solve the problems of the static display approach, multiplexed display
method is used.
Fig. 3.32 shows the 4 seven segment displays connected using multiplexed
method.
Here, common anode seven segment LEDs are used.
Fig. 3.34 shows the circuit for driving LCD seven segment display using IC 4543B.
Fig.3.35 Circuit for driving LCD seven segment display using 4543B
The Fig. 3.35 shows how above circuit can be used to drive a 4-digit no
multiplexed, 7- segment LCD display.
BCO input for each display is latched in the corresponding latch.
LCD Modules allow display of characters as well as numbers. They are
available in 16 x 2, 20 x 1, 20 x 2, 20 x 4 and 40 x 2 sizes.
The first figure represents number of character in each line and second figure
represents number of lines the display has.
The module has 14-pins.The function of each pin is given in the table 8.9.
The Fig. 3.36 shows the interfacing of a 20 character x 2-line LCD module
with the 8051. As shown in the Fig. 3.37, the data lines are connected to the port I
of 8051 and control lines RS, R/V and E are driven by 3.2, 3.3 and 3.1 lines of port 3,
respectively.
IT/ IIIYR / VSEM / VENKATESH Page 236
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The voltage at VEE pin is adjusted by a potentiometer to adjust the contrast of the LCD.
Fig. 3.38 shows the circuit diagram of key debounce. It consists of flip flop.
The output of flip-flop shown in Fig. 3.38 is logic t when key is at position. A
(unpressed) and it is logic 0 when key is t position B
Fig. 3.43 shows sixteen keys arranged in four rows and four columns.
When keys are open row and column do not have any connection, when
a key is pressed.
It shorts corresponding one row and one column.
D7 D6 D5 D4 D3 D2 D1 D0
1 1 COUNT STATUS CNT2 CNT1 CNT0 0
17. What is the purpose of control word written to control register in 8255?
(/May/June’13)
The control words written to control register specify an I/O function for each
I.O port. The bit D7 of the control word determines either the I/O function of the BSR
function.
*****
1. Draw the block diagram of 8279 keyboard/ Display controller and explain how to
interface the Hex Key pad and 7- segment LEDs using 8279. (May/June’12)
(Nov/Dec’12) (May/June’13)(Nov/Dec’17) [Ref Sec:3.7.1]
2. Draw the functional block diagram of 8254 timer and explain the different modes
of operation. (May/June’15) [Ref Sec: 3.6.3]
3. Draw the block diagram of 8259A and explain how to program 8259A.
(May/June’13) [Ref Sec:3.8.2]
4. Explain the data transfer on a parallel printer interface using a timing
diagram
(Nov/Dec’13) [Ref Sec:3.6]
5. Explain the interfacing of 4 X 4 matrix keyboard to the 8051 microcontroller with
neat diagram (Nov/Dec’13) [Ref Sec:3.10.4.4]
6. What are the signals a microprocessor should have to support DMA? List and
explain the sequence of operations carried out during a DMA transfer.
(Nov/Dec’12) (May/June’12) (May/June’14) [Ref Sec:3.9.3]
7. Explain the four modes of keyboard operation in 8279. (Nov/Dec’14) [Ref Sec:3.8.5]
8. Draw the architectural block diagram of 8259 Programmable interrupt controller
and Explain. (Nov/Dec’13) [Ref Sec:3.8.2]
9. Explain the parallel communication interface with microprocessor (Nov/Dec’12)
(April/May’17) [Ref Sec:3.3]
10.Explain the (i) modes of operation of timer and (ii) operation of interrupt controller
(May/June’13) (Nov/Dec’14) (May/June’14) [Ref Sec:3.6, 3.8]
11.Describe about serial port interface of 8051 (May/June’13) [Ref Sec:3.4] (Apr/May2019)
12. Draw the circuit diagram to interface an LCD with microcontroller and explain
how to display the data using LCD. (May/June’13) (Nov/Dec’12) [Ref Sec 3.10.3]
(Apr/May2019)
13. Explain the need of DMA controller with its functional diagram.(April/May’17)
14. Draw and explain the functional diagram of 8251. (Nov/Dec’17)
*****
UNIT 4
MICROCONTROLLER
REFERRED BOOK:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family
- Architecture, Programming and Design”, Second Edition, Prentice Hall of
India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly
and C”, Second
3. . DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH,2012
There are three decisive facts responsible for such a success of microcontrollers:
1. Their powerful, cleverly chosen electronics is able to control a variety of
processes and devices (industrial automatics, voltage, temperature, engines, etc)
independently or by means of I/O instruments such as switches, buttons, sensors,
LCD screens, relays
2. Their low cost makes them suitable for installing in places which attracted no
such interest in the past. This is the fact accountable for today's market being
swamped with cheap automatons and "intelligent" toys. 3. Writing and loading a
program into microcontroller requires practically no previous schooling. All that is
required is: any PC (software is very friendly and intuitive) and one simple device
(programmer) for loading a written program into microcontroller.
• Versatility
• General-purpose
Microcontroller
• CPU, RAM, ROM, I/O and timer are all on a single chip
• Fix amount of on-chip ROM, RAM, I/O ports
• They have instructions to set and clear individual bits and perform bit
operations.
• They have instructions for input/output operations, event timing, enabling
and setting priority levels for interrupts caused by external stimuli
• For applications in which cost, power and space are critical
• Single-purpose
CPU
Bus Serial
4 I/O Ports
OSC Control Port
P0 P1 P2 P3 TxDRxD
Address/Data
It contains several status bits that reflect the current state of the
CPU. Besides, this register contains four mathematical flags (Carry
flag, Auxiliary Carry, Overflow flag, parity bit) two register bank
select bits (RS1 & RS0), and one user-definable status flag (F0) and
one bit is not defined.
P - Parity bit: - If a number stored in the accumulator A contains even
number of 1’s then this bit will be automatically set (1), otherwise it
will be cleared (0). It is mainly used during data transmit and receive
via serial communication.
OV Overflow: - Overflow occurs when the result of an arithmetical
operation is larger than 255 and cannot be stored in one register.
Overflow condition causes the OV bit to be set (1). Otherwise, it will
be cleared (0).
RS0, RS1 - Register bank select bits. These two bits are used to select
one of four register banks of RAM. By setting and clearing these bits,
registers R0-R7 are stored in one of four banks of RAM.
RS1 RS0 Space in RAM
Bank0 (00H-
0 0 07H)
Page 163
SKR Engineering EC8691 – Microprocessor &
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Bank1
0 1
(08H- 0FH)
1 0
Bank2
1 1
(10H- 17H)
Bank3
(18H- 1FH)
F0 - Flag 0. This is a general-purpose user defined flagtheuse of this flag is
decided by the user.
AC - Auxiliary Carry Flag: - It is used for BCD operations only. This flag is set
to ‘1’ when in the addition operation the carry is generated at bit position D3
or in subtraction operation borrow is needed at the bit position D3.
CY - Carry Flag: - This flag is set to ‘1’ when in the addition operation the final
carry is generated or in subtraction operation the Minuend is less than the
Subtrahend.
PC (Program Counter): -It addresses the next instruction byte address in the
program memory. Program memory is on chip i.e. is 0000H to 0FFFH,
external to the chip for addresses that exceeds 0FFFH or total external
memory 0000h to 0FFFFH. The content of the PC is automatically
incremented after fetching of the instruction byte from the memory and
some instructions also change the value in the PC. The specialty of this
register is it doesn’t have any internal address.
DPTR (Data Pointer): - It is made up of two 8-bit registers those are DPH &
DPL. This register gives the memory addresses for internal and external code
access and external data access. The DPTR has two independent internal
addresses, one for DPL and another for DPH.
Internal Memory: - The 8051 Microcontroller has internal program memory
(ROM) and internal data memory (RAM). Due to this 8051 has a Harvard
architecture, which uses a same address in different memories, for code and
data.
Internal RAM: - The 8051 microcontroller has 128 bytes of internal RAM, its
address range from 00H to 07FH. From 80H to 0FFH addresses are assigned
to SFRs (Special Function Registers). The internal RAM 128Bytes can divide
into three parts. Those are
Example:
MOV A,
#25H MOV
R4, #62
MOV B,
#40H
MOV DPTR, #4521H
Although the DPTR register is 16-bit, it can also be accessed as two 8-bit registers,
DPH and DPL, where DPH is the high byte and DPL is the low byte.
Example:
MOV A, R0 ;copy the contents of R0 into A
MOV R2, A ;copy the contents of A in to R2
ADD A, R5 ;add the contents of R5 to
contents of A ADD A, R7 ;add the contents of R7
to contents of A MOV R6, A ;save accumulator in R6
It should be noted that the source and destination registers must match in size
IT/ IIIYR / VSEM / VENKATESH Page 179
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SKR Engineering EC8691 – Microprocessor &
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4.9.3 Direct Addressing mode
The RAM has been assigned addresses 00 to 7FH. The following is a summary of the
allocation of these 128 bytes
Although the entire 128 bytes of RAM can be accessed using direct addressing
modem it is most often used to access RAM locations 30 – 7FH. This is due to the
fact that register bank locations are accessed by the register names of R0-R7, but
there is no such name for other RAM locations
Example:
MOV A, @R0 ;move contents of RAM location whose address is held
by R0 into A
MOV @R1, B ;move contents of B into RAM location whose
address is held by R1
Notice that R0 is preceded by the “@” sign. In the absence of the “@” sign, MOV
will be interpreted as an instruction moving the contents of register R0 to A, instead
of the contents of the memory location pointed to by R0.
Advantages:
One of the advantages of register indirect addressing mode is that it makes
accessing data dynamic rather than static as in the case of direct addressing mode.
A,#0AAH MOV
P0,A
ACALL DELAY
SJMP BACK
Port 0 as Input
With resistors connected to port 0, in order to make it an input, the port must
be programmed by writing 1 to all the bits.
In the following code, port 0 is configured first as an input port by writing 1′s
to it, and then data is received from the port and sent to P1.
Port 1
Port 1 occupies a total of 8 pins (pins 1 through 8).
It can be used as input or output.
In contrast to port 0, this port does not need any pull-up resistors since it
already has pull-up resistors internally.
Upon reset, Port 1 is configured as an input port.
Example
The following code will continuously send out to port1 the alternating values
55H & AAH MOV A,#55H
BACK: MOV
P1,A
ACALL DELAY
CPL A
SJMP BACK
Port 1 as input
Port1 an input port, it must programmed as such by writing 1 to all its bits.
In the following code port1 is configured first as an input port by writing
1’s to it, then data is received from the port and saved in R7 ,R6 & R5.
MOV A,#0FFH ; A=FF HEX
MOV P1,A ; make P1 an input port by writing all
1’s to it
MOV A,P1 ; get data from P1
MOV R7,A ; save it in register R7
ACALL DELAY ; wait
MOV A,P1 ; get another data from P1
MOV R6,A ; save it in register R6
ACALL DELAY ; wait
MOV A,P1 ; get another data from P1
MOV R5,A ; save it in register R5
Port 2
Port 2 occupies a total of 8 pins (pins 21- 28).
It can be used as input or output.
Just like P1, P2 does not need any pull-up resistors since it already has pull-up
resistors internally.
IT/ IIIYR / VSEM / VENKATESH Page 183
KANNA.T
SKR Engineering EC8691 – Microprocessor &
CollegeUpon reset, Port 2 is configured as an output port.
Microcontroller
Example:
Fig.4.9.(a).External addressing
B. Stack Related Instructions: -There are two instructions are there in this group.
These instructions are used for data transfer between the internal RAM and the
specified Direct Address in the instruction. The internal RAM can be used as Stack.
The instructions are
i. PUSH ii. POP
i. PUSH Instruction: - This instruction is used for transferring the data from specified
Direct Address into Top of the Stack. For this instruction execution the SP content is
increment by ‘1’. In this instruction execution the internal operations are performed
in the following order. It support only Direct Addressing Mode
1. SP content increment by ‘1’
2. Specified Direct Address content is pushed on to SP specified location in the Stack.
Ex: - PUSH 76H
IT/ IIIYR / VSEM / VENKATESH Page 187
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SKR Engineering EC8691 – Microprocessor &
POP Instruction: -This instruction is used forMicrocontroller
College
ii. transferring the data from Top of the
Stack to specified Direct Address. For this instruction execution the SP content is
decrement by ‘1’. In
RLC Instruction: -This instruction is used to rotate the accumulator content bit by bit
to left side through Carry. MSbit is copiedto Carry flag position and Carry bit is
copied to LSbit position.
Ex: - RLC A
RRC Instruction: -This instruction is used to rotate the accumulator content bit by bit
to right side through Carry. LSbit is copiedto Carry flag position and Carry bit is
copied to MSbit position.
Ex: - RRC A
B. Bit level Logical Instructions: -These instructions perform operations on any Bit
Addressable RAM or SFR bits. The Carry flag in the PSW can be used as destination
for maximum number of instructions.
We have bit related instructions for the operations like Logical AND, OR,
Complement, Clear, Set and Move.
AND Instructions: -
i. ANL C, b: - This instruction is used logical AND between Carry Flag (CY) and the
specified direct addressed bit in the instruction. Ex: - ANL C, 64H.
ii. ANL C, : -This instruction is used logical AND between Carry Flag (CY) and
the
complement of specified direct addressed bit in the instruction. Ex: - ANL C,
OR Instructions: -
i. ORL C, b -This instruction is used FOR logical OR between Carry Flag (CY) and the
specified direct addressed bit in the instruction. Ex: - ORL C, 64H.
ii. ORL C, : -This instruction is used logical OR between Carry Flag (CY) and
the
complement of specified direct addressed bit in the instruction. Ex: - ORL C,
Complement Instructions: -
i. CPL C : - This instruction is used to Complement the Carry flag content.
ii. CPL b : - This instruction is used to Complement the specified direct addressed bit
content.
Clear Instructions: -
IT/ IIIYR / VSEM / VENKATESH Page 193
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SKR Engineering EC8691 – Microprocessor &
i. CLR C : - This instruction is used to Clear theMicrocontroller
College Carry flag content.
ii. CLRb -This instruction is used to Clear the specified direct addressed bit content.
Set Instructions: -
i. SETB C : - This instruction is used to Set the Carry flag content.
Branch Instructions
Mnemonic Description Byte Cycle
ACALL addr11 Absolute subroutine call 2 6
LCALL addr16 Long subroutine call 3 6
RET Returns from subroutine 1 4
RETI Returns from interrupt subroutine
1 4
AJMP addr11 Absolute jump 2 3
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SKR Engineering EC8691 – Microprocessor &
College
LJMP addr16 Long jump Microcontroller
3 4
Short jump (from –128 to
SJMP rel 2 3
+127 locations relative to the
following
Logic Instructions
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SKR Engineering EC8691 – Microprocessor &
College
Mnemonic Description Microcontroller
Byte Cycle
ANL A,Rn AND register to accumulator 1 1
ANL A,direct AND direct byte to 2 2
accumulator
Bit-oriented Instructions
Mnemonic Description Byte Cycle
CLR C Clears the carry flag 1 1
CLR bit Clears the direct bit 2 3
SETB C Sets the carry flag 1 1
IT/ IIIYR / VSEM / VENKATESH Page 205
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SKR Engineering EC8691 – Microprocessor &
SETB bit
College Sets the direct bit Microcontroller 2 3
CPL C Complements the carry flag 1 1
CPL bit Complements the direct bit 2 3
ANL C,bit AND direct bit to the carry flag 2 2
ANL C,/bit AND complements of direct bit to the 2 2
carry flag
ORL C,bit OR direct bit to the carry flag 2 2
2. Write an 8051 ALP to find the sum of values 79H, 0F5H, and 0E2H. Put the sum in
register R0 (Lower order Byte) and R1 (Higher order Byte).
MOV A, 00H
MOV R1, A
MOV R0, A
ADD A, #79H
JNC NEXT1
INC R1
NEXT1: ADD A, #0F5H
JNC NEXT 2
INC R1
NEXT 2: ADD A,
#0E2H JNC NEXT3
INC R1
NEXT 3: MOV R0, A
HERE: SJMP HERE
4. Write an 8051 ALP to toggle all the bits of Port 1 by sending to it the values 66H
and 0BBH continuously. Put a delay in between each issuing of data to port.
UP: MOV A,
#66H MOV P1,
A LCALL DELAY
MOV A, #0BBH
MOV P1, A
LCALL DELAY
SJMP UP
DELAY: MOV R3,
#0FFH AGAIN: DJNZ
R3, AGAIN RET
6. Write an 8051 ALP to find the Largest / Maximum number in the array.
MOV DPTR,
#3000H MOVX A,
@DPTR MOV R0,
#’N’
L1: MOV B, A
L3: DJNZ R0,
L2 SJMP
DOWN L2: INC
DPTR
MOVX A, @DPTR
CJNE A, B, UP
SJMP L3
UP: JC L3
SJMP L1
DOWN: MOV R1, B
*****
3. State the function of RS1 and RS0 bits in the flag register of Intel 8051
microcontroller? (May 2013)
How do you select register bank in 8051 [MAY/JUN 2015]
RS1 , RS0 – Register bank select bits
RS1 RS0 Bank
Selection
0 0 Bank 1
0 1 Bank 2
1 0 Bank 3
1 1 Bank 4
9. What is the size of the on-chip program memory and on-chip data memory of 8051
microcontroller? (May /June 2012)
• 4 kb on chip program memory
• 128 bytes on chip data memory
11. What are the addressing modes supported by 8051?(ECE M/J 2009)
• Immediate addressing mode.
• Register addressing mode.
• Direct addressing mode.
• Indirect addressing mode.
• Indexed addressing mode
19. Give the alternate functions for the port pins of port3? (April/May17)
• RD – Read data control output.
• WR – Write data control output.
• T1 – Timer / Counter1 external input or test pin.
• T0 – Timer / Counter0 external input or test pin.
• INT1- Interrupt 1 input pin.
23. What are the functions of the following signals of 8051? ALE/PROG, PSEN. (Nov/Dec
2010)
ALE:The ALE (Address latch enable) is used to latch the lower order address
so that it can be available in T2 and T3 and used for identifying the memory
address. During T1 the ALE goes high. When ALE goes low the lower order address
is latched until the next ALE.
PSEN: PSEN stands for program store enable. In 8051 based system in which
an external ROM holds the program code, this pin is connected to the OE pin of the
ROM.
24. What are the differences between the microprocessor and microcontroller(May/June
2014)
Microprocessor Microcontroller
Microprocessor contains ALU, general
Microcontroller contains the circuitry
purpose registers, stack pointer, of microprocessor and in addition it
program counter, clock timing has built- in ROM, RAM, I/O
circuit and interrupt circuit. devices, timers and counters.
28. What is the difference between MOVX and MOV? [NOV/DEC 2013]
Data transfer instructions move the content of one register to another.
The register the content of which is moved remains unchanged.
If they have the suffix “X” (MOVX), the data is exchanged with external memory.
29. What are the different ways of operand addressing in 8051? (May/June 2016)
An Addressing Mode indicates how the data is represented in the
instruction. 8051 supports 6 types of Addressing Modes, those are
Immediate Addressing mode
Register Addressing Mode
Register Indirect Addressing Mode
Direct Addressing Mode
Indexed Addressing Mode
Implicit Addressing Mode
30. Write an 8051 ALP to toggle P1 a total of 200 times. Use RAM location 32H to hold
your counter value instead of registers R0-R7.(May/June2016) (Apr/May 2019)
* ** * *
* ** * *
UNIT 5
INTERFACING MICROCONTROLLER
REFERRED BOOK:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family
- Architecture, Programming and Design”, Second Edition, Prentice Hall of
India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly
and C”, Second
1. DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH,2012
TMOD SFR:
The TMOD SFR is used to control the mode of operation of both timers.
Each bit of the SFR gives the microcontroller specific information concerning
how to run a timer.
The high four bits (bits 4 through 7) relate to Timer 1.
The low four bits (bits 0 through 3) perform the exact same functions, but for
timer 0.
The individual bits of TMOD have functions are shown in following table 5.2. :
TCON SFR
Finally, there’s one more SFR that controls the two timers and provides
valuable information about them. The TCON SFR has the following structure
shown in table :
Initializing a Timer
First initialize the TMOD SFR with first two bits, GATE0 and C/T0 are both 0
16-bit mode is timer mode 1 so we must clear T0M1 and set T0M0.
Only bit we want to turn on is bit 0 of TMOD.
Initialize the timer we execute the instruction:
MOV TMOD,#01h Timer 0 is now in 16-bit timer mode
Address: 87H
Where, SMOD is the 7th bit of PCON register fosc is the crystal oscillator
frequency
fosc/ (12 X [256- (TH1)]) is the timer overflow frequency in timer mode-2,
which is the auto-reload mode.
If timer-1 is not run in mode-2, then the baud rate is,
Where as
EX0 interrupt (External)
enable bit ET0 Timer-0 interrupt
enable bit
EX1 interrupt (External) enable bit
ET1 Timer-1 interrupt enable bit
ES Serial port interrupt enable bit
ET2 Timer-2 interrupt enable bit
PIN
NAME FUNCTION
NO
5 R/W Reading and writing data to the LCD for reading the
data R/W pin should be high (R/W=1) to write the data
to LCD R/W pin should be low (R/W=0)
7 DB0
8 DB1
9 DB2
10 DB3
13 DB6
14 DB7
2 Return home.
4 Decrement cursor
6 Increment cursor
ADC0804 input:
The voltage at Vref/2 (pin9) of ADC0804 can be externally adjusted to convert
smaller input voltage spans to full 8 bit resolution.
Vref/2 (pin9) left open means input voltage span is 0-5V and step size is 5/255=19.6V.
Have a look at the table below for different Vref/2 voltages and corresponding
analogue input voltage spans.
Vref/2 (pin9) (volts) Input voltage span (volts) Step size (mV)
Left open 0–5 5/255 = 19.6
2 0–4 4/255 = 15.69
1.5 0–3 3/255 = 11.76
1.28 0 – 2.56 2.56/255 = 10.04
1.0 0–2 2/255 = 7.84
0.5 0–1 1/255 = 3.92
Table 5.12 different Vref/2 voltages and corresponding analogue input voltage
Steps for converting the analogue input and reading the output from ADC0804.
Make CS=0 and send a low to high pulse to WR pin to start the conversion.
Now keep checking the INTR pin. INTR will be 1 if conversion is not finished
and INTR will be 0 if conversion is finished.
If conversion is not finished (INTR=1) , poll until it is finished.
If conversion is finished (INTR=0), go to the next step.
Make CS=0 and send a high to low pulse to RD pin to read the data from the
ADC.
PA.1 D1
PA.2 D2
PA.3 D3
PA.4 D4
4000CH
MEMORY ADDRESS OPCODE MNEMONICS
8500 74 80 MOV A, #80H
8502 90 FF 0F MOV DPTR, #CNTRL
8505 F0 MOVX @DPTR, A
8506 74 00 START: MOV A, #00H
8508 90 FF 0C L1: MOV DPTR, #PORTA
850B F0 MOVX @DPTR, A
850C 04 INC A
850D 70 F9 CJNE A, #0FF, L1
Table 5.14Memory Addresses of 8051
The idea is to use signal(s) in address decode to select the correct 2716 device.
Using partial address decoder may reduce number of signals used, and
possibly the size of the address decoder circuit.
From Table 5.15, signal A11 could be used to select each 2716.
This is because 2716 #0 has no addresses that A11 is 1.
Therefore, in case of using partial decoder, we can create a select signal Y
with “Y = A11”.
If Y is 0, Y will select 2716 #0. If Y is 1, Y will select 2716 #1.
Figure 5.22 shows the designed partial address decoder. Figure 5.23 shows
absolute address decoder case.
PIC MICROCONTROLLER:
Mid-range Architectures:
Mid-range Architectures are built by upgrading low-end architecture with
more number of peripherals,more numbers of register and more data
memory. Some of the mid-range devices are16C6X,
16C7X, 16F87X
↑Program memory
type C = EPROM
F=Flash
RC = Mask ROM.
Popularity of PIC microcontrollers is due to the following factors-
1. Speed: Harvard Architecture, RISC Architecture1
instruction Cycle = 4 clock cycles. For 20 MHz clock,
most of the instructions are executed in 0.2μsor five
instructions per mi- crosecond.
2. Instruction Set Simplicity:The instruction set consists of
just 35 instructions (as opposed to 111 instructions for
8051).
3. Power on reset Power-out reset Watch-dog
timerOscillator Options.
4. Programmable timer options on chip ADC.
5. Up to 12 independent interrupt sources
6. Powerful output pin control25mA (max.) current
sourcing capability.
7. EPROM/OTP/ROM/Flash memory options.
8. Free assembler and simulator support.
Fig.5.29.Architechture of PIC
W→Temporary holding register, often called as an accumulator, cannot be
accessed directly. Instead,contents must be moved to other registers that
can be accessed directly.
BANK ADDRESSING:
Fig.5.30.Bank addressing
RPO bit in the Status register detects the bank. 7 bit of direct address TRPO
determines the absolute address of the register. Indirect addressing
modeFSR contains the 8-bit address of the data/register.
Memory Organization;
The PIC 16C7X family has a 13-bit program counter capable of
addressing 8k×14 program memory.PIC16C74A has 4k×14 program
memory. For those devices with less than 8k program memory, accessing a
location above the physically implemented address will cause a wraparound.
ARM PROCESSORS:
ARM, previously Advanced RISC Machine, originally Acorn RISC
Machine, is a family of reduced instruction set computing (RISC)
architectures for computer processors, configured for various environments.
Arm Holdings develops the architecture and licenses it to other companies,
who design their own products that implement one of those architectures.
The ARM processor conjointly has other components like the Program status
IT/ IIIYR / VSEM / VENKATESH Page 255
KANNA.T
SKR Engineering EC8691 – Microprocessor &
College which contains the processor flags
register, (Z, S, V and C). The modes bits
Microcontroller
conjointly exist
Priority encoder: The encoder is used in the multiple load and store
instruction to point which register within the register file to be loaded or kept
.
Booth Algorithm:
Booth algorithm is a noteworthy multiplication algorithmic rule for 2’s
complement numbers. This treats positive and negative numbers uniformly.
Moreover, the runs of 0’s or 1’s within the multiplier factor are skipped over
without any addition or subtraction being performed, thereby creating
possible quicker multiplication. The figure shows the simulation results for
the multiplier test bench. It’s clear that the multiplication finishes only
in16 clock cycle.
Barrel Shifter:
The shift Value input bus is 6-bits, permitting up to 32 bit shift. The shifttype
indicates the needed shift sort of 00, 01, 10, 11 are corresponding to shift
left, shift right, an arithmetic shift right and rotate right, respectively. The
barrel shifter is especially created with multiplexers.
Control Unit:
For any microprocessor, control unit is the heart of the whole process
and it is responsible for the system operation,so the control unit design is the
most important part within the whole design. The control unit is sometimes a
pure combinational circuit design. Here, the control unit is implemented by
easy state machine. The processor timing is additionally included within the
control unit. Signals from the control unit are connected to each component
within the processor to supervise its operation.
The final thing that must be explained is how the ARM will be used and the
way in which the chip appear. The various signals that interface with the
processor are input, output or supervisory signals which will be used to
control the ARM operation.
Software
Keil compiler
Embedded C Language
The intensity control of the LED lights is possible by varying the duty cycle
from a DC source. A programmed ARM-Cortex microcontroller unit is
engaged to afford different intensities at different times of night by using the
Pulse Width Modulation technique. The charge controller circuit is used to
protect the battery from the deep discharge and overload conditions
4. What is TXD?
TXD- Transmitter Data Output .This output pin carries serial stream of the
transmitted data bits along with other information like start bit, stop bits and
priority bit.
7. State the function of RS1 and RS0 bits in the flag register of Intel8051
microcontroller? (May 2013)
11. What is the size of the on-chip program memory and on-chip data memory of 8051
microcontroller? (May /June 2012)
4 kb on chip program memory
128 bytes on chip data memory
13. What is the use of Verf pin in the ADC..( Nov/Dec 2012)
This pin used where FSD of input signal is lower than 5 volts.to get digit 255
for 8 bitADC,and 1023 for 10bit ADC.If maximum voltage is 2 volts connect Vref to 2
volt ,to get maximum resolution.If maximum voltage is 2 volts connect Vref to 2.56
volt ,to get maximum resolution
14. What is Baud rate for mode 0 operation of serial port of 8051. (May/June 2013)
Timer mode "1" is a 16-bit timer.
It functions just like 13-bit mode except that all 16 bits are used.
TLx is incremented from 0 to 255.
When TLx is incremented from 255,it resets 0 and causes THx to be
incremented by 1.
18. Give the alternate functions for the port pins of port3?
RD – Read data control output.
WR – Write data control output.
T1 – Timer / Counter1 external input or test pin.
T0 – Timer / Counter0 external input or test pin.
INT1- Interrupt 1 input pin.
INT 0 – Interrupt 0 input pin.
TXD – Transmit data pin for serial port in UART mode.
23. Write down the output control signals used in 8255A PPI?
OBF Output Buffer Full
ACK Acknowledgement
INTR Interrupt request
INTE Interrupt Enable
25. What are the types of sensors used for interfacing? (April/May’17, Nov/Dec’17)
8051 Connection to ADC0848 and Temperature Sensor ADC0804 is a very
commonly used 8-bit analog to digital convertor. It is a single channel IC, i.e.,
it can take only one analog signal as input.
27. Differentiate between timers and counters. Draw the diagram of TCON IN 8051
[MAY/JUNE 2015]
The timer content is available in four 8-bit special function registers, viz,
TL0,TH0,TL1 and TH1 respectively. In the "timer" function mode, the counter
is incremented in every machine cycle. The clock rate is 1/12 th of the
oscillator frequency.
In the "counter" function mode, the register is incremented in response to a 1
to 0 transition at its corresponding external input pin (T0 or T1). It requires 2
machine cycles to detect a high to low transition. Hence maximum count rate
is 1/24 th of oscillator frequency.
The diagram of TCON IN 8051
28. Which register is used for serial programming in 8051, illustrate it. [MAY/JUNE 2015]
Writing data to the SFR sbuf sets this data in the serial output buffer and
starts the transmission. Reading from the sbuf register reads data from the
serial receive buffer.
1. Describe the functional of the signals present in 8051. (Refer Sec 5.1)
(May/June 2013)
2. Explain how an LCD and keyboard is interfaced with 8051.(Refer
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KANNA.T
SKR Engineering EC8691 – Microprocessor &
Sec 5.4) (May/June 2013)
College Microcontroller
4. Explain 8051 serial port programming with example(Refer Sec 5.2) (May/June
2016)
7. Explain the internal data memory structure of 8051 microcontroller with its
SFRs.
(Refer Sec 5.1) (Nov/Dec 2012)
8. Draw the pin diagram of 8051 microcontroller and explain the functions of
each pin.
(Refer Sec 5.5.2)(Nov/Dec 2011)
*****