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MPMC 2019 IT Final

The document contains lecture notes for the EC8691 Microprocessor and Microcontroller course, detailing the course objectives, unit topics, and outcomes. It covers the architecture of the 8086 microprocessor and 8051 microcontroller, along with I/O interfacing and programming aspects. The notes also include references and an index of topics covered in the course, aimed at helping students design and implement microprocessor and microcontroller-based systems.

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0% found this document useful (0 votes)
10 views370 pages

MPMC 2019 IT Final

The document contains lecture notes for the EC8691 Microprocessor and Microcontroller course, detailing the course objectives, unit topics, and outcomes. It covers the architecture of the 8086 microprocessor and 8051 microcontroller, along with I/O interfacing and programming aspects. The notes also include references and an index of topics covered in the course, aimed at helping students design and implement microprocessor and microcontroller-based systems.

Uploaded by

tvk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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(Approved by AICTE, affiliated to AU, NAAC &NBA accredited)

DEPARTMENT
OF
INFORMATION TECHNOLGYENGINEERING

LECTURE NOTES
EC8691 – MICROPROCESSOR AND MICROCONTROLLER
(2017 Regulation)
Year/Semester: III/VI

Prepared by
T.VENKATESH KANNA,.AsstProf/ECE.
SKR Engineering College EC8691 – Microprocessor &
Microcontroller

EC8691 MICROPROCESSOR AND MICROCONTROLLER LTPC


30 0 3
OBJECTIVES:
The student should be made to:
 Study the Architecture of 8086 microprocessor.
 Learn the design aspects of I/O and Memory Interfacing circuits.
 Study about communication and bus interfacing.
 Study the Architecture of 8051 microcontroller.
UNIT I THE 8086 MICROPROCESSOR 9
Introduction to 8086 – Microprocessor architecture – Addressing modes -
Instruction set and assembler directives – Assembly language programming –
Modular Programming - Linking and Relocation - Stacks - Procedures –
Macros – Interrupts and interrupt service routines – Byte and String
Manipulation.
UNIT II 8086 SYSTEM BUS STRUCTURE 9
8086 signals – Basic configurations – System bus timing –System design
using 8086 – IO programming – Introduction to Multiprogramming – System
Bus Structure - Multiprocessor configurations – Coprocessor, Closely coupled
and loosely Coupled configurations – Introduction to advanced processors.
UNIT III I/O INTERFACING 9
Memory Interfacing and I/O interfacing - Parallel communication interface –
Serial communication interface – D/A and A/D Interface - Timer – Keyboard
/display controller – Interrupt controller – DMA controller – Programming and
applications Case studies: Traffic Light control, LED display , LCD display,
Keyboard display interface and Alarm Controller.
UNIT IV MICROCONTROLLER 9
Architecture of 8051 – Special Function Registers(SFRs) - I/O Pins Ports and
Circuits - Instruction set - Addressing modes - Assembly language
programming.
UNIT V INTERFACING MICROCONTROLLER 9
Programming 8051 Timers - Serial Port Programming - Interrupts
Programming – LCD & Keyboard Interfacing - ADC, DAC & Sensor Interfacing
- External Memory Interface- Stepper Motor and Waveform generation.
TOTAL: 45 PERIODS

OUTCOMES:
At the end of the course, the student should be able to:
 Design and implement programs on 8086 microprocessor.
 Design I/O circuits.
 Design Memory Interfacing circuits.
 Design and implement 8051 microcontroller based systems.
TEXT BOOKS:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family Architecture, Programming and Design”, Second Edition, Prentice
Hall of India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The 8051
Microcontroller and Embedded Systems: Using Assembly and C”, Second
Edition, Pearson Education, 2011
REFERENCE:
1. DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware: TMH, 2012
IT/ IIIYR / VSEM / VENKATESH KANNA.T Page 2
SKR Engineering College EC8691 – Microprocessor &
Microcontroller

INDEX
EC8691 – MICROPROCESSOR AND MICROCONTROLLER
S.NO TOPICS PAG
E
NO
UNIT I – THE 8086 MICROPROCESSOR
1 Introduction to 8086 7
2 Microprocessor architecture 7
3 Addressing modes 13
4 Instruction set 18
5 Assembler directives 38
6 Assembly language programming 42
7 Modular Programming 47
8 Linking and Relocation 48
9 Stacks 51
10 Procedures 52
11 Macros 54
12 Interrupts and interrupt service routines 56
13 Byte and String Manipulation. 59
14 2 Marks Questions & Answers 63
15 16 Marks Questions 67
UNIT 2 – 8086 SYSTEM BUS STRUCTURE
1 8086 signals 69
2 Basic configurations 72
3 System bus timing 75
4 System design using 8086 76
5 I/O Programming 77
6 Introduction to Multiprogramming 81
7 System Bus Structure 85
8 Multiprocessor configurations 86
9 Coprocessor, Closely coupled and loosely Coupled 86
configurations
10 Introduction to advanced processors 99
11 2 Marks Questions & Answers 109
12 16 Marks Questions 111
UNIT 3 – I/0 INTERFACING
1 Memory Interfacing and I/O interfacing 113
2 Parallel communication interface 117
3 Serial communication interface 120
4 D/A and A/D interface 123
5 Timer 127
6 Keyboard /display controller 130
7 Interrupt controller 133
8 DMA controller 136
9 Programming and applications 140
10 Case studies: 140
Traffic Light
control
11 LED display 143
12 LCD display 146
13 Keyboard display interface 149
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SKR Engineering College EC8691 – Microprocessor &


Microcontroller
14 2 Marks Questions & Answers 153
15 16 Marks Questions 157
UNIT 4 – MICROCONTROLLER
1 Architecture of 8051 159
2 Special Function Registers(SFRs) 167
3 I/O Pins Ports and Circuits 173
4 Instruction set 177
5 Addressing modes 171
6 Assembly language programming 187
7 2 Marks Questions & Answers 189
8 16 Marks Questions 193
UNIT 5 – INTERFACING MICROCONTROLLER
1 Programming 8051 Timers 195
2 Serial Port Programming 200
3 Interrupts Programming 203
4 LCD & Keyboard Interfacing 205
5 ADC 208
6 DAC 210
7 Sensor Interfacing 212
8 External Memory Interface 213
9 Stepper Motor 215
10 Waveform generation 216
11 PIC Microcontroller 218
12. ARM Processor and its Architecture 221
11 2 Marks Questions & Answers 226
12 16 Marks Questions 230
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SKR Engineering EC8691 – Microprocessor &
College Microcontroller

UNIT 1
THE 8086 MICROPROCESSOR

REFERRED BOOK:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family
- Architecture, Programming and Design”, Second Edition, Prentice Hall of
India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly
and C”, Second
1. DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH,2012

STAFF IN-CHARGE HOD

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Microcomputer:
 The term microcomputer is generally synonymous with personal computer, or
a computer that depends on a microprocessor.
 Microcomputers are designed to be used by individuals, whether in the form
of PCs, workstations or notebook computers.
 A microcomputer contains a CPU on a microchip (the microprocessor), a
memory system (typically ROM and RAM), a bus system and I/O ports,
typically housed in a motherboard.
Microprocessor:
 A silicon chip that contains a CPU. In the world of personal computers,
the terms microprocessor and CPU are used interchangeably.
 A microprocessor (sometimes abbreviated μP) is a digital electronic
component with miniaturized transistors on a single semiconductor
integrated circuit (IC).
 One or more microprocessors typically serve as a central processing unit
(CPU) in a computer system or handheld device.
 Microprocessors made possible the advent of the microcomputer.
 At the heart of all personal computers and most working stations sits a
microprocessor.
 Microprocessors also control the logic of almost all digital devices, from clock
radios to fuel-injection systems for automobiles.
 Three basic characteristics differentiate microprocessors:
 Instruction set: The set of instructions that the microprocessor can
execute.
 Bandwidth: The number of bits processed in a single instruction.
 Clock speed: Given in megahertz (MHz), the clock speed determines
how many instructions per second the processor can execute.
 In both cases, the higher the value, the more powerful the CPU. For example,
a 32 bit microprocessor that runs at 50MHz is more powerful than a 16-bit
microprocessor that runs at 25MHz.
 In addition to bandwidth and clock speed, microprocessors are classified as
being either RISC (reduced instruction set computer) or CISC (complex
instruction set computer).
Super computer:
 A supercomputer is a computer that performs at or near the currently highest
operational rate for computers.
 At any given time, there are usually a few well-publicized supercomputers
that operate at the very latest and always incredible speeds.
 The term is also sometimes applied to far slower (but still impressively fast)
computers.
 Most supercomputers are really multiple computers that perform parallel
processing.
 In general, there are two parallel processing approaches: symmetric
multiprocessing (SMP) and massively parallel processing (MPP).
Microcontroller:
 A highly integrated chip that contains all the components comprising a
controller.
 Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers.
 Unlike a general-purpose computer, which also includes all of these
components, a microcontroller is designed for a very specific task - to control
a particular system.
 A microcontroller differs from a microprocessor, which is a general-purpose
chip that is used to create a multi-function computer or device and requires
multiple chips to handle various tasks.
 A microcontroller is meant to be more self-contained and independent, and
functions as a tiny, dedicated computer.
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SKR Engineering EC8691 – Microprocessor &
 They are typically designed using Microcontroller
College CMOS (complementary metal oxide
semiconductor) technology, an efficient fabrication technique that uses less
power and is more immune to power spikes than other techniques.
 Microcontrollers are sometimes called embedded microcontrollers

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Difference between microprocessor and microcontroller
Microprocessor Micro Controller
It is a CPU It is a single chip
A microprocessor generally doesA microcontroller is 'all in one',
not have Ram, ROM and IO pins. the processor, ram, IO all on the
one chip
Microprocessor contains ALU Micro Controller contains MP memory ,i/o
control unit different register Interfacing circuit and peripheral
And interrupt circuit devices such as A/D converter serial
I/O timer
It has one or two bit handling It has many bit handling instruction
instruction
It has capable of being built intoIt is usually used for more dedicated
bigger general purpose applications.
applications
than a microcontroller
Table 1.1 Difference between microprocessor and microcontroller
The microprocessor used in some applications such as,
 For measurements, display and control of current, voltage,
temperature, pressure, etc.
 For traffic control and industrial tool control.
 For speed control of machines

1.1 INTRODUCTION TO 8086


1.1.1 Features:
 Intel 8086 was launched in 1978.
 It was the first 16-bit microprocessor.
 This microprocessor had major improvement over the execution speed of 8085.
 It is available as 40-pin Dual-Inline-Package (DIP).
 It is available in three versions:
 8086 (5 MHz)
 8086-2 (8 MHz)
 8086-1 (10 MHz)
 It consists of 29,000 transistors.
 The 8086 is 16 bit microprocessors. The term “16 bit” means that its
arithmetic logic unit, internal registers and most of its instructions are
designed to work with 16 bit binary words.
 The 8086 has a 16 bit data bus, so it can read data from or write data to
memory and ports either 16bits or 8bits at a time
 The 8086 has a 16 bit address bus ,so it can directly access 2 20 or 1048576
memory locations
 The 8086 can generate 16bit I/O address.
 The 8086provides fourteen 16 bit registers
 The 8086 has multiplexed address and data bus which reduces the number of
pins.
 The Intel 8086 supports multiprogramming
 Intel 8086 is designed to operate in two modes, namely the minimum
node and maximum node

1.2 ARCHITECTURE OF 8086 MICROPROCESSOR


 Intel 8086 is a 16 bit integer processor.
 It has 16-bit data bus and 20-bit address bus.
 The lower 16- bit address lines and 16-bit data lines are multiplexed (AD0-
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 20-bit address lines are available.
 8086 can access up to 220 or 1 Megabyte of physical memory.

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SKR Engineering EC8691 – Microprocessor &
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 The basic architecture of 8086 is shown below.
 The internal architecture of Intel 8086 is divided into two units, viz.,
 Bus Interface Unit (BIU) and
 Execution Unit (EU).

Bus Interface Unit (BIU) and Execution Unit (EU)


 The BIU performs all bus operations such as instruction fetching, reading
and writing operands for memory and calculating the addresses of the
memory operands.
 The instruction bytes are transferred to the instruction queue.
 EU executes instructions from the instruction system byte queue.
 Both units operate asynchronously to give the 8086 an overlapping
instruction fetch and execution mechanism which is called as Pipelining. This
results in efficient use of the system bus and system performance.
 BIU contains Instruction queue, Segment registers, Instruction pointer, and
Address adder.
 EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index
register, Flag register.

1.2.1 BUS INTERFACR UNIT (BIU):


 It provides a full 16 bit bidirectional data bus and 20 bit address bus.
 The bus interface unit is responsible for performing all external bus operations.
 it has the following functions:
 Instructions fetch Instruction queuing, Operand fetch and storage, Address
relocation and Bus control.
 The BIU uses a mechanism known as an instruction stream queue to
implement pipeline architecture.
 This queue permits pre fetch of up to six bytes of instruction code. Whenever
the queue of the BIU is not full, it has room for at least two more bytes and at
the same time the EU Is not requesting it to read or write operands from
memory.
 The BIU is free to look ahead in the program by prefetching the next
sequential instruction.
 These prefetching instructions are held in its FIFO queue. With its 16 bit data
bus, the BIU fetches two instruction bytes in a single memory cycle.
 After a byte is loaded at the input end of the queue, it automatically shifts up
through the FIFO to the empty location nearest the output.
 The EU accesses the queue from the output end. It reads one instruction byte
after the other from the output of the queue.
 If the queue is full and the EU is not requesting access to operand in memory.
 These intervals of no bus activity, which may occur between bus cycles, are
known as
Idle state. The following Figure 1.1 shows 8086 Internal Block Diagram.
 If the BIU is already in the process of fetching an instruction when the EU
request it to read or write operands from memory or I/O, the BIU first
completes the instruction fetch bus cycle before initiating the operand read /
write cycle.
 The BIU also contains a dedicated adder which is used to generate the 20bit
physical address that is output on the address bus.
 This address is formed by adding an appended 16 bit segment address and a
16 bit offset address.
 For example:
The physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the
current contents of the instruction pointer IP register.
 The BIU is also responsible for generating bus control signals such as those
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SKR Engineering EC8691 – Microprocessor &
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Microcontroller

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SKR Engineering EC8691 – Microprocessor &
College Microcontroller

Fig: 1.1 8086 Internal Block Diagram


1.2.2 EXECUTION UNIT (EU):
 The Execution unit is responsible for decoding and executing all instructions.
•The EU extracts instructions from the top of the queue in the BIU, decodes
them,
 Generates operands if necessary, passes them to the BIU and requests it to
perform the read or write by cycles to memory or I/O and perform the
operation specified by the instruction on the operands.
 During the execution of the instruction, the EU tests the status and control
flags and updates them based on the results of executing the instruction.
 If the queue is empty, the EU waits for the next instruction byte to be fetched
and shifted to top of the queue.
 When the EU executes a branch or jump instruction, it transfers control to a
location corresponding to another set of sequential instructions.
 Whenever this happens, the BIU automatically resets the queue and then
begins to fetch instructions from this new location to refill the queue.
1.2.3 Instruction Queue:
 The BIU fetches up to 6 instruction bytes for the following instructions.
 The BIU stores these perfected bytes in first-in-first-out register set called a
queue.
 When the EU is ready for its next instruction it simply reads the instruction
byte(s) for the instruction from the queue in the BIU.
 This is much faster than sending out an address to the system memory and
waiting for memory to send back the next instruction byte or bytes.
 Except in the case of JMP and CALL instructions, where the queue must be
dumped and then reloaded starting from a new address, this pre-fetch-and-
queue scheme greatly speeds up processing.
 Fetching the next instruction while the current instruction executes is called
pipelining. Pipeline Diagram is follows.

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Fig: 1.2 Pipelining


1.2.4 Register organization of 8086:
 8086 has a powerful set of registers containing general purpose and special
purpose registers. All the registers of 8086 are 16-bit registers.
 The general purpose registers, can be used either 8-bit registers or 16-bit
registers.
 The general purpose registers are either used for holding the data, variables
and intermediate results temporarily or for other purpose like counter or for
storing offset address for some particular addressing modes etc.
 The special purpose registers are used as segment registers, pointers, index
registers or as offset storage registers for particular addressing modes.
 Fig 1.3 shows register organization of 8086. We will categorize the register
set into four groups as follows:

1.2.5 General purpose registers:

Fig: 1.3 Register Organization of 8086


The registers AX, BX, CX, and DX are the general 16-bit registers.
AX Register:
Accumulator register consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16- bit register AX. AL in this case contains the
low-order byte of the word, and AH contains the high-order byte. Accumulator can
be used for I/O operations, rotate and string manipulation.
BX Register:
This register is mainly used as a base register. It holds the starting base
location of a memory region within a data segment. It is used as offset storage for
forming physical address in case of certain addressing mode.
CX Register:
It is used as default counter or count register in case of string and loop
instructions.
DX Register:
Data register can be used as a port number in I/O operations and implicit
operand or destination in case of few instructions. In integer 32-bit multiply and
divide instruction the DX register contains high-order word of the initial or resulting
number.
1.2.6 Segment Registers:
 To complete 1Mbyte memory is divided into 16 logical segments.
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 The complete1Mbyte memory segmentation
College is as shown in fig 1.5.
Microcontroller
 Each segment contains 64Kbyte of memory.

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 There are four segment registers such as,
1. Code segment (CS)
2. Stack segment (SS)
3. Data segment (DS)
4. Extra segment (ES)

1. Code segment (CS):


 Code segment (CS) is a 16-bit register containing address of 64 KB
segment with processor instructions.
 The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register.
 CS register cannot be changed directly.
 The CS register is automatically updated during far jump, far call and
far return instructions.
 It is used for addressing a memory location in the code segment of the
memory, where the executable program is stored.
2. Stack segment (SS):
 Stack segment (SS) is a 16-bit register containing address of 64KB
segment with program stack.
 By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack segment.
 SS register can be changed directly using POP instruction.
 It is used for addressing stack segment of memory.

3. Data segment (DS):


 Data segment (DS) is a 16-bit register containing address of 64KB segment
with program data. By default, the processor assumes that all data
referenced by general registers (AX, BX, CX, and DX) and index register (SI,
DI) is located in the data segment.
 DS register can be changed directly using POP and LDS instructions.

4. Extra segment (ES):


 Extra segment (ES) is a 16-bit register containing address of 64KB
segment, usually with program data.
 By default, the processor assumes that the DI register references the ES
segment in string manipulation instructions.
 ES register can be changed directly using POP and LES instructions.

Table 1.2 8086 default 16 bit segment and offset address combination

 It also refers to segment which essentially is another data segment of the


memory.
 It also contains data.

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Fig: 1.4 Memory Segmentation


1.2.7 Pointers and index registers:
 The pointers contain within the particular segments.
 The pointers IP, BP, SP usually contain offsets within the code, data
and stack segments respectively.
Instruction Pointer (IP):
 It is act as a program counter
 It points to the address of the next instruction to be executes.
 Its contents automatically incremented when the execution of a program
proceeds further
 The contents of the IP and code segments register are used to compute
the memory address of the instruction code to be fetched.
 This is done during the fetch cycle.
Stack Pointer (SP):
Stack Pointer (SP) is a 16-bit register pointing to program stack in stack
segment.
Base Pointer (BP):
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP
register is usually used for based, based indexed or register indirect addressing.
Source Index (SI):
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing.
Destination Index (DI):
 Destination Index Data addresses in string manipulation instructions.
 Destination Index (DI) is a 16-bit register.
 DI is used for indexed, based indexed and register indirect addressing, as
well as a destination data addresses in string manipulation instructions.
1.2.8 Flag register:

Fig: 1.5 Flag Register


 Flags Register determines the current state of the processor.
 They are modified automatically by CPU after mathematical operations
 It allows to determine the type of the result, and to determine
conditions to transfer control to other parts of the program.
 The 8086 flag register has 9 active flags and they are divided into two
categories:
1. Conditional Flags
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1. Conditional Flags:
Conditional flags are as follows:
Carry Flag (CY):
 This flag indicates an overflow condition for unsigned integer arithmetic.
 It is also used in multiple-precision arithmetic.
Auxiliary Flag (AC):
 If an operation performed in ALU generates a carry/barrow from
lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7).
 The AC flag is set i.e. carry given by D3 bit to D4 is AC flag.
 This is not a general-purpose flag.
 It is used internally by the Processor to perform Binary to BCD conversion.
Parity Flag (PF):
 This flag is used to indicate the parity of result.
 If lower order 8-bits of the result contains even number of 1’s.
 The Parity Flag is set and for odd number of 1’s,the Parity flag is reset.
Zero Flag (ZF):
 It is set; if the result of arithmetic or logical operation is zero else it is reset.
Sign Flag (SF):
 In sign magnitude format the sign of number is indicated by MSB bit.
 If the result of operation is negative, sign flag is set.
2. Control Flags:
Control flags are set or reset deliberately to control the operations of the execution
unit. Control flags are as follows:
Trap Flag (TF):
 It is used for single step control.
 It allows user to execute one instruction of a program at a time for debugging.
 When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF):
 It is an interrupt enable/disable flag.
 If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is disabled.
 It can be set by executing instruction sit and can be cleared by executing CLI
instruction.
Direction Flag (DF):
 It is used in string operation.
 If it is set, string bytes are accessed from higher memory address to
lower memory address.
 When it is reset, the string bytes are accessed from lower memory
address to higher memory address.

1.3 8086 MICROPROCESSOR ADDRESSING MODES


 The different ways that processor access data are referred to as addressing
modes.
 The addressing modes of any processor can be classified as:
1. Data addressing modes
2. Stack memory addressing modes
3. Program memory addressing modes
1.3.1. DATA ADDRESSING MODES:
The data addressing mode can be further classified as,
1. Addressing modes for accessing immediate and register data (register and
immediate modes)
2. Addressing modes for accessing data in memory(memory modes)
3. Addressing modes for accessing I/O Ports(I/O modes)
1.3.1.1. Addressing modes for accessing immediate and register data
1. Register addressing mode:
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mode specifies the source operand, destination operand or both to be contained
Microcontroller
in an 8086 register

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SKR Engineering EC8691 – Microprocessor &
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Sample Register addressing modes are,

Fig: 1.6 Register Addressing Modes


Example:
MOV BX, CX; copies the 16 bit content of CX
into BX MOV CL, BL ; copies 8 bit contents
of BL into CL
2. Immediate addressing mode:
 In an immediate mode,8 bit or 16 bit data can be specified as a part of
instruction.
 Transfers the source, an immediate byte or word of data, into the destination
register or memory location
 The source operand is a constant.
 The operand comes immediately after the opcode.
 For this reason, this addressing mode executes quickly.
 Immediate addressing mode can be used to load information into any of
the registers except the segment registers and flag registers..
Example:
 MOV BL,26H;copies the 8 bit data 26H into BL
 MOV CX.4567H;copies the 16 bit data 4567H into CX

Fig: 1.7 Immediate Addressing Modes


1.3.1.2. Addressing modes for accessing data in memory
 The execution unit has direct access to all registers and data for register and
immediate operands.
 The EU cannot directly access the memory operands.
 It must be use the BIU segment registers to access memory operands.
 For examples, when the EU needs a memory location, it sends an offset
value to the BIU.
 This offset is also called as Effective address(EA)
There are six ways to specify effective address (EA) in the instruction
a) Direct Addressing mode
b) Register Indirect Addressing mode
c) Based Addressing mode
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e) Based Indexed Relative Addressing mode
f) String addressing mode
1) Direct Addressing mode:
 In this mode the 16 bit effective address (EA) is taken directly from
displacement field of instruction.
 The displacement is stored in the location following the instruction opcode.
Example:
MOV AL,[3000H]
 This instruction will copy the contents of the memory location, at a
displacement of 3000H from the data segment base, into the AL register.
 Here, 3000H is the Effective address (EA) which is written directly in the
instruction.
Physical Address: [DS]X[10H]+EA=[DS]X[10H]+3000H
The physical address is calculated by combining the contents of offset location 2400 with
DS.

2) Register indirect addressing mode:


 In this mode, the EA is specified in either a pointer register or an index register.
 The pointer register can be either base register BX or base pointer register.
 Index register can be either source index (SI) register or destination index (DI)
register.
 The 20 bit physical address is computing using DS and EA.
Example:
1) MOV [DI], BX
 The instruction copies the 16-bit contents of BX into a memory location
offset by the value of EA specified in DI from the current contents in DS.
 Now, if [DS]=7205H, [DI]=0030H, and [BX]=8765H.
 Then after MOV [DI], BX, content of BX (8765H) is copied to memory locations
72080H.
Physical address:[DS] X [10H] +EA= [DS] X [10H] + [DI]
2) MOV AX,[BX]
 Moves into AX the contents of the memory location pointed to by DS along with
BX.
 Now, if [DS] value is 1000 and [BX] =1234.
 The physical address is calculated as 1000x10+1234=11234H
3) Base plus index addressing:
 Base plus index addressing is similar to indirect addressing because it
indirectly accessing data.
 This addressing uses in base register (BP or BX) and one index register (DI
or SI) to indirectly address memory.
 The base register often holds the beginning location of memory array.
 The index register holds relative position of an element in an array.
Example:
MOV CX, [BX + DI]
 In this mode the EA is given by the sum of base and index register ie) [BX] +
[DI]
Physical address:[DS] X [10H] + EA=[DS] X [10H] + [BX] +[DI]
4) Register Relative addressing mode:
 Register relative addressing is similar to base-plus-index addressing.
 The data in a segment of memory are addressed by adding the
displacement to the contents of a base on index register (BP, BX, DI or SI)
Example:
MOV CX [BX +0003H]; in this mode EA is given by sum of base register and displacement
5) Base Relative plus index addressing:
 The base relative plus index addressing is similar to the base plus index
addressing mode.
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 It adds a displacement besides using aMicrocontroller
College base register and an index register to
generate a physical address of the memory,
 This addressing mode is suitable to address data within the two dimensional
array.
Example:

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MOV AL, [BX + SI +10H] ; In this mode the EA is the sum of base register, index
register
and displacement
6) String addressing mode:
 This mode uses the index registers.
 The string instruction assumes SI to point to the first byte or word of the source
operand
 DI to point to the first byte or word of the destination operand.
 The contents of SI and DI are automatically incremented or decremented to
point to the next byte or word.
 The segment register for the source is DS.
 The segment register for the destination must be ES.
Example:
MOVE BYTE; If [DF]=0; [DS]=3000H; [SI]=0600H; [ES]=5000H; [DI]=0400H;
[30600H]=38H;
and [50400H]= 45H the after execution of the MOVS BYTE,[50400H]=38H;[SI]=0601H
and [DI]=0401H

1.3.1.3 Addressing modes for accessing I/O ports (I/O Modes)


 A standard I/O device uses port addressing modes.
 For memory –mapped I/O, memory addressing modes are used.
 There are two types of port addressing modes are
1) Direct port mode
2) Indirect port mode
Direct port mode:
 The port number is an 8-bit immediate operand.
 This allows fixed access to ports numbered 0 to 255.
Example:
 OUT 05H,AL; sends the contents of AL to 8 bit port 05H
 IN AX,80H;copies 16 bit contents of port 80H
Indirect Port mode:
 Here the port number is taken from DX allowing 64K 8 bit ports or 32 K bit ports.
Example:
 IN AL,DX; if [DX]=7890H,then it copies 8-bit content of port 7890H into AL
 IN AX,DX; copies the 8 bit contents of ports 7890H and 7891H into AL
and AH respectively.
1.3.2. PROGRAMMEMORY ADDRESSING MODES:
 JMP (Jump) and CALL instructions use program memory addressing modes.
 These instructions have three distinct forms;
1. Direct program memory addressing
2. Relative program memory addressing
3. Indirect program memory addressing
1) Direct program memory addressing:
 In this addressing mode address where to transfer program control is
specified within the instruction along with the opcode.
Example:
JMP 2000H;
This instruction loads CS with 2000H and IP with 0000H to jump to memory location
2000H
2) Relative program memory addressing:
 In this addressing mode, this term relative is restricted to instruction pointer
(IP).
 For example, if a JMP instruction skips the next 5 bytes of memory.
 The address in relation to the instruction pointer is a 5 that adds to the
instruction pointer.
 This generates the address of the next program instruction
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Example:
College Microcontroller
JMP [05];
 This instruction skips over the two bytes of memory that allow the JMP
instruction.
 When displacement is one byte (8 bit) it is called short jump.

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 When displacement is two byte (16 bit) it is called near jump.
 In both short and near cases only contents of IP register are modified;
 Contents of CS register are not modified; Such Jumps are called intra segment
jumps
 The relative JMP and CALL instructions can have either a 8 bit or a 16 bit
signed displacement that allows a forwarded memory reference or a reverse
memory reference.
3) Indirect program memory addressing:
 The 8086 allows several forms of program indirect memory addressing for
the JMP and CALL. Instructions.
 In this addressing mode, it is possible to use any 16 bit
register (AX,BX,CX,DX,SP,BP,DI or SI) and Relative register([BP],[BX],[DI]
or [SI]).
Assembly language Operation
JMP AX Jumps to the current code segment location addressed
by the contents of AX
JMP CX Jumps to the current code segment location addressed
by the contents of CX
JMP NEAR PTR [BX] Jumps to the current code segment location addressed
by the contents of the data
segment memorylocation
addressed by BX
JMP NEAR PTR[DI +2] Jumps to the current code segment location addressed
by
thecontents of the data segment memory
location addressed by DI plus 2
JMP TABLE[BX] Jumps to the current code segment location addressed
by the contents of the data
segment memorylocation
addressed by TABLE plus BX
JMP ECX Jumps to the current code segment location addressed
by the contents of ECX
Table 1.3 Jump Addressing Modes
1.3.3. STACK MEMORY ADDRESSING MODES
There are two stack operations are performed such as
 Push operations
 Pop operations
The figure 1.8 a) represents PUSH BX places the contents of BX onto the
stackThe figure 1.8 b) represents POP CX removes data from the stack and

places them into CX


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The complete Addressing modes of 8086:

Fig: 1.9 Summary of Addressing Modes

1.4 INSTRUCTION SET


The instruction set of the 8086 is divided into eight major groups as follows.
A. Data movement instructions
B. Arithmetic and logical instructions
C. String manipulation instruction
D. Program control transfer instructions
E. Iteration control instructions
F. Processor control instruction
G. External hardware synchronization instruction
H. Interrupt instruction
1.4.1 DATA TRANSFER INSTRUCTIONS:
 The data transfer instructions are those, which transfers the DATA from any
one source to any one destination.
 The data may be of any type. They are again classified into five groups.
 They are
a) MOV instructions to transfer byte or word
b) PUSH/POP instructions
c) Load effective address instruction
d) String data transfer instruction
e) Miscellaneous data transfer instructions
1.4.1.1 MOV instructions:
 It is a general purpose instruction to transfer byte or word from register
to register, register to memory or from memory to register
MOV destination, source
 The MOV instruction copies a word or a byte of data from some
source to a destination. The destination can be a register or a memory
location
 The source can be either can be register, a memory location or a immediate
number
 The source and destination in a MOV instruction must be a same type
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Example:
MOV BX, 592FH : Load the immediate number 592FH in BX
MOV CL, [357SAH] : Copy the contents of memory location at a
displacement of 357AH from data segment base into
the CL register
MOV DS, CX : copy word from CX register to data segment register
1.4.1.2 PUSH/POP Instructions:
 These instructions are used to load or receive data from the stack memory
PUSH Source:
 The PUSH instruction decrements stack pointer by two and copies a word
from source to the location in the stack.
 The source must be a word (16 bit).
 The source of the word can be general purpose register, a segment register or
memory.
 Whenever data is pushed on to the stack the first (MSB) data byte moves into
the stack segment memory location addressed by the SP-1.
 The second (LSB) data byte moves into the stack segment memory location
addressed by the SP-2.
Example:
1. PUSH CX ; decrements SP by 2, copy CX to stack
The following figure 1.10 shows the execution of PUSH CX instruction.
2. PUSHDS ; decrement SP by 2, copy DS to stack
3. PUSH NEXT [BX] ; decrement SP by 2, copy a word from memory in DS (i.e.
.PA=EA + DS) to stack with EA=NEXT + [BX]

Fig: 1.10 PUSH CX on the Stack


PUSHF:
 Puts the flag register contents on the stack
 Whenever instruction is executed on to the stack the first (MSB) data byte
moves into the stack segment memory location addressed by the SP-1.
 The stack the second (LSB) data byte moves into the stack segment
memory location addressed by the SP-2.
POP destination:
 The POP instruction copies a word from the stack location pointed by the
stack pointer to the destination.
 The destination can be general purpose register, a segment register or memory
location.
 After the word is copied to the specified destination, the stack pointer is
automatically incremented by 2
Example:
1. POP CX ; copy a word from top of the stack to CX and incremented
SP by 2 The following figure 1.11 shows the execution of POP CX
instruction.
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Fig: 1.11 POP CX on the Stack


2. POP DS ; copy a word from top of stack to DS and incremented SP by 2.
POPF:
 Removes the word from top of the stack to the flag register.
 Whenever instruction is executed, the byte from the stack segment
memory location addressed by SP moves into the most significant byte of
the flag register
 The byte from the stack segment memory location addressed by SP +1
moves into the least significant byte or the flag
1.4.1.3 Load Effective Address Instruction:
The Load effective address group includes following instructions.
1) LEA(Load Effective Address )
2) LDS(Load pointer using DS )
3) LES(Load ES with pointer )
1) LEA (Load Effective Address):
Format: LEA register, source
 This instruction determines offset of the variable or memory location.
 It loads a 16-bit register with the offset address of the data
specified by the source.
Example:
1. LEA CX, TOTAL ; loads CX with offset of TOTAL in DS
2. LEA AX, [BX], [DI] ; loads AX with EA = [BX] + [DI]
2) LDS (Load pointer using DS)
Format: LDS register, source
 It loads 32-bit pointer from memory source to destination register and DS.
 The offset is placed in the destination register and the segment is placed in DS.
 This instruction copies a word from two memory locations into the register
specified in the instruction.
 It then copies a word from the next two memory locations into the DS register.
Example:
LDS CX, [391AH] ; Copy the contents of memory at displacements of
391AH and 391BH to CX .Then copy the contents at
displacement of 391CH and 391DH in DS.
3) LES (Load ES with pointer)
Format: LES register, source
 It loads 32-bit pointer from memory source to destination register and ES.
 The offset is placed in the destination register and the segment is placed in ES.
 This instruction loads new values into specified register
 A successive four memory location loads into the ES register.
 The word from the first two memory locations is copied into the specified
register and the word from the next two memory locations is copied into the
ES register.
Example:
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CX, [3483H] ; Copy the contents of memory displacement of 3483H in DS to CL.
Microcontroller

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Contents of 3484H in DS to CH and
Copy the contents of memory at displacement of 3485H and
3486H in DS to ES register.
1.4.1.4 String Data Transfer Instruction
1) MOVS/MOVSB/MOVSW Instruction
 These instructions copy a byte or word from a location in the data segment to
a location in the extra segment.
 The offset of the source byte or word in the data segment must be in the SI
register.
 The offset of the destination byte or word in the data segment must be in the DI
register.
Example:
CLD ; Clear Direction Flag to auto increment SI
and DI MOV AX, 0000H
MOV OS, AX ; Initialize data segment register
to 0 MOV ES, AX ; Initialize extra segment
register to 0
MOV SI, 2000H ; Load offset of start of source string
into SI MOV DI, 2400H ; Load offset of start of
destination into DI MOV CX. 041-1 ; Load length of
string In CX as counter
REP MOVSB ; Decrement CX and MOVSB until CX will be 0.
After move SI will be one greater than offset of last byte in source string. D! will be
none greater than offset of last byte of destination string. CX will be 0.
2) REP / REPE / REPZ /REPNE/REPNZ Prefix:
 REP is a prefix which is written before one of the string instructions.
 These instructions repeat until specified condition exists.
Instruction Code Condition for Exit
REP CX=0
REPE/ REPZ CX =0 or ZF = 0
REPNE / REPNZ CX =0 or ZF=1
Table 1.4 Repeat Conditions
Example:
REPZ CMP SB ; Compare string bytes until CX = 0; or until string bytes not equal.
3) LODS / LODSB / LODSW
 This instruction copies a byte from a string location pointed to by SI to
AL, or a word from a string location pointed to by SI to AX.
 LODS does not affect any flags. LODSB copies byte and LODSW copies a word,
Example:
CLD ; Gear direction flag so SI is auto
incremented MOV SI, OFFSET S_STRING ; Point ST at string
WDS S_STRING.
4) STOS / STOSB / STOSW
 The STOS instruction copies a byte from AL or a word from AX to a memory
location in the extra segment.
 DI Is used to hold the offset of the memory location in the extra segment.
 After the copy, DI is automatically incremented or decremented to point to
the next string element in memory.
 If the direction flag, DF, is cleared, then DI will automatically be incremented
by one for a byte string or incremented by two for a word string.
 If the direction flag is set, DI will be automatically decremented by one for a
byte string or decremented by two for a word string.
 STOS does not affect any flags. STOSB copies byte and STOSW copies a word.
Example:
MOV Dl, OFFSET D_STRING ; Point DI at destination string
STOS D_STRING ; Assembler uses string name to
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Microcontroller
byte or type word. If byte string, then
string byte replaced With contents of
AL If word string, then

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String word replaced with contents
of AX MOV DI, OFFSET D_STRING ; Point DI at destination string
STOSB “B” added to 5105 mnemonic directly
tells assembler to replace byte in string with
byte from AL STOSW would tell assembler directly
to replace a
Word in the string with a word from AX.
1.4.1.5 Miscellaneous Data Transfer Instructions
This group consists of following instructions.
1) XCHG
2) LAHF
3) SAHP
4) XLAT
5) IN and OUT
1) XCHG Instruction:
Format: XCHG destination, source.
 The XCHG instruction register or the contents of a register with the
contents of a memory location(s).
 The instruction cannot exchange the contents of two memory locations.
 The source and destination both must be words or bytes.
 The segment registers can’t be used in these Instructions.
Example:
XCHG BX, CX ; Exchange word in BX with word in CX.
XCHG AL, CL ; Exchange byte in AL with byte in CL
XCHG AL, SUM [BX] ; Exchange byte in AL with byte in
memory at
; EA = SUM + [BX].
; PA = EA + DS.
2) LAHF Instruction:
 Load lower byte of flag register in AH.
 This instruction copies the contents of lower byte of 8086 flag register to AH
register.
3) SAHF Instruction:
 Copy AH registers to low byte of flag register.
 The contents of the AH register are copied into the lower byte of the 8086 flag
register.
4) XLAT Instruction:
 Translate byte in AL.
 The XLAT instruction replaces a byte in the AL register with a byte from a
lookup table in memory.
 BX register stores the offset of the starting address of the lookup table
 AL register stores the byte number from the lookup table.
 This instruction copies byte from address pointed by [BX + AL] back into AL.
5) IN and OUT instructions
IN Instruction:
 Input a byte or word from port.
 The IN instruction will copy data from a port to the accumulator.
 If an 8-bit port is read, the data will go to AL and if a 16-bit port is read the
data will go to AX.
The IN instruction can be executed in two different addressing modes,
1. Direct:
 In direct addressing mode 8-bit address of the port is a part of the instruction.
Example:
IN AL, 0F8H ; Copy a byte from port 0F8H
to AL IN AX, 95H ; Copy a word from port
95H to AX.
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2. Indirect:
College Microcontroller
 In indirect addressing, the address of the port is referred from DX register.
 Since DX is a 16-bit register, the port address can be any number between
0000H to FFFH.

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 Therefore it is possible address to up to65,536 ports in this mode.
Example:
MOV DX, 30F8H ; Load 16-bit address of the port in DX.
IN AL. DX ; Copy a byte from 8-bit port 30F8H to
AL. IN AX, DX ; Copy a word from 16-bit port 30F8H
to AX. OUT Instruction:
 Send a byte or word to a port.
 The OUT instruction copies a byte from AL or a word from AX to the specified
port.
 The OUT instruction can be executed in two different addressing modes.
1. Direct:
In direct addressing mode 8-bit address of the port is a part of the instruction.
Example:
OUT 0F8H.AL ; Copy contents of AL to 8 bit port
0F8H. OUT 0FBH, AX ; Copy contents of AX to 16-
bit port 0FBH.
2. Indirect:
 In indirect addressing, the address of the port is referred from DX register.
 It has advantage of accessing 216 i.e. 65536 ports as mentioned earlier.
Example:
MOV DX, 30F8H ; Load 16-bit address of the port in
DX. OUT DX, AL ; Copy the contents of AL to port
30F8H. OUT DX, AX ; Copy the contents of AX to
port 30F8H.
1.4.2 ARITHMETIC AND LOGICAL INSTRUCTIONS:
The arithmetic and logic group of instructions include
1) Addition instructions
2) Subtraction instructions
3) Multiplication instructions
4) Division
5) BCD and ASCII Arithmetic instructions
6) Comparison
7) Basic Logic Instructions - AND, OR NOT, XOR
8) Shift and Rotate instructions
1.4.2.1 Addition
This group of instructions consists of following instructions
a) ADD: Addition
b) ADC: Addition with carry
c) INC: Increment (Add 1)
a) & b) ADD/ADC Instruction:
Format: ADD destination, source / ADC destination, source.
 These instructions add a number from source to a number from destination
and put the result in the destination.
 The ADC, instruction also adds the status of carry flag in to the result. The
source may be an immediate number, a register, or a memory location.
 The source and the destination in an instruction cannot both be memory
locations.
 The source and destination both must be a word or byte.
Flags affected: AP, CF, OF, PP. SF, ZR
Example:
ADD AL, 0F0H ; Add immediate number 0F0H to contents of AL.
ADC DL. CL ; Add contents of CL to contents of DL with carry and store
result in DL i.e. DL+CL+CY
ADC DX, BX ; Add contents of BX to contents of DX with carry and store
result in DX i.e. DX DX + BX + CY
ADD CL, TOTAL [BX] ; Add byte from effective address TOTAL [BX] to contents of
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CL. ADD CX, TOTAL [BX] ; Add word from effective
College address TOTAL [BX] to
Microcontroller
contents of CX.
c) INC Instruction:
Format: Increment destination.
 The INC instruction adds 1 to the specified destination. The destination may be
a

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 Register or memory location.
 The AP, OF, PF, SF and ZF flags are affected.
Example:
INC AL ; Add 1 to contents of AL.
INC BX ; Add 1 to contents of BX.
INC BYTE PTR [BX] ; Increment byte at offset of BX in DS.
; BYTE PTR directive indicates to the assembler; that the
byte from memory is to be incremented.
INC WORD FIE [BX] ; Increment word at offset of BX in DS.
; WORD PTR directive indicates to the assembler; that
the word from memory is to be incremented.
1.4.2.2 Subtraction
This group of instructions consists of following group of instructions.
a) SUB : Subtraction
b) SBB : Subtraction with borrow
c) DEC: Decrement (subtract 1)
d) NEG : 2’s complement of a number
a) &b)SUB / SBB Instruction:
Format: SUB destination, Source.
SBB destination, Source.
 These instructions subtract the number in the source from the number in the
destination and put result in the destination.
 The SBB, instruction also subtracts the status of carry flag from the result.
 The source may be an immediate number, a register, or a memory location.
 The destination may be a register or a memory location.
 The source and the destination both cannot be memory locations.
 The source and destination both must be word or byte.
 If you want to subtract a byte from a word, you must copy the byte to a
word location and fill the upper byte of the word with zeroes before
subtracting.
Flags affected: AF, CF, OF, PF, SF, and ZF.
Example:
SUB AL, 0F0H ; Subtract immediate number 0F0H from contents of AL
store result in AL.
SBB DL, CL ; Subtract contents of CL and status of carry flag from the
contents of DL and store result in DL. i.e. DL-CL-CY
SBB DX, BX ; Subtract contents of BX and status of carry flag from
the DX and store result in DX. i.e. DX-BX-CY
SUB CL, TOTAL [BX] ; Subtract byte from effective address TOTAL [BX] from the
contents of CL and store result in CL
SUB CX, TOTAL [BX] ; Subtract word from effective address TOTAL [BX] from the
contents of CX and store result in CX.
c) DEC instruction:
Format: DEC Decrement destination.
 The DEC instruction subtracts 1 from the specified destination.
 The destination may be a register or a memory location.
Flags affected: AP, OF, PF, SF and ZF
Example:
DEC AL ; Subtracts 1 from the contents
of AL DEC BX ; Subtracts 1 from the contents
of BX.
d) NEG Instruction: Form 2’s complement.
 This instruction replaces the number in a destination with the 2’s
complement of that number. The destination can be a register or a memory
location.
 This Instruction can be implemented by inverting each bit and adding I to it.
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 The negate instruction updates the AF,Microcontroller
College CF, SF, PF, ZF and OF flags.

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Example:
; AL = 0011 0101 35H
NEC AL ; Replace number in AL with its 2’s complement
; AL = 1100 1011 = CBH
3) Comparison:
 The comparison instruction (CMI’) compares a byte/word from the specified
source with a byte/word from the specified destination.
 The source and destination both must be byte or word. The source
may be an immediate number, a register, or a memory Location.
 The destination may be a register or a memory location.
 The comparison is done by subtracting the source byte or word from the
destination byte or word. But the result is not stored in the destination.
 Source and destination remain unchanged, only flags are
updated. Flags: The AF, OF, SF, ZF, PF and CF are updated by the
CMP instruction. Example:
CMP BL, 01H ; Compare immediate number 01H with
byte in BL CMP CX, BX ; Compare word in BX with word in
CX.
CMP CX, TOTAL ; Compare word at displacement TOTAL in DS with word in CX.
The result of comparison is checked by conditional jump, conditional call and
conditional return instructions.
1.4.2.3 Multiplication
This group of instructions consists of following group of instructions.
a) MUL: Unsigned multiplication
b) IMUL: Signed multiplication
a) MUL Instruction:
Format: MUL source
 This instruction multiplies an unsigned byte from source and unsigned
byte in AL register or unsigned word from source and unsigned word in AX
register.
 The source can be a register or a memory location.
 When the byte is multiplied by the contents of AL, the result is stored in AX.
 The most significant byte is stored in AH and least significant byte is stored in
AL
Flags: MUL instruction affects AF, PF, SF, and ZF flags.
Example:
MUL BL ; ALx BL, result in AX.
MUT BX ; AX x BX, result high word in DX low word
in AX. MUL WORD PTR [BX] ; AX time’s word in DS pointed by
[BX]
; Result high word in DX Low word in AX.
b) IMUL Instruction:
 This instruction multiplies a signed byte from some source and a signed
byte in AL, or a signed word from some source and a signed word in AX.
 The source can be register or memory location.
 When a signed byte is multiplied by AL a signed result will be put in AX.
 When a signed word is multiplied by AX, the high-order word of the signed
result is put in DX and the low-order word of the signed result is put in AX.
Flags: MUL instruction affects AP, PF, and SF.
Example:
IMULBL ; AL x BL. Result in AX
IMULCX ; AX x CX, high-order word of result in DX and low-order word of result in
AX
1.4.2.4 Division
This group of instructions consists of following group of instructions
a) DIV Instruction:
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Format: Microcontroller
 This instruction is used to divide an unsigned word by a byte or to divide an
unsigned double word by a word.
 When dividing a word by a byte, the word must be in AX register.

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 After the division AL will contain an 8-bit quotient and AH will contain an 8-bit
remainder.
 For DIV instruction source may be a register or memory location.
Flags: All flags are undefined after a DIV instruction.
Example:
DIV CL ; Word in AX/byte in CL, Quotient in AL, remainder in AH.
DIV CX ; Double word in DX and AX/word in CX, Quotient in AX, remainder in DX.
b) IDIV Instruction:
Format: IDIV source.
 This instruction is used to divide a signed word by a signed byte or to divide
assigned double word (32-bits) by a signed word.
 Rest all is similar to DIV instruction.
1.4.3 BCD AND ASCII ARITHMETIC
The 8086 allows arithmetic manipulation of both BCD (Binary coded decimal)
and ASCII (American Standard Code for Information Interchange) data.
1.4.3.1 BCD Arithmetic
 The 8086 provides two instructions to support BCD arithmetic. They correct
result of a BCÐ addition and a BCD subtraction.
 The DAA (decimal adjust after addition) instruction follows BCD addition and
the DAS (decimal adjust after subtraction) follows BCD subtraction.
 Both instructions correct the result of the addition or subtraction so that
ills a BCD number.
DAA Instruction: Decimal Adjust Accumulator.
 This instruction is used to make sure the result of adding two packed BCD
numbers is adjusted to be a legal BCD number.Instruction works as follows:
 If the value of the low-order four bits (D3-D0) in the AL is greater than 9 or if
AF is set, the instruction adds 6 (06) to the low-order four bits.
 If the value of the high-order four bits( D7 - D4) in the AL is greater than 9 or
if carry flag is set, the instruction adds 6 (60) to the high-order four bits.
Example:
; AL = 0011 1001 = 39 BCD
; CL = 0001 0010 = 12 BCD
Add AL, CL ; AL = 0100 1011 =
4BH
DAA ; add 0110 because 1011 > 9
; AL 0101 0001 51 BCD
DAS Instruction: Decimal Adjust After Subtraction.
This instruction is used after subtracting two packed BCD numbers to make
sure the result is correct packed BCD.Instruction works as follows:
 If the value of the low-order four bits (D3-D0) in the AL is greater than 9 or if
AF is set; the instruction subtracts 6 (06) from the low-order four bits.
 If the value of the high-order four bits (D7-D4) in the AL is greater than 9 or if
carry flag is set, the instruction subtracts 6 (60) from the high-order four
bits.
Example:
; AL = 0011 0010 = 32 BCD
; CL = 0001 0111 = 17 BCD
SUB AL, CL ; AL 0001 1011 IBH
; Subtract 0110 Because 1011 > 9
; AL 0001 0101 = 15 BCD
 The DAS instruction updates the AF, CF, PF, and ZF.
 The 0F flag is undefined after DAS instruction.
1.4.3.2 ASCII Arithmetic
ASCII numbers range in value from 30H to 39H for the numbers 0-9.
The 8086provides four instructions for ASCII arithmetic.
1) AAA: ASCII adjust after addition

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2) AAS: ASCII adjust after subtraction
College Microcontroller
3) AAM: ASCII adjust after multiplication

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4) AAD: ASCII adjust before division
1) AAA Instruction: ASCII Adjust for Addition.
 The numbers from 0-9 are represented as 30H-39H in ASCII code.
 When you want to add two decimal digits which are represented in ASCII
code, it is necessary to mask upper nibble (3) from the code before addition.
 The 8086 allows you to add the ASCII codes for two decimal digits without
masking off the “3” in the upper nibble of each digit.
 The AAA instruction can be used after addition to get the current result in
unpacked BCD form.
Example:
;AL =0011 0100ASCII8
;CL =0011 1000 ASCII4
ADD AL, CL ;AL =0110 1100
; 6CH = Incorrect temporary result
AAA ; AL 0000 0010 Unpacked BCD for 2.
; carry =1 to indicate correct answer is 12 decimal.
The AAA instruction updates the AF and the CF, but the OF, PF, SF, and ZF are left
undefined.
2) AAS Instruction: ASCII Adjust after subtraction.
 The numbers from 0-9 are represented as 30-39 in ASCII code.
 When you want to subtract two decimal digits which are represented in ASCII
code, it is necessary to mask upper nibble (3) from the code before
subtraction.
 The 8086 allows you to subtract the ASCII codes for two decimal digits
without masking off the ‘3 in the upper nibble of each digit.
 The AAS instruction can be used after subtraction to get the current result in
unpacked BCD form.
Example:
; AL=0011 1000ASCÍI8
; CL = 0011 0010
ASCII 2 SUB AL, CL ;
AL=000001101BCD06
; CF = 0
AAS ;AL=00000010=BCD06
; CF = O no borrow required
3) AAM Instruction: ASCII Adjust After Multiplication.
After the two unpacked BCD digits are multiplied, the AAM instruction is used
to adjust the product to two unpacked BCD digits in AX.
Example:
; AL = 0000 0100 = Unpacked BCÐ 4
; CL=00000110= UnpackedBCD6
MULCL ; AL xCL Result in AX.
; AX = 0000 0000 0001 1000 = 0018H
AAM ; AX = 0000 0010 0000 0100=
0204H
; Which is unpacked BCD for 24.
Now by adding 3030H in AX register we get the result in ASCII form.
4) AAD Instruction: ASCII Adjust Before Division.
 AAD converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL.
 This adjustment must be made before dividing the two unpacked BCD
digits in AX by and packed BCD byte.
 After the division AL will contain the unpacked BCD quotient and AL will
contain the unpacked BCD remainder.
 The PF, SF and ZF are updated. The AF, CF and DF are undefined alter AAD.
Example:
; AX = 0403 unpacked BCD for 43 decimal, CL = 07H
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AADCollege ; Adjust to binary before division,
Microcontroller
; AX = 002BH = 2BH = 43 decimal.
DIV CL ; Divide AX by unpacked BCD in CL

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; AL = quotient = 06 unpacked BCD
; AH = remainder 01 unpacked BCD
Now by adding 3030H in AX register we get the quotient and remainder in
ASCII form.
1.4.4 BASIC LOGIC INSTRUCTIONS
 The basic logic instructions include AND, OR, Exclusive-OR, and NOT.
 This group also includes TEST instruction which is a special form of the AND
instruction.
1.4.4.1 AND Instruction:
Format: AND destination, source.
 AND operation with two inputs produces result logic 1 only when both
the inputs are logic 1.i.e. Y = A B.
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Table 1.5 Truth Table for AND gate
 This instruction logically ANDs each bit of the source byte or word
with the corresponding bit in the destination and stores result in the
destination.
 The source may be an immediate number, a register or a memory location.
 The destination may be a register or a memory location.
 The source and destination both cannot be memory locations in the same
instruction.
 The CF and OF are both 0 after AND. The PF, SF and ZF are affected.
 AF is undefined.
Example:
; AL=10010011=93H
; BL = 0111 0101 = 7511
AND BL,AL ;AND byte in AL with byte in BL
; BL = 0001 0001 = 11H
; CX = 0110 1011 1001 1110
AND CX, 00F0H ; CX = 0000 0000 1001 0000
 The AND operation clears bits of a binary number. The task of clearing a bit
in a binary number is called masking.

Fig: 1.12 Masking Using AND Operation


1.4.4.2 OR Instruction:
Format: OR destination, source.
OR operation with two inputs produces result logic 1 when any one or both inputs
arc logic 1. i.e., Y = A + B.
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Table 1.6 Truth Table for OR gate
 This instruction logically ORs each bit of the source byte or word with the

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Microcontroller
 The source may be an immediate number, a register or a memory location.
 The destination may be a register or a memory location.

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 The source and destination both cannot be memory locations in the same
instruction.
 The CF and OF are both 0 after OR.
 The PF, SF and ZF are affected. AF is undefined.
Example:
1. ; AL = 1001 0011 =
93H
; BL = 0111 0101 = 75K
OR BL, AL ; OR byte in AL with byte in BL.
. ;BL=1111O111=F7H
2. ; CX = 0110 1011 1001 1110
OR CX, 00F0H ; CX 0110 1011 1111 1110
The OR instruction is used to set (make one) any bit in the binary number.

Fig: 1.13 Masking Using AND Operation


1.4.4.3 XOR Instruction:
Format: XOR destination, source.
XOR operation produces result logic 1 when odd number of inputs are logic 1 i.e. Y=Aa
+aA
A a Y
0 0 0
0 1 1
1 0 1
1 1 0
Table 1.7 Truth Table for XOR gate
 This instruction logically XORs each bit of the source byte or word
with the corresponding bit in the destination and stores result in the
destination.
 The source may be an immediate number, a register or a memory location.
 The destination may be a register or a memory location.
 The source and destination both cannot be memory locations in the same
instruction.
 The CF and OF are both 0 after XOR. The PF, SF and ZF are affected.
 AF is undefined.
Example:
1. ; AL = 1010 1111 =
AFH
; BL = 1111 0000 = F0H
XOR BL, AL ; XOR byte in AL with byte in BL
; BL = 0101 1111 = 5FH
 The XOR instruction is used if some bits of a register or memory
location must be inverted.
 This instruction allows part of a number to be inverted or complemented.

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AND Operation
1.4.4.4 NOT Instruction:
Format: NOT
destination.
 The NOT instruction inverts each bit of a byte or a word.
 The destination can be register or a memory location.

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Flags: NOT instruction affects no flag.
Example:
; AL = 0110 1100
NOTAL ; AL= 10010011
; CX=1010 1111 0010 0110
NOT CX ; CX = 0101 0000
11011001
1.4.4.5 Test and bit test instructions:
 The TEST instruction performs the AND operation.
 The difference is that the AND instruction changes the destination operand,
while the TEST instruction does not A TEST only affects the condition of the
flag register, which indicates the result of the test.
 PF, SF and ZF will be updated to show the results of the ANDing.
 PF has meaning only for the lower 8 bits of the destination. AF will be undefined.
Example:
TEST AL, CL ; AND CL with AL
; Update flags, result is not stored.
TEST BX, CX ; AND CX with BX Update flags result is not stored.

Fig: 1.15 Test Operation


1.4.5 SHIFT AND ROTATE
1.4.5.1 Shift:
 Shift instructions position or move binary data to the left or right by shifting
them within the register or memory location.
 The shift operations can be classified as logical shifts and arithmetic shifts.
 The logical shifts move a 0 into the rightmost bit position for a logical left shift
(SHL).
 A 0 into the leftmost bit position for a logical right shift (SHR).
 The arithmetic left shift (SAL) and logical left shift operations are identical.

Fig: 1.16 Shift Operations


SAL/SHL Instruction:
Format: SAL/SHL destination, count.
 SAL and SHL arc two mnemonics for the same instruction.
 This instruction shifts each bit in the specified destination to the left and 0
is stored at LSB position.
 The MSB is shifted into the carry flag.
 The destination can be a byte or a word. It can be in a register or in a
memory location. Diagram 1.17 shows SAL instruction for byte operation.
Flags: All flags are affected.
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Fig: 1.17 SAL/SHL Instruction


Example:
SAL CX, 1 ; Shift word in CX 1 bit position left, O
in LSB MOV CL, 05H ; Load desired number of shifts in CL
SAL AX, CL ; Shift word in AX left 5 times
; 0s in 5 least-significant bits.
SHR Instruction:
Format: SHR destination, count.
 This instruction shifts each bit in the specified destination to the right and 0
is stored at MSB position.
 The 158 is shifted into the carry flag.
 The destination can be a byte or a word. It can be in a register or in a
memory location. Diagram 1.18 shows SHR instruction for byte operation.
Flags: All flags are affected.

Fig: 1.18 SHR Instruction


Example:
SHR CX, 1 ; Shift word in CX I bit position right, 0 in
MSB. MOV CL, 05H ; Load desired number of shifts in CL.
SHR AX, CL ; Shift word in AX right 5 times
; 0’s in 5 most significant bits.
SAR Instruction:
Format: SAR destination, count.
 This instruction shifts each bit in the specified destination some number of bit
positions to the right.
 As a bit is shifted out of the MSB position, a copy of the old MSB is put in
the MSB position.
 The LSB will be shifted into CF.
 The destination can be a byte or a word.
 It can be in a register or in a memory location. The number of shifts is
indicated by count Diagram 1.19 shows SAR instruction for byte operation.
Flags: All flags are affected.

Fig: 1.19 SHR Instructions


Example:
SAR BL, 1 ; Shift byte in BL one bit position
right. MOV CL, 04H ; Load desired number of shifts
in CL
SAR DX, CL ; Shift word stored in DX 4 bit positions right.
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1.4.5.2 Rotate
 Rotate instructions position or move binary data by rotating the information
in a register or memory location, either from one end to another or through
the carry flag.
 This is illustrated in the following figure 1.20

Fig: 1.20 Rotate Operations


ROL Instruction:
Format: ROL destination, count.
 This instruction rotates all bits in a specified byte or word to the left some
number of bit positions.
 MSB is placed as a new LSB and a new CF.
Diagram 1.21 shows ROL instruction for byte
rotation.

Fig: 1.21 ROL Instruction


 The destination can be a byte or a word.
 It can be in a register or in a memory location;
 The numbers of shifts are indicated by count.
Example:
ROL CX, 1 ; Word in CX one bit position left, MSB to LSB
and CF MOV CL 03H ; Load desired number of bits to rotate in
CL.
ROL BL. CL ; Rotate BL three positions.
ROR Instruction:
Format: ROR destination, count.
 This instruction rotates all bits in a specified byte or word to the right some
number of bit positions.
 LSB is placed as a new MSB and a new CF.
 The destinations can be a byte or a word.
It can be in a register or in a memory location. The number of shifts arc indicated
by count.
Diagram 1.22 shows ROR instruction for byte rotation.

Fig: 1.22 ROR Instruction


Example:
ROR CX, 1 ; Rotated word in CX one bit position right,
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MOV CL, 03H ; Load number of bits to rotate
in CL ROR BL, CL ; Rotate BL three positions.

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RCL Instruction:
Format: RCL destination, count.
 This instruction rotates all of the bits in a specified word or byte some
number of bit positions to the left along with the carry flag.
 MSB is placed as a new carry and previous carry is placed as a new LSB.
 The destination can be a byte or a word.
 It can be in a register or in a memory location.
 The numbers of shifts are indicated by
count. Diagram shows 1.23 RCL instructions for
byte rotation.

Fig: 1.23 RCL Instruction


RCR Instruction:
Format: RCR destination, count.
 This instruction rotates all of the bits in a specified word or byte some
number of bit Positions to the right along with the carry flag.
 LSB is placed as a new carry and previous carry is placed as a new MSB.
 The destination can be a byte or a word.
 It can be in a register or in a memory location.
 The numbers of shifts are indicated by
count. Diagram 1.24 shows RCR instruction for
byte rotation.

Fig: 1.24 RCR Instruction


Example:
RCR CX, 1 ; Word in CX 1 bit right, LSB to CF, CF to
MSB. MOV CL, 04H ; Load number of bit positions to rotate in
CL. RCR AL, CL ; Rotate AL 4 bits right
1.4.6 STRING COMPARE INSTRUCTIONS
The string comparison instructions allow the programmer to test a section of
memory against a constant or against another section of memory.
The 8086 provides two instructions for string comparisons:
1) CMPS (compare string)
2) SCAS (string scan).
1.4.6.1 CMPS / CMPSB / CMPSW Instruction:
 A string is a series of the same type of data items in sequential memory
locations.
 The CMI’S instruction can be used to compare a byte in one string with a byte in
another
 String or to compare a word in one string with a word in another string.
 SI is used to hold the offset of a byte or word in the source string
 Dl is used to hold the offset of a byte or a word in the other string.
 The comparison is done by subtracting the byte or word pointed to by DI from
the byte or word pointed to by SI.
 The AF, CF, OF, E’F, SF, and ZF flags are affected by the comparison.
Example:
MOV SI, OFFSET F_STRING ; Point SI at source string,
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MOV DI, OFFSET S_STRING
College ; Point Dl at Microcontroller
destination
string CLD ; DF cleared so SI and DI
will
; auto increment after compare

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CMPS F_STRING, S_STRING ; The assembler uses names to determine whether
; strings were declared as type byte or as type, word.
MOV CX, 100 ; Put number of siring elements
in CX, MOV SI. OFFSET F_STRING ; Point SI at source of string
MOV Dl, OFFSET S_STRING ; Point DI at destination of string
STD ; DF set so SI and DI will auto decrement
after
; compare
REPE CMPSB ; Repeat the comparison of string bytes until
end
; of string or until compared bytes arc not equal.
1.4.6.2 SCAS / SCASB / SCASW Instruction:
 SCAS compares a string byte with a byte in AL or a string word with word in AX.
 The instruction affects the flags, but it does not change either the operand in
AL (AX) or the operand in the string.
 The string to be scanned must be in the extra segment and DI must contain
the offset of the byte or the word to be compared.
 SCAS affects the AF, CF, OF, PF, SF and ZF flags.
Example:
; Scan a text string of 80 characters
; for a carriage return
MOV AL, 0DH ; Byte to be scanned for
into AL MOV DI, OFFSET TEXT_STRING ;Offset of string
to Dl
MOV CX, 80 ; CX used as clement counter
CLD ; Clear DF, so DI auto increments
REPNE SCAS TEXT_STRING ; Compare byte in string with byte
in AL.
SCASB says compare strings as bytes and SCASW says compare strings as words.
1.4.7 Program Control Instruction:
 The 8086 to Fetch is next instruction from the location specified or
indicated by instruction rather than from the next location after the JMP
instruction.
 The JMP instructions arc basically classified as
1) Unconditional Jump (JMP)
2) Conditional jump instructions.
 A conditional jump instruction allows the programmer to make decisions
based upon numerical tests.
 The results of numerical tests are held in the flag bits, which are then
tested by conditional jump instructions.
 The jump instructions are further classified as
1) Short jump instructions,
2) Near jump instructions
3) Far jump instructions.
 A short jump is a two-byte instruction that allows jumps or branches to
memory locations within +127 and - 128 bytes from the address following
the jump.
 A three byte near jump allows a branch or jump within ± 32k bytes (from the
instruction in the current code segment.
 A five byte far jump allows a jump to any memory location within the real
memory system.
 The short and near jump are often called intra segment jumps and the far
jumps are often called intersegment jumps.
 The short jumps are also called relative jumps because in such
instructions the destination location is specified relative to the current
location.

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for short, near and far jumps
instructions.

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Fig: 1.25 Instruction formats for short, near and far jumps instructions
 Near and far jumps are further described as
1) Direct
2) Indirect.
 If the destination address for the jump is specified directly within the
instruction, then the jump is described as direct.
 If the destination address for the jump is contained in a register or memory
location, the jump is referred us indirect.
Example: (Unconditional jump)
JMP NEXT ; Fetch next instruction from address at label NEXT.
J Cond - Conditional Jump:
 Conditional jumps are always short jumps in the 8086.
 These instructions will cause a jump to a label given in the instruction if
the desired condition(s) occurs in the program before the execution of the
instruction.
 The destination must be in the range of -128 bytes to +127 bytes from the
address of the instruction after the conditional transfer instruction.
 1f the Jump is not taken execution simply goes on to the next instruction.

Fig: 1.26 Jump Instructions


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1.4.8. ITERATION CONTROL INSTRUCTIONS:
 These instructions are used to execute a series of instructions some number of
times.
 The number is specified in the CX register.
 The CX register is automatically decremented by one, each time after
execution of LOOP instruction.
 Until CX = 0, execution will jump to a destination specified by a label in the
instruction.
 The destination address for the jump must be in the range of -128 bytes to
+127 bytes.
Instruction code Description Condition for
exit
1. LOOP Loop through a sequence CX = 0
of instructions
2. LOOPE / LOOPZ Loop through a sequence CX =0 or ZF=0
of instructions
3. LOOPNE/ LOOPNZ Loop through a sequence CX = 0 or ZF = 1
of instructions

Table 1.8 Iteration Control Instructions


1.4.9 MACHINE CONTROL AND MISCELLANEOUS INSTRUCTIONS
STC Instruction:
 This instruction sets the carry flag; STC does not affect any other flag.
CLC Instruction:
 This instruction resets the carry flag to Zero. CLC does not affect any other flag.
CMC Instruction:
 This instruction complements the carry flag. CMC does but affect any other flag.
STD Instruction:
 This instruction is used to set the direction flag to one.
 SI and/or DI can be decremented automatically after execution of string
instructions.
 STD does not affect any other flag.
CLD Instruction:
 This instruction is used to reset the direction flag to zero.
 SI and/or Dl can be incremented automatically after execution of string
instructions.
 CLD does not affect any other flag.
STI Instruction:
 This instruction sets the interrupt flag to one.
 This enables INTR interrupt of the 8086.
 STI does not affect any other flag.
CLI Instruction:
 This instruction resets the interrupt flag to zero.
 Due to this 8086 will not respond to an interrupt signal on its INTR input.
 CLI does not affect any other flag.
HLT Instruction:
 The HLT instruction will cause the 8086 to stop fetching and executing
instructions.
 The 8086 will enter a halt state.
WAIT Instruction:
 When this instruction executes, the 8086 enters an idle condition where it
is doing no processing.
 The 8086 will stay in this idle state until a signal is asserted on the 8086
TEST input pin, or until a valid interrupt signal is received on the INTR or the
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 WAIT affects no flags. The WAIT instruction is used to synchronize the
8086 with external hardware such as the 8087 math coprocessor.
ESC Instruction:
 This instruction is used to pass instructions to a coprocessor such as
the8087 math coprocessor

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 When the 8086 fetches an ESC instruction, the coprocessor decodes the
instruction
 The 8086 treats the ESC instruction as a NOP
LOCK Instruction:
 The LOCK prefix allows a microprocessor to make sure that another
processor does not take control of the system bus.
 The LOCK prefix is put in front of the critical instruction. When an
instruction with a LOCK prefix executes, the 8086 will assert its bus lock
signal output.
 This signal is connected to an external bus controller device which then
prevents any other processor from taking over the system bus. LOCK
affects no flags.
Example:
LOCK XCHG SEMAPHORE, AL ; The XCHG instruction requires two bus
accesses.
: The LOCK prefix prevents another
processor from taking control of the
system bus between the two accesses.
NOP Instruction:
 At the time of execution of NOP instruction, no operation is performed
except fetch and decode. It takes three clock cycles to execute the
instruction.
 NOP instruction does not affect any flag.
 This instruction is used to fill in time delays or to delete and insert
instructions in the program while trouble shooting.
CBW: Convert Signed Byte to Signed Word
 This instruction copies the sign of a byte in AL to all the bits in AH.
 CBW does not affect any flag.
Example:
; AX = 0000 0000 1001 1010
CBW ; convert signed byte in AL to signed word in AX
; Result: AX = 1111 11111001 1010
CWD: Convert Signed Word to Signed Double Word.
This instruction copies the sign bit of a word in AX to all the bits of the DX
register CWD does not affect any flag.
Example:
; DX =0000 0000 0000 0000
; AX = 1001 0000 1001 0001
CWD ; Convert signed word in AX to signed double word in DX : AX
; Result: DX = 1111 1111 1111 1111
AX = 1001 0000 1001 0001
1.4.10 INTERRUPT INSTRUCTIONS
INT Instruction:
Format: INT Type
 The term type in the instruction refers to a number between 0-255 which
identifies the interrupt.
 The address of the procedure is taken from the memory whose address is
four times the type number.
INTO Instruction:
 If the overflow flag is set, this instruction will cause an indirect far call to a
procedure
 The 8086 will read anew value for IP from address 000IOH and a new value
of CS from addresses 00012H.
IRET Instruction:
 The IRET instruction is used at the end of the interrupt service
routine to return execution to the interrupted program.
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 The 8086 copies return address from stack
College into IP and CS registers and the
Microcontroller
stored value of flags back to the flag register.

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1.5 ASSEMBLER DIRECTIVES
1.5.1 Assembler directives
 The Assembler directives enable to control the way in which a program
assembles and lists.
 They act during the assembly of a program and do not generate any
executable machine
 Code.
 There are many specialized assembler directives are,
ALIGN, ASSUME, .CODE, .DATA, DB, DW, DD, DQ, and DT, DUP
END, EQU, EVEN, EXTRN, GROUP, LABEL, LENGTH, MACRO and ENDM
NAME, .MODEL, OFFSET, ORG, PTR, PAGE, PROC and ENDP
PUBLIC, SHORT, .STACK, TITLE, TYPE
Assembler Directives:
1) ASSUME
2) DB - Defined Byte.
3) DD - Defined Double Word
4) DQ - Defined Quad Word
5) DT - Define Ten Bytes
6) DW - Define Word
1.5.1.1 ASSUME Directive
The ASSUME directive is used to tell the assembler that the name of the
logical segment should be used for a specified segment.
The 8086 works directly with only 4 physical segments:
 a Code segment,
 a data segment,
 a stack segment,
 an extra segment.
Example:
ASUME CS: CODE; CODE contains the Instruction statements for the program and should
be treated as a code segment.
ASUME DS: DATA; Any instruction which refers to a data in the data segment, data will
found in the logical segment DATA.
1.5.1.2 DB Directive:
DB directive is used to declare a byte type variable or to store a byte in memory location.
Example:
1. PRICE DB 49h, 98h, 29h ;Declare an array of 3 bytes, named as PRICE and initialize.
2. NAME DB ‘ABCDEF’; Declare an array of 6 bytes and initialize with ASCII code for
letters
3. TEMP DB 100 DUP (?); Set 100 bytes of storage in memory and give it the name as
TEMP
1.5.1.3 DW Directive
The DW directive is used to define a variable of type word or to reserve
storage location of type word in memory.
Example:
MULTIPLIER DW 437Ah; this declares a variable of type word and named it as
MULTIPLIER. This variable is initialized with the value 437Ah when it is loaded into
memory to run.
EXP1 DW 1234h, 3456h, 5678h; this declares an array of 3 words and initialized with
specified Values.
1.5.1.4 STOR1 DW 100 DUP(0) Directive;
Reserve an array of 100 words of memory and initialize all words with 0000. Array is
named as STOR1.
1.5.1.5 END Directive
END directive is placed after the last statement of a program to tell the assembler that
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1.5.1.6 ENDP Directive
ENDP directive is used along with the name of the procedure to indicate the end of
a procedure to the assembler.
Example:
SQUARE_NUM PROCE; It start the procedure; some steps to find the square root of a
number
SQUARE_NUM ENDP; Hear it is the End for the procedure.
1.5.1.7 END - End Program
1.5.1.8 ENDP - End Procedure
1.5.1.9 ENDS- End Segment
1.5.1.10 EQU - Equate
1.5.1.11 EVEN - Align on Even Memory Address
1.5.1.12 EXTRN
1.5.1.13 ENDS Directive
This ENDS directive is used with name of the segment to indicate the end of
that logic segment.
Example:
CODE SEGMENT; It Start the logic segment containing code some instructions
statements to perform the logical operation.
CODE ENDS; End of segment named as CODE
1.5.1.14 EQU Directive
 This EQU directive is used to give a name to some value or to a symbol.
 Each time the assembler finds the name in the program, it will replace the
name with the value or symbol you given to that name.
Example:
FACTOR EQU 03H; the starting of your program and later in the program can use this
ADD AL, FACTOR ; if FACTOR is used many no of times in a program and you want
to change the value, all you had to do is change the EQU statement at beginning, it
will changes the rest of all.
1.5.1.15 EVEN Directive
 This EVEN directive instructs the assembler to increment the location of the
counter to the next even address
 If the word is at even address 8086can read a memory in 1 bus cycle.
 If the word starts at an odd address, the 8086 will take 2 bus cycles to get the
data.
Example:
DATA1 SEGMENT; Location counter will point to 0009 after assembler reads
next statement
SALES DB 9 DUP(?) ;declare an array of 9 bytes
EVEN; increment location counter to 000AH
RECORD DW 100 DUP ( 0 ) ;Array of 100 words will start from an even address for
quicker read
DATA1 ENDS
1.5.1.16 GROUP - Group Related Segments
1.5.1.17 LABLE
1.5.7.18 NAME
1.5.7.19 OFFSET
1.5.1.20 ORG – Originate
1.5.1.21 GROUP Directive
The GROUP directive is used to group the logical segments named after the directive
into one logical group segment.
1.5.1.21 INCLUDE Directive
This INCLUDE directive is used to insert a block of source code from the named file
into the current source module.
1.5.1.22 PROC - Procedure
1.5.1.23 PTR - Pointer

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1.5.1.24
College PUBLC Microcontroller
1.5.1.25 SEGMENT

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1.5.1.26 SHORT
1.5.1.27 TYPE
1.2.1.28 PROC Directive
The PROC directive is used to identify the start of a procedure. The term near or far is
used to specify the type of the procedure.
Example:
SMART PROC FAR; this identifies that the start of a procedure named as SMART
and Instructs the assembler that the procedure is far
SMART ENDP This PROC is used with ENDP to indicate the break of the procedure.
1.5.1.29 PTR Directive
This PTR operator is used to assign a specific type of a variable or to a label.
Example:
INC [BX] ;This instruction will not know whether to increment the byte pointed to by BX
or a Word pointed to by BX.
INC BYTE PTR [BX] ;increment the byte pointed to by BX.
This PTR operator can also be used to override the declared type of
variable. If we want to access the a byte in an array WORDS DW
437Ah, 0B97h, MOV AL, BYTE PTR WORDS
1.5.1.30 PUBLIC Directive
The PUBLIC directive is used to instruct the assembler that a specified name or label will
be accessed from other modules.
Example:
PUBLIC DIVISOR, DIVIDEND; these two variables are public so these are available to all
modules. If an instruction in a module refers to a variable in another assembly
module, we can access that module by declaring as EXTRN directive.
1.5.1.31 TYPE Directive
TYPE operator instructs the assembler to determine the type of a variable and determines
the number of bytes specified to that variable.
Example:
Byte type variable – assembler will give a value 1
Word type variable – assembler will give a value 2
Double word type variable – assembler will give a value 4
ADD BX, TYPE WORD_ ARRAY; here we want to increment BX to point to next word
in an array of words.
1.5.1.32 MACROS:
 Macros are just like procedures, but not really. Macros Look like
procedures, but they exist only
 Until your code is compiled
 After compilation all macros are replaced with real instructions.
 If you declared a macro and never used it in your code, compiler will imply
ignore it.
Example:
Macro definition:
name MACRO [parameters,...]
<instructions>
ENDM
Unlike procedures, macros should be defined above the code that uses it, for example:
MyMacro MACRO p1, p2,
p3
MOV AX, p1
MOV BX, p2
MOV CX, p3
ENDM
ORG 100h
MyMacro 1, 2, 3
MyMacro 4, 5, DX

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The above code is expanded
into: MOV AX, 00001h
MOV =X,
00002h MOV
CX, 00003h
MOV AX,
00004h MOV
BX, =0005h
MOV CX, DX
Summary Of Assembler Directives:

Fig: 1.27 Summary of Assembler Directives

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1.6 Assembly language programming
There are three language levels that can be used to write a program
1. Machine level language
2. Assembly level language
3. High level language programs
1.6.1 Machine Level Language Programs
A program which has simply a sequence of the binary codes for the instructions
is called machine level language program.
1.6.2 Assembly Language Programs:
 Programmers write programs in assembly language. They then translate the
assembly language program to machine language so that it can be loaded
into ‘memory and executed.
 Assembly language uses two, three or four letter words to represent each
instruction types these words are referred to as mnemonics.
 The letters in an assembly language mnemonic are usually initials or a
shortened form of the English word(s) for the operation performed by the
instruction.
 For example, the mnemonic for addition is ADD, the mnemonic for logic AND
operation is AND, and the mnemonic for the instruction for copy data from
one location to another is MOV.
1.6.3 Assembly Instruction Format:
 The assembly text is usually divided into fields, separated by spaces and tabs.
 A format for assembly language program can be given as
Label: Mnemonic Operand l, Operand 2; Comment
 The first held, which is optional, is the label field, used to specify symbolic
labels.
 A label is an identifier that is assigned to the address of the first byte of the
instruction in
 The second field is mnemonic, which is compulsory. All instructions must
contain a mnemonic.
 The third and following fields are operands. The operands depends on the
instruction.
 If there are two operands, they are separated by a comma.
 The last field is a comment field. It begins with a delimiter such as the
semicolon.

Fig: 1.28 Instruction Format


1.6.4 Comparison between various micro computer languages

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Fig: 1.29 Comparison between various micro computer languages

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1.6.5 Assembly process
Developing and execution steps of assembly language.

Fig: 1.30 Developing and execution steps of assembly language


 The first step in the development process is to write an assembly language
program.
 The assembly language program can be written with an ordinary text editor.
 The assembly language program text is an input to the assembler.
 The assembler translates assembly language statements to their binary
equivalents, usually known as object code.
Assemble Time:
 Time required translating assembly code to object code is called assembles
time.
 During assembling process assembler checks for syntax errors and
displays them before giving object code module,
Object code module:
 The object code module contains the information about where the program or
module to be loaded in memory.
 If the object code module is to be linked with other separately assembled
modules then it contains additional linkage information.
Link time:
 Assembled modules are combined into one single load module, by the linker.
 The linker also adds any required initialization or finalization code to allow the
operating system to start the program running and to return control to the
operating system after the program has completed.
1.6.5.1 ASSEMBLER
 Assembler translates a source file that was created using the editor into
machine language such as binary or object code.
 The assembler reads the source file of our program from the disk where
we saved it after editing.
 An assembler usually reads our source file more than once.
 The assembler generates two files on the floppy or hard during these two
passes.
1) The first file is called the object file. The object file contains the binary
codes for the instructions and information about the addresses of the
instructions.
2) The second file generated by the assembler is called assembler list file.
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language statements, the binary code
for each instruction, and the offset for each instruction.
 In the first pass, the assembler performs the following operations:

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1) Reading the source program instructions.
2) Creating a symbol table in which all symbols used in the program,
together with their attributes, are stored.
3) Replacing all mnemonic codes by their binary codes.
4) Detecting any syntax errors in the source program.
5) Assigning relative addresses to instructions and data.
 On a second pass through the source program, the assembler extracts the
symbol from the operand field and searches for it in the symbol table.
 If the symbol does not appear in the table, the corresponding statement is
obviously erroneous. If the symbol does appear in the table, the symbol is
replaced by its address or value.
 We can use a suitable Editor to type .asm file. We can convert object file from
.asm file using popular assemblers MASM (Microsoft macro assembler) or
TASM (Turbo assembler).
 The command on command prompt performing this operation is as given below
C:\ MASM\ BIN\> MASM myprog.asm
 Where myprog.asm is name of the .asm file which is to be converted to .obj file.
1.6.5.2 LINKER
 A linker is a program used to join together several object files into one large
object file.
 When writing large programs, it is usually much more efficient to divide
the large program into smaller modules.
 Each module can be individually written, tested and debugged.
 When all the modules work, they can be linked together to form a large
functioning program.
 The command on command prompt for converting .obj file to .EXE files as
given below: C: \ MASM BIN \ > LINK myprog.obj;
1.6.6 Translation of assembler instructions:
 The instructions of 8086 vary from 1 to 6 bytes in length.
 The figure 1.31 shows the instruction formats for 1 to 6 bytes instruction format
 The first field is the operation code field, commonly known as opcode field.
 Opcode field indicates the type of operation lo be performed by the processor.
 The other field in the instruction format is operand field.
 The operand field may consists of source/destination operand, source
operand address, destination operand address or next instruction address,
 The operand (displacement) may be either 8-bit or 16-bit long depend on
the instruction and its addressing mode.
The opcode/addressing mode byte(s) may be followed by:
1) No additional byte
2) Two byte EA (For direct addressing only).
3) One or two byte displacement
4) One or two byte immediate operand
5) One or two byte displacement followed by a one or two byte
immediate operand 8066 has special 1-bit indicators. They are:
W-bit:
 W-bit in the opcode of such instruction specify whether instruction is a byte
instruction(W
= 0) or a word instruction (W = I).
D-bit:
 The D-bit in the opcode of the instruction indicates that the register specified
within the instruction is a source register (D = 0) or destination register (D
=1).
S-bit:
 An 8-bit 2s complement number can be extended to a 16-bit 2’s complement
number
 All of the bits in the higher-order byte equal the most significant bit in the low
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 This is known as sign extension. The S-bit along with the W-bit indicate:

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Fig: 1.31 Operations of S and W


V- bit:
 V-bit decides the number of shifts for rotate and shift instructions. if V =
0,then count =1; if V=1, the count is in CL register.
 For example, if V = I and CL =2then shift or rotate instruction shifts or rotates 2-

bits.
Fig: 1.32 Addressing Modes
Z-bit:
 It is used for string primitives such as REP for comparison with ZF Flag.
 1f it is 1, the instruction with REP prefix is executed until the zero flag
matches the Z-hit.

Fig: 1.33 Two Opcode Addressing Modes


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Where Mod, Reg and R/M fields specify operand as described in the following tables.

Fig: 1.34 Mod Field Assignment

Fig: 1.35 REG Field Assignment

Fig: 1.36 R/M Field Assignment


1.6.7 Assembly Language Programming Guidelines:
a) What is an optimum solution? :
 Takes minimum memory space for the program and minimum time for the
execution of a task.
 Consider space for program storage (program length), space for data storage
and space used by the stack.
b) Use of proper instructions:
 More than one set of instructions are available to perform particular function.
 For example, if the function is add 01 in the BX register of 8086 we have two

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ADD BX, 0001H or INC BX.
 Check the space and time for both the options and then select the option
which requires less space and time.
 The instruction ADD BX, 000IH is 4 byte Instruction and requires 4 clock cycles
execute.
 The INC BX is a single byte instruction and requires 2 cycles for the execution.
c) Use of advanced instructions:
 Write a program to move a block of data from the source to destination location
 a programmer may initialize a pointer to indicate source location, a
pointer to indicate destination location
 After transfer of one data element from source to destination location
programmer may use INC. DEC and JNZ instructions to increment source
and destination pointers, decrement counter and to check whether all data
elements are transferred or not, respectively.
The part listing of the program with both the approaches and then we compare them.
1. Part listing of program with general approach
MOV SI, 1000H : Initialize source pointer
MOV DI, 2000 H ; Initialize destination
pointer MOV CX, 0020 H ; Initialize
counter
BACK: MOV AX, [SI] ; Get data element from
source MOV [DI], AX : Store it at destination
INC SI ; Increment source pointer
INC DI ; Increment destination pointer
DEC CX ; Decrement counter
JNZ BACK ; if count is not zero repeats
Use of proper addressing modes:
 Easily make out that the register addressing takes less time to access
operand than the index and indirect addressing modes.
 It is obvious that when operands are available in CPU registers they are
immediately available for Operation.
 Fetching operands takes more time.
 Store most of the operands in the CPU registers.
 CPU registers are limited in numbers.
Prepare documentation:
1. Description of the purpose of the program module.
2. In case of subroutine program list of passing parameters and return value.
3. Register and memory locations used.
4. Proper comments for each instruction used.

1.7 MODULAR PROGRAMMING


 Programming tasks is divided into subtasks, separate modules are written for
performing subtasks.
 Each module is tested separately.
 The common routines required in modules are written in separate module
and they are called from individual modules.
 Programming done in this fashion is called modular programming
Advantages of modular programming:
 Code is short, simple and easy to understand
 To make development is faster.
 It is easier to design, test, and debug a single module as compared to
an entire program.
 The scoping of variables can easily be controlled
 Documentation can be easily understood
 Retype the codes frequently modules are stored into the libraries and used
by several programs
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 It is easy to do modifications if any in aMicrocontroller
College single module rather than in a program

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The assembly languages components are classified into 4 types
1) Linking and Relocation.
2) Structures
3) Procedures or subroutines
4) Macros

1.8 LINKING AND RELOCATION


 The DOS linking program links the different object modules of a source
program and Function library routines.
 To generate an integrated executable code of the source program.
 The main input to the linker is the .OBJ file that contains the object
modules of the source programs.
 Other supporting information may be obtained from the files generated by the

MASM.
Fig: 1.37 Steps in program development and execution
 The linker program is invoked using the following options.
C> LINK
Or
C>LINK MS.OBJ
 The .OBJ extension is a must for a file to be accepted by the LINK as a valid
object file.
 The first object may generate a display asking for the object file, list file and
libraries as inputs and an expected name of the .EXE file to be generated.
 The output of the link program is an executable file with the entered filename
and .EXE extension.
 This executable filename can further be entered at the DOS prompt to execute
the file.
 In the advanced version of the MASM, the complete procedure of assembling
and linking is combined under a single menu invokable compile function.
 A linker links the machine codes with the other required assembled codes.
 The linked file in binary for run on a computer is commonly known as
executable file or simply ‘.exe.’ file.
 The DOS linking program links the different object modules of a source
program and function library routines to generate an integrated executable
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 The main input to the linker is the .OBJ file that contains the object
modules of the source programs.
 The linked file in binary for run on a computer is commonly known as
executable file or simply ‘.exe.’ file.
 After linking, there has to be re-allocation of the sequences of placing the
codes before actually placement of the codes in the memory.
 The loader program performs the task of reallocating the codes after finding
the physical RAM addresses available at a given instant.
 The loader is a part of the operating system and places codes into the
memory after reading the ‘.exe’ file.
 Memory addresses may not start from 0x0000, and binary codes have to
be loaded at the different addresses during the run.
 The loader is used and it loads into a section of RAM the program
 A program called locator reallocates the linked file and creates a file for
permanent location of codes in a standard format.
1.8.1 Segment combination
 The assembler provides a means of regulating the way segments in
different object modules are organized by the linker.
 Segments with same name are joined together by using the modifiers
attached to the SEGMENT directives.
 SEGMENT directive may have the form
Segment name SEGMENT Combination-type
 Where the combine-type indicates how the segment is to be located
within the load module.
 Segments that have different names cannot be combined and segments with
the same name but no combine-type will cause a linker error.
 The possible combine-types are:
PUBLIC
 If the segments in different modules have the same name and combine-type
PUBLIC.
 Then they are concatenated into a single element in the load module.
COMMON
 If the segments in different object modules have the same name and the
Combine-type is COMMON.
STACK
 If segments in different object modules have the same name and the
combine type STACK.
 One segment whose length is the sum of the lengths of the individually
specified segments.
AT
 The AT combine-type is followed by an expression that evaluates to a
constant which is to be the segment address.
 It allows the user to specify the exact location of the segment in memory.
MEMORY
 The segment to be placed at the last of the load module. If more than one
segment with the MEMORY combine-type is being linked.
 The below figure shows the combined type of PUBLIC and COMMON .the use
of PUBLIC eliminates the need to change the contents of the CS register as
the program passes between sets of instruction within the code segment.
 Data segments can be given the PUBLIC combine type to cause the several
set of data to be combined into one larger set.
 The COMMON combine type creates a pool of locations.
 STACK provides a one stack that can be shared by several modules.

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Fig: 1.38 Generated Load Modules

Fig: 1.39 Source Modules 1 and 2


1.8.2 Access to External Identifiers
 If an identifier is defined in an object module, then it is said to be a local (or
internal)
Identifier relative to the module.
 If it is not defined in the module but is defined in one of the other modules
being linked, then it is referred to as an external (or global) identifier relative to
the module.
 Each module in multi-module programs may contain two lists, one
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can be referred to by other modules.

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 Two lists are implemented by the EXTRN and PUBLIC directives, which have the
forms:
EXTRN Identifier: Type…, Identifier: Type
and
PUBLIC Identifier… Identifier
 Where the identifiers are the variables and labels
 External identifiers before it can generate the proper machine code.
 Specified must be associated with each identifier in an EXTRN statement.
 For a variable the type may be BYTE, WORD, or DWORD and
 For a label it may be NEAR or FAR.

1.9 STACKS
The information is written on the stack, the operation is called PUSH. The
information is read from the stack, the operation is called POP.
1.9.1 Stack Structure of 8086/88
 The 8086/88 has a special 16-bit register, SP to work as a stack pointer.
 The stack pointer (SP) register contains the 16-bit offset from the start of the
segment to the top of stack.
 Physical address is produced by adding the contents of stack pointer
register to the segment base address in SS.
 The contents of the stack segment register are shifted four bits left and the
contents of SP are added to the shifted result.
 If the contents of SP are 9F20H and SS are 4000Hthen the physical
address. SS = 4000H after shifting four bits left SS = 40000H
Now
SS 40000H
+ SP 9F20H

Physical address

49F20H End of stack


segment 4FFFFH
1.9.2 PUSH and POP Operations
 Stores the present contents of the registers in the stack with the help
of PUSH instruction.
 Loads the previous contents of the register from the stack with the
help of POP instruction.
PUSH Operation:
 The PUSH instruction decrements stack pointer by two and copies a word
from some source to the location in the stack where the stack pointer points.
 The source must be a word (16 bit).
 The source of the word can be a general purpose register, a segment
register or memory.
POP Operation:
 The POP instruction copies a word from the stack location pointed by the
stack pointer to the destination.
 The destination can be a general purpose register, a segment register, or
a memory location.
 After the word is copied to the specified destination, the stack pointer is
automatically incremented by 2.
1.9.3 CALL Operation
 The CALL instruction is used to transfer execution to a subprogram or
procedure.
 There are two basic types of CALLS,
1) Near
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 A near CALL is a call to a procedure which is in the same code
segment as the CALL instruction.

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 A far CALL is a call to a procedure which is in a different segment
from that which contains the CALL instruction.
1.9.4 RET Operation
The RET instruction will return execution from a procedure to the next instruction after
the CALL instruction in the calling program.
 If the procedure is a near procedure the return will be done by replacing
the instruction pointer with a word from the top of the stack.
 If the procedure is a far procedure then the instruction pointer will be
replaced by the word at the top of the stack.
 The stack pointer will then be incremented by two.
1.9.5 Overflow and Underflow of Stack
 During PUSH operation stack pointer is decremented by two.
 Maximum length of stack segment is 64K.
 One time the contents of SP will be 0000H. Any further attempt to PUSI-l
data on the stack will result in stack overflow.
 On the other hand, at onetime the contents of SP will be FFFFH. Any further
attempt to POP data from the stack will result in stack underflow .

1.10 PROCEDURES
 The procedure is a group of instructions stored as a separate program in
the memory and it is called from the main program.
The type of procedure depends on where the procedure is stored in the
memory.
 Two types of procedures:
1) Near Procedure
2) Far procedure
 Near Procedure and Far Procedure:
 If it is in the same code segment where the main program is stored then it is
called near procedure otherwise it is referred to as far procedure.
 For near procedure CALL instruction pushes only the IP register contents on the
stack
 For far procedures CALL instruction pushes both IP and CS on the stack.
1.10.1 Reentrant Procedure.
 Procedure 1 is called from main program, procedure2 is called from
procedure1 and procedure 1 is again called from procedure2.
 Program execution flow reenters in the procedure 1. This type of
procedures is called reentrant procedures.
 The flow of program execution for reentrant procedure is shown in Fig.1.40

Fig: 1.40 Flow Diagram and Pseudo code for Reentrant procedure
1.10.2 Recursive Procedure
 A recursive procedure is a procedure which calls itself.
 Recursive procedures are used to work with complex data structures called

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 Figure shows the flow diagram and pseudo-code for recursive procedure.

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Fig: 1.41 Flow Diagram and Pseudo code for recursive procedure
1.10.3 Passing parameters:
There are four ways to pass parameters to and from the procedure
1) Using registers
2) Using general memory
3) Using pointers
4) Using stack
1.10.3.1. Passing Parameters Using Registers
 The data, to be passed is stored in the registers and these registers are
accessed in the procedure to process the data.
Example:
Passing Parameters Using Registers
; Main program
CODE SEGMENT
MOV AL, DATA ; Data to be passed is loaded in the AL register
…..
CALL PRO1
....
; Procedure
PRO1 PROC NEAR
MOV INPUT, AL ; Procedure access the data from AL register
…. RET
PRO1. ENDP CODE
ENDS
1.10.3.2. Passing Parameters Using Memory
 To pass few parameters to and from a procedure, registers are a
convenient way to do it.
 To pass a large number of parameters to procedure we use memory.
 This memory may be a dedicated section of general memory or a part of stack.
Example:
Passing using general memory
; Main program
DATA SEGMENT
BCD_INPUT DB 42 ; Storage for BCD
value HEX_VALUE DB ? ; Storage for HEX
value DATA ENDS
CODE SEGMENT
CALL PRO1
; Procedure
PRO1 PROC NEAR MOV
AL, BCD_INPUT MOV
HEX_VALUE, AL

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RET
PRO1 ENDP
CODE ENDS
1.10.3.3. Passing Parameters Using Pointers
Example:
Passing Parameters Using Pointers
; Main program
DATA
SEGMENT
BCD_INPUT DB 42 ; Storage for BCD
value HEX_VALUE DB ? ; Storage for HEX
value DATA ENDS
CODE SEGMENT
MOV SI, OFFSET BCD_YNPUT
MOV DI, OFFSET REX_VALUE
CALL PRO1
; Procedure
PRO1 PROC NEAR
MOV AL, [SI] ; Get BCD number pointed by SI in accumulator
MOV [DI], AL ; Store result in location pointed
by DI RET
PRO1 ENDP
CODE ENDS
1.10.3.4 Passing Parameters Using Stack
What is pushed on the stack and where the stack pointer points all the
time in the program.
Example:
Passing Parameter Using Stack
; Main program
DATA
SEGMENT
BCD_INPUT DW 4209 ; Storage for BCD
value HEX VALUE DW? ; Storage for HEX
value DATA ENDS
CODE SEGMENT
MOV JX, OFFSET BCD_INPUT
PUSH AX
CALL PRO1
; Procedure
PRO1 PROC NEAR
NOV AX, [BP+2] ; Base pointer is decremented by 2 when the
; Procedure is called. So BCD_INPUT
; is available at location [BP+21.
NOV [BP+2], AX; Store the result on the
stack RET
PRO1 ENDP
CODE ENDS

1.11 MACROS
 Macro is a group of instructions. The macro assembler generates the
code in the program each time where the macro is ‘called’.
 Macros can be defined by MACRO and ENDM assembler directives.
Example:
Macro definition for initialization of segment registers.
INIT MACRO; Define macro
MOV AX, data;
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MOV ES AX;

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ENDM; End macro
The assembler places the macroinstructions in the program each time
when it is invoked. This procedure is known as Macro expansion.
1.11.1 Comparison of Procedure and Macro
SI.NO Procedure Macro
1 Accessed by CALL and RET Accessed during assembly with
instruction during program name given to macro when
execution. defined
2 Machine code for instructions is Machine code is generated for
put instructions each time when
only once in the memory. macro is called.
3 With procedures less memory is With macros more memory is
required. required.
4 Parameters can be passed in Parameters passed as part of
registers, memory locations, or statement which calls macro.
stack.
Table 1.9 Comparisons of Procedure and Macro
1.11.2 Passing Parameters in Macro
In Macro, parameters are passed as a part of statement which calls Macro.
Example:
PROMPT MACRO MESSAGE ; Define macro with MESSAGE as a
parameter MOVAH, 09H
LEA MESSAGE
INT 21H
ENDM
DATA ;End macro
MES1 DB 10, 13, ‘Student Name: $
MES2 DB 10, 13, ‘Student Address:
$
.CODE
START: MOV AX, @data ; Initialize
MOV DS, AX ; data segment
PROMPTMES1 ; Display MES1
PROMPT MES2 ; Display MES2
MOV AH, 4CH ; Return to
DOS INT 21H
END START
1.11.3 Local Variables in a Macro
Body of the Macro can use local variables. To define a local variable, LOCAL
directive is
used.
Example
DISPLAY MACRO A ; Displays ASCII character in
uppercase LOCAL J_LABEL ; Defines J_LABEL as
local
PUSH DX
CMP
AL,’Z
JBE J_LABEL ; Check if uppercase
SUB AL, 20H ; Convert to
uppercase
J_LABEL: MOV DL,AL
MOV
AH,02H INT
21H POP
DX END
1.11.4 Conditional Assembly Statements In Macros
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1.11.4.1
College lF-ELSE-ENDlF Statement Microcontroller
IF - ELSE -ENDIF structure general format for the IF family of conditional statements.
.IF XX (condition)
.ELSE (optional) Conditional Block

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. ENDIF (end of IF)
 Every IF directive must have a matching ENDIF to terminate a tested condition
 .ELSE is optional
Statement Function
IF If the expression is true
IFB If the argument is blank
IFE If the expression is not true
IFDEF If the label has been defined
IFNB If argument is not blank
TFNDEF If the label has not been defined
IFIDN If argument 1 equals argument 2
IFDIF If argument 1 does not equal argument 2
Table 1.10 conditional assembly language IF statements
1.11.4.2 REPEAT Statement
REPEAT statement is used to repeat macro sequence for a fix number of time. The
repetition count is specified immediately after the REPEAT statement.
1.11.4.3 WHILE Statement
 WHILE statement is used to repeat macro sequence until the expression
specified with it is true.
 The WHILE statement allows to use relational operators in its expression.
Operator Function
EQ Equal
NE Not equal
LE Less than or Equal
LT Less than
GE Greater than or Equal
GT Greater than
NOT Logical inversion
AND Logical AND
OR Logical OR
XOR Logical exclusive-OR
Table 1.11 Relational Operators used in WHILE statements
1.11.4.4 FOR Statement:
A FOR statement in the macro repeats the macro sequence for a list of
data.

1.12 INTERRUPTS AND INTERRUPT SERVICE ROUTINES


 The most common method of servicing such device is the polled approach.
 This is where the processor must test each device in sequence and in effect
“ask” each one if it needs communication with the processor.
 It is easy to see that a large portion of the main program is looping
through this continuous polling cycle.
 When a microprocessor is interrupted, it stops executing its current program
and calls a special routine which “services” the interrupt.
 The event that causes the interruption is called interrupt and the
special routine executed to service the interrupt is called interrupt service
routine/procedure.
 Normal program can be interrupted by three ways:
1. By external signal
2. By a special instruction in the program or
3. By the occurrence of some condition.
1.12.1 Sources of Interrupts in 8086:
8086 Interrupt come from any one of the three sources:
1) External signal
2) Special Instructions in the program
3) Condition produced by instruction
1.12.1.1 External signal (Hardware Interrupt)
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An 8086 can get interrupt from an external signal applied to the non maskable
interrupt (NMI) input pin ‚or interrupt (INTR) input pin.
1.12.1.2 Special Instruction
 8086 supports a special instruction.INT to execute special program.
 At the end of the interrupt service routine, execution is usually returned to
the interrupted program.
1.12.1.3 Condition Produced by Instruction
 An 8086 is interrupted by some condition produced in the 8086 by the
execution of an Instruction.
 At the end of each instruction cycle 8086 checks to see if there is any interrupt
request.
 If so, 8086 responds to the interrupt by performing series of actions (Refer Fig.

1.42).
Fig: 1.42 8086 interrupt Response
1. It decrements stack pointer by 2 and pushes the flag register on the stack.
2. It disables the LNTR interrupt input by clearing the interrupt flag in the flag register.
3. It resets the trap flag in the flag register.
4. It decrements stack pointer by 2 and pushes the current code segment
register contents on the stack.
5. It decrements stack pointer by 2 and pushes the current instruction pointer
contents on the stack.
6. It does an indirect far Jump at the start of the procedure by loading the CS and
IP values for the start of the interrupt service routine (ISR).
The block of memory is often called the interrupt vector table or the interrupt
pointer
table.

Fig: 1.43 8086 interrupt vector table


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Fig. 1.43 shows how the 256 interrupt pointers
College are arranged in the memory table.
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 Each interrupt type is given a number between O to 255 and the address
of each interrupt is found by multiplying the type by 4
 E.g. for type 11, interrupt address is11x4=4410= 0002CH
 Only first five types have explicit definitions such as divide by zero and non
maskable
 Interrupt.
 The next 27 interrupt types, from 5 to 31, are reserved by Intel for use
in future microprocessors.
 The upper 224 interrupt types, from 32 to 255, are available for user for
hardware or software interrupts.
When the 8086 responds to an interrupt, It automatically goes to the
specified location in the interrupt vector table to get the starting address of
interrupt service routine. So user has to load these starting addresses for different
routines at the start of the program.
1.12.2 8086 Interrupt Types
1.12.2.1 Divide by Zero Interrupt (Type O)
 When the quotient from either a DIV or 10W instruction is too large to fit
in the result register; 8086 will automatically execute type O interrupt.
1.12.2.2 Single Step Interrupt (Type 1)
 The type 1 interrupt is the single step trap. In the single step mode, system
will execute one instruction and wait for further direction from user.
 An 8086 system is used in the single step mode by setting the trap flag.
 If the trap flag is set, the 8086 will automatically execute a type 1
interrupt after execution of each instruction.
1.12.2.3 Non Maskable Interrupt (Type 2)
 Interrupt cannot be disabled by any software instruction.
 This interrupt is activated by low to high transition on 8086 NMI input pin.
1.12.2.4 Breakpoint Interrupt (Type 3)
 The type 3 interrupt is used to implement break point function in the system.
 The type 3 interrupt is produced by execution of the INT 3 instruction.
 Break point function is used as a debugging
1.12.2.5 Overflow Interrupt (Type 4)
 The type 4 interrupt is used to check overflow condition after any signed
arithmetic Operation in the system.
 The 8086 overflow flag, OF, will be represented in the destination register
or memory location.
 For example. If you add the 8-bit signed number 0111 1000 (+ 120 decimal)
and the 8 bit signed number 0110 1010 (+ 106 decimal), result is 1110 0010
(-98 decimal).
 In signed numbers, MSB (Most Significant Bit) is reserved for sign and
other bits represent magnitude of the number.
1.12.3 Software Interrupts
Type 0 - 255:
 The 8086 INT instruction can be used to cause the 8086 to do one of the 256
possible interrupt types.
 To test the NMI routine without needing to apply an external signal to the NMI
input of the 8086.
 The IBM PC has in its ROM collection of routines, each performing some
specific function such as reading character from keyboard, writing character
to CRT. This collection of routines referred to as Basic Input Output System or
BIOS.
 The BIOS routines are called with INT instructions.
Summarize interrupt response and how It is serviced by going through following steps.
1. 8086 pushes the flag register on the stack.
2. It disables the single step and the INTR input by clearing the trap flag and
interrupt flag in the flag register.
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3. It saves the current CS and LP register contents
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4. It does an indirect far jump to the start of the routine by loading the new
values of CS and IP register from the memory whose address calculated by
multiplying 4 to the interrupt type.
5. Once these values arc loaded in the CS and IP, 8086 will fetch the
instruction from the new address which is the starting address of interrupt
service routine.
6. An IRET instruction at the end of the interrupt service routine gets the
previous values of CS and IP by popping the CS and IP from the stack.
7. At the end the flag register contents are copied back into flag register by popping
the flag register form stack.
1.12.4 Maskable Interrupt (INTR)
 The 8086 INTR input can be used to interrupt a program execution.
 The 8086 is provided with a maskable handshake interrupt.
 This interrupt is implemented by using two pins - INTR and INTA
 This interrupt can be enabled or disabled by STI (IF=1) or CLI(IF=O),
respectively.
 When the 8086 is reset, the interrupt flag is automatically
cleared(IF=0). The 8086 responds to an INTR I interrupt as follows:
1. The 8086 first do two interrupt acknowledge machine cycles as shown in the
Fig. 1.44 to get the interrupt type from the external device.
In the first interrupt acknowledge machine cycle the 8086 floats the data bus
lines AD0- AD15 and sends out an INTA pulse on its INTA output pin.
During the second interrupt acknowledge machine cycle the 8086_sends out
another pulse on its INTA output pin

Fig: 1.44 Interrupt acknowledge machine cycle


2. Once the 8086 receives the Interrupt type, it pushes the flag register on the
stack clears TF and IF, and pushes the CS and IP values of the next instruction on
the stack.
3. The 80S6 then gets the new value of IP from the memory address equal to 4
times the interrupt type (number), and CS value (rom memory address equal
to 4 times the interrupt number plus 2.

1.13 Byte and String Manipulation.


1.13.1 String Manipulation Instruction:
1) MOVS/MOVSB/MOVSW Instruction
 These instructions copy a byte or word from a location in the data segment
to a location in the extra segment.
 The offset of the source byte or word in the data segment must be in the SI
register.
 The offset of the destination byte or word in the data segment must be in the DI
register.
Example:
CLD ; Clear Direction Flag to auto increment SI
and DI MOV AX, 0000H
MOV OS, AX ; Initialize data segment register
to 0 MOV ES, AX ; Initialize extra segment
register to 0
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MOV SI, 2000H
College ; Load offset of start of source string
Microcontroller
into SI MOV DI, 2400H ; Load offset of start of
destination into DI MOV CX. 041-1 ; Load length of
string In CX as counter
REP MOVSB ; Decrement CX and MOVSB until CX will be 0.
After move SI will be one greater than offset of last byte in source string. D! will
be none greater than offset of last byte of destination string. CX will be 0.

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2) REP / REPE / REPZ /REPNE/REPNZ Prefix:
 REP is a prefix which is written before one of the string instructions.
 These instructions repeat until specified condition exists.
Instruction Code Condition for Exit
REP CX=0
REPE/ REPZ CX =0 or ZF = 0
REPNE / REPNZ CX =0 or ZF=1
Table 1.12 Repeat Conditions
Example:
REPZ CMP SB ; Compare string bytes until CX = 0; or until string bytes not equal.
3) LODS / LODSB / LODSW
 This instruction copies a byte from a string location pointed to by SI to
AL, or a word from a string location pointed to by SI to AX.
 LODS does not affect any flags. LODS copies byte and LODSW copies a word,
Example:
CLD ; Gear direction flag so SI is auto
incremented MOV SI, OFFSET S_STRING ; Point ST at string
WDS S_STRING.
4) STOS / STOSB / STOSW
 The STOS instruction copies a byte from AL or a word from AX to a memory
location in the extra segment.
 DI Is used to hold the offset of the memory location in the extra segment.
 After the copy, DI is automatically incremented or decremented to point to
the next string element in memory.
 If the direction flag, DF, is cleared, then DI will automatically be incremented
by one for a byte string or incremented by two for a word string.
 If the direction flag is set, DI will be automatically decremented by one for
a byte string or decremented by two for a word string.
 STOS does not affect any flags. STOSB copies byte and STOSW copies a word.
Example:
MOV Dl, OFFSET D_STRING ; Point DI at destination string
STOS D_STRING ; Assembler uses string name to determine
; Whether string is of type byte or type word.
; If byte string, then string byte replaced
; With contents of AL If word string, then
; String word replaced with contents of AX
MOV DI, OFFSET D_STRING ; Point DI at destination string
STOSB ; “B” added to 5105 mnemonic directly
; tells assembler to replace byte in string with byte
from

; AL STOSW would tell assembler directly to replace a


; Word in the string with a word from AX.
1.13.2 Byte Manipulation Instruction:
AND Instruction:
Format: AND destination, source.
 AND operation with two inputs produces result logic 1 only when both
the inputs are logic 1.i.e. Y = A B.
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Table 1.13 Truth Table for AND gate

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 This instruction logically ANDs each bit of the source byte or
word with the corresponding bit in the destination and stores
result in the destination.
 The source may be an immediate number, a register or a memory location.
 The destination may be a register or a memory location.
 The source and destination both cannot be memory locations in the same
instruction.
 The CF and OF are both 0 after AND. The PF, SF and ZF are affected.
 AF is undefined.
Example:
; AL=10010011=93H
; BL = 0111 0101 = 7511
AND BL,AL ; AND byte in AL with byte in BL
; BL = 0001 0001 = 11H

; CX = 0110 1011 1001 1110


AND CX, 00F0H ; CX = 0000 0000 1001
0000
 The AND operation clears bits of a binary number. The task of
clearing a bit in a binary number is called masking.

Figure 1.45 Masking Using AND Operation


OR Instruction:
Format: OR destination, source.
OR operation with two inputs produces result logic 1 when any one or both inputs
arc logic 1. i.e., Y = A + B.
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Table 1.14 Truth Table for OR gate
 This instruction logically ORs each bit of the source byte or word with the
corresponding bit in the destination and stores result in the destination.
 The source may be an immediate number, a register or a memory location.
 The destination may be a register or a memory location.
 The source and destination both cannot be memory locations in the same
instruction.
 The CF and OF are both 0 after OR.
 The PF, SF and ZF are affected. AF is undefined.
Example
; AL = 1001 0011 = 93H
; BL = 0111 0101 = 75K
OR BL, AL ; OR byte in AL with byte in BL.
. ;BL=1111O111=F7H
; CX = 0110 1011 1001 1110
OR CX, 00F0H ; CX 0110 1011 1111 1110
The OR instruction is used to set (make one) any bit in the binary number.
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Figure 1.46 Masking Using AND Operation


XOR Instruction:
Format: XOR destination, source.
XOR operation produces result logic 1 when odd number of inputs are logic 1 i.e. Y=Aa
+aA

A a Y
0 0 0
0 1 1
1 0 1
1 1 0
Table 1.15 Truth Table for XOR gate
 This instruction logically XORs each bit of the source byte or
word with the corresponding bit in the destination and stores
result in the destination.
 The source may be an immediate number, a register or a memory
location. The destination may be a register or a memory location.
 The source and destination both cannot be memory locations in the same
instruction.
 The CF and OF are both 0 after XOR. The PF, SF and ZF are affected. AF is
undefined.
Example:
; AL = 1010 1111 = AFH
; BL = 1111 0000 = F0H
XOR BL, AL ; XOR byte in AL with byte in BL
; BL = 0101 1111 = 5FH
 The XOR instruction is used if some bits of a register or memory
location must be inverted. This instruction allows part of a number to
be inverted or complemented.

Figure 1.47 Masking Using AND Operation


NOT Instruction:
Format: NOT destination.
 The NOT instruction inverts each bit of a byte or a word. The destination can
be register or a memory location.
Flags: NOT instruction affects no flag.
Example:
; AL = 0110 1100
NOTAL ; AL= 10010011
; CX=1010 1111 0010 0110
NOT CX ; CX = 0101 0000
11011001

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Part-A (2 Marks Questions and Answers)
1. What is Microprocessor? Give the power supply & clock frequency of 8085.
(Nov/Dec’11)
A microprocessor is a multipurpose, programmable logic device that reads
binary instructions from a storage device called memory accepts binary data as
input and processes data according to those instructions and provides result as
output. The power supply of 8085 is
+5V and clock frequency in 3MHz.

2. List few applications of microprocessor-based system.


a) For measurements, display and control of current, voltage, temperature,
pressure, etc.
b) For traffic control and industrial tool control.
c) For speed control of machines.

3. What is Stack pointer?


Stack pointer is a 16 bit register. This register is always incremented/
decremented by 2. It is used as a memory pointer. The beginning of the stack is
defined by loading a 16-bit address in the stack pointer.

4. What is the function of program counter? (Nov/Dec’13)


The function of the program counter is to point the memory address from
which the next byte is to be fetched. When a byte is being fetched the PC is
incremented by one to point to the next memory locations.

5. Define opcode and operand.


 Opcode is the part of an instruction that identifies a specific operation.
 Operand is a part of an instruction that represents a value on which the
instruction acts.

6. What are the I/O instructions are used in 8086?


The I/O instructions are as follows:
 IN (Initiate Input Operation)
 OUT (Initiate Output Operation)

7. What are the different functional units in 8086?


Bus Interface Unit and Execution unit are the two different functional units in
8086.

8. What does EU do?


Execution Unit receives program instruction codes and data from BIU,
executes instructions and store the result in general registers.

9. Which Stack is used in 8086?


FIFO (First in First Out) stack is used in 8086.In this type of Stack the first
stored information is retrieved first.

10. Discuss the function of instruction Queue in 8086?


In 8086, a 6-byte instruction queue is presented at the Bus Interface Unit
(BIU). It is used to prefetch and store at the maximum of 6 bytes of instruction code
from the memory. Due to this, overlapping instruction fetch with instruction
execution increases the processing speed.

11. What are the various interrupts in 8086?


Maskable interrupts Non-Maskable interrupts. 256 Software interrupts like
Divide by zero, single step, non-maskable interrupts Breakpoint, Overflow interrupt
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NMI and INTR.

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12. Define bit, byte and word.
A digit of the binary number or code is called bit. Also, the bit is the
fundamental storage unit of computer memory. The 8-bit (8-digit) binary number or
code is called byte and 16-bit binary number or code is called word. (Some
microprocessor manufactures refer the basic data size operated by the processor as
word)

13. What is a bus?


Bus is a group of conducting lines that carries data, address and control signals.

14. What is the function of microprocessor in a system?


The microprocessor is the master in the system, which controls all the
activity of the system. It issues address and control signals and fetches the
instruction and data from memory. Then it executes the instruction to take
appropriate action.

15. What is REP prefix? How it functions for string instructions?


This REP prefix is used for repeating the instruction with REP prefix will
execute repeatedly till the count in the cx register will be zero. This can be used in
with some of the string handling instructions give one example also.

16. Explain the instruction CLD (Nov/Dec’13)


CLD: this will clear the direction flag.

17. List the various addressing modes present in 8086? (Apr/May2019)


There are 12 addressing modes present in 8086. They are,
(a) Register and immediate addressing modes
 Register addressing modes
 Immediate addressing mode
(b)Memory addressing modes.
 Direct addressing modes
 Register indirect addressing modes
 Based addressing modes
 Indexed addressing modes
 Based Indexed addressing modes
 String addressing modes
(c) I/O addressing modes
 Direct addressing mode
 Indirect addressing mode
(d)Relative addressing mode
(e) Implied addressing mode

18. What is an assembler directive? (Nov/Dec’14)


Assembler directives are non-executable instruction for 8086 assembler; they
will help the assembler in the execution of a program.
Example: assume. Ends, end and org.

19. What is assembler (/May/June’13)


The assembler translates the assembly language program text which is given
as input to the assembler to their binary equivalents known as object code. The
time required to translate the assembly code to object code is called access time.
The assembler checks for syntax errors & displays them before giving the object
code.

20. Explain ALIGN & ASSUME (Nov/Dec’14)


The ALIGN directive forces the assembler to align the next segment at an
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Microcontroller
can be 2, 4, 8 or 16. Example: ALIGN 8. The ASSUME directive assigns a logical
segment to a physical segment at

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any given time. It tells the assembler what address will be in the segment registers at
execution time. Examples: ASSUME CS: code, DS: data, SS: stack

21. What is interrupt service routine? (Nov/Dec’11,12)


Interrupt means to break the sequence of operation. While the CPU is
executing a program an interrupt breaks the normal sequence of execution of
instructions & diverts its execution to some other program. This program to which
the control is transferred is called the interrupt service routine.

22. What are Macros? (Apr/May’13)(Nov/Dec’17) (Apr/May2019)


Macro is a group of instruction. The macro assembler generates the code in
the program each time where the macro is called. Macros are defined by MACRO &
ENDM directives. Creating macro is similar to creating new opcodes that can be
used in the program
INIT MACRO
MOV AX,
data MOV
DS
MOV ES,
AX ENDM

23. What is the use of addressing modes, mention the different types (May/June’14)
The various formats of specifying the operands are called addressing modes,
it is used to access the operands or data. The different types are as follows
1) Immediate addressing
2) Register addressing
3) Direct addressing
4) Indirect addressing
5) Implicit addressing

24. What is the need of a flag register in 8086 (May/June’15)


It indicates the status of the accumulator. There are 6 one bit flags are
present. They are, AF - Auxiliary Carry Flag
CF - Carry Flag
OF - Overflow
Flag SF - Sign
Flag
PF - Parity
Flag ZF - Zero
Flag

25. Define Flags


The flags are used to reflect the data conditions in the accumulator. The
8085 flags are S-Sign flag, Z-Zero flag, AC-Auxiliary carry flag, P-Parity flag, CY-
Carry flag

26. Define BIOS (Nov/Dec’12) (May/June’13)


The IBM PC has in its ROM a collection of routines, each of which performs
some specific function such as reading a character from keyboard, writing character
to CRT. This collection of routines is referred to as Basic Input Output System or
BIOS

27. Define pipelining? (Nov/Dec’15)


In 8086, to speed up the execution of program, the instructions fetching and
execution of instructions are overlapped each other. This technique is known as
pipelining. In pipelining, when the n instruction is executed, the n+1 instruction is
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Microcontroller

28. Discuss the function of instruction queue in 8086? (May/June’15)


In 8086, a 6 -byte instruction queue is presented at the Bus Interface Unit
(BIU). It is used to prefetch and store at the maximum of 6 bytes of instruction code
from the memory. Due to this, overlapping instruction fetch with instruction
execution increases the processing speed.

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29. Name the hardware interrupts of 8086 (May/June’14)
1) Divide by Zero Interrupt(Type 0)
2) Single Step Interrupt (Type 1)
3) Non Maskable Interrupt (Type 2)
4) Breakpoint Interrupt (Type 3) and Overflow Interrupt (Type 4)

30. What is the function of LOCK and RQ/GT signals? (May/June’13) (Nov/Dec 2017)
LOCK: This signal indicates that an instruction with a LOCK prefix is being
executed and the bus is not to be used by another processor.
RQ/GT1 and RQ/GT0: In the maximum mode, HOLD and HLDA pins are
replaced by RQ (Bus request)/GT0 (Bus Grant), and RQ/GT1 signals.

31. Comparison of Procedure and Macro (Nov/Dec’15)

Procedure Macro
Accessed by CALL and RET Accessed during assembly with
instruction during name given to macro when
program defined
execution.
Machine code for instructions is Machine code is generated
put only once in the memory. for instructions each time
when macro is called.
With procedures less memory With macros more memory is
is required. required.
Parameters can be Parameters passed as part
passed in registers, of statement which calls
memory locations, macro.
or
stack.

32. Explain PTR & GROUP


A program may contain several segments of the same type. The GROUP
directive collects them under a single name so they can reside in a single segment,
usually a data segment. The format is Name GROUP Seg-name, Seg-name PTR is
used to assign a specific type to a variable or a label. It is also used to override the
declared type of a variable.

33. Define Stack Register. (April/May 2017)


In 8086, the main stack register is called stack pointer - SP. The stack
segment register (SS) is usually used to store information about the memory
segment that stores the call stack of currently executed program. SP points to
current stack top. To push a value to the stack, the PUSH instruction is used. To pop
a value from the stack, the POP instruction is used.

34. Explain PROC & ENDP


PROC directive defines the procedures in the program. The procedure name
must be unique. After PROC the term NEAR or FAR are used to specify the type of
procedure. Example: FACT PROC FAR. ENDP is used along with PROC and defines
the end of the procedure.

35. Explain SEGMENT & ENDS


An assembly program in .EXE format consists of one or more segments.
The starts of these segments are defined by SEGMENT and the end of the
segment is indicated by ENDS directive. Format Name SEGMENT Name ENDS

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36. Define variable
College Microcontroller
A variable is an identifier that is associated with the first byte of data item.
In assembly language statement: COUNT DB 20H, COUNT is the variable.

37. What is the maximum memory size that can be addressed by 8086?

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In 8086, a memory location is addressed by 20 bit address and the address
bus is 20 bit address and the address bus is 20 bits. So it can address up to one
mega byte (2^20) of memory space.

38. What is the function of the BHE signal in 8086? (Apr/May2019)


BHE signal means Bus High Enable signal. The BHE signal is made low when
there is some read or writes operation is carried out. i.e. whenever the data bus of
the system is busy.

39. What do you meant by addressing mode (May/June’14)


The different ways that processor access data are referred to as addressing
modes.
The addressing modes of any processor can be classified as:
 Data addressing modes
 Stack memory addressing modes
 Program memory addressing modes

40. What is meant by a vectored interrupt? (May/June’14)


When the external device interrupts the processor, has to execute interrupt
service routine for servicing that interrupt. If the internal control circuit of the
processor produces a CALL to a predetermined memory location, which is the
starting address of interrupt service routine. That address is called vectored
interrupt.
*****
Part-B (16 Marks Questions)

1. Explain the Features of 8086 microprocessor (May/June’12) [Refer Sec:1.1.1]


2. Explain the register organization of 8086 processor in detail
(May/June’12) [Refer Sec:1.2.4)
3. Draw and explain in detail about the architecture of 8086. (Nov/Dec’12, 13)
(Apr/May’11) (Apr/May’17) [Refer Sec:1.2] (Apr/May2019).
4. Explain any 8 addressing modes of 8086 processor with an example
(May/June’13) (Nov/Dec’12) [Refer Sec.1.3]
5. Give an example for 8086 instructions.
 String Instructions [Refer Sec:1.13.1]
 Bit manipulation instructions [Refer Sec:1.13.2]
 Program Control instruction (Nov/Dec’12) [Refer Sec:1.4.7]
6. Explain about the any 5 assembler directives (May/June’11,13) [Refer Sec:1.5]
7. State important guidelines for 8086 assembly language Programming [Refer
Sec:1.6.7]
8. Explain how to access external identifiers. [Refer Sec:1.8.2]
9. Explain the structure of stack of 8086 (Nov/Dec’13) [Refer Sec:1.9]
10.Define macro. Explain how to pass parameters to macros.
(May/June’12, 14,15) [Refer Sec:1.11]
11.List different types of 8086 hardware interrupt (Apr/May’10) (Nov/Dec’12)
(Apr/May’17) [Refer Sec:1.12.1)
12.Draw and discuss the interrupt vector of 8086. (May/June’13,15) [Refer Sec:1.12.1.3]
(Apr/May2019)
*****

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UNIT 2
8086 SYSTEM BUS STRUCTURE

REFERRED BOOK:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family
- Architecture, Programming and Design”, Second Edition, Prentice Hall of
India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly
and C”, Second
1. DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH,2012

STAFF IN-CHARGE HOD

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2.1 8086 SIGNALS

PIN OUT SIGNALS AND FUNCTIONS OF 8086


8086 is available in three clock rates, i.e. 5, 8 and 10 MHz, packaged as a 40
pin chip. The 8086 operates in single processor or multiprocessor configurations to
achieve high performance.

Fig: 2.1 Pin configurations of 8086


The following signal descriptions are common for both the minimum and
maximum modes.
AD15-- AD0 These are the time multiplexed memory I/O address and data lines.
Address remains on the lines during T1 state, while the data is available on the data
bus duringT2, T3, Tw andT4. Here T2, T3, T4 and Tw are the clock states of a machine
cycle. Tw is a wait state. These lines are active high and float to a tristate during
interrupt acknowledge and local bus hold acknowledge cycles.
A19/S6,A18/S5,A17/S4, A16/S3 These are the time S3 Indications
multiplexed address and status lines. During
T1, these are the most significant address lines
for memory operations. During I/O operations,
these lines are low.
During memory or I/O operations, status
information is available on those lines for T2, T3,
Tw andT4. The status of the interrupt enable flag
bit (displayed on S5) is updated at the beginning
of each clock cycle. The S4 and S3 combined
indicate which segment register is presently
being used for memory accesses as shown in
Table 1.1. These lines float to tri-state off
(tristate) during the local bus hold acknowledge.
The status line S6 is always low (logical). The

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separated from the status bits using latches
controlled by the ALE signal. S4
0 0 Alternate Data

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0 1 Stack
1 0 Code or none
1 1 Data
Table 2.1

BHE / S7-Bus High Enable/Status The bus high enable signal is used to indicate the
transfer of data over the higher order (D15—D8) data bus as shown in Table 1.2. It
goes low for the data transfers over D 15—D8 and is used to derive chip selects of
odd address memory bank or peripherals. BHE is low during T 1 for read, write and
interrupt acknowledge cycles, whenever a byte is to be transferred on the higher
byte of the data bus. The status information is available during T2, T3 andT4. The
signal is active low and is tristated during ‘hold’. It is low during T 1 for the first pulse
of the interrupt acknowledges cycle.

BHE A0 Indications
0 0 Whole Word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 None
Table 2.2 Bus High Enable/Status
RD-Read Read signal, when low, indicates the peripherals that the processor is
performing a memory or I/O read operation. RD is active low and shows the state
for T2, T3, Tw of any read cycle. The signal remains tristated during the ‘hold
acknowledge’.

READY This is the acknowledgement from the slow devices or memory that they
have completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the 8086. The
signal is active high.

INTR- Interrupt Request This is a level triggered input. This is sampled during the last
clock cycle of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters the interrupt acknowledge cycle.
This can be internally masked by resetting the interrupt enable flag. This signal is
active high and internally synchronized.

TEST This input is examined by a ‘WAIT’ instruction. If the TEST input goes low,
execution will continue, else, the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.

NMI-Non-maskable InterruptThis is an edge-triggered input which causes a Type2


interrupt. The NMI is not maskable internally by software. A transition from low to
high initiates the interrupt response at the end of the current instruction. This input
is internally synchronized.
RESET This input causes the processor to terminate the current activity and start
execution from FFFF0H. The signal is active high and must be active for at least
four clock cycles. It restarts execution when the RESET returns low. RESET is also
internally synchronized.
CLK-Clock InputThe clock input provides the basic timing for processor operation
and bus control activity. Its an asymmetric square wave with 33% duty cycle. The
range of frequency for different 8086 versions is from 5MHz to 10MHz.
Vcc +5V power supply for the operation of the internal circuit.
GND ground for the internal circuit.
MN/MX The logic level at this pin decides whether the processor is to operate in
either minimum (single processor) or maximum (multiprocessor) mode.
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2.1.1 Minimum Mode
The following pin functions are for the minimum mode operation of 8086.
M / I/O -Memory/IOThis is a status line logically equivalent to S2 in maximum mode.
When it is low, it indicates the CPU is having an I/O operation, and when it is
high, it indicates that the

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CPU is having a memory operation. This line becomes, active in the previous T 4 and
remains active till final T4 of the current cycle. It is tristated during local bus “hold
acknowledge”.
INTA -Interrupt AcknowledgeThis signal is used as a read strobe for interrupt
acknowledge cycles. In other words, when it goes low, it means that the processor
has accepted the interrupt. It is active low during T2, T3,and Tw of each interrupt
acknowledge cycle.
ALE-Address Latch Enable This output signal indicates the availability of the valid
address on the address/data lines, and is connected to latch enable input of latches.
This signal is active high and is never tristated.
DT / R-Data Transmit/ReceiveThis output is used to decide the direction of data flow
through the transceivers (bidirectional buffers). When the processor sends out data,
this signal is high and when the processor is receiving data, this signal is low.
Logically, this is equivalent to S 1 in maximum mode. Its timing is the same as M/ I/O.
This is tristated during ‘hold acknowledge’.
DEN-Data Enable This signal indicates the availability of valid data over the
address/data lines. It is used to enable the transceivers (bidirectional buffers) to
separate the data from the multiplexed address/data signal. It is active from the
middle of T2 until the middle of T4. DEN is tristated during ‘hold acknowledge’ cycle.
HOLD, HLDA-Hold /Hold Acknowledge When the HOLD line goes high, it indicates to
the processor that another master is requesting the bus access. The processor,
after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin,
in the middle of the next clock cycle after completing the current bus (instruction)
cycle. At the same time, the processor floats the local bus and control lines. When
the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an
asynchronous input, and it should be externally synchronized.
If the DMA request is made while the CPU is performing a memory or I/O cycle, it
will release the local bus during T 4 provided:
1. The request occurs on or before T2 state of the current cycle.
2. The current cycle is not operating over the lower byte of a word (or operating
on an odd address).
3. The current cycle is not the first acknowledge of an interrupt acknowledge
sequence. A Lock instruction is not being executed.

2.1.2 Maximum Mode Signals


The following pin functions are applicable for maximum mode operation of 8086.
S2, S1, S0-Status Lines These are the status lines which reflect the type of operation,
being carried out by the processor. These become active during T 4 of the previous
cycle and remain active during T 1 and T2 of the current bus cycle. The status lines
return to passive state during T 3 of the current bus cycle so that they may again
become active for the next bus cycle during T 4. Any change in these lines during T 3
indicates the starting of a new cycle, and return to passive state indicates end of
the bus cycle. These status lines are encoded in Table 1.3.
S2 S1 S0 INDICATIONS
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write memory
1 1 1 Passive
Table 2.3
LOCK This output pin indicates that other system bus masters will be prevented
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system bus, while the LOCK signal is low. The LOCK signal is activated by the LOCK
prefix instruction and remains active until the completion of the next instruction.
This floats to tri-state off during “hold acknowledge”. When the CPU is executing a
critical instruction which requires the system bus, the LOCK prefix instruction
ensures that other processors connected in the

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system will not gain the control of the bus. The 8086, while executing the prefixed
instruction, asserts the bus lock signal output, which may be connected to an
external bus controller.
QS1, QS0-Queue Status These lines give information about the status of the code
prefetch queue. These are active during the CLK cycle after which the queue
operation is performed. These are encoded as shown in Table 1.4.
QS1 QS2 Indications
0 0 No operation
0 1 First byte of opcode from the
queue
1 0 Empty queue
1 1 Subsequent
Table 2.4

RQ / GT0 , RQ / GT1 -Request/GrantThese pins are used by other local bus masters,
in maximum mode, to force the processor to release the local bus at the end of the
processor’s current bus cycle. Each of the pins is bidirectional with RQ / GT0 having
higher priority than
RQ / GT1 . RQ / GT pins have internal pull-up resistors and may be left unconnected.
The request/grant sequence is as follows:
1. A pulse one clock wide from another bus master requests the bus access to
8086.
2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from 8086
to the requesting master, indicates that the 8086 has allowed the local bus to
float and that it will enter the “hold acknowledge” state at next clock cycle.
The CPU’s bus interface unit is likely to be disconnected from the local bus of
the system.
3. A one clock wide pulse from another master indicates to 8086 that the ‘hold’
request is about to end and the 8086 may regain control of the local bus at
the next clock cycle.
Thus each master to master exchange of the local bus is a sequence of 3
pulses. There must be at least one dead clock cycle after each bus exchange. The
request and grant pulses are active low. For the bus requests those are received
while 8086 is performing memory or I/O cycle, the granting of the bus is governed
by the rules as discussed in case of HOLD and HLDA in minimum mode.

2.2 BASIC CONFIGURATIONS


2.2.1 Minimum Mode 8086 System and Timings
The microprocessor 8086 is operated in minimum mode by strapping its MN/
MX pin to logic 1. In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the minimum mode
system. The remaining components in the system are latches, transceivers, clock
generator, memory and I/O devices. Some type of chip selection logic may be
required for selecting memory or I/O devices, depending upon the address map of
the system.
The latches are generally buffered output D-type flip-flops, like, 74LS373 or
8282. They are used for separating the valid address from the multiplexed
address/data signals and are controlled by the ALE signal generated by 8086.
Transceivers are bidirectional buffers and are called as data amplifiers. They are
required to separate the valid data from the time multiplexed
address/data signal. They are controlled by two signals, namely, DEN and DT/ R .
The DEN
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signal Microcontroller
on the data bus, while DT/ R
indicates the direction of data, i.e. from or to the processor. The system contains
memory for the monitor and users program storage. Usually, EPROMS are used for
monitor storage, while RAMs for users program storage. A system may contain I/O
devices for communication with the processor as well as some special purpose I/O
devices. The clock generator generates the clock from the crystal oscillator and
then shapes it and divides to make it more precise so that it can be used as an
accurate timing reference for the system. The clock generator also synchronizes
some external signals with the system clock. Since it has 20 address lines and 16
data lines, the 8086

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CPU requires three octal address latches and two octal data buffers for the
complete address and data separation. The system configuration is shown below.
The read cycle begins in T1 with the assertion of address latch enable (ALE)
signal and also M / IO signal. During the negative going edge of this signal, the valid
address is latched on the local bus.
The BHE and A0 signals address low, high or both bytes. From T1 to T4, the
M/IO signal indicates a memory or I/O operation.
At T2, the address is removed from the local bus and is sent to the output.
The bus is then tri-stated. The read (RD) control signal is also activated in T2.The
read (RD) signal causes the address device to enable its data bus drivers. After RD
the valid data is available on the data bus. When the processor returns the read
signal to high level, the addressed device will again tristate its bus drivers.

Fig: 2.2 Minimum Mode 8086 System


A write cycle also begins with the assertion of ALE and the emission of the
address. The M/ IO signal are again asserted to indicate a memory or I/O operation.
In T2, after sending the address in T1, the processor sends data to be written to
the addressed location. The data
remains on the bus until middle ofT 4 state. WR becomes active at the beginning ofT 2
. BHE and A0 are used to select the proper byte or bytes of memory or I/O word to
be read or written.

Fig: 2.3(a) Read Cycle Timing diagram for minimum mode

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Fig: 2.3(b) Write Cycle Timing diagram for minimum operation

M/ IO RD WR Indications
0 0 1 I/O Read
0 1 0 I/O Write
1 0 1 Memory
Read
1 1 0 Memory
Write

2.2.2 Maximum Mode 8086 System and Timings


In the maximum mode, the 8086 is operated by strapping the MN/ MX pin to
ground. In
this mode, the processor derives the status signals S2 , S1 and S0 . Another chip
called bus
controller derives the control signals using this status information. In the maximum
mode, there may be more than one microprocessor in the system configuration.
The other components in the system are the same as in the minimum mode
system.
The basic functions of the bus controller chip 1C8288, is to derive control signals
like
RD andWR (for memory and I/O devices), DEN , DT/ R , ALE, etc. using the information
made
available by the processor on the status lines. The bus controller chip has S2 ,
input lines and
S1 and S0 CLK. These inputs to 8288 are driven by the CPU. It derives the outputs
ALE, DEN , DT/ R , MRDC , MWTC , AMWC , IORC, IOWCand AIOWC. The AEN , IOB
and CEN pins
are specially useful for multiprocessor systems. AEN and IOB are generally grounded.
CEN pin
is usually tied to +5V. The significance of the MCE/ PDEN output depends upon the
status of the IOB pin. If IOB is grounded, it acts as master cascade enable to control
cascaded 8259A, else it acts as peripheral data enable used in the multiple bus
configurations. INTA pin is used
to issue two interrupt acknowledge pulses to the interrupt controller or to an
interrupting device.
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Microcontroller
respectively.
These signals enable an IO interface to read or write the data from or to the addressed
port.

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Fig: 2.4 Maximum Mode 8086 system

The MRDC , MWTC are memory read command and memory write command
signals respectively and may be used as memory read and write signals. All these
command signals instruct the memory to accept or send data from or to the bus.
For both of these write command
signals, the advanced signals namely AMWC and AIOWC are available. They also
serve the same purpose, but are activated one clock cycle earlier than the IOWC
and MWTC signals, respectively. The maximum mode system is shown in Fig.
1.10.The maximum mode system
timing diagrams are also divided in two portions as read (input) and write
(output) timing
diagrams. The address/data and address/status timings are similar to the minimum
mode. ALE is asserted in T1, just like minimum mode.
S0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will
output a pulse as on the ALE and apply a required signal to its DT / R pin during T1.
In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will
activate MRDC or IORC. These signals are activated until T4. For an output, the
AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3
to T4.
The status bit S0 to S2 remains active until T3 and become passive during
T3 and T4. If reader input is not activated before T3, wait state will be
inserted between T3 and T4.

2.3 SYSTEM BUS TIMING


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Microcontroller

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Memory Write Timing Diagram for Maximum Mode Operation of 8086:

2.4 SYSTEM DESIGN USING 8086

2.4.1 Minimum Mode 8086 System


The Fig. 2.5 shows the typical minimum mode 8086 system.
 For interfacing memory module to 8086, it is necessary to have odd and even
memory banks. This is implemented by using two EPROMs and two RAMs.
 Data lines DI5-D8 are connected to odd bank of EPROM and RAM,, and data
lines DrD0 are connected to even bank of EPROM and RAM.
 Address lines are connected to EPROM and RAM as per their capacities.
 RD signal is connected to the output enable (0E) signals of EPROMs and RAMs.
 WR signal is connected to WR signal of RAMs.
 Two separate decoders are used to Generate chip select signals for memory
and I/O devices. These chip select signals are logically ORed with either BHE
or to generate final chip select signals.
 RD and WR signals are connected to the RD and WR signals of I/O device.
 Data lines D15-D0 are connected to the data lines of I/O device

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Fig: 2.5 Minimum Mode 8086 system


2.4.2 Maximum Mode 8086 System
 The Fig. 2.6 shows the typical maximum mode 8086 system.
 Here interfacing of memory and I/O devices are shown with the basic
maximum mode configuration.
 The connections for memory and I/O devices are similar to that of minimum
mode configuration. The generation of control signals from 8086 is done by
external bus controller 8288.
 The transfer of data between keyboard and microprocessor, and
microprocessor and display device is called input /output data transfer or
I/O data transfer.
 This data transfer is done by using I/O ports.

Fig: 2.6 Maximum Mode 8086 system

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2.5 IO PROGRAMMING
2.5.1 Input port:
 It is used to read data from the input device such as keyboard.
 The simplest form of input port is a buffer.
 The input device is connected to the microprocessor through buffer as shown
Data bus Fig 2.7.

Fig: 2.7 Input Port


 This buffer is a tri-state buffer and its output is available only Enable when
enable signal is active.
 When microprocessor wants to read data from the input device (keyboard),
the control signals from the microprocessor activates the buffer by asserting
enable Input of the buffer,
 Once the buffer is enabled, data train the Input device is available on the data
bus.
 Microprocessor reeds this data by Initiating reed command.

2.5.2 Output port:


 It is used to send data to the output device such as display from the
microprocessor.
 The simplest form of output port is a latch. The output device is
connected to the microprocessor through latch, as shown In the Fig. 2.8.
 When microprocessor wants to send data to the output device, it puts the
data on the data bus and activates the clock signal of the latch.

Fig: 2.8 Output Port


2.5.3 Programmed I/O:
 I/O operations will mean a data transfer between an I/O device and memory
or between an I/O device and the CPU.
 If in any computer system I/O operations are completely controlled by the
CPU, then that system is said to be using ‘programmed I/O’.
 When such a technique is used, CPU executes programs that initiate, direct
and terminate the I/O operations, including sensing device status, sending a
read or write command and transferring the data.
 It is the responsibility of the processor to periodically check the status of the
I/O system until it finds that the operation is complete. This process is
illustrated in below figure 2.9.

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Fig: 2.9 Flowchart for I/O service routine


2.5.4 Interrupt Driven I/O
 The moat common method of servicing such device is the polled approach.
 This is where the processor must test each device in sequence.
 It needs communication with the processor.
 It is easy to see that a large portion of the main program is looping
through this continuous polling cycle.
 Allows the processor to execute its main program and only stop to service
peripheral devices when it is told to do so by the device itself.
 The method would provide an external asynchronous input to the processor.
 Instruction that is currently being executed and fetch a new routine that will
service the requesting device.
 Once this servicing is completed, the processor would resume exactly where It
left off.
 This method of servicing I/O request is called Interrupt driven I/O.
 When a processor is interrupted,Itstops. Executing its current program
and calls a special routine which services the Interrupt this is illustrated in
fig.2.10.
 Interruption is called Interrupt and the special routine executed to service the
Interrupt is called Interrupt Service routine (ISR).

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Fig: 2.10 Interrupt Operation


2.5.5 Comparison between Programmed I/O and Interrupt Driven I/O

Table 2.5 Comparison between Programmed I/O and Interrupt Driven I/O
2.5.6 Direct Memory Access (DMA) Transfer
 In software control data transfer, processor executes a series of instructions
to carry out data transfer.
 For each instruction execution fetch, decode arid execute phases are required.
 Fig. 2.11 gives the flowchart to transfer data from memory to I/O device.
 So this method of data transfer is not suitable for large data transfers.

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Fig: 2.11 Flowchart to Transfer Data from Memory to I/O Device

2.5.6.1 Drawbacks in Programmed I/O and Interrupt Driven I/O


 Transfer rate is limited by the speed
 The time that the CPU spends testing I/O device status and executing a
number of instructions for I/O data transfer can often be better spent on
other processing tasks
2.5.6.2 DMA Operation
 DMA controlled data transfer is used for large data transfer. For example to
read bulk amount of data from disk to memory.
 To read a block of data from the disk processor sends a series of commands
to the disk controller device
 Read the desired block of data from the disk.
 When disk controller is ready to transfer first byte of data from disk, it
sends DMA request DRQ signal to the DMA controller.
 Then DMA controller sends a hold request HRQ, signal to the processor HOLD
Input.
 The processor responds this HOLD signal by floating its buses and sending
out a hold acknowledge signal HLDA to the DMA controller.
2.5.6.3 DMA Active Cycle
 When DMA controller gets control of the buses, it sends tie memory address
and Italso sends a DMA acknowledge, DACK signal to the disk controller
device telling it to get ready to output the byte.
 Finally, it asserts both the I/O and MEMW signals on tie control bus.

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College Fig: 2.12 DMA Controller Operating Microcontroller
In A Microprocessor System

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2.5.7 Comparison of I/O program controlled transfer and DMA transfer:
S.No I/O program controlled transfer DMA transfer
1 It is software controlled Hardware controlled transfer
transfer
2 Data transfer speed is low Data transfer is high
3 CPU is involved in the transfer CPU is not involved in the transfer
4 Extra hardware is not required DMA controller is required to carry
out
data transfer
5 During data transfer data is During data transfer data does not
routed through processor routed
through processor
Table 2.6 Comparison of I/O Program Controlled Transfer and DMA Transfer

2.6 INTRODUCTION TO MULTIPROGRAMMING


2.6.1 Multiprogramming:
 A process can be defined as a programming unit which performs an
independent task.
 A processor that process (execute) serially, because it can process one task
at a time that’s why it is called uni-programming system.
 In a multiprogramming environment, the codes for two ‘or’ more
processes are in memory at the same time and are executed by time-
multiplexing.
 The performance of a system is generally measured in terms of the
number of jobs completed in a time period (that is referred as system
through put).
The following Figure presents completion of a task consisting two processes
P1 and P2 by using uni-programming.
1) The P1 starts and continue until F/O is required (Point A), then FÍO is
initialized and the processing continues in parallel with 1/0 until the
processing requires the input data. At this time it should wait until I/O is

finished (Point B).


Fig: 2.45Uni-programming Approach
2) The 110 in finished (Point C) the processing is resumed and the same
description applies to point D, E and F. At the end of P1, P2 can start which
has the same operation as that P1.

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College Fig: 2.14 Multiprogramming Approach
Microcontroller
 A multiprogramming system may be capable of accommodating several
users at the same time.
 Multiprogramming can be used in a system that includes more than one
Processor, such systems are called multiprogramming systems.

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2.6.2 Process Management
A process is sequential program in execution. A process defines the
fundamental unit of computation for the computer. Components of the process are:
1) Object program
2) Data
3) Resources
4) Status of the process execution.
2.6.2.1 Processes and Programs
 Process is a dynamic entity, which is a program in execution.
 A process is a sequence of instruction executions. Process exists in a
limited span of time.
 Two or more processes can execute the same program, each using their own
data and resources.
 Program is a static entity made up of program statement.
2.6.2.2 Process State
 When process executes, it changes state.
 Process state is defined as the current activity of the process.
 Fig. 2.15 shows the general form of the process state transition diagram.
 Process state contains five states. The states are listed below.
1) New
2) Ready
3) Running
4) Waiting
5) Terminated(exist)

Fig: 2.15 Process State transition Diagram


1. New:
 A process that has just been created.
2. Ready:
 Ready processes are waiting to have the processor allocated to them by
the operating system so that they can run.
3. Running:
 The process that is currently being executed.
 A running process possesses all the resources needed for its execution,
including the processor.
4. Waiting:
 A process that cannot execute until some event occurs such as the
completion of an 1/O operation.
 The running process may become suspended by invoking an I/O routine.
5. Terminated:
 A process that has been released from the pool of executable
processes by the operating system.
5.1.1.1 Process Control Block (PCB)
Each process contains the process control block (PCB). PCB is the data
structure used by the operating system.
1. Pointer:
 Pointer points to another process control block. Pointer is used for
maintaining the list Scheduling list
2. Process state:

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 Process state may be new, ready, Memory location running, waiting and so on. .
3. Program counter:
 It indicates the address of the next instruction to be executed for this process.
4. CPU registers:
 It includes general purpose block register, stack pointers, index registers and
accumulators etc.
5. Memory management information:
 Include the value of base and limit register.
 Information is useful for deallocating the memory when the process terminates.
6. Accounting information:
 The information includes the amount of CPU and real-time used, time limits,
job or process numbers, account numbers etc.
2.6.3 Semaphore
 The software technique used to solve the same problem is, Mutual exclusion.
 The program region where the common resources, are used is called critical
program region.
Semaphore implementation in 8086:
In 8086, the XCHG instruction along with the LOCK prefix can be used to set
or reset Semaphore.
Program sequence : MOV AL, 00H
Check again : LOCK XCHG semaphore, AL
TEST AL, AL
JZ check again
. . Critical region in which program access the shored
resources MOV semaphore, 1
The XCHG semaphore, AL instruction exchanges the contents of the AL
register with the contents of the memory location in which semaphore is stored.
The XCHG instruction requires two bus cycles.
1) During this XCHG instruction, achieved by LOCK prefix in the 8086. LOCK prefix
activates the LOCK output pin during the execution of the instruction that
follows the prefix.
2) During the execution of XCHG instruction, The LOCK output pin is in the active
state which does not allow other processor to get control of the system bus.
2.6.4 Swapping
 Swapping is a technique of temporarily removing inactive program (from the
memory al a system.)
 It removes the process from the primary memory when it is blocked and
deallocating the memory. Fig. 2.16 shows the swapping of process.
 For example. When process P1 requests an I/O operation. It becomes blocked
and will not return to the ready state.
 Process manager places the process P1 into a blocked state, then the
memory manager swaps the process P1 from primary memory to secondary
memory and process P, secondary memory to primary memory Process P,

changes the state, after swapping.


Fig: 2.16 Swapping of Processes
 When process is swapped out, its executable image is copied to secondary
memory.
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 When the process is swapped back into available primary memory and
swapped out is copied into the new block allocated by the memory manager.
Binding Method:
 If the address binding is done at load time then the process is moved to same
location of previous one
 If the address binding done at execution time then the process can be
swapped into a different memory space.
2.6.5 Memory Management:
 The placement of blocks of information in a memory system is called memory
allocation.
 The memory management system keeps the table.
 The table indicates which parts of memory are available and which are
occupied.
 The criteria for selecting a particular block is replaced Is indicated by the
replacement policy.
Non-preemptive allocation:
First fit:
 In this algorithm, searching is started either at the beginning of the memory
or where the previous first-fit search ended.
 In this algorithm the first free memory block which is big enough is allocated to
the block
k. The searching process is stopped as soon as a free memory block with enough
space is allocated.
Best fit:
 In this algorithm, all free memory blocks are searched and smallest free
memory block which is large enough to accommodate desired k Block is used
to allocate k.
 This algorithm uses free memory space more efficiently than first-fit algorithm.
 The Fig 2.24 Shows the allocation of memory blocks using first fit and best fit
algorithms.

Fig: 2.17 Non-Preemptive Memory Allocations


Preemptive Allocation:
 Non-preemptive allocation cannot make efficient use of memory in all situations.
 Much more efficient use of the available memory space is possible if the
occupied space can be reallocated to make room for incoming blocks.
 Reallocation of the blocks can be done by a method is called Compaction.

2.7 SYSTEM BUS STRUCTURE


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 The following figure 2.18 illustrates the
College fundamental structure of a system
Microcontroller
bus and its relationship to be various components if the computer system.
 The complexity of the bus control logic depends in the amount of
translation needed between the system bus and the pins on the CPU.

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 All of the address and data lines and most of the control lines use are capable
of being logically disconnected from the CPU or bus control logic.
 The timing of the signals within the CPU and bus control logic is controlled by a
clock.
 The bus cycles and CPU activity are controlled by ground of clock pulses.
 The CPU on put is transaction would processed by outputting the address of
the data during first clock cycle.
 Read is to take place during the second clock cycle.
 Waiting an intermediate number of clock cycles for the addressed device to
put the data on the data lines, inputting the data and signaling the device
that the transfer is complete during the last clock cycle

Fig: 2.18 Typical System bus Architecture

2.8 MULTIPROCESSOR CONFIGURATIONS


2.8.1 Definition:
 If a microprocessor system contains two or more components that can
execute instructions independently, then the system is called multiprocessor
system.
 Multiprocessor system uses a distributed approach.
 Here More than one processor is used to do the subtasks instead of doing
entire task by a single processor.
Advantages:
I. Improves cost/performance ratio of the system.
2. Avoiding the expense of the unneeded capabilities of a centralized system.
3. Tasks are divided among the modules. If failure occurs, it is easier and
cheaper to find and replace the malfunctioning processor.
Types:
 The multiprocessor systems are implemented using one of the two basic
architectures:
 Loosely coupled architecture and closely coupled architecture.
 The systems using these architectures are known as loosely coupled
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Microcontroller

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2.9 COPROCESSOR, CLOSELY COUPLED
AND LOOSELY COUPLED
CONFIGURATIONS
2.9.1 Closely Coupled Multiprocessor Configuration
 In the closely coupled system (CCS) the processors or supporting processors
(coprocessor, math’s processor) share clock generator, bus control logic, and
entire memory and I/O subsystem.
 Such systems communicate through a shared main memory.
 Data can communicate from one processor to the other is on the order of the
bandwidth of the memory.
 Due to memory contentions two or more processors attempt to access the
same memory unit concurrently. When high-speed or real-time processing is
desired. Closely coupled systems (CCS) may be used.
There are two models of a CCS:
1. CCS without private cache
2. CCS with private cache.
2.9.1.1 CCS without Private Cache
The Fig 2.19 shows the closely coupled multiprocessor system without private
cache.
It consists of processors, M memory modules and C input-output channels.
These units are connected through a set of three interconnection networks, viz.
1. The processor-memory interconnection network (PMIN)
2. The input-output processor interconnection network (IOPIN)
3. The interrupt-signal interconnection network (ISIN)

Fig: 2.19 CCS without Private Cache


 The PMIN is a switch which is used to connect every processor to every
memory module. This switch is P by M crossbar with PM sets of cross points.
 When the crossbar switch is distributed across the memory modules, the
system is known as a multiportedmemory system.
 A memory can satisfy only one processor’s request in a given memory cycle.
Hence, if two or more processors attempt to access the same memory
module, a conflict occurs which is resolved or arbitrated by PMIN.
 To avoid excessive conflicts the number of memory module L is usually as large
as P.
 Another method to minimize conflicts is to associate a reserved storage area
with each processor. This is the unmapped Local memory (ULM).
 ULM is used to store kernel code and operating system tables often used
by the processes running on that processor.
 The IOPIN is used to allow a processor to communicate with an I/O channel
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 The ISIN is used for two purposes: To direct an interrupt to any other
interprocessor network and to initiate hardware alarm in case of processor
failure.

2.9.1.2 CCS with Private Cache


 In the first model (that is without private cache) each memory reference goes
through the PMIN, it encounters delay in the process or memory switch and
hence the instruction cycle time increases.
 The increase in the instruction cycle lime reduces the system throughput.
 This delay can be reduced by associating a cache with each processor to
capture most of the references made by a processor.
 Another advantage of the cache is that the traffic through the crossbar switch
can be reduced, which subsequently reduces the contention at the cross
points.

Fig: 2.20 CCS with Private Cache


 More than one inconsistent copy of data may exist in the system as this
multiprocessor organization encounters the cache coherence problem.
2.9.1.3 Closely Coupled System using 8086
 The CPU (8086) is the master or host and the supporting processor is the slave.
 Therefore, two 8086s cannot appear in this configuration.
 The CPU provides the bus control logic.
 So the bus request signal from the supporting processor is connected
to the CPU. The Fig. 2.28 shows the simplest form of closely coupled
configuration.

Fig: 2.21 Closely Coupled Configurations


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2.9.1.4
CollegeInteraction between CPU and independent processor
Microcontroller
 In a closely coupled system no special instruction such as WAIT or ESC is used.

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 The communication between host and independent processor is done
through memory space.
 The independent processor then accesses the memory to execute the task in
parallel with the host.
 When task is completed, the external processor informs the host processor
about the completion of task by using either a status bit or an interrupt
request.
Fig. 2.29 shows the interaction between CPU and independent processor
in closely coupled configuration.

Fig: 2.22 Interactions between CPU and Independent Processor


2.9.2 Loosely Coupled Multiprocessor Configuration
 Each processor has a set of input-output devices and a large local memory.
The processor, its local memory and input-output interfaces are together
called computer module.
 Processes which execute on different computer modules communicate by
exchanging messages through a Message Transfer System (MTS).
 The coupling in such a system is very loose. Hence, such systems are also
referred to as distributed systems. The Fig. 2.30 shows nonhierarchical
loosely coupled multiprocessor system.

Fig: 2.23 Loosely Coupled Configurations


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2.9.2.1 Loosely Coupled System using 8086
 It consists of different modules. Each module may consist of an 8086.
 A processor capable of being a bus master, or a co-processor or closely
coupled configuration.
 Normally each processor has its own local memory and I/O devices, to with
other processors do not have direct access. Fig.2.30showsthe loosely
coupled configuration.
2.9.2.2 Advantages of Loosely Coupled System
 Better system throughput by having more than one processor.
 Each processor may have a local bus to access local memory or I/O
devices so that a greater degree of parallel processing can be achieved.
 System structure is more flexible. As the system consist of different
modules, one can easily add or remove modules to change the System
configuration
 A failure in one module normally does not cause a breakdown of the entire
system.
2.9.3 Numeric Processor 8087
The numeric processor 8087 is a coprocessor which has been specially
designed to work under the control of the processor 8086 and to support
additional numeric processing capabilities.
2.9.3.1 Features of 8087
 It can operate on data of the integer, decimal, and real types, with lengths
ranging from 2 to 10 bytes.
 Its instruction set not only includes various forms of addition and
subtraction, but also provides many useful functions such as square root,
exponential, tangent, and so on.
 It is high performance numeric data processor. It can multiply two 64 bit real
numbers in about 27 is and calculate square root in about 36 ps.
 It follows IEEE floating point standard.
 It is multi bus compatible.
2.9.3.2 Pin Diagram of 8087
Fig. 2.31 shows pin diagram of 8087.

Fig: 2.24 Pin Diagram of NOP 8087


The address/data, status, ready, reset, dock, power and ground pins of the
NDP are similar to the 8086 pins. Among the remaining 8 pins, four are not used.
The other pins are as follows:
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1. BUSY:
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 BUSY signal from the 8087 is connected to the TEST input of the 8086.

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 If the 8086 needs the result of some computation that the 8087 is doing
before it can execute next instruction in the program.
 A low on the 8087 BUSY output indicates that the 8087 has completed the
computation
2. RQ / GT0
 This request / grant signal from the 8087 is usually connected to the request /
grant (RQ
/ GT0 or RQ / CT1) pin of the 8086.
3. RQ / GT1:
 This request / grant signal is connected to the request I grant pin of the
independent processor such as 8089.
4. INT:
 The interrupt pin is connected to the interrupt management logic.
 The 8087 can interrupt the 8086 through this interrupt management logic
at the time, error condition exists.
5. S0 - S2: These are the status bits of 8087 which arc encoded as follows:
S2 S1 S0 Status
0 X X unused
1 0 0 unused
1 0 1 read memory
1 1 0 write memory
1 1 1 passive
6. QS0- QS1: These signals give the queue status as follows:
QS1 QS0 Operation
0 1 no operation
0 1 first byte of opcodefrom Queue
1 0 queue empty
1 1 subsequent byte from the
queue
2.9.3.3 8087 Architecture

Fig: 2.25 Block Diagram of 8087


2.9.3.3.1 Instruction Queue
 It maintains a 6 byte instruction queue and tracks a execution sequence of the
host.
 The 8087 decodes the external opcode to perform the specified operation
and captures the operand address.
2.9.3.3.2 Data Registers
 It has 8 data registers.
 Each register is 80-bit and it is accessed as a stack.
 An operand may be pushed or popped from top of stack.
 ‘Push’ operation decrements TOP of stack by 1 and loads a value into
the new top register.
 A ‘pop’ operation stores the value from the current top register and then
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Microcontroller
13, 12 and 11 of the status register.

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2.9.3.3.3 Status Registers
 The status register is 16 bit register.
 It indicates various errors, stores condition code for instructions,
 Fig 2.33 shows the bit definitions of the Status Register.
Error Flags
1) IE: An invalid operation such as stack overflow, stack underflow, invalid
operand, square root of a negative number etc.
2) DE: The operand is not normalized.
3) ZE: A divide by zero error.
4) OE:An exponent overflows error.
5) PE: A precision error.
Interrupt Flag:IR:indicatesthe existence of the interrupt request.
Condition Code
 C0 - C3 indicates the condition code.
 The condition codes are set by the compare and examine instructions.
Stack Bits
 ST: S0-S2 indicates the top of stack.
Busy Status:
B: Indicates current operation is not completed.

Fig: 2.26 Bit Pattern of Status Register


2.9.3.3.4 Control Register
 The control register is also 16 bit.
 The 8087 provides several processing options which are selected by
loading a word from memory into the control register.
 The control register gives the facility to mask each error type individually
from causing an interrupt
 It can be used to set precision levels, rounding type and infinity
representation. Fig. 2.34 shows the bit definition of control register.

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 1.
Fig: 2.27 Bit definition of control register

 Bits 5-0 of the control registers contain individuals masks for each
of the six exceptions
 Bit 7 contains a general mask bit for all 8087 interrupts.
 The high order byte of the control register configures the 8087
operating mode including precision, rounding, and infinity controls.
After reset or initialization of the 8087, these bits are PC = 11, RC= 00, IC =0, IEM = 0
and all error mask bits are

Tag Register: TAG register holds the status of the contents of data
register. This includes
0 0– Data Valid
0 1 - Zero
1 0 – A special value
1 1 - Empty
2.9.3.4 Data Formats and Conversions of 8087:
The 8087 can operate on memory operands of seven different data types:
1) Word integer
2) Short integer
3) Long integer
4) Packed BCD
5) Short real
6) Long real
A real format is divided into three fields:
 Sign
 Exponent
 Mantissa.
Real number n = sign x mantissa.
 To convert any number to real format, we have to move the decimal point
to the right of the most significant, non zero digit.
 This process of moving the decimal point to the right of the most
significant, nonzero digit is referred to as Normalization.
The 8087 recognizes three real data types:
1) Short real (32-bit)
2) Long real (64-bit)
3) Temporary real (80-bits)
Format has field:sign, exponent and mantissa.

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Fig: 2.28 Data Format of NDP 8087


Example 1: Convert 125912510 in short real, long real and temporary real formats

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2.9.3.5 Stacks in 8087
 The 8087 has a 3-bit stack pointer which holds the number of the register
which is the current top-of-stack.
 When the 8087 is initialized, the 3-bit stack pointer in the 8087 is loaded
with 000 that indicates register C) is a top of stack.
 As shown in Fig. 2.36, the stack of 8087.When 8087 reads the first number,
stack is decremented to 111(7) and the number is stored in register number
111(7), now register 7 is the top of stack.

Fig: 2.29 Register Stack in 8087


2.9.3.6 Instructions in 8087
The 8087 instructions, which can be divided into six groups.
1) Data transfer instructions
2) Arithmetic instructions
3) Compare instructions
4) transcendental instructions
5) Load constant instructions
6) Processor control instructions.
2.9.3.6.1 Data Transfer Instructions
a) Real Transfers
FLD source:
 Decrements the stack pointer by one and copies a real number from a slack
element or memory location to the new ST.
 A short-real or Long-real number from memory is automatically converted
to temporary real format by the 8087 before it is put in ST.
Exceptions: I, D.
Examples:
FLD ST (2) ; Copies ST(2) to ST
FLD [BX] ; Number from memory pointed by BX copied to ST
FST destination:
 Copies ST to a specified stack position or to a specified memory location.
Exceptions: 1, 0, U. P.
Examples:
FST ST (3) ; Copy ST to ST(3)
FST [BX] ; Copy ST to memory pointed by IBXI
FSTP destination:
 Copies ST to a specified stack element or memory location and increments the
stack
pointer by one to point to the next element on the stack.
 This is a stack POP operation.

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2.9.3.6 .2 Arithmetic Instructions
a) Addition
FADD destination, source:
 Adds real number from specified source to real number at specified destination.
 Source can be stack clement or memory location.
 Destination must be a stack element
Exceptions: I, D, O, U, P.
Examples:
FADD ST(2), ST ; Add ST to ST(2), result in
ST(2) FADD ST. ST(5) ; Add ST(5) to ST.
result in ST FADD SUM ; Real number from
memory + ST FADD ; ST + ST(1), pop stack-result
at ST FADDP destination, source:
 Adds ST to specified stack element and increments stack pointer b one.
Exceptions: I. D, O, U, P.
Example:
FADDP ST(2) ; Add ST(2) to ST.
Increment stack pointer so ST(2) becomes ST.
FIADD source:
 Adds integer from memory to ST, stores the result in ST.
Exceptions: I, D, O, P.
Example
FIADD CARS_SOLD ; Integer number from memory + ST
b) Subtraction
FSUB destination, source:
 Subtracts the real number at the specified source from the real number at
the specified destination and puts the result in the specified destination.
Exceptions: I, D O, U, P.
Examples:
FSUI3 ST (3), ST ; ST(3) - ST(2) - ST
FSUL3 DIFFERENCE ; ST * ST - real from
memory FSUI3 ;ST* {ST(1)-ST)
FSUBP destination, source:
 Subtracts ST from specified stack element and puts result in specified
stack element. Then increments stack pointer by one.
Exceptions: I, D, 0, U, P.
Examples
FSUBP ST (2) ; ST (2) - ST. ST (l) becomes new ST.
FISUB source:
 Subtracts integer number stored in memory from ST and stores result in ST.
Exceptions: I, D,O, P.
Example
FISUB DIFFERENCE ; ST ST - integer from memory
C) Reversed Subtraction
FSUBR destination, source
FSUBRP destination, source
FISUBR source
 These instructions operate same as the FSUB instructions.
 Subtract the contents of the specified destination from the contents of
the specified source and put the difference in the specified destination.
d) Multiplication
FMUL destination, source:
 Multiply real umber from source by real number from specified destination,
and put result in specified stack element.
Exceptions: I, D, O, U, P.
FMUL ST(2), ST ; Multiply ST(2) and ST. result in ST(2)
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FMUL ST,ST(5) ; Multiply ST(5) to ST. result in ST
2.9.3.6.3 Compare instructions
 Compares the contents of ST with contents of specified or default source.
 The source may be another stack element or real number in memory.
 These compare instructions set the condition code bits C3, Q, and CO of the
status word shown in Table:2.7

Table 2.7 C3, Q and CO Status word


2.9.3.6.4 Processor Control Instructions
 These instructions do not perform computations.
 They are used to do tasks such as initializing the 8087, enabling interrupts,
writing the status word to memory, etc.
FINIT / FNINT:
 Initializes8087. Disables interrupt output, sets stack pointer to register 7, sets
default
status.
FDIS / FNDISI:
 Disables the 8087 interrupt output pin so that it cannot cause an interrupt
when an exception (error) occurs.
FENI / FNENI:
 Enables 8087 interrupt output so it can cause an interrupt when an exception
occurs.
FLDCW source:
 Loads a status word from a memory location into the 8087 status register.
 This instruction should be preceded by the FCLEX instruction to prevent a
possible exception response
FSTCWIFNSTCW destination:
 Copies the 8087 control word to a memory location. Determine its current
value with 8086 Instructions.
FSTSW / FNSTW destination:
 Copies the 8087 status word to a memory location.
FCLEX/FNCLEX:
 Clears all of the 8(187 exception flag bits in the status register. Un asserts
BUSY and
INT outputs.
FSAVE / FNSAVE destination:
 Copies the 8087 control word, status word, pointers, and entire register stack
to 94-byte area of memory.
FRSTOR source:
 Copies a 94-byte area of memory into the 8087 control register, status
register. pointer registers, and stack registers.
FSTENV / FNSTENV destination:
 Copies the 6087 control register, status register, tag words, and exception
pointers to a series of memory locations.
FLDENV source:
 Loads the 8087 control register, status register, tag word, and exception
pointers from a named area in memory.
FINCSTP:
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 Increment the 8087 stack pointer by one.
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2.9.3.7 I/O Processor 8089

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 Microprocessor can transfer data with input/output ports. Here
Microprocessor is required to set up and perform the actual transfer.
 For high speed data transfers CPU uses the DMA controller to transfer data.
 But microprocessor still needs to set up the device controller, initiate the
DMA operation, and examine the post transfer status after the completion of
each DMA operation.
 Fig. 2.37 (a) shows input/output handled by microprocessor with DMA controller.

Fig: 2.30 I/O Handled by Microprocessor


2.9.3.7.1 Features:
An IOP can fetch and execute its own instruction.
Instructions are design for I/O processing
8089 can perform arithmetic and logic operations, branches, searching, and
translation. IOP does all work involved transfer.
IOP can transfer data from an 8bit source to 16 bit
destination Communication through memory based control
blocks.
IOP supports multiprocessing environment.
IOP and CPU can do processing simultaneously.
CPU defines tasks in the control blocks to locate a program sequence called
a channel program.
2.9.3.7.2 Architecture of 8089
The following diagram shows the internal block diagram of the 8089.
a) Channel Registers
 Fig. 2.38Internal block diagram of 8089. Each channel has an identical set
of registers. Each set is divided into two groups
1. Pointer (20-bit) - GA, GB, GC, TP, PP
2. Register (16-bit) - IX, BC, MC, CC
 Each pointer register, except PP is assigned with a tag bit.
 Tag bit indicates whether the contents of pointer register represent 20-
bit memory address (tag = 0) or a 16-bit I/O address (tag = 1).
 P register is always used to address memory. i.e. 20-bit address.
 The registers GA, GB, CC, BC, IX and MC can be used as general purpose
registers in a channel program to do arithmetic and logic operations and

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Fig: 2.31 Internal Block Diagram 0f 8089

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b) Addressing Memory Operands
 GA, GB, CC, and PP can be used as a base pointer for accessing memory
operands.
C) DMA operation
1. GA and GB:
 GA and GB are used as source and destination pointers.
 If GA points to source, GB points to destination, and vice versa.
2. GC:
 When a translation operation is performed along with a DMA transfer, CC
stores the base address of 256 byte.
3. BC:
 BC is used as a byte counter.
 It is decremented by 1 after each, byte transfer and 2 after each word transfer.
4. MC:
 MC is used for mask compare operation.
 MC stores the byte to be compared in its lower byte and mask pattern in
the higher byte.
5. IX:
 IX register is used as an index register.
6. TP:
 TP is a task pointer
 Stores the address of the next instruction to be executed.
 It has a TAG bit to indicate whether the next instruction is stored in the
system or I/O space.
7. PP:
 PP is a parameter pointer.
 It is automatically filled by 8089 at the time of initialization of a task.
 It stores an address of the parameter block.

Fig: 2.32 Channel control Register

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2.10 INTRODUCTION TO ADVANCED PROCESSORS
2.10.1 Limitations of 80286:
1. Slow processing speed
2. Less addressing capacity
3. Smaller data paths
4. Not able to do floating point arithmetic on its own
5. Lack of security mechanism required for multiuser and multitasking
environment
6. Not able to do parallel processing
7. Lack of enhanced pipelined architecture
8. Lack of powerful instruction set which can support operating system
9. Does not support paging and virtual addressing
10.Does not support branch predictions to improve overall operation speed.
2.10.2 Features
1) The 80286 is a 16-bit processor. The 16-bit ALU allows to process 16-bit data.
2) It has 24-bit address bus. It can access up to 16 Mbytes (224) of physical
memory or 1 Gigabyte (2°) of virtual memory.
3) The 80286 can be operated at three different clock speeds. These are 4 MHz
(80286-4), 6 MHz (80286-6), and 8 MHz (80286).
4) The 80286 includes special instructions to support operating systems.
5) The 80286 is housed in a 68-pin leadless flat package.
6) It contains four separate processing units. These are the Bus Unit
(BU), the Instruction Unit (lii), the Address Unit (AU) and the
Execution Unit (EU
7) The 80286 microprocessor is compatible with their earlier 8086, 8088,
80186 and
80188 chips.
8) It has virtual memory-management circuitry and protection circuitry.
2.10.3 Block Diagram of 80286:
Fig. 2.40 shows the block diagram of Intel 80226 microprocessor. The
80286 is divided into four sub units:
 Bus Unit (BU)
 Address Unit (AU)
 Execution Unit (EU) and Instruction Unit (lU)
Bus Unit:
 It includes address latches and data transceivers, bus interface and
control circuitry, instruction pre fetches and a 6 byte instruction queue.
 The Bus unit does all the memory and 1/O read/write operations.
 It pre fetches instruction bytes and puts them in a 6 byte pre fetch queue.
 The Bus unit is responsible for the transfer of data to and from the
processor extension devices

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2. Address Unit:
 It includes the segment registers (same as on 8086 and 80186), an offset
adder and a physical address adder.
 The 80286 can be operated in two memory addressing modes:
1) Real address mode
2) Protected virtual address mode.
 The address unit computes 20-bit physical address based on the 16-bit
contents of a segment register and a 16-bit offset just like an 8086.
 The CS, DS, SS and ES registers are used to hold the base addresses for the
segments currently in use.
 The instruction pointer IP, stack pointer SP is used to hold the offset for
code segment and stack segment respectively.
3. Execution Unit:
 The execution unit includes ALU, registers (same as on 8086 and 80186) and
the CPU.
 The registers consists general purpose registers, index registers, pointer
registers, flag register and the 16-bit machine status word (MSW) register.
4. Instruction Unit:
 It includes an instruction decoder and a three decoded instructions queue.
 The instruction unit decodes unto three prefetched instructions and holds
them in the queue.
5. Flag Register:
The flag register of 80286 consists of two new flags:

Fig: 2.34 Bit Patterns of 80286 status word and flag register
 NT (Nested flag): This flag is set when one system task invokes another
task.
 IOPL (110 Privilege level) : The two bits in the IOPL are used by the
processor and the operating system to determine your application’s
access to I/Facilities.

2.10.4 Operating Modes of 80286

2.10.4.1 80286 Real Address Mode


 It can access up to 1 Mbyte of physical memory.
 Physical memory addresses are produced directly by adding an offset to
a segment base.
 The interrupt vector table of the 80286 is located in the first 1 Kbyte of memory.

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The table 2.8shows the 80286 interrupt types and their vector locations.

Table 2.8 Interrupt Types


2.10.4.2 80286 Protected Virtual Address Mode (PVAM)
 The protection bit of the machine status word, (MSW) it is possible to
switch operation mode from REAL to PVAM.
 The Protected Virtual Address Mode (PVAM) provides memory management,
protection, task switching and interrupt processing.
 The Protected Virtual Address Mode is also called protected mode.
2.10.4.3 Physical Address Generation
 Its virtual address consists of a16-bit selector and 16-bit offset.
 The memory management unit (MMU) uses 14 most significant bits.
 The descriptor contains the 24-bit physical base address, the privilege level,
and some control bits for the segment.
 If the memory access meets the privilege level test and the segment is
present in the physical memory.
 The MMU will add the 16-bit offset to the 24-bit base address from the
descriptor to produce the 24-bit physical address.

Fig: 2.35 Physical address generation mechanisms


2.10.4.4 Segment Descriptors:
 Each 80286 descriptor describes a 64-Kbyte memory segment and the 80286
allows16K (2N) descriptors.
 The size of the each descriptor in the descriptor table is 8 byte.

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 The 80286 has segment descriptors for code, stack and data segments,
and system control descriptor for special system data segments and control
transfer operations.
 Fig. 2.43 shows the code/data segment and system segment descriptors.
 P bit indicate whether the segment is present in the physical memory or not.
 DPL gives the descriptor privilege level.
 Type field indicates the type of segment such as executable, readable,
conforming, and writeable, expand down, and expand up .
 Base field gives 24-bit segment base address and limit field specifies the
maximum length of the segment.

Fig: 2.36 Descriptors


2.10.5 80386 Microprocessor
A feature of the 80386DX is its ability to operate in three different modes:
 Real Address Mode
 Virtual 8086 Mode
 Protected Virtual 8086 Mode.
2.10.5.1 80386 Features:
1) The 80386 is a 32-bit processor. The 32-bit ALU allows to process 32-bit data.
2) It has 32-bit address bus.
3) The 80386 runs with speed up to20 MHz instructions per second.
4) The pipelined architecture of the 80386, allows simultaneous
instruction fetching, decoding, execution and memory management.
5) It allows programmers to switch between different operating systems
6) It can operate on 7 different data types:
a. Bit b. Byte c. Word d. Double word e. word f. Quad word g. Ten byte.
7) The 80386 can operate in real mode, protected mode or a variation of
protected mode called virtual 8086 mode.
8) The 80386 microprocessor is compatible with their earlier 8086, 8088.
2.10.5.2 Architecture of 80386DX
The internal architecture of the 80386 consists of six functional units:
1) Bus Interface Unit
2) Code Fetch Unit
3) Instruction Decode Unit
4) Execution Unit
5) Segmentation Unit
6) Paging Unit
These units operate in parallel. Fetching, decoding, execution, memory
management and bus accesses for several instructions are performed
simultaneously. This parallel operation is called pipelined instructions processing.
Fig. 2.45 shows instruction pipelining in 80386.
i) Bus Interface Unit
it provides a full 32-bit bi-directional data bus and 32-bit address
bus. The bus Interface unit is responsible for following
operations:
1) It accepts internal requests for code fetch and for data transfers
from the code fetch unit and from the execution unit.
2) It sends address, data and control signals to communicate with
memory and I/O devices.

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4) It also provides the address relocation facility.

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Fig: 2.37 Block Diagram for 80386


ii) Code Prefetch Unit
 The code prefetch unit fetches sequentially the instruction byte stream from the
memory.
 The code prefetch unit uses bus interface unit to fetch instruction bytes.
 These prefetched instruction bytes are stored in the 16-byte code queue.
 If memory access is without any wait state, prefetch activity never delays
execution.
 Due to prefetch activity processor spends practically zero time waiting
for the next instruction.

Fig: 2.38 Instructions Pipelining in 80386


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Fig: 2.39 Functional units of 80386


iii) Instruction Decode Unit
 The instruction decodes unit takes Instruction bytes from the code prefetch
queue and translates them into microcode.
 The decoded instructions are then stored in the instruction queue.
iv) Execution Unit
 The execution unit reads the instruction from the instruction queue and
executes the instructions.
 It consists of three subunits: Control Unit, Data Unit and Protection Test Unit.
1. Control Unit:
 It contains microcode and special hardware.
 The microcode and special hardware allows 80386DX to reduce time
required for execution of multiply and divide instructions.
 It also speeds the effective address calculation.
2. Data Unit:
 The data unit contains the ALU, eight 32-bit general purpose registers
and a 64-bit barrel shifter.
 The barrel shifter is used for multiple bit shifts in one dock.
 The entire data unit is responsible for data operations requested by the control
unit.
3. Protection Test Unit:
 The protection test unit checks for segmentation violations under the
control of the microcode.
 The execution unit partially supports pipelining.
 It overlaps the execution of any memory reference instruction with
the previous instruction.
v) Segmentation Unit
 The segmentation unit translates logical addresses into linear.
 The segmentation unit compares the effective address for the length limit.
 The segment unit adds the segment base and the effective address to
generate linear address.
vi) Paging Unit
The paging unit translates linear addresses generated by the segmentation
unit or the code prefetching unit into physical addresses.
vii) 80386 Functional Units
Bus Interface Unit:
 Responsible for memory access, I/O access, and coprocessor interface
and address relocation.
Code Prefetch Unit:
 Responsible for instruction fetch
Instruction Decode Unit:
 Responsible for instruction decode
Execution Unit:
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 Execute instruction with the help of control, Data and Protection Unit
Segmentation Unit:
 Translates Logical address to, linear address and provides segment level
protection.
2.9.2.3 Register set of 80386:
The 80386 register set can be categories according to their usage.
1) General purpose registers
2) Segment registers
3) Index, pointers and base registers
4) Flag registers
5) System address registers
6) Control registers
7) Debug registers
2.10.6 80486 Microprocessor:
2.10.6.1 80486 Processor Features
1. It is a highly integrated device containing about 1.2 million transistors.
2. The 80486 operates on 25 MHz, 33 MHz, 50 MHz, 66 MHz or 100 MHz
3. It has built-in math coprocessor.
4. 80486 is a 32-bit architecture with on-chip memory management
and cache memory units.
5. On-chip cache memory allows reducing accesses to the external bus.
6. MMU consists of segmentation unit and paging unit.
7. The MMU provides four levels of protection
8. The 80486 has three modes of operation: Read mode, protected
mode and Virtual 8086 mode.
9. It is available in two versions: 80486 DX and 80486SX.
10. Most of the 80486 instructions require only one clock instead of
two clocks required by the 80386.
11.It supports five-stage instruction pipeline scheme
12.It executes conditional JUMP instructions more efficiently.
13. It has built-in parity check/generator unit to implement parity
detection and generation for memory reads and writes.
14.It supports burst mode memory reads and writes to implement fast cache
fills.
15.It executes a few new instructions that control the internal cache
memory and allow addition (XADD) and comparison (CMPXCHG) with an
exchange and a
16.It supports built-in-self-test.
17.It has additional test registers (TR3 - TR5) to test the cache memory.
2.10. 6.2 Block Diagram of 80486
 The Fig. 2.60 shows the block diagram of the internal architecture of the 80486.
 It consists the execution unit, segmentation unit, paging unit, bus interface
unit, prefetch unit and decode unit are similar to the 80386 architecture.
 The code queue in the prefetch unit has been doubled in size to 32 bytes.
 This allows more instructions to be held on chip ready for decode and execution.
 Also an improved algorithm is now used by the translation look aside buffer in
the paging unit.
 Finally, the bus interface unit has been modified to give the 80486.
 Architecture a much faster and more versatile processor bus.
 It is supported with additional parity checker/generator.
 Parity checker/generator generates parity during each write cycle. Parity is
generated as an even parity and parity bit is provided for each byte of
memory
 The cache unit of 80486 consists of an 8 Kbyte code and data cache.
Faster Floating Point Unit:
 The floating-point unit has been completely redesigned over the 80486 CPU.
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 Faster algorithms provide up to ten tines
College speed-up for common
Microcontroller
operations including add, multiply, and load.
Improved Cache Structure:

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 Pentium processors include separate code and data caches integrated on-
chip to meet performance goals.
 Each cache is 8 Kbytes in size, with a 32-by Look aside Buffer TLB) to
translate linear addresses to physical addresses.
 The data cache tags are triple ported to support two data transfers aid an
inquire cycle in the same clock.
 Individual pages can be configured as cacheable or non-cacheable by
software or hardware. The caches: A be enabled or disabled by software or
hardware.
Dual Integer Processor:
 Pentium processor has a dual integer processor.
 It allows execution of two instructions per clock.
Branch Prediction Logic:
 The Pentium uses technique called branch prediction to check whether a
branch will be valid or invalid.
Data Integrity and Error Detection:
 The Pentium processors are added significant data integrity and error
detection capability. Data part checking is still supported on a byte-by-byte
basis.
 parity checking, and internal panty checking features have been added alone
with a new exception, the machine check exception.
Functional Redundancy Checking:
 The Pentium processors have implemented functional redundancy checking
 To execute in lock step with the “master’ processor.
 The checker applies the masters outputs and compares those values with the
values the computes internally, and asserts an error signal if a mismatch
occurs
Enhancement Virtual 8086 Mode:
 To increase performance by reducing the number of times it is necessary
to trap to a virtual 8086 monitor.

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Microcontroller

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Superscalar Processor:
 Processors capable of parallel instruction execution of multiple instructions
are known as superscalar processors.
 Executing two integer or two floating point instructions simultaneously
and thus it support superscalar architecture.

2.10.7 Pentium Processor Architecture


 Fig. 2.62 shows internal architecture of Pentium program.
 There are two pipelines, the U pipeline and the V pipeline.
 The U-pipeline can execute all integers and floating point instructions.
 The V pipeline can execute simple integer instructions and the FXCH
floating-point instructions.
Bus Unit
It consists of following functional entities:
Address Driven and Receivers:
 During bus cycles the address drivers push the address onto the
processors local address bus (A31:A3 and BE7:BE,,).
 The address bus transfers addresses back to the Pentium address
receivers during cache snoop cycles.
 Only address lines A31:A5 are input during cache snoop cycles.
Write Buffers:
 The Pentium processor provides two write buffers, one for each of the
two internal execution pipelines.
 This architecture improves performance when back-to-back writes occur.
Data Bus Transceivers:
 The transceivers send data onto the Pentium processors local data bus
during write bus cycles.
 Receive data into the processor during read bus cycles.
Bus Control Logic:
 The Bus Control Logic control whether a standard or burst bus cycle is to be run.
Bus Master Control:
 Bus Master control signals allow the processor to request the use of the
Level Two (U) Cache Control:
 The Pentium processor includes the ability to control a (secondary)
external cache operation.
Internal Cache Control:
 Internal Cache Control logic monitors input signals to determine when to
snoop the address bus and outputs signals
Parity Generation and Control:
 It generates even data parity for each of the eight data paths
 It also generates a parity bit for the address during write bus cycles

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Fig: 2.41 Block Diagram of Pentium processor


Code Cache
 It holds copies of the most frequently used instructions,
 It is dedicated to supplying instructions to each of the processor’s execution
pipelines.
 The cache is organized as a two-way set associative cache.
Prefetcher
 Prefetcher requests for Instructions from the code cache.
Prefetch Buffers
 Pentium provides four prefetch buffers.
 They work as two independent pairs. When instructions are prefetchedfrom
the cache, they are placed into one set of prefetchbuffers
Instruction Decode Unit
1. Pentium provides two stage decoding.
2. The instructions are decoded in two stages known as Decode I (Dl) and Decode
2 (D2).
Control Unit
 It is also referred to as the Microcode Unit. This control unit consists of the
following sub- units:
1) Microcode Sequencer
2) Microcode Control ROM
Arithmetic Logic Units (ALUs)
 Pentium provides two ALUs to perform the arithmetic and logical operations.
 The ALU for the UM pipeline can complete and operation prior to the ALU
in the “V” pipeline,

*****

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Part-A (2 Marks Questions and Answers)

1. What are tightly coupled systems or closely coupled systems? (Apr/May2019)


In a tightly coupled systems the microprocessor (either coprocessor or
independent processors may share a common clock and bus control logic. The two
processors in a closely coupled system may communicate using a common system
bus or common memory.

2. What are loosely coupled systems?


In loosely coupled systems each CPU may have its own bus control logic. The
bus arbitration is handled by an external circuit, common to all processors. The
loosely coupled system configuration like LAN & WAN can be spreader over a large
area.

3. Write some advantages of loosely coupled systems over tightly coupled systems
More number of CPUs can be added in loosely coupled systems to improve the
system performance. The system structure is modular and hence easy to maintain and
troubleshoot.
A fault in a single module does not lead to a complete system breakdown.
Due to the independent processing modules used in the system, it is more fault
tolerant, more suitable to parallel applications due to its modular organizations.

4. Draw the format of flag register. (Apr/May2019)

5. What are the multi microprocessor configuration methods?


Tightly coupled systems or closely coupled systems
Loosely coupled systems

6. What is meant by Daisy chaining method?


It does not require any priority resolving network, rather the priorities of all
the devices are essentially assumed to be in sequence. All the masters use a single
bus request line for requesting the bus access. The controller sends a bus grant
signal, in response to the request, if the busy signal is inactive when the bus is free.

7. What is independent bus request scheme?


Each of the masters requires a pair of request and grant pins which are
connected to the controlling logic. The busy line is common for all the masters. The
controlling logic receives a request on a bus request line, it immediately grants the
bus access using the corresponding bus grant signal, provided the BUSY line is
inactive, and then grants the request. This is quite fast, because each of the
masters can independently communicate with the controller.

8. List the modes of operations? (Nov/Dec 2017)


 Maximum mode
 Minimum mode
9. What is meant by polling?
In polling schemes, a set of address lines is driven by the controller to
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address
College each of the masters in sequence. When a bus request is received from a
Microcontroller
device by the controller, it generates the address on the address lines. If the
generated address matches with that of the requesting masters, the controller
activates the BUSY line.

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10. Name the data types of 8087.
 Binary integer
 Word
 Short
 Long
 Packed decimal number(BCD)
 Floating point /real number
 Short
 Long
 Temporary real

11. What is meant by Multiprogramming? (April/May 2017)


Two or more processes code is stored in memory at the same time and is
executed in a time multiplexed manner that system is called as
multiprogramming.
12. What are the three basic Multiprocessor Configurations that the 8086 can
support?
i. Coprocessor Configuration
ii. Closely Coupled Configuration
iii.Loosely Coupled Configuration

13. What do you meant by Numeric Data Processor?


Numeric Data Processor is specially designed to perform arithmetic
operations efficiently. It adds arithmetic, trigonometric, exponential and logarithmic
instructions to8086/8088 instruction set for all data types.

14. What are the functional blocks of 8089?


a. I/O Channels
b. Channel registers
c. Control Logic
d. Channel Control Pointer
e. ALU

15. Define coprocessor (/May/June’13)


A processor, which can be connected with the main processor in a parallel
manner, in order to do some complex problems, referred to as co-processor.

16. List the advantages of co-processor (/May/June’14)


 Speed operation
 Can solve complex problems
 Can be acted as such processor

17. Write some examples for advanced processors.(April/May &Nov/Dec 2017)


 80286
 80386
 80486
 Pentium processor

18. How does CPU differentiate the 8087 instructions from its own instructions
(May/June’12)
The 8087 instructions can be distinguished from 8086 instructions by letter F
which stands for floating point number. All mnemonics in 8087 begins with the
letter F.

19. What are the modes of operation of 8087? (May/June’13)


The modes of operation of 8087 are Real Mode, Protected mode and Virtual mode
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20. How 8089 operates in loosely coupled configuration and tightly coupled
configuration (May/June’14)
In 8086 is used in its maximum mode. The 8089, 8086 reside on the same
local bus, sharing the same set of system buffers.

21. In what ways are the standard microprocessor and coprocessor differ from each
other (Nov/Dec’13)
A processor provides auxiliary functions or features that the main processor
does not have. These might include floating point support or hardware encryption. A
coprocessor is generally not usable without its main processor, whereas a processor
may function in a crippled or less powerful form without a coprocessor.

22. What do you meant by CCW in an I/O processor? (Nov/Dec’14)


CCW is the first byte of the control block, which indicates the action to be
taken by the channel. CCW consists of Parity bit, Zero, Bus load limit, interrupt
control field, common field

23. Compare closely coupled configuration features with loosely coupled


configuration features. (May/June’12)

SI.No Closely Coupled System Loosely Coupled System


1 It has common memory Each processor have own
private local memory
2 System structure is less flexible System structure is more flexible
3 Parallelism can be implemented Parallelism can be
less efficiently implemented more
efficiently
4 Information can be shared Information is transferred from
among CPU one processor to other processor

Part-B (16 Marks Questions)

1. Explain in detail about various signals of 8086 microprocessor


(Nov/Dec’12) [Refer Sec:2.1]
2. Draw the internal block diagram of 8087 Co-processor and explain it with
8087 control word and status word formats. (May/June’12) [Refer Sec:
2.9.3.3]
3. Draw the block diagram of 8087 numeric Data processor and explain.
(Nov /Dec’13) (May/June’13) [Refer Sec: 2.9.3]
4. Discuss briefly the instructions supported by 8087 Numeric Data Processor.
(Nov/Dec’13) [Refer Sec 2.9.3.6]]
5. Explain the block diagram of 8089 I/O processor. (Nov/Dec’12, 13) (May/June’
10.12,14) [Refer Sec:2.9.3.7]
6. Explain the salient features of 8087 coprocessor units in architectural diagram
(Nov/Dec’14) [Refer Sec: 2.9.3.3]
7. Describe maximum mode of operation of 8086 (May/June’15) [Refer Sec:2.2.2]
8. Draw and discuss a typical minimum mode 8086 system (May/June’14) [Refer
Sec:2.2.1]
9. Give two examples of 8087 data transfer instructions, arithmetic instructions,
Processor control instructions and transcendental instructions. (May/June’12)
[Refer Sec:2.9.3.6.1]
10. Explain the Closely Coupled configuration with neat diagram.(April/May’17)[Ref 2.9.1]
11.Explain the loosely Coupled configuration with neat diagram.(Nov/Dec’17) [Ref Sec:
2.9.2]
12.Explain the system bus structure of 8086. Draw the timing diagram
for interrupts acknowledgementcycle(April/May’17) (Nov/Dec’17)
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13. Explain the interrupt system based on multiple 8259 with necessary diagram.
(Apr/May2019)

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UNIT 3
I/O INTERFACING

REFERRED BOOK:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family
- Architecture, Programming and Design”, Second Edition, Prentice Hall of
India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly
and C”, Second
1. DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH,2012

STAFF IN-CHARGE HOD

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3.1 MEMORY INTERFACING AND I/O INTERFACING

3.1.1 MEMORY INTERFACING


We have four common types of memory
 Read only memory (ROM)
 Flash memory (EEPROM)
 Static Random access memory (SARAM)
 Dynamic Random access memory (DRAM)
Pin connections
 Common to all memory devices are: The address input, data output or
input/outputs, selection input and control input used to select a read or write
operation.
Address connections
 All memory devices have address inputs that select a memory location
within the memory device.
 Address inputs are labeled from A0 to An.
Data connections
 All memory devices have a set of data outputs or input/outputs.
 Today many of them have bi-directional common I/O pins.
Selection connections
 Each memory device has an input that selects or enables the memory device.
 This kind of input is most often called a chip select (CS), chip enable (CE)
or simply select (S) input.

Fig: 3.1 Memory components illustrating the address, data and control connections
ROM
It read only memory permanently stores programs and data and data was
always
present, even when power is disconnected. It is also called as nonvolatile memory.
RAM
 RAM memory device has either one or two control inputs. If there is one
control input it is often called R/W.
 This pin selects a read operation or a write operation only if the device is
selected by the selection input (CS).
 If the RAM has two control inputs, they are usually labeled WE or W and
OE or G. (WE) write enable must be active to perform a memory write
operation and OE must be active to perform a memory read operation.
 When these two controls WE and OE are present, they must never be active
at the same time.
EPROM
 Erasable Programmable Read Only Memory is also erasable if exposed to
high intensity ultraviolet light for about 20 minutes or less, depending upon
the type of EPROM as shown in figure 3.2.
 We have PROM (Programmable Read Only Memory)
RMM
 Read Mostly Memory is also called the flash memory.
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 The flash memory is also called as an EEPROM (Electrically Erasable
Programmable ROM), EAROM (Electrically Alterable ROM), or a NOVROM
(Nonvolatile ROM).
 These memory devices are electrically erasable in the system, but require
more time to erase than a normal RAM.

Fig: 3.2 Pin configuration of 2716 EPROM

A0 –A10 ADDRESSES
PD/PGM POWER DOWN PROGRAM/
CS CHIP SELECT
O0-O7 OUT PUTS
Table 3.1
Static Random access memory (SARAM)
 Static RAM memory device retain data for as long as DC power is applied.
 Because no special action is required to retain stored data, these devices are
called as static memory.
 They are also called volatile memory because they will not retain data without
power.
 The main difference between a ROM and RAM is that a RAM is written
under normal operation, while ROM is programmed outside the computer and
is only normally read.
 The SRAM stores temporary data and is used when the size of read/write
memory is relatively small.
 The control inputs of this RAM are slightly different from those presented earlier.
 The OE pin is labeled G, the CS pin S and the WE pin W. This 4016 SRAM
device has 11 address inputs and 8 data input/output connections

3.1.2 Block Diagram


Block diagram and pin diagram are shown in figure 3.3 and 3.4.

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Microcontroller

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3.1.3 Pin Diagram

Fig 3.4: Pin configuration of 4016 SRAM

A 0 –A 10 ADDRESSES
_
WRITE ENABLE
W
_
CHIP SELECT
S

DQ 0 - DQ 8 DATA IN / DATA OUT


_
OUT PUT ENABLE
G
Vss GROUND
Vcc + 5 V SUPPLY

Table 3.2
Dynamic RAM
 Whenever a large capacity memory is required in a microcomputer system,
the memory subsystem is generally designed using dynamic RAM because
there are various advantages of dynamic RAM is shown in figure 3.5.
 The basic dynamic RAM cell uses a capacitor to store the charge as a
representation of data.
 This capacitor is manufactured as a diode that is reverse biased so that the
storage capacitance comes into the picture.
 This storage capacitance is utilized for storing the charge representation of
data but the reverse-biased diode has leakage current that tends to
discharge the capacitor giving rise to the possibility of data loss. To avoid this
possible data loss, the data stored in a dynamic RAM cell must be refreshed
after a fixed time interval regularly.
 The process of refreshing the data in RAM is called as Refresh cycle.
 The refresh activity is similar to reading the data from each and every cell of
memory, independent of the requirement of microprocessor.
 During this refresh period all other operations related to the memory
subsystem are suspended.
 Hence the refresh activity causes loss of time, resulting in reduces system
performance.
 However keeping in view the advantages of dynamic RAM, like low power
consumption, high packaging density and low cost, most of the advanced
computing system are designed using dynamic RAM, at the cost of operating
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 A dedicated hardware chip called as dynamic RAM controller is the most
important part of the interfacing circuit. The Refresh cycle is different from
the memory read cycle in the

following aspects.

Fig 3.5: Dynamic RAM controller

3.2 I/O INTERFACING


Input and output ports are shown in figure 3.6 and 6.7
3.2.1 I/O port

Fig 3.6: I/O port


3.2.2 O/P port

Fig 3.7: O/P port


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3.2.3 I/O Interfacing Techniques
I/O devices can be interfaced in two ways
 Memory mapped I/O device.
 Standard I/O mapped I/O of device or isolated I/O mapping.

Table 3.3

3.3 PARALLEL COMMUNICATION INTERFACE


8255 - Programmable Peripheral Input-Output port
The parallel input-output port chip 8255 is also called as programmable
peripheral input-output port.The Intel’s 8255 is designed for use with Intel’s 8- bit,
16-bit and higher capability microprocessors.
It has 24 input/output lines which may be individually programmed in two
groups of twelve lines each, or three groups of eight lines. The two groups of I/O
pins are named as Group A and Group B.
Each of these two groups contains a subgroup of eight I/O lines called as 8-bit
port and another subgroup of four lines or a 4-bit port. Thus Group A contains an 8-
bit port A along with a 4-bit port. C upper
The port A lines are identified by symbols PA0-PA7 while the port C lines are
identified as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing lines
PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper and port C
lower can be used in combination as an 8-bit port C.
Both the port C are assigned the same address. Thus one may have either
three 8- bit I/O ports or two 8-bit and two 4-bit ports from 8255. All of

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independently either as input or as output ports. This can be achieved by
programming the bits of an internal register of 8255 called as control word register
(CWR ).
The internal block diagram and the pin configuration of 8255 are shown in
Figure 3.8(a)
. The 8-bit data bus buffer is controlled by the read/write control logic.
The read/write control logic manages all of the internal and external transfers
of both data and control words. RD, WR, A1, A0 and RESET are the inputs provided
by the microprocessor to the READ/ WRITE control logic of 8255.
Signal description of 8255
PA7-PA0: These are eight port A lines that acts as either latched output or buffered
input lines depending upon the control word loaded into the control word register.
PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or
input buffers lines. This port also can be used for generation of handshake lines in
mode 1 or mode 2.
PC3-PC0 : These are the lower port C lines, other details are the same as PC7- PC4
lines.
PB0-PB7 : These are the eight port B lines which are used as latched output lines or
buffered input lines in the same way as port A.
RD : This is the input line driven by the microprocessor and should be low to
indicate read operation to 8255.
WR : This is an input line driven by the microprocessor. A low on this line
indicates write operation.
CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to
RD and WR signals, otherwise RD and WR signal are neglected.
A1-A0 : These are the address input lines and are driven by the microprocessor.
These lines A1-A0 with RD, WR and CS from the following operations for 8255.
These address lines are used for addressing any one of the four registers, i.e. three
ports and a control word register as given in table below.
In case of 8086 systems, if the 8255 is to be interfaced with lower order data
bus, the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.
D0-D7 : These are the data bus lines those carry data or control word to/from the
microprocessor.
RESET : A logic high on this line clears the control word register of 8255. All ports
are set as input ports by default after reset.
A1 A0 Input (Read) cycle
RD WR CS
0 1 0 0 0 Port A to Data bus
0 1 0 0 1 Port B to Data bus
0 1 0 1 0 Port C to Data bus
1
0 1 0 1 CWR to Data bus

RD WR CS A1 A0 Output (Write) cycle


1 0 0 0 0 Data bus to Port A
1 0 0 0 1 Data bus to Port B
1 0 0 1 0 Data bus to Port C
1 0 0 1 1 Data bus to CWR

CS A1 A0 Function
RD WR
X X 1 X X Data bus tristated

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1 1 0 X X Data bus tristated

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Fig: 3.8(b) Signals of 8255


Fig: 3.8(a) 8255A Pin Configuration

3.3.1 Block Diagram of 8255 (Architecture)


It has
1. Data bus buffer
2. Read Write control logic
3. Group A and Group B controls
4. Port A, B and C
Block Diagram of 8255 (Architecture)

Fig: 3.9 Block Diagram of 8255 (Architecture)


3.3.1.1 Data bus buffer: This is a tristate bidirectional buffer used to interface the
8255 to system data bus. Data is transmitted or received by the buffer on execution
of input or output instruction by the CPU. Control word and status information are
also transferred through this unit.
3.3.1.2 Read/Write control logic: This unit accepts control signals ( RD, WR ) and also
inputs from address bus and issues commands to individual group of control blocks
( Group A, Group B).
It has the following pins.

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 CS – Chip select: A low on this PIN enables the communication between
CPU and 8255.
 RD (Read) – A low on this pin enables the CPU to read the data in the
ports or the status word through data bus buffer.
 WR (Write): A low on this pin, the CPU can write data on to the ports or
on to the control register through the data bus buffer.
 RESET: A high on this pin clears the control register and all ports are
set to the input mode
 A0 and A1 (Address pins): These pins in conjunction with RD and
WR pins control the selection of one of the 3 ports.
3.3.1.3 Group A and Group B controls: These block receive control from the CPU and
issues commands to their respective ports. Group A - PA and PCU (PC7–PC4) Group
B - PCL (PC3 – PC0) Control word register can only be written into no read operation
of the CW register is allowed
 Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be
programmed in 3 modes – mode 0, mode 1, mode 2.
Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be
programmed in mode 0, mode1.
 Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer.
This port can be divided into two 4 bit ports and can be used as control
signals for port A and port
B. it can be programmed in mode 0.

Fig: 3.10 Control Word Format of 8255

3.4 SERIAL COMMUNICATION INTERFACE


 A serial communications interface (SCI) is a device that enables the serial
(one bit at a time) exchange of data between a microprocessor and
peripherals such as printers, external drives, scanners, or mice.
 In this respect, it is similar to a serial peripheral interface ( SPI ). But in
addition, the SCI enables serial communications with another
microprocessor or with an external network.
3.4.1 8251A- Universal Synchronous Asynchronous Receiver Transmitter (USART)
 8251Ais a USART (Universal Synchronous Asynchronous Receiver
Transmitter)for serial data communication.
 As a peripheral device of a microcomputer system, the 8251Areceives
parallel data from the CPU and transmits serial data after conversion.
 This device also receives serial data from the outside and transmits parallel
data to the CPU after conversion.
 The 8251A configures a fully static circuit using silicon gate CMOS
technology. Therefore, it operates on extremely low power at 100 mA (max)
of standby current by suspending all operations.
3.4.2 Features
 Wide power supply voltage range from 3 V to 6 V
 Wide temperature range from –40°C to 85°C
 Synchronous communication up to 64 Kbaud

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 Asynchronous communication up to 38.4 Kbaud
 Transmitting/receiving operations under double buffered configuration.
 Error detection (parity, overrun and framing)
3.4.3 Block diagram of 8251A
8251A Block diagram is shown in figure 3.11

Fig 3.11: Block diagram of 8251A


Data buffer
 Interface the internal bus of 8251 with the system bus
 Control word and status information are also transferred through this unit.
Read/write control logic
 To control the operations of the peripherals operations initiated by CPU.
 This unit select one of the internal address either control address and
data address using C/D signal
 The CPU interface shares common interface signals with the CPU: Data
Bus, Read, Write, Chip selects, Reset and Master CLK.
Transmit control
 Totransmit the data bytes received by data buffer from the CPU
 It decides transmission rate which is controlled by TXC input frequency
 It drive the two transmitter status signals TXRDY,TXEMPTY for CPU handshaking
Transmitter Buffer
 The Transmitter Buffer and Control logic accept parallel data from the Data
Bus Buffer, convert it to serial, inserting required characters or bits
depending on communication protocol, and output the formatted serial
stream to the TxD output pin.
Modem Control Logic
 The Modem Control Logic consists of a set of inputs and outputs that can be
used to interface to almost any modem.
 It handles the modem handshake signals to coordinate the communication
between modem and 8251
Receiver control
 ToReceive the data bytes from the Serial device
 It decides Receiver rate which is controlled by RXC input frequency
 It also drive the two Receiver status signals RXRDY for CPU handshaking
 It also detect the a break in data string in Asynchronous mode
 In synchronous mode it detect SYNC characters using SYNDET/BD

Receiver Buffer
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 The Receiver Buffer and Control accept serial data, convert it to parallel
format, check for parity, framing, overrun, and break.

3.4.4 Pin diagram of 8251A

8251A pin diagram is shown in below fig 3.12

Fig: 3.12 Pin Configuration of 8251A


D0 to D7 (l/O terminal)
 This is bidirectional data bus which receives control words and transmits data
from the CPU and sends status words and received data to CPU.
RESET (Input terminal)
 A “High” on this input forces the 8251Ainto “reset status.” The device waits
for the writing of “mode instruction.” The min. reset width is six clock inputs
during the operating status of CLK.
CLK (Input terminal)
 CLK signal is used to generate internal device timing. CLK signal is
independent of RXC or TXC.
 However, the frequency of CLK must be greater than 30 times the RXC and
TXC at Synchronous mode and Asynchronous “x1” mode, and must be
greater than 5 times at Asynchronous “x16”and “x64” mode.
WR (Input terminal)
 This is the “active low” input terminal which receives a signal for writing
transmit data
and control words from the CPU into the 8251A.
RD (Input terminal)
 This is the “active low” input terminal which receives a signal for reading
receive data
and status words from the 8251A.
C/D(Input terminal)
 This is an input terminal which receives a signal for selecting data or
command words and status words when the 8251Ais accessed by the CPU
.If C/D = low, data will be
accessed. If C/D = high, command word or status word will be accessed.
CS (Input terminal)
 This is the “active low” input terminal which selects the 8251Aat low level
when the CPU accesses.
TXD (output terminal)
 This is an output terminal for transmitting data from which serial-converted
data is sent out. The device is in “mark status” (high level) after resetting or
during a status when transmit is disabled.
 It is also possible to set the device in “break status” (low level) by a command.
TXRDY (output terminal)
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 This is an output terminal which indicates
College that the 8251Ais ready to accept a
Microcontroller
transmitted data character.

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 But the terminal is always at low level if CTS = high or the device was set in
“TX disable status” by a command.
TXEMPTY (Output terminal)
 This is an output terminal which indicates that the 8251Ahas
transmitted all the characters and had no data character.
 In “synchronous mode,” the terminal is at high level, if transmit data
characters are no longer remaining and sync characters are automatically
transmitted.
 If the CPU writes a data character, TXEMPTY will be reset by the leading edge
of WR
signal.
TXC (Input terminal)
 This is a clock input signal which determines the transfer speed of transmitted
data.
 In “synchronous mode,” the baud rate will be the same as the frequency of TxC.
 In “asynchronous mode”, it is possible to select the baud rate factor by mode
instruction.
 It can be 1, 1/16 or 1/64 the TxC. The falling edge of TXC sifts the serial data
out of the
8251A.
RXD (input terminal)
 This is a terminal which receives serial data. RXRDY (Output terminal) this is
a terminal which indicates that the 8251Acontains a character that is ready
to READ.
 If the CPU reads a data character, RXRDY will be reset by the leading edge of
RD signal. Unless the CPU reads a data character before the next one is
received completely.
 The preceding data will be lost. In such a case, an overrun error flag status
word will be set.

RXC (Input terminal)


 This is a clock input signal which determines the transfer speed of received
data. In “synchronous mode,” the baud rate is the same as the frequency of
RxC.
 In “asynchronous mode,” it is possible to select the baud rate factor by mode
instruction. It can be 1, 1/16, 1/64 the RXC.
SYNDET/BD (Input or output terminal)
 This is a terminal whose function changes according to mode. In “internal
synchronous mode.” this terminal is at high level, if sync characters are
received and synchronized.
 If a status word is read, the terminal will be reset. In “external synchronous
mode, “this is an input terminal.
DSR (Input terminal)
 This is an input port for MODEM interface.
 The input status of the terminal can be recognized by the CPU reading status
words.
DTR (Output terminal)
 This is an output port for MODEM interface. It is possible to set the status of
DTR by a command.
CTS (Input terminal)
 This is an input terminal for MODEM interface which is used for controlling a
transmit circuit. The terminal controls data transmission if the device is set in
“TX Enable” status by a command. Data is transmittable if the terminal is at
low level.
RTS (Output terminal)
 This is an output port for MODEM interface. It is possible to set the status RTS
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3.5 A/D AND D/A INTERFACE
3.5.1 Interfacing Analog to Digital Data Converters
 In most of the cases, the PIO 8255 is used for interfacing the analog to digital
converters with microprocessor. We have already studied 8255 interfacing
with 8086 as an I/O port, in previous section. This section we will only
emphasize the interfacing techniques of analog to digital converters with
8255.

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 The analog to digital converters is treaded as an input device by the
microprocessor that sends an initializing signal to the ADC to start the
analogy to digital data conversation process.
 The start of conversation signal is a pulse of a specific duration. The process
of analog to digital conversion is a slow process, and the microprocessor has
to wait for the digital data till the conversion is over.
 After the conversion is over, the ADC sends end of conversion EOC signal to
inform the microprocessor that the conversion is over and the result is ready
at the output buffer of the ADC. These tasks of issuing an SOC pulse to ADC,
reading EOC signal from the ADC and reading the digital output of the ADC
are carried out by the CPU using 8255 I/O ports.
 The time taken by the ADC from the active edge of SOC pulse till the active
edge of EOC signal is called as the conversion delay of the ADC. It may range
anywhere from a few microseconds in case of fast ADC to even a few
hundred milliseconds in case of slow ADCs.
 The available ADC in the market use different conversion techniques for
conversion of analog signal to digitals. Successive approximation techniques
and dual slope integration techniques are the most popular techniques used
in the integrated ADC chip.
3.5.1.1 General algorithm for ADC interfacing contains the following steps:
 Ensure the stability of analog input, applied to the ADC.
 Issue start of conversion pulse to ADC
 Read end of conversion signal to mark the end of conversion processes.
 Read digital data output of the ADC as equivalent digital output.
 Analog input voltage must be constant at the input of the ADC right from the
start of conversion till the end of the conversion to get correct results. This
may be ensured by a sample and hold circuit which samples the analog
signal and holds it constant for specific time duration. The microprocessor
may issue a hold signal to the sample and hold circuit.
 If the applied input changes before the complete conversion process is over,
the digital equivalent of the analog input calculated by the ADC may not be
correct.
3.5.1.2 ADC 0808/0809
 The analog to digital converter chips 0808 and 0809 are 8-bit CMOS,
successive approximation converters.
 This technique is one of the fast techniques for analog to digital conversion.
 The conversion delay is 100μs at a clock frequency of 640 KHz, which is quite
low as compared to other converters. These converters do not need any
external zero or full scale adjustments as they are already taken care of by
internal circuits.
 These converters internally have a 3:8 analog multiplexer so that at a time
eight different analog conversion by using address lines - ADD A, ADD B, ADD
C.
 Using these address inputs, multi-channel data acquisition system can be
designed using a single ADC.
 The CPU may drive these lines using output port lines in case of multi-
channel applications.
Analog / Address lines
select C B A
I/P0 0 0 0
I/P1 0 0 1
I/P2 0 1 0
I/P3 0 1 1
I/P4 1 0 0
I/P5 1 0 1
I/P6 1 1 0
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1 1
Table 3.5

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Block Diagram of ADC 0808/0809

Fig: 3.13 Block Diagram of ADC 0808/0809

Timing Diagram of ADC 0808

Fig: 3.14 Timing Diagram of ADC 0808

Pin Diagram of ADC 0808/0809

Fig: 3.15 Pin diagram of ADC 0808/0809


Vcc : Supply pins +5V
GND : GND
Vref+ : Reference voltage positive +5 Volts maximum.
Vref_ : Reference voltage negative 0Volts minimum.
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I/P0 –I/P7 : Analog inputs
ADD A,B,C : Address lines for selecting analog inputs.
O7-00 : Digital 8-bit output with O7 MSB and O0 LSB
SOC : Start of conversion signal pin
EOC : End of conversion signal pin
OE : Output latch enable pin, if high enables output
CLK : Clock input for ADC
3.5.2 Interfacing Digital to Analog Converters
 The digital to analog converters convert binary number into their equivalent
voltages.
 The DAC find applications in areas like digitally controlled gains, motors
speed controls, programmable gain amplifiers etc.AD 7523 8-bit Multiplying
DAC:
 This is a 16 pin DIP, multiplying digital to analog converter, containing R-2R
ladder for D-A conversion along with single pole double thrown NMOS
switches to connect the digital inputs to the ladder.
Pin Diagram

Fig: 3.16 Pin diagram of AD7523


 The pin diagram of AD7523 is shown in Fig, the supply range is from +5V to
+15V, while Vref may be anywhere between -10V to +10V.
 The maximum analog output voltage will be anywhere between -10V to
+10V, when all the digital inputs are at logic high state.
 Usually a zener is connected between OUT1 and OUT2 to save the DAC from
negative transients.
 An operational amplifier is used as a current to voltage converter at the
output of AD to convert the current output of AD to a proportional output
voltage. It also offers additional drive capability to the DAC output.
Example:
 Interfacing DAC AD7523 with an 8086 CPU running at 8MHZ and write an
assembly language program to generate a saw tooth waveform of period 1ms
with Vmax 5V.
 Solution: Figure 3.17 shows the interfacing circuit of AD 74523 with 8086
using 8255. ASSUME CS:CODE
CODE SEGMENT
START: MOV AL,80h ;make all ports
output OUT CW, AL
AGAIN: MOV AL, 00h ;start voltage for
ramp BACK: OUT PA, AL
INC AL
CMP AL, 0FFh
JB BACK
JMP AGAIN
CODE ENDS
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Fig: 3.17 Interfacing of AD7523

 In the above program, port A is initialized as the output port for sending the
digital data as input to DAC. The ramp starts from the 0V (analog), hence AL
starts with 00H.
 To increment the ramp, the content of AL is increased during each execution
of loop till it reaches F2H. After that the saw tooth wave again starts from
00H, i.e. 0V(analog) and the procedure is repeated.
 The ramp period given by this program is precisely 1.000625 ms. Here the
count F2H has been calculated by dividing the required delay of 1ms by the
time required for the execution of the loop once.
 The ramp slope can be controlled by calling a controllable delay after the
OUT instruction.

3.6 PROGRAMMABLE INTERVAL TIMER


3.6.1 Intel 8253
The Intel 8253 is a programmable counter / timer chip designed for use as an
Intel microcomputer peripheral. It uses nMOS technology with a single +5V supply
and is packaged in a 24-pin plastic DIP. It is organized as 3 independent 16-bit
counters, each with a counter rate up to 2 MHz. All modes of operation are software
programmable. The 82C54 is pin compatible with the HMOS 8254, and is a superset
of the 8253.
3.6.2 Features
The timer has three counters, called channels. Each channel can be
programmed to operate in one of six modes. Once programmed, the channels can
perform their tasks independently. The timer is usually assigned to IRQ-0 (highest
priority hardware interrupt) because of the critical function it performs and because
so many devices depend on it.
3.6.3 Block diagram
The block labeled data bus buffer contains the logic to buffer the data bus to /
from the microprocessor, and to the internal registers.
The block labeled read / write logic controls the reading and the writing of the
counter registers. The final block, the control word register, contains the
programmed information that is sent to the device from the microprocessor.
Each counter in the block diagram has 3 logical lines connected to it. Two of these
lines, clock and gate, are inputs. The third, labeled OUT is an output. The function of
these lines changes and depends on how the device is initialized or programmed

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Fig: 3.18 Block diagram of an 8253 programmable interval timer


3.6.4 PIN Configuration

Fig: 3.19 Pin Configurations


This is the clock input for the counter. The counter is 16 bits. The maximum
clock frequency is 1 / 380 nanoseconds or 2.6 megahertz. The minimum clock
frequency is DC or static operation.

This single output line is the signal that is the final programmed output of the
device. Actual operation of the outline depends on how the device has been
programmed. This input can act as a gate for the clock input line, or it can act as a
start pulse, depending on the programmed mode of the counter.

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3.6.5 Internal 8253 register


Here is a list of the internal 8253 registers that will program the internal
counters of the
8253:

Counter #0, #1, #2 Each counter is identical, and each consists of a 16-bit, pre-
settable, down counter. Each is fully independent and can be easily read by the
CPU. When the counter is read, the data within the counter will not be disturbed.
This allows the system or your own program to monitor the counter's value at any
time, without disrupting the overall function of the 8253.
Control Word Register This internal register is used to write information to,
prior to using the device. This register is addressed when A0 and A1 inputs are
logical 1's. The data in the register controls the operation mode and the
selection of either binary or BCD (binary coded decimal) counting format
3.6.6 Modes
The following text describes all possible modes. The modes used in the MZ-
700 and set by the monitor's startup are mode 0, mode 2, and mode 3.

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Mode 0 Interrupt on Terminal Count
The counter will be programmed to an initial value and afterwards
counts down at a rate equal to the input clock frequency. When the
count is equal to 0, the OUT pin will be a logical 1. The output will stay a
logical 1 until the counter is reloaded with a new value or the same
value or until a mode word is written to the device.
Once the counter starts counting down, the GATE input can disable the
internal counting by setting the GATE to a logical 0.
Mode 1 Programmable One-Shot
In mode 1, the device can be setup to give an output pulse that is an
integer number of clock pulses. The one-shot is triggered on the rising
edge of the GATE input. If the trigger occurs during the pulse output, the
8253 will be retriggered again.
Mode 2 Rate Generator
The counter that is programmed for mode 2 becomes a "divide by n"
counter. The OUT pin of the counter goes to low for one input clock
period. The time between the pulses of going low is dependent on the
present count in the counter's register. I mean the time of the logical 1
pulse.

3.7 KEYBOARD / DISPLAY CONTROLLER


3.7.1 8279 – Keyboard / Display Controller
While studying 8255, we have explained the use of 8255 in interfacing
keyboards and displays with 8086.
The disadvantages of this method of interfacing keyboard and display with
8086 is that the processor has to refresh the display and check the status of the
keyboard periodically using polling technique.
Thus a considerable amount of CPU time is wasted, reducing the system
operating speed. Intel’s 8279 is a general purpose keyboard display controller that
simultaneously drives the display of a system and interfaces a keyboard with the
CPU, leaving it free for its routine task.
3.7.2 Architecture of 8279
The keyboard display controller chip 8279 provides:
a) a set of four scan lines and eight return lines for interfacing keyboards
b) A set of eight output lines for interfacing display.
I/O Control and Data Buffers:
The I/O control section controls the flow of data to/from the 8279. The data
buffers interface the external bus of the system with internal bus of 8279. The I/O
section is enabled only if CS is low. The pins A0, RD and WR select the command,
status or data read/write operations carried out by the CPU with 8279.
Control and Timing Register and Timing Control:
These registers store the keyboard and display modes and other operating
conditions programmed by CPU. The registers are written with A0=1 and WR=0.
The Timing and control unit controls the basic timings for the operation of the
circuit. Scan counter divide down the operating frequency of 8279 to derive scan
keyboard and scan display frequencies.
Scan Counter:
The scan counter has two modes to scan the key matrix and refresh the
display. In the encoded mode, the counter provides binary count that is to be
externally decoded to provide the scan lines for keyboard and display (Four
externally decoded scan lines may drive up to 16 displays). In the decode scan
mode, the counter internally decodes the least significant 2 bits and provides a
decoded 1 out of 4 scan on SL0-SL3( Four internally decoded scan lines may drive
up to 4 displays). The keyboard and display both are in the same mode at a time.
Return Buffers and Keyboard Debounce and Control:
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Microcontroller
keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). After the
debounce period, if the

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key continues to be detected. The code of key is directly transferred to the sensor
RAM along with SHIFT and CONTROL key status.
FIFO/Sensor RAM and Status Logic:
In keyboard or strobed input mode, this block acts as 8-byte first-in-first-out
(FIFO) RAM. Each key code of the pressed key is entered in the order of the entry
and in the mean time read by the CPU, till the RAM become empty. • The status
logic generates an interrupt after each FIFO read operation till the
FIFO is empty. In scanned sensor matrix mode, this unit acts as sensor RAM.
Each row of the sensor RAM is loaded with the status of the corresponding row of
sensors in the matrix. If a sensor changes its state, the IRQ line goes high to
interrupt the CPU.
Display Address Registers and Display RAM:
The display address register holds the address of the word currently being
written or read by the CPU to or from the display RAM. The contents of the registers
are automatically updated by 8279 to accept the next data entry by CPU.

Fig: 3.20 8279 Internal Architecture


3.7.3 Signal description of of 8279
DB0-DB7: These are bidirectional data bus lines. The data and command words to
and from the CPU are transferred on these lines.
CLK: This is a clock input used to generate internal timing required by 8279.
RESET: This pin is used to reset 8279. A high on this line reset 8279. After resetting
8279, its in sixteen 8-bit display, left entry encoded scan, 2-key lock out mode. The
clock prescaler is set to 31.
CS: Chip Select – A low on this line enables 8279 for normal read or write
operations. Other wise, this pin should remain high.
A0: A high on this line indicates the transfer of a command or status information. A
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low on this line indicates the transfer of data.
College This is used to select one of the
Microcontroller
internal registers of 8279.

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RD, WR (Input/Output) READ/WRITE: These input pins enable the data buffers to
receive or send data over the data bus.
IRQ: This interrupt output lines goes high when there is a data in the FIFO sensor
RAM. The interrupt lines goes low with each FIFO RAM read operation but if the FIFO
RAM further contains any key-code entry to be read by the CPU, this pin again goes
high to generate an interrupt to the CPU.
Vss, Vcc: These are the ground and power supply lines for the circuit.
SL0-SL3-Scan Lines: These lines are used to scan the key board matrix and display
digits. These lines can be programmed as encoded or decoded, using the mode
control register.
RL0 - RL7 - Return Lines: These are the input lines which are connected to one
terminal of keys, while the other terminal of the keys is connected to the decoded
scan lines. These are normally high, but pulled low when a key is pressed.
SHIFT: The status of the shift input lines is stored along with each key code in FIFO,
in scanned keyboard mode. It is pulled up internally to keep it high, till it is pulled
low with a key closure.
BD – Blank Display: This output pin is used to blank the display during digit switching
or by a blanking closure.
OUT A0 – OUT A3 and OUT B0 – OUT B3: These are the output ports for two 16*4 or
16*8 internal display refresh registers. The data from these lines is synchronized
with the scan lines to scan the display and keyboard. The two 4-bit ports may also
as one 8-bit port.
CNTL/STB- CONTROL/STROBED I/P Mode: In keyboard mode, this line is used as a
control input and stored in FIFO on a key closure. The line is a strobed line that
enters the data into FIFO RAM, in strobed input mode. It has an interrupt pull up.
The lines are pulled down with a key closer.

Fig: 3.21(b) 8279 Signal group


Fig: 3.21(a) 8279 Pin Configuration

3.7.4 Modes of Operation of 8279


The modes of operation of 8279 are as follows:
1. Input (Keyboard) modes.
2. Output (Display) modes.
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1. Input (Keyboard) Modes:

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(a) Scanned Keyboard Mode : This mode allows a key matrix to be interfaced
using either encoded or decoded scans. In encoded scan, an 8*8 keyboard or
in decoded scan, a 4*8 keyboard can be interfaced. The code of key pressed
with SHIFT and CONTROL status is stored into the FIFO RAM.
(b) Scanned Sensor Matrix : In this mode, a sensor array can be interfaced with
8279 using either encoded or decoded scans. With encoded scan 8*8 sensor
matrix or with decoded scan 4*8 sensor matrix can be interfaced. The sensor
codes are stored in the CPU addressable sensor RAM.
(c) Strobed input: In this mode, if the control lines goes low, the data on return
lines, is stored in the FIFO byte by byte.
2. Output (Display) Modes:
8279 provides two output modes for selecting the display options. These are
discussed
briefly.
(a) Display Scan: In this mode 8279 provides 8 or 16 character multiplexed displays
those can be organized as dual 4- bit or single 8-bit display units.
(b) Display Entry : ( right entry or left entry mode ) 8279 allows options for data
entry on the displays. The display data is entered for display either from the
right side or from the left side.
Keyboard Modes
 Scanned Keyboard mode with 2 Key Lockout
 Scanned Keyboard with N-Key Rollover
 Scanned Keyboard Special Error Mode
 Sensor Matrix Mode
Display Modes
 Left Entry Mode
 Right Entry Mode

3.8 INTERRUPT CONTROLLER


3.8.1 8259 A - Priority Interrupt Controller
The processor 8085 had five hardware interrupt pins. Out of these five
interrupt pins four pins were allotted fixed vector address but the pin INTR was not
allotted any vector address, rather than external device was supposed to
hand over the type of interrupt
i.e (Type 0 Type 7 for RST0 to RST 7) to the CPU.
The processor then gets this type and derives the interrupt vector address
from that. Consider an application, where a number of IO devices are connected
with CPU desire to transfer data using interrupt driven mode.
In these case, more number of interrupt pins are required than available in a
CPU. Moreover, in these multiple interrupt systems, the processor will have to take
care of priorities for the interrupt, simultaneously occurring at the interrupt request
pins. The 8086 has only two interrupt inputs, NMI and INTR.
To overcome all these difficulties, we require a programmable interrupt
controller which is able to handle a number of interrupt at a time. This relieves the
processor from this entire task. The 8259 was designed to operate only with 8 bits
microprocessors like 8085.A modified version; 8259A is compatible with 8 bit as
well as 16 bits processors

3.8.2 Interrupt Mask Register (IMR)


 This register stores the bits required to mask the interrupt inputs.
 IMR operates on IRR at the direction of the Priority Resolver.
Block diagram of 8259 A
Interrupt Request Register (RR)
 The interrupts at IRQ input lines are handled by Interrupt Request internally.
 IRR stores the entire interrupt request in it in order to serve them one by
one on the priority basis.
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In-Service Register (ISR)

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 This stores all the interrupt requests those are being served, i.e. ISR keeps a
track of the requests being served.

Fig 3.22: Block diagram of 8259 A

Priority Resolver
 This unit determines the priorities of the interrupt requests appearing
simultaneously.
 The highest priority is selected and stored into the corresponding bit of ISR
during INTA pulse.
 The IR0 has the highest priority while the IR7 has the lowest one,
normally in fixed priority mode.
 The priorities however may be altered by programming the 8259A in
rotating priority mode.
3.8.3 Interrupt Control Logic
 This block manages the interrupt and interrupt acknowledge signals to be
sent to the CPU for serving one of the eight interrupt requests.
 This also accepts the interrupt acknowledge (INTA) signal from CPU that
causes the 8259A to release vector address on to the data bus.
Data Bus Buffer
 This tristate bidirectional buffer interfaces internal 8259A bus to the
microprocessor system data bus.
 Control words, status and vector information pass through data buffer
during read or write operations.
Read/Write Control Logic
 This circuit accepts and decodes commands from the CPU.
 This block also allows the status of the 8259A to be transferred on to the data
bus.
Cascade Buffer/Comparator
 This block stores and compares the ID’s all the 8259A used in system.
 The three I/O pins CASO-2 are outputs when the 8259A is used as a master.
 The same pins act as inputs when the 8259A is in slave mode.
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 The 8259A in master mode sends the ID of the interrupting slave device on
these lines. The slave thus selected, will send its preprogrammed vector
address on the data bus during the next INTA pulse.
INT:
 This pin goes high whenever a valid interrupt request is asserted. This is used
to interrupt the CPU and is connected to the interrupt input of CPU.
IR0 – IR7 (Interrupt requests):
 These pins act as inputs to accept interrupt request to the CPU. In edge
triggered mode.
 An interrupt service is requested by raising an IR pin from a low to a high
state and holding it high until it is acknowledged, and just by latching it to
high level, if used in level triggered mode.
INTA (Interrupt acknowledge):
 This pin is an input used to strobe-in 8259A interrupt vector data on to the data
bus.
 In conjunction with CS, WR and RD pins, this selects the different operations
like, writing command words, reading status word, etc.
3.8.4 Interrupt Sequence in an 8086-8259A system
 One or more IR lines are raised high that set corresponding IRR bits.
 8259A resolves priority and sends an INT signal to CPU.
 The CPU acknowledge with INTA pulse.
 Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set
and the corresponding IRR bit is reset. The 8259A does not drive data during
this period.
 The 8086 will initiate a second INTA pulse. During this period 8259A releases
an 8-bit pointer on to a data bus from where it is read by the CPU.
 This completes the interrupt cycle. The ISR bit is reset at the end of the
second INTA pulse if automatic end of interrupt (AEOI) mode is programmed.
Otherwise ISR bit remains set until an appropriate EOI command is issued at
the end of interrupt subroutine.
Command Words of 8259A
The command words of 8259A are classified in two groups
 Initialization command words (ICW) and
 Operation command words (OCW).
Initialization Command Words (ICW)
 Before it starts functioning, the 8259A must be initialized by writing two to
four command words into the respective command word registers.
 These are called as initialized command words.ICW1 and ICW2 are
compulsory command words in initialization sequence of 8259A while ICW3
and ICW4 are optional.
Operation Command Words:
 Once 8259A is initialized it is ready for its normal function, i.e. for accepting
the interrupts but 8259A has its own way of handling the received interrupts
called as modes of operation. These modes of operations can be selected by
programming, i.e. writing three internal registers called as operation
command words registers.
 The data written into them is called as operational
command words. There are three operation command
words
 OCW1
 OCW2
 OCW3
Every bit corresponds to some operational feature of the mode selected,
except for a few bits those are either 1 or0.

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3.8.5 Operating Modes of 8259
College Microcontroller
 The different modes of operation of 8259A can be programmed by setting or
resting the appropriate bits of the ICW or OCW
The different modes of operation of 8259A
 Fully Nested Mode

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 End of Interrupt (EOI)
 Automatic Rotation
 Automatic EOI Mode
 Specific Rotation
 Specific Mask Mode
 Edge and Level Triggered Mode
 Reading 8259 Status
 Poll Command
 Special Fully Nested Mode
 Buffered Mode
 Cascade Mode
 Fully Nested Mode

3.9 DMA CONTROLLER


It is a device to transfer the data directly between IO device and memory
without through the CPU. So it performs a high-speed data transfer between
memory and I/O device.
Features:
 It is a 4-channel DMA.So 4 I/O devices can be interfaced to DMAC
 It is designed by Intel
 Each channel have 16-bit address and 14 bit counter
 It provides chip priority resolver that resolves priority of channels in
fixed or rotating mode.
 It generates a TC signal to indicate the peripheral that the programmed
number of data bytes has been transferred.
It is operate in two modes.
 Master Mode
 Slave Mode

3.9.1 Architecture of DMAC:


It contains four main Blocks.
 Data bus buffer
 Read/Control logic
 Control logic block
 Priority resolver & DMA channels.
Data Bus Buffer:
It contain tri-state, 8-bit bi-directional buffer.). It provides the link between
the internal structure of 8257 and the system bus. In Slave mode, it transfers data
between microprocessor and internal data bus. Master mode, these lines are used
to carry address information A8-A15 bits of memory address (Unidirectional).
Read/Control Logic:
It controls all internal Read/Write operation of DMAC. In Slave mode, it
accepts address bits and control signals from microprocessor. But in Master mode,
it generates address bits and control signals to the Slave DMACs.
Control Logic:
In Master mode, It control the sequence of DMA operation during all DMA
cycles. It generates address and control signals which are necessary for the
operation. It increments 16 bit address and decrement 14 bit counter registers
values. It activates a HRQ signal on DMA channel Request when it receives any
DREQ signal from external devices. But in Slave mode it is disabled.
DMA Channels:
DMAC has four DMA channels (CH3-CH0). Each channel has two 16-bit registers.
External devices are connected to this channels the external devices send their
DMA requests to DMAC through DRQ inputs and they get the acknowledgements
through DACK outputs.
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Fig 3.23: Architecture of DMAC

Priority Resolver:
This block assigns the priorities to the DMA channels of DMAC based on mode
of operation.
First/Last Flip Flop (FF):
8257 have 8bit data line and 16 bit address line.8086 it is getting 8-bit data
in simultaneously.8086 cannot access 16-bit address in simultaneously.A0-A3 lines
are used to distinguish between registers, but they are not distinguishing lower and
higher address. It is reset by external RESET signal. It is also reset by whenever
mode set register is loaded. So program initialization with a dummy (00 H).
i. FF=1=Higher byte of address
ii. FF=0=Lower byte of address.

3.9.2 Pin Diagram of 8257 DMAC:


Description of pin diagram:
D0-D7 (Data Lines): - These lines carry Command words from the processor and the
Status information from the 8257 in Slave Mode of operation. But in Master mode of
operation these lines carry the higher order byte address to the latch. These lines
also used for data transmissions.

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Fig 3.24: Pin Configuration of DMAC


DRQ0 – DRQ3 (DMA Request) Signals: - These lines are used by peripheral devices for
requesting DMA services. The DRQ0 has the highest priority while DRQ3 has the
lowest priority in Fixed Priority mode.
DACK0 – DACK3 (DMA Acknowledge) Signals: - These four lines are active low signals.
These lines are used to inform the requesting peripheral that the request has been
honored and the bus is relinquished by the CPU.
IOR (IO Read) Signal: -It is an input signal in Slave Mode of operation of 8257 in that
mode this signal is used by CPU to read the information from the internal registers
of 8257. It is acts as an output signal in Master Mode of operation it is used to read
data from a peripheral during a memory write operation. This signal is an active low
signal.
IOW (IO Write) Signal: -It is an input signal in Slave Mode of operation of 8257 .this
signal is used by CPU to write the information to the internal registers of 8257. It
acts as an output signal in Master Mode of operation and it is used to write data to
a peripheral during a memory read operation. This signal is an active low signal.
A0-A3 (Address Lines): - These are the tri-state bidirectional address lines. In slave
mode, these lines are used as address inputs lines and internally decoded to access
the internal registers. In master mode, these lines are used as address outputs
lines,A0-A3 bits of memory address on the lines. The addresses for internal registers
of 8257are assigned by using A0, A1, A2, & A3are as follows.
Register Byte A3 A2 A1 A0 F/L
CH-0 DMA Address Register LSB 0 0 0 0 0
CH-0 DMA Address Register MSB 0 0 0 0 1
CH-0 DMA Terminal Count Register LSB 0 0 0 1 0
CH-0 DMA Terminal Count Register MSB 0 0 0 1 1
CH-1 DMA Address Register LSB 0 0 1 0 0
CH-1 DMA Address Register MSB 0 0 1 0 1
CH-1 DMA Terminal Count Register LSB 0 0 1 1 0
CH-1 DMA Terminal Count Register MSB 0 0 1 1 1
CH-2 DMA Address Register LSB 0 1 0 0 0

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CH-2 DMA Address Register
College MSB 0 1
Microcontroller 0 0 1

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CH-2 DMA Terminal Count Register LSB 0 1 0 1 0
CH-2 DMA Terminal Count Register MSB 0 1 0 1 1
CH-3 DMA Address Register LSB 0 1 1 0 0
CH-3 DMA Address Register MSB 0 1 1 0 1
CH-3 DMA Terminal Count Register LSB 0 1 1 1 0
CH-3 DMA Terminal Count Register MSB 0 1 1 1 1
Mode Set Register 1 0 0 0 0
Status Register 1 0 0 0 0

**Where F/L indicates First/Last Flip-Flop.


CS (Chip Select) Signal: - It is active low, Chip select input line. In the slave mode, it
is used to select the chip. In the master mode, it is ignored.
A4-A7 (Address Lines):- These are the tri-state output address lines. In slave mode,
these lines are used as address outputs lines. In master mode, these lines are used
as address outputs lines, of memory address on the lines.
READY Signal: - It is an asynchronous input line. In master mode, When ready is
high it is received the signal from the selected peripheral. When ready is low, it
adds wait state to the operation.
HRQ (HOLD Request): - It is used to send a DMA request signal to the processor
from DMA controller8257 to take the control over the system bus. This signal is
directly connected to the HOLD signal of the processor.
HLDA (HOLD Acknowledge) Signal: - It is acknowledgment signal from
microprocessor. If the DMA request is accepted by the processor and it is ready to
release the control over system bus the processor issues this signal. HLDA signal of
the processor is directly connected to HLDA signal of DMAC.
MEMR (Memory Read) Signal:- It is active low output line. This is used to read data
from the peripheral during DMA read cycle.
MEMW (Memory Write) Signal:- It is active low output line. This is used to write on to
the selected memory location in the DMA Write operation.
AEN (Address enable) Signal: - It is a control output line. In master mode, it is high. In
slave mode, it is low. It is used it isolate the system address, data, and control lines.
During DMA mode, the AEN signal is also used to disable the buffers and latches
used for address, data and control signals of the processor.
ADSTB (Address Strobe): - It is a control output line. Used to split data and address
line. It is working in master mode only. In slave mode it is ignore.
TC (Terminal Count) Signal: - It is a status of output line. This output notifies the
currently selected peripheral that the present DMA cycle is the last DMA cycle for
this data block. TC STOP bit in the Mode Set register is set then the selected
channel is automatically disabled at the end of the DMA cycle.
MARK Signal: -It is a Modulo 128 MARK output line. This output notifies the selected
peripheral that the current DMA cycle is 128 th cycle since the previous MARK. This
signal always occurred at 128 cycles from the end of the data block.
CLK (Clock) Signal: - It is the input line; it is connected to the clock generator 8284
in the system.
RESET Signal: -It disables all channels of DMA controller and it is used to clear mode
set register, status register and internal registers of DMAC.
Register Organization of 8257 DMAC: -Each channel of DMA controller has a pair of
16-bit registers. Those are Address Register, and Terminal Count Register.
There are common registers of all channels those are Mode Set Register and Status
Register both are 8-bit registers.
DMA Address Register: - The function of this register in any channel is it can store
the address of starting memory location, which will be accessed by the DMA
channel. It is a 16-bit register.
Terminal Count Register: - This 16-bit register is used for ascertaining that the data
transfer through DMA channel ceases or stops after the required number of DMA
cycles. The lower order 14-bits of terminal count register are initialized with the
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Collegeequivalent of the number of Microcontroller

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required DMA cycles minus one. After each DMA cycle, The Terminal Count Register
content will be decremented by one and finally it becomes zero after the required
number of DMA cycles are over. The higher order two bits of this register indicate
the type of the DMA operation.

3.9.3 Modes of Operation:


1. Rotating priority Mode:
The priority of the channels has a circular sequence. After each DMA cycle
the priorities of channels are changed. The channel which had just been serviced
will have the lowest priority.
2. Fixed Priority Rotating Mode:
The priority is fixed. Every time CH-0 has highest priority and CH-3 has lowest
priority.
3. Auto Load Mode Operation:
This mode of operation permits the Channel – 2(CH-2) for repeat block or
block chaining operation, without immediate software intervention between blocks.
Channel- 2 registers are initialized as usual for first data block transfer. The
Channel- 3 registers are used to store the block re-initialization parameters. After
the first block of DMA operation is performed by Channel- 2 the parameters stored
in the Channel- 3 registers are transferred to Channel- 2 registers during Update
cycle.

3.10 PROGRAMMING AND APPLICATIONS CASE


STUDIES (TRAFFIC LIGHT CONTROL, LED DISPLAY, LCD
DISPLAY,
KEYBOARD DISPLAY INTERFACE & ALARM CONTROLLER)

3.10.1 TRAFFIC LIGHT CONTROL

 Design a microprocessor system to control traffic lights. The traffic light


arrangement is as shown in Fig. 3.25.

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College Fig: 3.25 Traffic light control
Microcontroller
 The traffic should be controlled in the following manner.

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1) Allow traffic from W to E and E to W transition for 20 seconds.
2) Give transition period of 5 seconds (Yellow bulbs ON)
3) Allow traffic from N to S and S to N for 20 seconds
4) Give transition period of 5 seconds (Yellow bulbs ON)
5) Repeat the process
Hardware:
 Fig. 3.26 shows the interfacing diagram to control 12 electric bulbs.
 Port A is used to control lights on N-S road and Port B is used to control
lights on W-E road. Actual pin connections are listed in Table 3.9.

Table. 3.9 TLC pin connections


 The electric bulbs are controlled by relays.
 The 8255 pins are used to control relay on off action with the help of
relay driver circuits.
 The driver circuit includes 12 transistors to drive 12 relays.
 Fig. 3.26 also shows the interfacing of 8255 to the system.

Fig. 3.26 The interfacing diagram for traffic light control system

I/O Map

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Table: 3.10 Ports/Control Register and address lines

Software:

Control word: For initialization of 8255.

Table: 3.11 (a) Control word

Table 3.11(b) Combinations data bytes

Source program:

MVI A, 80H ; Initialize 8255, port A and


port B OUT 83!! (CR) ; in output mode
START: MVI A, 09H ;
OUT 80H (PA) ; Send data on PA to glow R1
and R3 MVI A. 24H
OUT 81H (PB) ; Send data on PB to glow G3
and G4 MVI C. 28H ; Load multiplier count (40)
for delay CALL DELAY ; Call delay subroutine
MVI A, 12H
OUT (8 1H) PA ; Send data on Port A to glow Y1
and Y OUT (81H) PB ; Send data on port B to glow
Y3 and Y4 MVI C, OAH ; Load multiplier count
(10) for delay CALL DELAY ; Call delay subroutine
MVI A, 24H
OUT (80H) PA ; Send data on port A to glow G1
and G2 MVI A.09H
OUT (81H) PB ; Send data on port B to glow R3
and R0 MVI C. 28H ; Load multiplier count (40)
for delay CALL DELAY ; Call delay subroutine
MVI A.12H
OUT PA ; send data on port A to glow Y1 and Y2

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OUT PB ; Send data on port B to glow Y3
and Y4 MVI C.OAH ; Load multiplier count (1O)
for delay CALL DELAY ; Call delay subroutine
JMP START

3.10.2 LED DISPLAY


LED displays are available in two very common formats.
 7 segment displays
 5 by 7 dot-matrix displays.

Seven-Segment display
 Seven segment displays are generally used as numerical indicators
 It consists of a number of LEDs arranged in seven segments shown
in the Fig. 3.27.

Fig: 3.27 seven segments Display


Any number between O and 9 can be indicated by lighting the Segments. Fig.
3.28

3.10.2.1 Seven segment display

Fig: 3.28 seven segment display

 The seven segments are labeled a biasing different LED segments.


 To display O, we need to light up a, segments a, f, g. c and d.
 These 7 Segment displays are of two types:
 Common Anode Type
 Common Cathode Type
 In common a node, all anodes of LEDs are connected together as in common
cathode Fig. 3.29 (a) Common anode type,
 All cathodes are connected together, Fig. 3.29 (b) Common cathode type
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Fig: 3.29(a) Common anode type

Fig: 3.29(b) Common cathode type

3.10.2.2 5 by 7 DOT matrix LED


Fig. 3.30(a) and (b) show the 5 by 7 dot matrix LED display and its circuit
connections.

Fig: 3.30(a) 5X7 dot matrix LED display

Fig: 3.30(b) 5X7 dot matrix Circuit Connections

 This display can be used to display number as well as alphabets.


 Keyboard and Display Interfacing 329

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Interfacing LED Displays
 Static Display Fig. 3.31 shows a circuit to drive a single, seven segment,
common a node LED Display.
 For common anode, when anode is connected to positive supply, a low
voltage is applied to a cathode to turn it on.
 BCO to seven segment decoder, IC 7447 is used to apply low voltages at
cathodes according to BCD input applied to 7447.
 This circuit connection is referred to as a static display.

Fig: 3.31 Circuit for driving single seven segment LED display

The value of the resistor in series with the segment can be calculated as follows:
 Vcc — drop across LED segment — IR = O.
 Drop across LED segment is nearly
1.5 V. IR = Vcc. - 1.5 V
= 5 — 1.5 V
= 3.5 V
 Each LED segment requires a current of between 5 and 30 mA to light.
Let’s assume that current through LED segment is 15 mA and R=35V/15mA = 233ohm
 The voltage drop across the LED and the output of 7447 are not exactly
predictable.
 A standard value 220 Q can be used.
 The static display circuits work well for driving just one or two LED digits.
 When there is more number of digits, the first problem is power consumption.
 For worst-case calculations, assume that all eight digits with all segments are lit.
 Therefore, worst case current required is
I = 8 (digits) x 7 (segment) x 15 mA (current per segment)
=84OmA
A second problem of the static approach is that each display digit requires a
separate BCD to 7 segment decoder.

Multiplexed Display
 To solve the problems of the static display approach, multiplexed display
method is used.
 Fig. 3.32 shows the 4 seven segment displays connected using multiplexed
method.
 Here, common anode seven segment LEDs are used.

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Fig: 3.32 Seven segment display in multiplexed connection

 Anodes are connected to +5V through transistor, Cathodes of all seven


segments are connected in parallel and then to the output of 7447 IC
through resistors.
 The same number only if all the digits are turned on at the same time.
 The PNP transistors connected in series with the common anode of each digit
act as an ON and OFF switch for that digit. Here’s how the multiplexing
process works.
 The BCD code for digit 1 is first output from port A, to the 7447.
 The 7447, B to seven segment decoder outputs the corresponding seven
segment code on the segment bus lines.
 The transistor Q connected to digit 1 is then turned on by outputting a low to
that bit of port B.
 All of the rest of the bits of port B are made high.
 The BCD code for digit 2 is then output to the port A, and bit pattern to turn
on digit 2 is output on port B.
 After 2ms, digit 2 is turned off and the process is repeated for digit 3 and digit 4.
 After completion of turn for each digit, the entire digits arc lit again in turn In
multiplexed display, the segment current is kept in between 40 mA to 60 mA.

3.10.3 LCD DISPLAY


 The liquid crystals are one of the most fascinating material systems in
nature, having properties of liquids as well as of a solid crystal.
 The terms liquid crystal refers to the fact that these compounds have a
crystalline arrangement of molecules, yet they flow like a liquid.
 Liquid crystal displays do not emit or generate light, but rather alter
externally generated illumination.
 Their ability to modulate light when electrical signal is applied has made
them very useful in flat panel display technology.
 There are two types of liquid crystal displays (LCDs) according to the
theory of operation:
1. Dynamic scattering
2. Field effect.
 Fig. 3.34 shows the construction of a typical liquid crystal display. It consists
of two glass plates with a liquid crystal fluid in between.
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 The back plate is coated with thin transparent layer of conductive material.
Whereas front plate has a photo etched conductive coating with seven
segment pattern as shown in Fig. 3.33.
 Orientation order is maintained in the crystal allowing light to transmit. This
makes LCD display clear.
 The current through the liquid crystal causes orientation order to collapse.
 The random orientation results scattering of light which lights display
segment on a dark background.

Fig: 3.33 Liquid crystal display construction

Fig. 3.34 shows the circuit for driving LCD seven segment display using IC 4543B.

Fig: 3.34 LCD seven segment display using IC 4543B

Fig.3.35 Circuit for driving LCD seven segment display using 4543B

 The 45438 BCD-to-7 segment latch/decoder/driver is designed for


liquid crystal displays.
 Pins A, 8, C and D represent BCD inputs with A as a least significant bit (LSB)
and D as a most significant bit (MSB).
 Pins a through g are the seven segment outputs.
 The 4543B has three control terminals: LD (Latch Disable), PH (Phase), and BL
(Blank).
 The state of the PH terminal depends on the type of display that is being driven.
 For driving LCD displays, a square wave (about 60Hz swinging fully
between the GND and Vcc values) must be applied to the phase terminal.
 The display can be blanked by simply driving the BL terminal to the logic high
state.
 When the LD terminal is in its normal high state, BCD inputs are decoded
and fed directly to the seven segment output terminals of the IC.

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 When the LD terminal is pulled low, the
College BCD input signals that are
Microcontroller
present at the moment of transition are latched into memory and fed to the
seven segment outputs.

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Fig: 3.35 4-7 segment LCD display driving circuit

 The Fig. 3.35 shows how above circuit can be used to drive a 4-digit no
multiplexed, 7- segment LCD display.
 BCO input for each display is latched in the corresponding latch.
 LCD Modules allow display of characters as well as numbers. They are
available in 16 x 2, 20 x 1, 20 x 2, 20 x 4 and 40 x 2 sizes.
 The first figure represents number of character in each line and second figure
represents number of lines the display has.
 The module has 14-pins.The function of each pin is given in the table 8.9.

Table 3.12 Pin description for LCD module

The Fig. 3.36 shows the interfacing of a 20 character x 2-line LCD module
with the 8051. As shown in the Fig. 3.37, the data lines are connected to the port I
of 8051 and control lines RS, R/V and E are driven by 3.2, 3.3 and 3.1 lines of port 3,
respectively.
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The voltage at VEE pin is adjusted by a potentiometer to adjust the contrast of the LCD.

Fig: 3.36 Interfacing LCD module with 8051

3.10.4 KEYBOARD INTERFACING

For interfacing keyboard to the microprocessor based systems, usually


push button keys are used. These push button keys when pressed. Bounces a few
times, closing and opening the contacts before providing a steady reading, as
shown in the Fig. 3.37 Reading taken during bouncing period may be faulty.
Therefore, microprocessor must wait until the key reach to a steady state; this is
known as key de bounce.

Fig: 3.37 Bouncing of Key Switch

3.10.4.1 Key Debounce using Hardware

Fig. 3.38 shows the circuit diagram of key debounce. It consists of flip flop.
The output of flip-flop shown in Fig. 3.38 is logic t when key is at position. A
(unpressed) and it is logic 0 when key is t position B

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Fig: 3.38 Circuit diagram of key debounce

3.10.4.2 Key Debouncing using Software


 In the software technique, when a key press is found, the microprocessor
waits for at Least.
 10ms before it accepts the key as an input.
 This 10 ms period is sufficient to settle key at steady state.
 Fig. 3.40 shows the flowchart with key debounce technique.

Fig: 3.39 Flowchart with key debounce technique

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3.10.4.3 Simple keyboard interface

Fig 3.41 shows simple keyboard interface

Fig: 3.40 Simple keyboard interface


Here eight keys are individually connected to specific pins of input port.
Each port pin gives the status of key connected to that pin. When port pin is logic 1,
key is open. Otherwise key s closed is shown in below.

3.10.4.4 Matrix Keyboard Interface


 In simple keyboard interface one input line is required to interface one key
and pins number will increase with number of keys.
 Therefore, such technique is not suitable when it is necessary to interface
large number of keys. To reduce number of connections keys are arranged in
the mat form as shown in the Fig. 3.41

Fig: 3.41 Matrix keyboard

 Fig. 3.43 shows sixteen keys arranged in four rows and four columns.
 When keys are open row and column do not have any connection, when
a key is pressed.
 It shorts corresponding one row and one column.

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 This matrix keyboard requires eight lines to make all the connections
instead of the sixteen hours required if the keys are connected individually,
as shown in Fig. 3.41
 Fig. 3.42 shows the interfacing of matrix keyboard.
 It requires two ports:
1. an input port
2. An output port.
 Rows are connected to the input port referred to as returned lines, and
columns are connected to the output port referred to as scan lines.
 When all keys are open row and column do not have any connection. When
any key is pressed it shorts corresponding row and column.
 If the output line of this column is low, it makes corresponding row line low;
otherwise the status of row line is high.
 The key is identified by data sent on the output port and input code
received from the input port. The following section explains the steps
required to identify pressed key.

Fig 3.42 Matrix keyboard connections


Check 1:
 Whether any key is pressed or not
 Make all column lines zero by sending low on all output lines. This activates
all keys in the keyboard matrix
 Read the status of return Lines. If the status of all lines is logic high, key is
not pressed; otherwise key is pressed.
Check 2:
 Activate keys from any one column by making any one column line zero.
 Read the status of return lines. The zero on any return line indicates key is
pressed from the corresponding row and selected column
 Activate the keys from the next column and repeat 2 and 3 for all columns.
In Fig. 3.43 the scan lines are connected to the port C, of 8255 and returns
lines are connected to the port C1, of 8255.

Fig: 3.43 Interfacing of 4 X 4 keyboard with 8086

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Part-A (2 Marks Questions and Answers)

1. What are the modes of operation used in 8253?


1. Mode 0 (Interrupt on terminal count)
2. Mode 1 (Programmable mono shot)
3. Mode 2 (Rate generator)
4. Mode 3 (Square wave generator)
5. Mode 4 (Software triggered strobe)
6. Mode 5 (Hardware triggered strobe)

2. What are the different types of write operations used in 8253?


There are two types of write operations in 8253
(1)Writing a control word register
(2)Writing a count value into a count register
The control word register contents are used for
(a) Initializing the operating modes (mode 0-mode4)
(b)Selection of counters (counter 0- counter 2)
(c) Choosing binary /BCD counters
(d)Loading of the counter registers.

3. Draw the format of read back command register, of 8254.(April/May’17)

D7 D6 D5 D4 D3 D2 D1 D0
1 1 COUNT STATUS CNT2 CNT1 CNT0 0

D5-0 –Latch Count of Selected counter.


D4- 0- Latch Status of selected Counter.
D3- 1 - Select Counter 2.
D2 -1- Select
Counter 1 D1-1- Select
Counter 0.

4. Give the operating modes of 8259?


(a) Fully Nested Mode
(b)End of Interrupt (EOI)
(c) Automatic Rotation
(d)Automatic EOI Mode
(e) Specific Rotation
(f)Special Mask Mode
(g)Edge and level Triggered Mode
(h)Reading 8259 Status
(i) Poll command
(j) Special Fully Nested Mode
(k)Buffered mode
(l) Cascade mode

5. Define scan counter? (Nov/Dec’13)


The scan counter has two modes to scan the key matrix and refresh the
display. In the encoded mode, the counter provides binary count that is to be
externally decoded to provide the scan lines for keyboard and display. In the
decoded scan mode, the counter internally decodes the least significant 2 bits and
pro vides a decoded 1 out of scan on SL0-SL3.

6. What is the output modes used in 8279? (Apr/May2019)


8279 provides two output modes for selecting the display options.

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1. Display Scan: In this mode, 8279 providesMicrocontroller
College 8 or 16 character-multiplexed
displays those can be organized as dual 4-bit or single 8-bit display units.

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2. Display Entry: 8279 allows options for data entry on the displays. The display
data is entered for display from the right side or from the left side.

7. What are the modes used in keyboard modes?


1. Scanned Keyboard mode with 2 Key Lockout.
2. Scanned Keyboard with N-key Rollover.
3. Scanned Keyboard special Error Mode.
4. Sensor Matrix Mode.

8. What are the modes used in display modes?


1. Left Entry mode In the left entry mode, the data is entered from the left side
of the display unit.
2. Right Entry Mode In the right entry mode, the first entry to be displayed is
entered on the rightmost display.

9. What is the use of modem control unit in 8251?


The modem control unit handles the modem handshake signals to coordinate
the communication between the modem and the USART.

10. Give the register organization of 8257?


The 8257 perform the DMA operation over four independent DMA channels.
Each of the four channels of 8257 has a pair of two 16-bit registers. DMA address
register and terminal count register. Also, there are two common registers for all
the channels; namely, mode set registers and status register. Thus there are a total
of ten registers. The CPU selects one of these ten registers using address lines A-0 A
-3.

11. What is the function of DMA address register?


Each DMA channel has one DMA address register. The function of this register
is to store the address of the starting memory location, which will be accessed by
the DMA channel. Thus the starting address of the memory block that will be
accessed by the device is first loaded in the DMA address register of the channel.

12. What is the use of terminal count register?


Each of the four DMA channels of 8257 has one terminal count register. This
16-bit register is used for ascertaining that the data transfer through a DMA channel
ceases or stops after the required number of DMA cycles.

13. What is the function of mode set register in 8257?


The mode set register is used for programming the 8257 as per the
requirements of the system. The function of the mode set register is to enable the
DMA channels individually and also to set the various modes of operation.

14. Distinguish between the memories mapped I/O peripheral I/O.


Memories mapped I/O Peripheral I/O
16-bit device address 8-bit device address
More hardware is required Less hardware is required to
to decode 16-bit address decode 8-bit address
Arithmetic or logic operation can be
Arithmetic or logical operation
directly performed with I/O data cannot be directly performed
with data I/O data

15. List the operation modes of 8255


a) I.O Mode
i. Mode 0-Simple Input/Output.

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College ii. Mode 1-Strobed Input/output (Handshake mode)
Microcontroller

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iii.Mode 2-Strobed bidirectional mode
b) Bit Set/Reset Mode
16. What is a control word?
It is a word stored in a register (control register) used to control the operation
of a program digital device.

17. What is the purpose of control word written to control register in 8255?
(/May/June’13)
The control words written to control register specify an I/O function for each
I.O port. The bit D7 of the control word determines either the I/O function of the BSR
function.

18. What is the handshake signals used in Mode-2 configuration of 8255?(Nov/Dec’17)


, ,IBF, ,INTR

19. What is memory mapping? (Nov/Dec’12)


The assignment of memory addresses to various registers in a memory chip
is called as memory mapping.

20. What is I/O mapping? (Nov/Dec’14)


The assignment of addresses to various I/O devices in the memory chip is
called as I/O mapping.

21. What is an USART? (Nov/Dec’12)


USART stands for universal synchronous/Asynchronous Receiver/ Transmitter.
It is a programmable communication interface that can communicate by using
either synchronous or asynchronous serial data.

22. What is the use of 8251 chip?


8251 chip is mainly used as the asynchronous serial interface between the
processor and the external equipment.

23. List the major components of the keyboard/Display interface.


 Keyboard section
 Scan section
 Display section
 CPU interface section

24. What is Key bouncing?


Mechanical switches are used as keys in most of the keyboards. When a key
is pressed the contact bounce back and forth and settle down only after a small
time delay (about 20ms). Even though a key is actuated once, it will appear to have
been actuated several times. This problem is called Key Bouncing.

25. Define HRQ?


The hold request output requests the access of the system bus. In non-
cascaded 8257 systems, this is connected with HOLD pin of CPU. In cascade mode,
this pin of a slave is connected with a DRQ input line of the master 8257, while that
of the master is connected with HOLD input of the CPU.

26. What is the use of stepper motor?


A stepper motor is a device used to obtain an accurate position control of
rotating shafts. A stepper motor employs rotation of its shaft in terms of steps,
rather than continuous rotation as in case of AC or DC motor.
27. What is TXD?
TXD- Transmitter Data Output This output pin carries serial stream of the
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transmitted
College data bits along with other information like start bit, stop bits and
Microcontroller
priority bit.

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28. What is RXD?
RXD- Receive Data Input This input pin of 8251A receives a composite stream
of the data to be received by 8251A.

29. What are the basic modes of operation of 8255? (May/June’15)


There are two basic modes of operation of 8255, viz.
1. I/O mode.
2. BSR mode.
In I/O mode, the 8255 ports work as programmable I/O ports, while In BSR
mode only port C (PC0-PC7) can be used to set or reset its individual port bits.
Under the IO mode of operation, further there are three modes of operation of 8
255, So as to support different types of applications, viz. mode 0, mode 1 and mode
2.
Mode 0 - Basic I/O mode
Mode 1 - Strobed I/O
mode
Mode 2 - Strobed bi-directional I/O

30. Write the features of mode 0 in 8255? (Apr/May2019)


 Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and
lower) are available. The two 4-bit ports can be combined used as a third 8-
bit port.
 Any port can be used as an input or output port.
 Output ports are latched. Input ports are not latched
 A maximum of four ports are available so that overall 16 I/O configurations are
possible.

31. What are the features used mode 1 in 8255?


Two groups – group A and group B are available for strobe data transfer.
1. Each group contains one 8-bit data I/O port and one 4-bit control/data
port.
2. The 8-bit data port can be either used as input or output port.
The inputs and outputs both are latched.
3. Out of 8-bit port C, PC0-PC2 is used to generate control signals for
port B and PC3=PC5 are used to generate control signals for port
A. The lines PC6, PC7 may be used as independent data lines.

*****

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Part-B (16 Marks Questions)

1. Draw the block diagram of 8279 keyboard/ Display controller and explain how to
interface the Hex Key pad and 7- segment LEDs using 8279. (May/June’12)
(Nov/Dec’12) (May/June’13)(Nov/Dec’17) [Ref Sec:3.7.1]
2. Draw the functional block diagram of 8254 timer and explain the different modes
of operation. (May/June’15) [Ref Sec: 3.6.3]
3. Draw the block diagram of 8259A and explain how to program 8259A.
(May/June’13) [Ref Sec:3.8.2]
4. Explain the data transfer on a parallel printer interface using a timing
diagram
(Nov/Dec’13) [Ref Sec:3.6]
5. Explain the interfacing of 4 X 4 matrix keyboard to the 8051 microcontroller with
neat diagram (Nov/Dec’13) [Ref Sec:3.10.4.4]
6. What are the signals a microprocessor should have to support DMA? List and
explain the sequence of operations carried out during a DMA transfer.
(Nov/Dec’12) (May/June’12) (May/June’14) [Ref Sec:3.9.3]
7. Explain the four modes of keyboard operation in 8279. (Nov/Dec’14) [Ref Sec:3.8.5]
8. Draw the architectural block diagram of 8259 Programmable interrupt controller
and Explain. (Nov/Dec’13) [Ref Sec:3.8.2]
9. Explain the parallel communication interface with microprocessor (Nov/Dec’12)
(April/May’17) [Ref Sec:3.3]
10.Explain the (i) modes of operation of timer and (ii) operation of interrupt controller
(May/June’13) (Nov/Dec’14) (May/June’14) [Ref Sec:3.6, 3.8]
11.Describe about serial port interface of 8051 (May/June’13) [Ref Sec:3.4] (Apr/May2019)
12. Draw the circuit diagram to interface an LCD with microcontroller and explain
how to display the data using LCD. (May/June’13) (Nov/Dec’12) [Ref Sec 3.10.3]
(Apr/May2019)
13. Explain the need of DMA controller with its functional diagram.(April/May’17)
14. Draw and explain the functional diagram of 8251. (Nov/Dec’17)
*****

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UNIT 4
MICROCONTROLLER

REFERRED BOOK:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family
- Architecture, Programming and Design”, Second Edition, Prentice Hall of
India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly
and C”, Second
3. . DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH,2012

STAFF IN-CHARGE HOD

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Intel 8051 Microcontroller
4.1 Introduction to microcontrollers
The powerful component is actually very simple in its essence. It was built using
the tested solutions and ingredients by the following recipe:
1. Processor was removed from the simplest of computers to be used as the
"brain" for the upcoming system.
2. Depending on the manufacturers' taste, some memory was added, a
few A/D converters, timers, I/O communication lines, etc.
3. It was all placed in a standard casing.
4. Simple software that everybody could learn was developed for controlling
the thing.

There are three decisive facts responsible for such a success of microcontrollers:
1. Their powerful, cleverly chosen electronics is able to control a variety of
processes and devices (industrial automatics, voltage, temperature, engines, etc)
independently or by means of I/O instruments such as switches, buttons, sensors,
LCD screens, relays
2. Their low cost makes them suitable for installing in places which attracted no
such interest in the past. This is the fact accountable for today's market being
swamped with cheap automatons and "intelligent" toys. 3. Writing and loading a
program into microcontroller requires practically no previous schooling. All that is
required is: any PC (software is very friendly and intuitive) and one simple device
(programmer) for loading a written program into microcontroller.

4.2 Microprocessors Vs. Microcontrollers


Microprocessor
• CPU is stand-alone, RAM, ROM, I/O, timer are separate
• Designer can decide on the amount of ROM, RAM and I/O ports.
• Expansive
• Their instructions operate on nibbles, bytes, words, or even double words.
• Addressing modes provide access to large arrays of data using pointers and
offsets.

• Versatility
• General-purpose
Microcontroller
• CPU, RAM, ROM, I/O and timer are all on a single chip
• Fix amount of on-chip ROM, RAM, I/O ports
• They have instructions to set and clear individual bits and perform bit
operations.
• They have instructions for input/output operations, event timing, enabling
and setting priority levels for interrupts caused by external stimuli
• For applications in which cost, power and space are critical
• Single-purpose

CPU RAM ROM


A single chip

I/O Timer Serial


Port
4.3 Introduction to 8051 Microcontroller
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The 8051 is one of the most popular microcontrollers
College in use today. Many derivative
Microcontroller
microcontrollers have since been developed that are based on and compatible with
the 8051. Thus, the ability to program an 8051 is an important skill for anyone who
plans to develop products that will take advantage of microcontrollers.

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4.4 Features of the standard 8051
– 4K bytes internal ROM (program)
– 128 bytes internal RAM (data)
– Four 8-bit I/O ports
– Two 16-bit timers
– Serial interface
– 64K external code memory space
– 64K external data memory space
– 210 bit-addressable locations

4.5 Block diagram of 8051


External interrupts
On-chip
Timer/Counte r
Interrupt ROM for
On-chip Timer 1 Counter
Control program
RAM Inputs
code Timer 0

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxDRxD
Address/Data

Fig: 4.1 Block diagram of 8051


Architecture of 8051
Accumulator (ACC) :
The accumulator register act as an operand register, in case of some
instructions .This may either be implicit or specified in the instruction. The Acc
register has been allotted and address in the on chip special function register bank.
B Register :
The register in used to store one of the operands for multiply and divide
instructions . In other instructions, it may just be used as a scratch pad. This
register is considered as a special faction register.
Program status word (PSW)
This set of flags contains the status information and is considered as one on
of the special registers.
Stack pointer (Sp) :
This 8 bit wide register is incremented before the data is stored on to the
stack using push or call instructions. The register contains 8 bit stack top address.
This stack may be defined anywhere in the on chip 128 by the RAM. After reset,
the SP register is initialized to
07. After each write to stack operation, the 8 bit contents of the operand are stored
on to the stack after incrementing the SP register by one . Thus if SP contains 07H,
the forthcoming PUSH operation will store the data at address 08 H in the internal
RAM .The SP content will be incremented to 08.The 8051 stack is not a top down
data structure, like other Intel processors This register has also been allotted an
address in the special function register bank .
Data Pointer (DTPR)
This 16 bit register contains a higher byte (DPH) and the lower byte (DPL) of a

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16 bit external data RAM address. It is accessed
College as a 16 bit register or two 8bit
Microcontroller
register as specified above. It has been allotted two address in the special Function
register bank for its two bytes DPH and DPL

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Fig: 4.2 Architecture of 8051


Port 0 to 3 latches and Drivers:
These four latches and drivers pairs are allotted to each of the four on chip
I/O Ports. These latches have been allotted addresses in the special function
register bank using the allotted address the user can communicate with these ports.
These are identified as P0, P1, P2 and P3
Serial data buffer:
The serial data buffer internally contains two independent registers. one of
them is a transmit buffer which is necessarily a parallel .
Timing and control unit :

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This unit derives all the necessary timing and control signal required
for the internal operation of the circuit It also derives control signal
required for controlling the external system bus oscillator : This circuit
generates the basic timing clock signal for the operation of the circuit
using crystal oscillator .
Instruction Register :
This register decodes the opcode of an instruction to be executed
and gives information to the timing and control unit to generate necessary
signals for the execution of the instruction EPROM and Program Address
Register :
These blocks provide an on chip EPROM and a mechanism to
internally adders it Note that EPROM is not available in all 8051 versions.
RAM and RAM address Register .
This block provide internal 128 bytes of RAM and mechanism to address it
internally .
ALU :
The arithmetic and logic unit performs 8 bit arithmetic and logical
operations over the operands held by the temporary registers TMPI and
TMP2 .Users cannot access these temporary registers .
SFR Register Bank :
This is a set of special function registers which can be addressed
using their respective address which lie in the range 80 H to FFH . Finally
the interrupt , serial port and timer units control and perform their special
functions under the control of the timing and control unit in serial out
register . The other is called receive butter which in a serial in parallel out
register. Loading a byte to the transmit buffer initiates serial transmission
of that byte. The serial data butter in identified as SBUF and is one of the
special function registers. If a byte is written to SBUF, it initiates serial
transmission and if the SBUF is read, it reads received serial data .
Timer Register :
These two 16 bit register can be accessed as their lower and upper
bytes. For example TL0 represents the lower byte of the timing register 0,
while TH0 represents higher bytes of the timing register 0. Similarly TL1
and TH1 represents lower and higher bytes of timing register 1. All these
registers can be accessed using the 4 addresses allotted to them which lies
in the special function registers. SFR address range, ie 80H to FFH .
Control Registers :
The special function registers IP, IE, TMOD, TCON, SCON and PCON
contain control and status information for interrupt timer/ counters and
serial port.These register have been allotted address in the SFR bank of
8051 .
Program Status Word Register(PSW): -
D6 D5 D4 D3 D2 D1 D0

AC F0 RS1 RS0 OV ---- PF

It contains several status bits that reflect the current state of the
CPU. Besides, this register contains four mathematical flags (Carry
flag, Auxiliary Carry, Overflow flag, parity bit) two register bank
select bits (RS1 & RS0), and one user-definable status flag (F0) and
one bit is not defined.
P - Parity bit: - If a number stored in the accumulator A contains even
number of 1’s then this bit will be automatically set (1), otherwise it
will be cleared (0). It is mainly used during data transmit and receive
via serial communication.
OV Overflow: - Overflow occurs when the result of an arithmetical
operation is larger than 255 and cannot be stored in one register.
Overflow condition causes the OV bit to be set (1). Otherwise, it will
be cleared (0).
RS0, RS1 - Register bank select bits. These two bits are used to select
one of four register banks of RAM. By setting and clearing these bits,
registers R0-R7 are stored in one of four banks of RAM.
RS1 RS0 Space in RAM
Bank0 (00H-
0 0 07H)

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Bank1
0 1
(08H- 0FH)
1 0
Bank2
1 1
(10H- 17H)
Bank3

(18H- 1FH)
F0 - Flag 0. This is a general-purpose user defined flagtheuse of this flag is
decided by the user.
AC - Auxiliary Carry Flag: - It is used for BCD operations only. This flag is set
to ‘1’ when in the addition operation the carry is generated at bit position D3
or in subtraction operation borrow is needed at the bit position D3.
CY - Carry Flag: - This flag is set to ‘1’ when in the addition operation the final
carry is generated or in subtraction operation the Minuend is less than the
Subtrahend.
PC (Program Counter): -It addresses the next instruction byte address in the
program memory. Program memory is on chip i.e. is 0000H to 0FFFH,
external to the chip for addresses that exceeds 0FFFH or total external
memory 0000h to 0FFFFH. The content of the PC is automatically
incremented after fetching of the instruction byte from the memory and
some instructions also change the value in the PC. The specialty of this
register is it doesn’t have any internal address.
DPTR (Data Pointer): - It is made up of two 8-bit registers those are DPH &
DPL. This register gives the memory addresses for internal and external code
access and external data access. The DPTR has two independent internal
addresses, one for DPL and another for DPH.
Internal Memory: - The 8051 Microcontroller has internal program memory
(ROM) and internal data memory (RAM). Due to this 8051 has a Harvard
architecture, which uses a same address in different memories, for code and
data.
Internal RAM: - The 8051 microcontroller has 128 bytes of internal RAM, its
address range from 00H to 07FH. From 80H to 0FFH addresses are assigned
to SFRs (Special Function Registers). The internal RAM 128Bytes can divide
into three parts. Those are

1. Register Banks – 32 Bytes (00H – 1FH)


2. Bit/Byte addressable memory – 16 Bytes (20H – 2FH)
3. User memory or General purpose memory—80 Bytes (30H – 7FH)
4.6 Memory Organization
The 8051 microcontroller utilizes the Harvard architecture, with separate code and
data spaces. Memory organization in 8051 is similar to that of the industry standard
8051. There are three memory areas, as shown in Figure 3:
•Program Memory (Internal RAM, External RAM, or External ROM)
•External Data Memory (External RAM)
•Internal Data Memory (Internal RAM)

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Microcontroller

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4.6.1 Program Memory
8051 can address up to 64kB of program memory space, from 0000H to FFFFH. The
External Bus Interface services program memory when the MEMPSRD signal is
active. Program memory is read when the CPU performs fetching instructions or
MOVC. After reset, the CPU starts program execution from location 0000H. The
lower part of the program memory includes interrupt and reset vectors. The
interrupt vectors are spaced at eight-byte intervals, starting from 0003H. Program
memory can be implemented as Internal RAM, External RAM, External ROM, or a

combination of all three.


Fig: 4.4 Program memory
4.6.2 External Data Memory
8051 can address up to 64kB of external data memory space, from 0000H to
FFFFH. The External Bus Interface services data memory when the MEMRD signal is
active. Writing to external program memory is only supported in debug mode using
the OCI logic block and external debugger hardware and software. 8051 writes into
external data memory when the CPU executes MOVX @Ri ,A or MOVX @DPTR,A
instructions. The external data memory is read when the CPU executes MOVX A,
@Ri or MOVX A,@DPTR instructions. There is improved variable length of the MOVX
instructions to access fast or slow external RAM and external peripherals. The three
low-ordered bits of the CKCON register control stretch memory cycles. Setting
CKCON stretch bits to logic 1 values enables access to very slow external RAM or
external peripherals.
There are two types of instructions; one provides an 8-bit address to the
external data RAM, the other a 16-bit indirect address to the external data RAM. In
the first instruction type, the contents of R0 or R1 in the current register bank
provide an 8-bit address. The eight high ordered bits of address are stuck at zero.
Eight bits are sufficient for external l/O expansion decoding or a relatively small
RAM array. For somewhat larger arrays, any output port pins can be used to output
higher-order address bits. These pins are controlled by an output instruction
preceding the MOVX. In the second type of MOVX instructions, the data pointer
generates a 16- bit address. This form is faster and more efficient when accessing
very large data arrays (up to 64kB), since no additional instructions are needed to
set up the output ports. In some situations, it is possible to mix the two MOVX
types. A large RAM array, with its high-order address lines, can be addressed via the
data pointer or with code to output high-order address bits to any port followed by a
MOVX instruction using R0 or R1.

4.6.3 Internal Data Memory


The internal data memory interface services up to 256 bytes of off-core data
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memory.
College The internal data memory address Microcontroller
is always one byte wide. The memory
space is 256 bytes large (00H to FFH) and can be accessed by direct or indirect
addressing. The SFRs occupy the upper 128 bytes. This SFR area is available only
by direct addressing. Indirect addressing accesses

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the upper 128 bytes of internal RAM. The lower 128 bytes contain work registers
and bit addressable memory. The lower 32 bytes form four banks of eight registers
(R0-R7). Two bits on the program memory status word (PSW) select which bank is in
use. The next 16 bytes form a block of bit-addressable memory space at bit
addressees 00H-7FH. All of the bytes in the lower 128 bytes are accessible through
direct or indirect addressing. The internal data memory is not instantiated in 8051.
The user may use internal memory resources if the ProASICPLUS or Axcelerator
families are used. The SX-A and RTSXS-S families have no internal memory
resources, thus the user would need to either create and instantiate a distributed
RAM or use an external memory device.

Lower 128 Bytes of Internal RAM


Fig: 4.5 Internal Data Memory
4.6.4 On-Chip Memory.
The 8051 includes a certain amount of on chip memory. On-chip memory is really
one of two (SFR) memory. The layout of the 8051's internal memory is presented in
the following memory map:

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Fig: 4.6 On-Chip Memory


As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM.
This Internal RAM is found on-chip on the 8051 so it is the fastest RAM available, and
it is also the most flexible in terms of reading, writing, and modifying it’s contents.
Internal RAM is volatile, so when the 8051 is reset this memory is cleared. The 128
bytes of internal ram is subdivided as shown on the memory map. The first 8 bytes
(00h - 07h) are "register bank 0". By manipulating certain SFRs, a program may
choose to use register banks 1, 2, or 3. These alternative register banks are located
in internal RAM in addresses 08h through 1Fh. We'll discuss "register banks" more
in a later chapter. For now it is sufficient to know that they "live" and are part of
internal RAM. Bit Memory also lives and is part of internal RAM. Bit memory actually
resides in internal RAM, from addresses 20h through 2Fh. The 80 bytes remaining of
Internal RAM, from addresses 30h through 7Fh, may be used by user variables that
need to be accessed frequently or at high-speed. This area is also utilized by the
microcontroller as a storage area for the operating stack. This fact severely limits
the 8051’s stack since, as illustrated in the memory map, the area reserved for the
stack is only 80 bytes and usually it is less since this 80 bytes has to be shared
between the stack and user variables.
4.6.5 Bit Memory
The 8051, being a communications oriented microcontroller, gives the user
the ability to access a number of bit variables. These variables may be either 1 or 0.
There are 128 bit variables available to the user, numbered 00h through 7Fh. The
user may make use of these variables with commands such as SETB and CLR. It is
important to note that Bit Memory is really a part of Internal RAM. In fact, the 128
bit variables occupy the 16 bytes of Internal RAM from 20h through 2Fh. Thus, if you
write the value FFh to Internal RAM address 20h you’ve effectively set bits 00h
through 07h. But since the 8051 provides special instructions to access these 16
bytes of memory on a bit by bit basis it is useful to think of it as a separate type of
memory. However, always keep in mind that it is just a subset of Internal RAM—and
that operations performed on Internal RAM can change the values of the bit
variables.
Bit variables 00h through 7Fh are for user defined functions in their programs.
However, bit variables 80h and above are actually used to access certain SFRs on a
bit-by-bit basis.
4.6.6 Special Function Register (SFR) Memory
Special Function Registers (SFRs) are areas of memory that control specific
functionality of the 8051 processor. For example, four SFRs permit access to the
8051’s 32 input/output lines. Another SFR allows a program to read or write to the
8051’s serial port. Other SFRs allow the user to set the serial baud rate, control and
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access
Collegetimers, and configure the 8051’s interrupt system. When programming, SFRs
Microcontroller
have the illusion of being Internal Memory. When using this method of memory
access (it’s called direct address), any instruction that has an address of 00h
through 7Fh refers to an Internal RAM memory address; any instruction with an
address of 80h through FFh refers to an SFR control register.

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4.7 8051 SFRs
What Are SFRs?
The 8051 is a flexible microcontroller with a relatively large number of modes of
operations. Your program may inspect and/or change the operating mode of the
8051 by manipulating the values of the 8051's Special Function Registers (SFRs).
SFRs are accessed as if they were normal Internal RAM. The only difference is that
Internal RAM is from address 00h through 7Fh whereas SFR registers exist in the
address range of 80h
through FFh. Each SFR has an address (80h through FFh) and a name. The following
chart provides a graphical presentation of the 8051's SFRs, their names, and their
address.
As you can see, although the address range of 80h through FFh offer 128 possible
addresses, there are only 21 SFRs in a standard 8051. All other addresses in the
SFR range (80h through FFh) are considered invalid. Writing to or reading from
these registers may produce undefined values or behavior
4.7.1 SFR Types
As mentioned in the chart itself, the SFRs that have a blue background are SFRs
related to the I/O ports. The 8051 has four I/O ports of 8 bits, for a total of 32 I/O
lines. Whether a given I/O line is high or low and the value read from the line are
controlled by the SFRs in green. The SFRs with yellow backgrounds are SFRs which
in some way control the operation or the configuration of some aspect of the 8051.

Fig: 4.7 SFR


For example, TCON controls the timers, SCON controls the serial port. The
remaining SFRs, with green backgrounds, are "other SFRs." These SFRs can be
thought of as auxiliary SFRs in the sense that they don't directly configure the 8051
but obviously the 8051 cannot operate without them. For example, once the serial
port has been configured using SCON, the program may read or write to the serial
port using the SBUF register.
4.7.1.1 SFR Descriptions
This section will endeavor to quickly overview each of the standard SFRs found in
the above SFR chart map. It is not the intention of this section to fully explain the
functionality of each SFR--this information will be covered in separate chapters of
the tutorial. This section is to just give you a general idea of what each SFR does.
4.7.1.2 P0 (Port 0, Address 80h, Bit-Addressable):
This is input/output port 0. Each bit of this SFR corresponds to one of the pins on the
microcontroller. For example, bit 0 of port 0 is pin P0.0, bit 7 is pin P0.7. Writing a
value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.

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4.7.1.3
CollegeSP (Stack Pointer, Address 81h): Microcontroller
This is the stack pointer of the microcontroller. This FR indicates where the next
value to be taken from the stack will be read from in Internal RAM. If you push a
value onto the stack, the

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value will be written to the address of SP + 1. That is to say, if SP holds the value
07h, a PUSH instruction will push the value onto the stack at address 08h. This SFR
is modified by all instructions which modify the stack, such as PUSH, POP, LCALL,
RET, RETI, and whenever interrupts are provoked by the microcontroller.
4.7.1.4 DPL/DPH (Data Pointer Low/High, Addresses 82h/83h):
The SFRs DPL and DPH work together to represent a 16-bit value called the Data
Pointer. The data pointer is used in operations regarding external RAM and some
instructions involving code memory. Since it is an unsigned two-byte integer value,
it can represent values from 0000h to FFFFh (0 through 65,535 decimal).
4.7.1.5 PCON (Power Control, Addresses 87h):
The Power Control SFR is used to control the 8051's power control modes. Certain
operation modes of the 8051 allow the 8051 to go into a type of "sleep" mode which
requires much less power. These modes of operation are controlled through PCON.
Additionally, one of the bits in PCON is used to double the effective baud rate of the
8051's serial port.
4.7.1.6 TCON (Timer Control, Addresses 88h, Bit-Addressable):
The Timer Control SFR is used to configure and modify the way in which the 8051's
two timers operate. This SFR controls whether each of the two timers is running or
stopped and contains a flag to indicate that each timer has overflowed. Additionally,
some non-timer related bits are located in the TCON SFR. These bits are used to
configure the way in which the external interrupts are activated and also contain
the external interrupt flags which are set when an external interrupt has occurred.
Timer/Counter Control Register (TCON)
Table displays the TCON register flags.
MSB LSB
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Table 4.1• TCON Register Bit Functions
Bit Symbol Function
Timer 1 overflow flag. This flag is set when Timer 1
7 TF1
overflows. This flag should be cleared by the user’s
software.
6 TR1 Timer 1 Run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag. This flag is set when Timer 0
5 TF0
overflows. This flag should be cleared by the user’s
software.
4 TR0 Timer 0 Run control bit. If cleared, Timer 0 stops.
3 IE1 Interrupt 1 edge flag. This flag is set when a falling edge
on the external pin int1 is observed. This flag is
cleared when an
interrupt is processed.
2 IT1 Interrupt 1 type control bit. This bit selects whether a
falling edge or a low level on input pin int1 causes an
interrupt.
1 IE0 Interrupt 0 edge flag. This flag is set when a falling edge
on the external pin int0 is observed. This flag is
cleared when an
interrupt is processed.
0 IT0 Interrupt 0 type control bit. This bit selects whether a
falling edge or a low level on input pin int0 causes an
interrupt.

4.7.1.7 TMOD (Timer Mode, Addresses 89h):


The Timer Mode SFR is used to configure the mode of operation of each of the two
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timers.
College Using this SFR your program may configure each timer to be a 16-bit timer,
Microcontroller
an 8-bit auto reload timer, a 13-bit timer, or two separate timers. Additionally, you
may configure the timers to only count when an external pin is activated or to count
"events" that are indicated on an external pin.

Timer/Counter Mode Control Register (TMOD)

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MSB LSB
GATE C/T M1 M0 GATE C/T M1 M0
< Timer 1 < Timer 1
Table 4.2 • TMOD Register Bits Description
Bit Symbol Function
7,3 GATE If set, enables external gate control (pin int0 or int1 for
Counter 0 or Counter 1, respectively). When int0 or int1
is high, and the trx bit is set (see TCON register), the
counter is incremented every
falling edge on the t0 or t1 input pin.
6, 2 C/T Selects Timer or Counter operation. When set to logic
1, a Counter operation is performed. When cleared to
logic 0, the
corresponding register will function as a Timer.
5, 1 M1 Selects the mode for Timer/Counter 0 or Timer/Counter 1.
4, 0 M0 Selects the mode for Timer/Counter 0 or Timer/Counter 1.

Table provides timer and counter mode descriptions.


M1 M0 Mode Function
0 0 Mod 13-bit Counter/Timer, with five lower bits in the tl0
e0 or tl1 register and eight bits in the th0 or th1
register (for Timer
0 and Timer 1, respectively). The three high order
bits of the tl0 and tl1 registers are held at zero.
Mod
0 1 16-bit Counter/Timer
e1
1 0 Mode2 8-bit auto-reload Counter/Timer. The reload value
is kept in the TH0 or TH1 register, while the tl0 or
tl1 register is incremented every machine cycle.
When the tl0 or tl1
register overflows, the value in the th0 or th1
register is copied to the tl0 or tl1 register,
respectively.
1 1 Mode3 If the M1 and M0 bits in Timer 1 are set to logic 1,
Timer 1 stops. If the M1 and M0 bits in Timer 0 are
set to logic 1, Timer 0 acts as two
independent 8-bit
Timers/Counters.
4.7.1.8 TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Bh):
These two SFRs, taken together, represent timer 0. Their exact behavior depends
on how the timer is configured in the TMOD SFR; however, these timers always
count up. What is configurable is how and when they increment in value.
4.7.1.9 TL1/TH1 (Timer 1 Low/High, Addresses 8Ch/8Dh):
These two SFRs, taken together, represent timer 1. Their exact behavior depends
on how the timer is configured in the TMOD SFR; however, these timers always
count up. What is configurable is how and when they increment in value.
4.7.1.10 P1 (Port 1, Address 90h, Bit-Addressable):
This is input/output port 1. Each bit of this SFR corresponds to one of the pins on the
microcontroller. For example, bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a
value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.
4.7.1.11 SCON (Serial Control, Addresses 98h, Bit-Addressable):
The Serial Control SFR is used to configure the behavior of the 8051's on-board
serial port. This SFR controls the baud rate of the serial port, whether the serial port
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is activated to receive data, and also contains
College flags that are set when a byte is
Microcontroller
successfully sent or received.
4.7.1.12 SBUF (Serial Control, Addresses 99h):
The Serial Buffer SFR is used to send and receive data via the on-board serial port.
Any value written to SBUF will be sent out the serial port's TXD pin. Likewise, any
value which the 8051 receives via the serial port's RXD pin will be delivered to the
user program via SBUF. In other words, SBUF serves as the output port when
written to and as an input port when read from.

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4.7.1.13 P2 (Port 2, Address A0h, Bit-Addressable):
This is input/output port 2. Each bit of this SFR corresponds to one of the pins on the
microcontroller. For example, bit 0 of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a
value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.
4.7.1.14 IE (Interrupt Enable, Addresses A8h):
The Interrupt Enable SFR is used to enable and disable specific interrupts. The low 7
bits of the SFR are used to enable/disable the specific interrupts, where as the
highest bit is used to enable or disable ALL interrupts. Thus, if the high bit of IE is 0
all interrupts are disabled regardless of whether an individual interrupt is enabled
by setting a lower bit.
4.7.1.15 P3 (Port 3, Address B0h, Bit-Addressable):
This is input/output port 3. Each bit of this SFR corresponds to one of the pins on
the microcontroller. For example, bit 0 of port 3 is pin P3.0, bit 7 is pin P3.7. Writing
a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.
4.7.1.16 IP (Interrupt Priority, Addresses B8h, Bit-Addressable):
The Interrupt Priority SFR is used to specify the relative priority of each interrupt.
On the 8051, an interrupt may either be of low (0) priority or high (1) priority. An
interrupt may only interrupt interrupts of lower priority. For example, if we configure
the 8051 so that all interrupts are of low priority except the serial interrupt, the
serial interrupt will always be able to interrupt the system, even if another interrupt
is currently executing. However, if a serial interrupt is executing no other interrupt
will be able to interrupt the serial interrupt routine since the serial interrupt routine
has the highest priority.
4.7.1.17 PSW (Program Status Word, Addresses D0h, Bit-Addressable):
The Program Status Word is used to store a number of important bits that are set
and cleared by 8051 instructions. The PSW SFR contains the carry flag, the auxiliary
carry flag, the overflow flag, and the parity flag. Additionally, the PSW register
contains the register bank select flags which are used to select which of the "R"
register banks are currently selected.
4.7.1.18 ACC (Accumulator, Addresses E0h, Bit-Addressable):
The Accumulator is one of the most used SFRs on the 8051 since it is involved in so
many instructions. The Accumulator resides as an SFR at E0h, which means the
instruction MOV A,#20h is really the same as MOV E0h,#20h. However, it is a good
idea to use the first method since it only requires two bytes whereas the second
option requires three bytes.
4.7.1.19 B (B Register, Addresses F0h, Bit-Addressable):
The "B" register is used in two instructions: the multiply and divide operations. The
B register is also commonly used by programmers as an auxiliary register to
temporarily store values.
4.8 8051 Basic Registers
4.8.1 Accumulator
If you’ve worked with any other assembly languages you will be familiar with the
concept of an Accumulator register. The Accumulator, as it’s name suggests, is used
as a general register to accumulate the results of a large number of instructions. It
can hold an 8-bit (1-byte) value and is the most versatile register the 8051 has due
to the shear number of instructions that make use of the accumulator. More than
half of the 8051’s 255 instructions manipulate or use the accumulator in some way.
For example, if you want to add the number 10 and 20, the resulting 30 will be
stored in the Accumulator. Once you have a value in the Accumulator you may
continue processing the value or you may store it in another register or in memory.
4.8.2 "R" registers
The "R" registers are a set of eight registers that are named R0, R1, etc. up to and
including R7. These registers are used as auxiliary registers in many operations. The
use of the "R" registers as a way to store values temporarily.
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4.8.3 "B" Register
College Microcontroller
The "B" register is very similar to the Accumulator in the sense that it may hold an
8-bit (1-byte) value. The "B" register is only used by two 8051 instructions: MUL AB
and DIV AB. Thus, if you want to quickly and easily multiply or divide A by another
number, you may store the other number in "B" and make use of these two
instructions. Aside from the MUL and DIV

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instructions, the "B" register is often used as yet another temporary storage register
much like a ninth "R" register.
4.8.4 Data Pointer (DPTR)
The Data Pointer (DPTR) is the 8051’s only user-accessible 16-bit (2-byte) register.
The Accumulator, "R" registers, and "B" register are all 1-byte values. DPTR, as the
name suggests, is used to point to data. It is used by a number of commands which
allow the 8051 to access external memory. When the 8051 accesses external
memory it will access external memory at the address indicated by DPTR. While
DPTR is most often used to point to data in external memory, many programmers
often take advantage of the fact that it’s the only true 16- bit register available. It is
often used to store 2- byte values which have nothing to do with memory locations.
4.8.5 Program Counter (PC)
The Program Counter (PC) is a 2-byte address which tells the 8051 where the next
instruction to execute is found in memory. When the 8051 is initialized PC always
starts at 0000h and is incremented each time an instruction is executed. It is
important to note that PC isn’t always incremented by one. Since some instructions
require 2 or 3 bytes the PC will be incremented by 2 or 3 in these cases. The
Program Counter is special in that there is no way to directly modify it’s value. That
is to say, you can’t do something like PC=2430h. On the other hand, if you execute
LJMP 2340h you’ve effectively accomplished the same thing. It is also interesting to
note that while you may change the value of PC (by executing a jump instruction,
etc.) there is no way to read the value of PC.
4.8.6 Stack Pointer (SP)
The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte)
value. The Stack Pointer is used to indicate where the next value to be removed
from the stack should be taken from. When you push a value onto the stack, the
8051 first increments the value of SP and then stores the value at the resulting
memory location. When you pop a value off the stack, the 8051 returns the value
from the memory location
indicated by SP, and then decrements the value of SP. This order of operation is
important. When the 8051 is initialized SP will be initialized to 07h. If you
immediately push a value onto the stack, the value will be stored in Internal RAM
address 08h. This makes sense taking into account what was mentioned two
paragraphs above: First the 8051 will increment the value of SP (from 07h to 08h)
and then will store the pushed value at that memory address (08h). SP is modified
directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI. It
is also used intrinsically whenever an interrupt is triggered

4.9 8051 Addressing Modes


An Addressing Mode indicates how the data is represented in the instruction. 8051
supports 6 types of Addressing Modes, those are
1. Immediate Addressing mode
2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Direct Addressing Mode
5. Indexed Addressing Mode
6. Implicit Addressing Mode
1. Immediate Addressing Mode: -In these addressing mode instructions the data is
directly placed in the source operand field of the instruction, and a ‘#’ symbol must
prefix for the data. Ex: -MOV A, #38H
ADD A, #67H
2. Register Addressing Mode: -In these addressing mode instructions the data is
directly placed in the operand field of the instruction through a GPR (General
Purpose Register).
EX: - MOV A, B
ADD A, R0
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Register Indirect Addressing Mode: -In these
College
3. addressing mode instructions the
Microcontroller
address of the data is indirectly placed in the operand field of the instruction
through a GPR (General Purpose Register) R0 or R1.
Ex: - MOV A, @R0

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ADD A, @R1
4. Direct Addressing Mode: - In these addressing mode instructions the address of the
data is directly placed in the operand field of the instruction. The address is the
internal RAM or internal SFR (Special Function Register).
Ex: - MOV A, 20H
MOV R1, 70H
5. Indexed Addressing Mode: -In these addressing mode instructions the address of
the data is indirectly placed in the operand field of the instruction through
combination ‘A’ register PC or DPTR.
Ex: - MOVC A,
@A+DPTR MOVC A,
@A+PC
6. Implied Addressing Mode: -In this addressing mode instruction the operand is
implicitly represented in the operation code of the instruction.
Ex: - NOP, RET, RETI
4.9 8051 Addressing Modes( 12Mark)
Definition:
 The different ways in which a source operand in an instruction are known
as the addressing modes.
 The 8051 provides a total of five distinct addressing modes
 Immediate Addressing mode
 Register Addressing mode
 Direct Addressing mode
 Register Indirect Addressing mode
 Indexed Addressing mode

4.9.1 Immediate Addressing mode


 In this addressing mode the source operand is constant. In immediate
addressing mode, when the instruction is assembled, the operand comes
immediately after the op-code.
 The immediate data must be preceded by ‘#’ sign.
 This addressing mode can be used to load information into any of the
register, including the DPTR

Example:
MOV A,
#25H MOV
R4, #62
MOV B,
#40H
MOV DPTR, #4521H
Although the DPTR register is 16-bit, it can also be accessed as two 8-bit registers,
DPH and DPL, where DPH is the high byte and DPL is the low byte.

4.9.2 Register addressing mode


Register addressing mode involves the use of registers to hold the data to be
manipulated.

Example:
MOV A, R0 ;copy the contents of R0 into A
MOV R2, A ;copy the contents of A in to R2
ADD A, R5 ;add the contents of R5 to
contents of A ADD A, R7 ;add the contents of R7
to contents of A MOV R6, A ;save accumulator in R6
It should be noted that the source and destination registers must match in size
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4.9.3 Direct Addressing mode
The RAM has been assigned addresses 00 to 7FH. The following is a summary of the
allocation of these 128 bytes

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 RAM location 00 - 1FH are assigned to the register banks and stack
 RAM location 20 - 2FH are set aside as bit-addressable space to save
single- bit data.
 RAM location 30 - 7FH are available as a place to save byte-sized data.

Although the entire 128 bytes of RAM can be accessed using direct addressing
modem it is most often used to access RAM locations 30 – 7FH. This is due to the
fact that register bank locations are accessed by the register names of R0-R7, but
there is no such name for other RAM locations

4.9.4 Register Indirect Addressing mode


In the register indirect addressing mode, a register is used as a pointer to the data.
If the data is inside the CPU, only registers R0 and R1 are used for this purpose.
When R0 and R1are used as pointers, that is, when they hold the addresses of RAM
locations, they must be preceded by the “@”sign.

Example:
MOV A, @R0 ;move contents of RAM location whose address is held
by R0 into A
MOV @R1, B ;move contents of B into RAM location whose
address is held by R1
Notice that R0 is preceded by the “@” sign. In the absence of the “@” sign, MOV
will be interpreted as an instruction moving the contents of register R0 to A, instead
of the contents of the memory location pointed to by R0.

Advantages:
One of the advantages of register indirect addressing mode is that it makes
accessing data dynamic rather than static as in the case of direct addressing mode.

4.9.5 Indexed Addressing mode


In these addressing mode used access the program memory only.In these
addressing mode instructions the address of the data is indirectly placed in the
operand field of the instruction through combination ‘A’ register PC or DPTR.
Ex: - MOVC A, @A+DPTR
MOVC A, @A+PC
4.9.6.Implied Addressing Mode: -In this addressing mode instruction the operand is
implicitly represented in the operation code of the instruction.
Ex: - NOP, RET, RETI

4.10 I/O PINS PORTS AND CIRCUITS


 There are four ports P0, P1, P2 and P3 each use 8 pins, making them 8-bit
ports.
 All the ports upon RESET are configured as output, ready to be used as output
ports.
 To use any of these ports as an input port, it must be programmed.
 Pin configuration of 8051/8031 microcontroller.

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Fig 4.8: Pin configuration of 8951


Port 0
 Port 0 occupies a total of 8 pins (pins 32-39) .It can be used for input or output.
 To use the pins of port 0 as both input and output ports
 Each pin must be connected externally to a 10K ohm pull-up resistor.
 Due to the fact that P0 is an open drain, unlike P1, P2, and P3.
 Open drain is a term used for MOS chips in the same way that open collector
is used for TTL chips. With external pull-up resistors connected upon reset, port 0 is
configured as an output port.
Example:
The following code will continuously send out to port 0 the alternating values 55H
and AAH BACK: MOV A,#55H
MOV P0,A
ACALL DELAY
MOV

A,#0AAH MOV
P0,A
ACALL DELAY
SJMP BACK

Port 0 as Input
 With resistors connected to port 0, in order to make it an input, the port must
be programmed by writing 1 to all the bits.
 In the following code, port 0 is configured first as an input port by writing 1′s
to it, and then data is received from the port and sent to P1.

MOV A,#0FFH ; A = FF hex


MOV P0,A ; make P0 an input port
BACK: MOV A,P0 ; get data from
P0 MOV P1,A ; send it to port 1
SJMP BACK ; keep doing it

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Fig 4.9: Port 0 with pull-up resistors


Dual role of port 0
 Port 0 is also designated as AD0-AD7, allowing it to be used for both address
and data.
 When connecting an 8051/31 to an external memory, port 0 provides both
address and data.
 The 8051 multiplexes address and data through port 0 to save pins.

Port 1
 Port 1 occupies a total of 8 pins (pins 1 through 8).
 It can be used as input or output.
 In contrast to port 0, this port does not need any pull-up resistors since it
already has pull-up resistors internally.
 Upon reset, Port 1 is configured as an input port.
Example
The following code will continuously send out to port1 the alternating values
55H & AAH MOV A,#55H
BACK: MOV
P1,A
ACALL DELAY
CPL A
SJMP BACK
Port 1 as input
 Port1 an input port, it must programmed as such by writing 1 to all its bits.
 In the following code port1 is configured first as an input port by writing
1’s to it, then data is received from the port and saved in R7 ,R6 & R5.
MOV A,#0FFH ; A=FF HEX
MOV P1,A ; make P1 an input port by writing all
1’s to it
MOV A,P1 ; get data from P1
MOV R7,A ; save it in register R7
ACALL DELAY ; wait
MOV A,P1 ; get another data from P1
MOV R6,A ; save it in register R6
ACALL DELAY ; wait
MOV A,P1 ; get another data from P1
MOV R5,A ; save it in register R5
Port 2
 Port 2 occupies a total of 8 pins (pins 21- 28).
 It can be used as input or output.
 Just like P1, P2 does not need any pull-up resistors since it already has pull-up
resistors internally.
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CollegeUpon reset, Port 2 is configured as an output port.
Microcontroller
Example:

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The following code will send out continuously to port 2 the alternating values 55h
and AAH. That is all the bits of port 2 toggle continuously.
MOV A,#55H
BACK: MOV P2,A
ACALL DELAY
CPL A
SJMP BACK
Port 2 as input
 To make port 2 an input, it must programmed as such by writing 1 to all its bits.
 In the following code, port 2 is configured first as an input port by writing 1’s to
it.
 Then data is received from that port and is sent to P1 continuously.
Example:
MOV A,#0FFH ;A=FF hex
MOV P2,A ;make P2 an input port by writing all
1’s to it BACK: MOV A,P2 ;get
data from P2
MOV P1,A ;send it to Port1
SJMP BACK ;keep doing that
Dual role of port 2
 In systems based on the 8751, 8951, and DS5000, P2 is used as simple I/O.
 in 8031-based systems, port 2 must be used along with P0 to provide the 16-
bit address for the external memory.
 While P0 provides the lower 8 bits via A0-A7, it is the job of P2 to provide bits
A8-A15 of the address.
 In other words, when 8031 is connected to external memory.
 P2 is used for the upper 8 bits of the 16 bit address, and it cannot be used for
I/O.
Port 3
 Port 3 occupies a total of 8 pins, pins 10 through 17.
 It can be used as input or output. P3 does not need any pull-up resistors, the
same as P1 and P2 did not.
 Although port 3 is configured as an output port upon reset.
 Port 3 has the additional function of providing some extremely important
signals such as interrupts.
 This information applies both 8051 and 8031 chips.
P3 BIT FUNCTION PIN
P3.0 RXD 10
P3.1 TXD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17

Table 4.3: Functions of port 3


 P3.0 and P3.1 are used for the RxD and TxD serial communications signals.
 Bits P3.2 and P3.3 are set aside for external interrupts.
 Bits P3.4 and P3.5 are used for timers 0 and 1.
 Finally P3.6 and P3.7 are used to provide the WR and RD signals of external
memories connected in 8031 based systems.
4.11 INSTRUCTION SET
Instruction Set of 8051 Microcontroller: -All instructions of 8051 can be divided in to
Four different groups, those are

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1.
CollegeData Transfer Instructions Microcontroller
2. Arithmetic Instructions

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3. Logical Instructions
4. Branching Instructions
1. Data Transfer Instructions: -Data transfer instructions are also called as Data
Movement Instructions or Data Copying Instructions. Data transfer instruction
execution doesn’t effect on the Mathematical flags in PSW. In this group of
instructions the Xerox copy of data is transferred from source to destination,
because of this after execution of the instruction the content of source is equal to
the content of destination. In this microcontroller data transfer instruction three
types.
A. Move Related Instructions
B. Stack Related Instructions
C. Exchange Related Instructions
A. Move Related Instructions: - There are three types move related instructions.
i. MOV ii. MOVX iii. MOVC
i. MOV Instruction:-This instruction is used for onboard data transfers in 8051
Microcontroller. Ex: - MOV R1, #68H MOV A, #88H
MOV A, R0 MOV DPTR, #0896H
ii. MOVX Instruction: - This instruction is used for data transfers between external
RAM and Microcontroller through ‘A’ register. This instruction only supports Register
Indirect Addressing Mode.
Ex: - MOVX A, @RP MOVX A, @DPTR
MOVX @RP, A MOVX @DPTR, A
iii. MOVC Instruction: - This instruction is used for data transfers between internal or
external ROM and the Microcontroller through ‘A’ register. This instruction only
supports Indexed Addressing Mode it is one type of Register Addressing Mode.
Ex: - MOVC A, @A+DPTR MOVC A, @A+PC

External Addressing Using MOVX and MOVC Instructions: -

Fig.4.9.(a).External addressing
B. Stack Related Instructions: -There are two instructions are there in this group.
These instructions are used for data transfer between the internal RAM and the
specified Direct Address in the instruction. The internal RAM can be used as Stack.
The instructions are
i. PUSH ii. POP
i. PUSH Instruction: - This instruction is used for transferring the data from specified
Direct Address into Top of the Stack. For this instruction execution the SP content is
increment by ‘1’. In this instruction execution the internal operations are performed
in the following order. It support only Direct Addressing Mode
1. SP content increment by ‘1’
2. Specified Direct Address content is pushed on to SP specified location in the Stack.
Ex: - PUSH 76H
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POP Instruction: -This instruction is used forMicrocontroller
College
ii. transferring the data from Top of the
Stack to specified Direct Address. For this instruction execution the SP content is
decrement by ‘1’. In

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this instruction execution the internal operations are performed in the following order. It
supports only Indirect Addressing Mode.
1. SP specified location in the Stack content is copied to Specified Direct
Address in instruction.
2. SP content decrement
by ‘1’ Ex: - POP 86H
C. Exchange Related Instructions: -In this group there are two instructions. In these
instructions one operand is accumulator register ‘A’. These instructions don’t
support Immediate Addressing Mode.
i. XCH ii. XCHD
i. XCH Instruction: - This instruction is used for data exchanging between
Accumulator register ‘A’ and the specified other operand in the instruction.
Ex: - XCH A, R0 XCH A,
@R1 XCH A, 46H
ii. XCHD Instruction: -This instruction is used for Least Significant Nibbles data
exchanging between Accumulator register ‘A’ and the specified other operand in
the instruction.
Ex: - XCHD A, R0 XCHD A,
@R1 XCHD A, 46H
2. Arithmetic Instructions: -The microcontroller 8051 supports the following
arithmetic operations. If any arithmetic instruction is executed by controller based
on the result the mathematical flags are modified. For these arithmetic instructions
one operand must be the content of accumulator ‘A’and after completion of
operation the result is stored in register ‘A’.
i. Addition ii. Subtraction iii. Multiplication iv. Division
v. Increment vi. Decrement vii. Decimal Adjust
i. Addition Instructions: -There are two instructions for to perform addition operation.
Those are
a. ADD b. ADDC
a. ADD Instruction: -This instruction is used to perform addition between
Accumulator and specified another operand in the instruction. It supports all
addressing modes.
Ex: - ADD A, R0 ADD A, #24H ADD A, @R0 ADD A, 68H
b. ADDC Instruction: -This instruction is used to perform addition between
Accumulatorspecified another operand in the instruction and previous operation
generated carry. It supports all addressing modes.
Ex: - ADDC A, R0 ADDC A, #24H
ADDC A, @R0 ADDC A, 68H
ii. Subtraction Instruction: -Only one instruction is there for performing the
subtraction operation. That is subtraction with borrow ‘SUBB’. For this Accumulator
content is Minuend. SUBB Instruction: -This instruction is used to
perform subtraction between Accumulatorspecified another
operand in the instruction and previous operation generated carry. It supports all
addressing modes.
Ex: - SUBB A, R0 SUBB A,
#24H SUBB A, @R0 SUBB A, 68H
iii. Multiplication Instruction: -Only one instruction is there for performing the
Multiplication operation. This instruction syntax is fixed, and it support only two 8-
bits numbers Multiplication. MUL Instruction: - This instruction is used to perform
Multiplication between ‘A’ register and ‘B’ register. The result of the Multiplication
is stored in B & A registers. MSByte is stored in ‘B’ register and LSByte is stored
in ‘A’ register.
Ex: - MUL AB
iv. Division Instruction: -Only one instruction is there for performing the Division
operation. This instruction syntax is fixed, and it support only two 8-bits numbers
Division.
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Instruction: -- This instruction is used to perform
DIVCollege Division between ‘A’ register and
Microcontroller
‘B’ register. The result of the Division is stored in A & B registers. Quotient is stored
in ‘A’ register and Remainder is stored in ‘B’ register.
Ex: - DIV AB

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v. Increment Instruction: - Only one instruction is there for performing the Increment
operation. It supports all types of addressing modes except Immediate addressing
Mode. No mathematical flag is affected for this instruction execution.
INC Instruction: -This instruction is used to increment the specified operand content
by ‘1’. The operand may not an immediate data.
Ex: - INC R0 INC 70H INC @R0 INC DPTR INC A
vi. Decrement Instruction: -Only one instruction is there for performing the
decrement operation. It supports all types of addressing modes except Immediate
addressing Mode. No mathematical flag is affected for this instruction execution.
DEC Instruction: -This instruction is used to decrement the specified operand
content by ‘1’. The operand may not an immediate data.
Ex: - DEC R0 DEC 70H DEC @R0 DEC DPTRDEC A
vii. Decimal Adjust Instruction: -Only one instruction is there for performing the
decimal adjust operation. It supports only register addressing mode. For this
Instruction the operand is Accumulator register ‘A’ only.
DA A Instruction: -This instruction is used to decimal adjust the accumulator content,
it means convert the binary content of register ‘A’ into BCD form.
Ex: - DA A
3. Logical Instructions: -The 8051 support two types of logical operations based on
the size of applied data. Those are Byte level Logical Instructions and Bit Level
Logical Instructions. 8051 support the following logical operations,
i. AND ii. OR iii. XOR iv. NOT
A. Byte level Logical Instructions: -
i. AND Instructions: -Only one instruction is there for performing the logical AND
operation.It supports all addressing modes.
ANL Instruction: - This instruction is used to perform Logical AND operation between
the source operand and destination operands. The destination operand is either ‘A’
register or an Address but the source is a register, or an immediate data, or an
address.
Ex: - ANL A, R0 ANL 70H, R1 ANL A, #80H ANL 76H, #74H ANL A, @R0
ii. OR Instruction: -Only one instruction is there for performing the logical OR
operation.It supports all addressing modes.
ORL Instruction: - This instruction is used to perform Logical OR operation between
the source operand and destination operands. The destination operand is either ‘A’
register or an Address but the source is a register, or an immediate data, or an
address.
Ex: - ORL A, R0 ORL 70H, R1 ORL A, #80H ORL 76H, #74H ORL A, @R0
iii. XOR Instruction: -Only one instruction is there for performing the logical XOR
operation.It supports all addressing modes.
XRL Instruction: - This instruction is used to perform Logical XOR operation between
the source operand and destination operands. The destination operand is either ‘A’
register or an Address but the source is a register, or an immediate data, or an
address.
Ex: - XRL A, R0 XRL 70H, R1 XRL A, #80H XRL 76H, #74H XRL A, @R0
iv. NOT Instruction: -Only one instruction is there for performing the logical NOT
operation. For this instruction the operand is Accumulator register ‘A’.
CPL Instruction: - This instruction is used to complement the content of Accumulator
register. Ex: - CPL A
Rotation Related Instructions: -All these instructions are designed based on the ‘A’
register is an operand of the instruction, and all these instructions support register
addressing mode only. RL Instruction: - This instruction is used to rotate the
accumulator content bit by bit to left side. MSbit is copied into LSbit and Carry flag
position.
Ex: - RL A

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RR Instruction: -This instruction is used to rotate
College the accumulator content bit by bit
Microcontroller
to right side. LSbit is copied intoMSbit and Carry flag position.

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Ex: - RR A

RLC Instruction: -This instruction is used to rotate the accumulator content bit by bit
to left side through Carry. MSbit is copiedto Carry flag position and Carry bit is
copied to LSbit position.
Ex: - RLC A

RRC Instruction: -This instruction is used to rotate the accumulator content bit by bit
to right side through Carry. LSbit is copiedto Carry flag position and Carry bit is
copied to MSbit position.
Ex: - RRC A

SWAP Instruction: - This instruction is used to exchange the nibbles of Accumulator


register. Ex: - SWAP A

B. Bit level Logical Instructions: -These instructions perform operations on any Bit
Addressable RAM or SFR bits. The Carry flag in the PSW can be used as destination
for maximum number of instructions.
We have bit related instructions for the operations like Logical AND, OR,
Complement, Clear, Set and Move.
AND Instructions: -
i. ANL C, b: - This instruction is used logical AND between Carry Flag (CY) and the
specified direct addressed bit in the instruction. Ex: - ANL C, 64H.
ii. ANL C, : -This instruction is used logical AND between Carry Flag (CY) and
the
complement of specified direct addressed bit in the instruction. Ex: - ANL C,
OR Instructions: -
i. ORL C, b -This instruction is used FOR logical OR between Carry Flag (CY) and the
specified direct addressed bit in the instruction. Ex: - ORL C, 64H.
ii. ORL C, : -This instruction is used logical OR between Carry Flag (CY) and
the
complement of specified direct addressed bit in the instruction. Ex: - ORL C,
Complement Instructions: -
i. CPL C : - This instruction is used to Complement the Carry flag content.
ii. CPL b : - This instruction is used to Complement the specified direct addressed bit
content.

Clear Instructions: -
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i. CLR C : - This instruction is used to Clear theMicrocontroller
College Carry flag content.
ii. CLRb -This instruction is used to Clear the specified direct addressed bit content.
Set Instructions: -
i. SETB C : - This instruction is used to Set the Carry flag content.

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ii. SETB b: - This instruction is used to Set the specified direct addressed bit content.
Move Instructions: -
i. MOV C, bInstruction: - This instruction is used Move the content of the specified
direct addressed bit in the instruction to the Carry Flag (CY). Ex: - MOV C, 64H.
i. MOV b, CInstruction: - This instruction is used Move the content ofthe Carry Flag
(CY) tothespecified direct addressed bit in the instruction. Ex: - MOV 64H, C.
4. Branching Instructions: - These instructions are also called as Transfer of control
Instructions, or Program flow control instructions. By using these instructions the
program flow control is transferred from one location to another location
conditionally or unconditionally. Basically these are two types of instructions
A. Unconditional Branching Instructions
B. Conditional Branching Instructions
A. Unconditional Branching Instructions: -These instructions are used to change the
program flow control from one location to another location without taking any
condition from the flags of PSW or Accumulator content. In this mainly there are two
types of instructions.
a. Jump Related Instructions,
b. Call and Return Related Instructions.
a. Jump Related Instructions: -These instructions are used to change the program
execution from one location to another location unconditionally.Inthis different
instructions are available in 8051 Microcontroller instruction set. Those are
i. SJMP ii. AJMP iii. LJMP iv. JMP
i. SJMP Instruction: -It is a Short Jump Instruction. By using this jump instruction
execution is moved to the previous locations or next locations. The destination must
be in the range -128 to
+127 from the current instruction. For this instruction the operand is an 8-bit relative
address. The operand address is added to or subtracted from the current content of
PC. This instruction is also used as termination instruction in 8051 programs.
Ex: - SJMP 8-bit Relative address
ii. AJMP Instruction: -It is anAbsolute Jump Instruction. By using this jump instruction
execution is moved to only next locations. The destination must be within 2K
locations from the current instruction. For this instruction the operand is an 11-bit
address. The operand address is added to the current content of PC.
Ex: - AJMP 11-bit address
iii. LJMP Instruction: -It is a Long Jump Instruction. By using this jump instruction
execution is moved to only next locations. The destination is any location in the 64K
locations of the memory. For this instruction the operand is a 16-bit address. The
operand address is added to the current content of PC.
Ex: - LJMP 16-bit address
iv. JMP Instruction: -It is a simple Jump Instruction. By using this jump instruction
execution is moved to the location address is provided by the combination of ‘A’
register and DPTR register.
Ex: - JMP @A + DPTR
b. Call and Return Related Instructions: - By using the Call and Return instructions the
subprogram is called into the main program. Call instruction is used to change the
program execution from the main program to subprogram, and by using Ret
instruction the program execution is shifted from the subprogram to the main
program. There are two Call related instructions, those are
i. ACALL ii. LCALL
i. ACALL Instruction: -By using this instruction to call a subprogram into the main
program. But the subprogram must be within the 2K locations. In another way the
subprogram and the main program must be in the same page and the page size is
2KB.
Ex: - ACALL 11-bit address
ii. LCALL Instruction: -By using this instruction to call a subprogram into the main
program. The subprogram is in any location in the 64K locations. Ex: - LCALL 16-bit
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There are two Return Related Instructions, those are
i. RET ii. RETI

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i. RET Instruction: -By using this instruction the program execution is shift from the
subprogram to the main program, and this instruction is used as last instruction in
the subprogram. This instruction is comes under implicit addressing mode. Ex: - RET
ii. RETI Instruction: -By using this instruction the program execution is shift from
theInterrupt Service Routine (ISR) to the main program, and this instruction is used
as last instruction in the ISR. This instruction also comes under implicit addressing
mode.
Ex: - RETI
B. Conditional Branching Instructions: -These instructions are used to change the
program flow control from one location to another location with taking condition
from the flags of PSW or Accumulator content. All Conditional Jump instructions are
Relative Jump instructions or Short Jump Instructions. In this mainly there are three
types of instructions.
a. Conditional Jump Instructions
b. Comparison Related Instructions
c. Decrement Related Instructions
a. Conditional Jump Instructions: -These Instructions are designed based on the
conditions of Carry flag in the PSW, Accumulator content and the specified bit.
i. JC Instruction: -By using this instruction the program execution is shift from one
location to other location only if the CY = ‘1’. Otherwise the instruction is ignored.
Ex: - JC 8-bit rel add
ii. JNC Instruction: -By using this instruction the program execution is shift from one
location to other location only if the CY = ‘0’. Otherwise the instruction is ignored.
Ex: - JNC 8-bit rel add
iii. JZ Instruction: -By using this instruction the program execution is shift from one
location to other location only if the Accumulator (A) content = ‘0’. Otherwise the
instruction is ignored.
Ex: - JZ 8-bit rel add
iv. JNZ Instruction: -By using this instruction the program execution is shift from one
location to other location only if the Accumulator (A) content not equal to‘0’.
Otherwise the instruction is ignored. Ex: - JNZ 8-bit rel add
v. JB instruction: -By using this instruction the program execution is shift from one
location to other location only if the Specified bit = ‘1’. Otherwise the instruction is
ignored.
Ex: - JB b, 8-bit rel add where ‘b’ indicates the Direct Address of the Bit.
vi. JNB instruction: -By using this instruction the program execution is shift from one
location to other location only if the Specified bit = ‘0’. Otherwise the instruction is
ignored.
Ex: - JNB b, 8-bit rel add where ‘b’ indicates the Direct Address of the Bit.
vii. JBC instruction: -By using this instruction the program execution is shift from one
location to other location only if the Specified bit = ‘1’, and clear that bit also.
Otherwise the instruction is ignored.
Ex: - JBC b, 8-bit rel add where ‘b’ indicates the Direct Address of the Bit.
b. Comparison Related Instruction: -This instruction are used compare the
accumulator content with any memory location content or an immediate data or a
memory location content is compare with an immediate data or any GPR content is
compare with an immediate data. After comparison if both operands are not equal
then jump to the specified relative address. Only this instruction has three operand
fields.
Ex: -CJNE A, #70H, CJNE A, 80H, CJNE Rn, #78H, CJNE @Ri, #32H
Where Rn = any GPR (R0 to R7) and Ri = either R0 or R1
c. Decrement Related Instructions: -This instruction is used to Decrement the
specified GPR content or the Direct Address content by ‘1’ and that is not equal to
zero then jump to the specified relative address.
Ex: - DJNZ R0, 8-bit rel add, DJNZ 64H, 8-bit rel add

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CollegeAn instruction set is a group of commands for a CPU in machine language.
Microcontroller
 The term can refer to all possible instructions for a CPU or a subset of
instructions to enhance its performance in certain situations.

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Arithmetic instructions
 Arithmetic instructions perform several basic operations such as addition,
subtraction, division, multiplication etc.
 After execution, the result is stored in the first operand. Some of the
Instructions are
Arithmetic Instructions
Mnemonic Description Byte Cycle
ADD A,Rn Adds the register to the accumulator 1 1
ADD A,direct Adds the direct byte to the accumulator 2 2
ADD A,@Ri Adds the indirect RAM to the 1 2
accumulator
ADD A,#data Adds the immediate data to the 2 2
accumulator
Adds the register to the accumulator
ADDC A,Rn 1 1
with a carry flag
Adds the direct byte to the accumulator
ADDC A,direct 2 2
with
a carry flag
Adds the immediate data to the
ADDC A,#data 2 2
accumulator with a carry flag
Subtracts the register from the
SUBB A,Rn 1 1
accumulator
with a borrow
Subtracts the direct byte from
SUBB A,direct 2 2
the accumulator with a
borrow
Subtracts the indirect RAM from the
SUBB A,@Ri 1 2
accumulator with a borrow
INC A Increments the accumulator by 1 1 1
INC Rn Increments the register by 1 1 2
INC Rx Increments the direct byte by 1 2 3
INC @Ri Increments the indirect RAM by 1 1 3
DEC A Decrements the accumulator by 1 1 1
DEC Rn Decrements the register by 1 1 1
DEC Rx Decrements the direct byte by 1 1 2
INC DPTR Increments the Data Pointer by 1 1 3
MUL AB Multiplies A and B 1 5
DIV AB Divides A by B 1 5

Table 4.4: Arithmetic instructions


Branch Instructions
There are two kinds of branch instructions:
 Unconditional jump instructions: upon their execution a jump to a new location
from where the program continues execution is executed.
 Conditional jump instructions: a jump to a new program location is executed
only if a specified condition is met. Otherwise, the program normally proceeds with
the next instruction. Some of the instructions are

Branch Instructions
Mnemonic Description Byte Cycle
ACALL addr11 Absolute subroutine call 2 6
LCALL addr16 Long subroutine call 3 6
RET Returns from subroutine 1 4
RETI Returns from interrupt subroutine
1 4
AJMP addr11 Absolute jump 2 3
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LJMP addr16 Long jump Microcontroller
3 4
Short jump (from –128 to
SJMP rel 2 3
+127 locations relative to the
following

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instruction)

JC rel Jump if carry flag is set. Short 2 3


jump.
Jump if carry flag is not set.
JNC rel 2 3
Short jump.
JB bit,rel Jump if direct bit is set. Short 3 4
jump.
Jump if direct bit is set and clears
JBC bit,rel 3 4
bit. Short jump.
Jump if the accumulator is
JZ rel 2 3
zero. Short jump.
Jump if the accumulator is not
JNZ rel 2 3
zero. Short jump.
Compares direct byte to
CJNE
the accumulator and 3 4
A,direct,rel
jumps if not equal.
Short jump.
Compares immediate data to
CJNE
the accumulator and jumps if 3 4
A,#data,rel
not equal. Short jump.
Compares immediate data to
CJNE
the register and jumps if not 3 4
Rn,#data,rel
equal. Short jump.
Compares immediate data to
CJNE
indirect register and jumps if not 3 4
@Ri,#data,rel
equal. Short jump.
Decrements register and jumps if
DJNZ Rn,rel 2 3
not
0. Short jump.
Decrements direct byte and
DJNZ Rx,rel 3 4
jump if not 0. Short jump.
NOP No operation 1 1

Table 4.5: Branch Instructions

Data Transfer Instructions


 Data transfer instructions move the content of one register to another.
 The register the content of which is moved remains unchanged.
 If they have the suffix “X” (MOVX), the data is exchanged with external
memory. Some of the instructions are
Data Transfer Instructions
Mnemonic Description Byte Cycle
MOV A,Rn Moves the register to the 1 1
accumulator
MOV A,direct Moves the direct byte to the 2 2
accumulator
Moves the indirect RAM to
MOV A,@Ri 1 2
the accumulator
Moves the immediate data to
MOV A,#data 2 2
the accumulator
MOV Rn,A Moves the accumulator to the 1 2
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MOV Rn,direct Moves the direct byte to the register 2 4
Moves the immediate data to
MOV Rn,#data 2 2
the register

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MOV direct,A Moves the accumulator to the direct 2 3
byte
MOV direct,Rn Moves the register to the direct byte 2 3
MOV
Moves the direct byte to the direct 3 4
direct,direct
byte
MOV Moves the indirect RAM to the
direct,@Ri 2 4
direct byte
MOV Moves the immediate data to the
3 3
direct,#data direct byte
Moves the accumulator to the
MOV @Ri,A 1 3
indirect RAM
MOV Moves the direct byte to the
2 5
@Ri,direct indirect RAM
MOV Moves the immediate data to the
2 3
@Ri,#data indirect RAM
MOV
Moves a 16-bit data to the data 3 3
DPTR,#data
pointer
Moves the code byte relative to the
MOVC
DPTR to the accumulator 1 3
A,@A+DPTR
(address=A+DPTR)
MOVC Moves the code byte relative to the
1 3
A,@A+P PC to the accumulator
C (address=A+PC)
Moves the external RAM (8-bit
MOVX A,@Ri 1 3-10
address) to the accumulator
MOVX Moves the external RAM (16-
1 3-10
A,@DPTR bit address) to the accumulator
Moves the accumulator to the
MOVX @Ri,A 1 4-11
external RAM (8-bit address)
MOVX Moves the accumulator to the
1 4-11
@DPTR,A external RAM (16-bit address)
PUSH direct Pushes the direct byte onto the 2 4
stack
POP direct Pops the direct byte from the 2 3
stack/td>
Exchanges the register with
XCH A,Rn 1 2
the accumulator
Exchanges the direct byte with
XCH A,direct 2 3
the accumulator
Exchanges the indirect RAM with
XCH A,@Ri 1 3
the accumulator
Exchanges the low-order nibble
XCHD A,@Ri 1 3
indirect RAM with the accumulator

Table 4.6: Data Transfer Instructions


Logic Instructions
Logic instructions perform logic operations upon corresponding bits of two
registers. After execution, the result is stored in the first operand. Some of the
instructions are

Logic Instructions
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Mnemonic Description Microcontroller
Byte Cycle
ANL A,Rn AND register to accumulator 1 1
ANL A,direct AND direct byte to 2 2
accumulator

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ANL A,@Ri AND indirect RAM to 1 2
accumulator
AND immediate data
ANL A,#data 2 2
to accumulator
ANL direct,A AND accumulator to direct 2 3
byte
AND immediae data to
ANL direct,#data 3 4
direct register
ORL A,Rn OR register to accumulator 1 1
ORL A,direct OR direct byte to accumulator 2 2
ORL A,@Ri OR indirect RAM to 1 2
accumulator
ORL direct,A OR accumulator to direct byte 2 3
ORL direct,#data OR immediate data to direct 3 4
byte
Exclusive OR register
XRL A,Rn 1 1
to accumulator
Exclusive OR direct byte
XRL A,direct 2 2
to accumulator
Exclusive OR indirect RAM
XRL A,@Ri 1 2
to accumulator
Exclusive OR immediate data
XRL A,#data 2 2
to accumulator
Exclusive OR accumulator
XRL direct,A 2 3
to direct byte
Exclusive OR immediate data
XORL 3 4
to direct byte
direct,#data
CLR A Clears the accumulator 1 1
Complements the
CPL A 1 1
accumulator
(1=0, 0=1)
Swaps nibbles within
SWAP A 1 1
the accumulator
Rotates bits in the
RL A 1 1
accumulator left
Rotates bits in the
RLC A 1 1
accumulator left through carry
Rotates bits in the
RR A 1 1
accumulator right
Rotates bits in the
RRC A 1 1
accumulator right through
carry

Table 4.7: Logic Instructions


Bit-oriented Instructions
 Similar to logic instructions, bit-oriented instructions perform logic operations.
 The difference is that these are performed upon single bits. Some of the
instructions are

Bit-oriented Instructions
Mnemonic Description Byte Cycle
CLR C Clears the carry flag 1 1
CLR bit Clears the direct bit 2 3
SETB C Sets the carry flag 1 1
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SETB bit
College Sets the direct bit Microcontroller 2 3
CPL C Complements the carry flag 1 1
CPL bit Complements the direct bit 2 3
ANL C,bit AND direct bit to the carry flag 2 2
ANL C,/bit AND complements of direct bit to the 2 2
carry flag
ORL C,bit OR direct bit to the carry flag 2 2

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ORL C,/bit OR complements of direct bit to the carry 2 2
flag
MOV C,bit Moves the direct bit to the carry flag 2 2
MOV bit,C Moves the carry flag to the direct bit 2 3

Table 4.8: Bit-oriented Instructions

4.11 ASSEMBLY LANGUAGE PROGRAMMING.


1. Write an 8051 ALP to save the status of bits P1.1 and P1.2 on RAM bit locations
08H and 09H respectively.
MOV C, P1.1
MOV 08H, C
MOV C, P1.2
MOV 09H, C
UP: SJMP UP

2. Write an 8051 ALP to find the sum of values 79H, 0F5H, and 0E2H. Put the sum in
register R0 (Lower order Byte) and R1 (Higher order Byte).
MOV A, 00H
MOV R1, A
MOV R0, A
ADD A, #79H
JNC NEXT1
INC R1
NEXT1: ADD A, #0F5H
JNC NEXT 2
INC R1
NEXT 2: ADD A,
#0E2H JNC NEXT3
INC R1
NEXT 3: MOV R0, A
HERE: SJMP HERE

3. Write an 8051 ALP to add ‘2’ to the accumulator by 600H times.


MOV A, #77H
MOV R2,
#10H
NEXT: MOV R3,
#60H AGAIN: ADD
A, #02H DJNZ R3,
AGAIN DJNZ R2,
NEXT STOP: SJMP
STOP

4. Write an 8051 ALP to toggle all the bits of Port 1 by sending to it the values 66H
and 0BBH continuously. Put a delay in between each issuing of data to port.
UP: MOV A,
#66H MOV P1,
A LCALL DELAY
MOV A, #0BBH
MOV P1, A
LCALL DELAY
SJMP UP
DELAY: MOV R3,
#0FFH AGAIN: DJNZ
R3, AGAIN RET

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5.
CollegeWrite an 8051 ALP to find the number of 1’s in a 0FFH.
Microcontroller
MOV R2, #00H

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MOV R3, #08H
MOV A, #0FFH
REPEAT: RLC A
JNC NEXT
INC R2
NEXT: DJNZ R3, REPEAT
HERE: SJMP HERE

6. Write an 8051 ALP to find the Largest / Maximum number in the array.
MOV DPTR,
#3000H MOVX A,
@DPTR MOV R0,
#’N’
L1: MOV B, A
L3: DJNZ R0,
L2 SJMP
DOWN L2: INC
DPTR
MOVX A, @DPTR
CJNE A, B, UP
SJMP L3
UP: JC L3
SJMP L1
DOWN: MOV R1, B

*****

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Part-A
1. What is mean by microcontroller?
A device which contains the microprocessor with integrated peripherals like
memory, serial ports, parallel ports, timer/counter, interrupt controller, data
acquisition interfaces like ADC,DAC is called microcontroller.

2. Explain DJNZ instructions of Intel 8051 microcontroller? (Nov/Dec’17)


a) DJNZ Rn, rel : Decrement the content of the register Rn and jump if not zero.
b) DJNZ direct , rel :Decrement the content o f direct 8-bit address and
jump if not zero.

3. State the function of RS1 and RS0 bits in the flag register of Intel 8051
microcontroller? (May 2013)
How do you select register bank in 8051 [MAY/JUN 2015]
RS1 , RS0 – Register bank select bits
RS1 RS0 Bank
Selection
0 0 Bank 1
0 1 Bank 2
1 0 Bank 3
1 1 Bank 4

4. Explain the function of the pins PSEN and EA of 8051


PSEN: PSEN stands for program store enable.
In 8051 based system in which an external ROM holds the program code, this
pin is connected to the OE pin of the ROM.
EA : EA stands for external access.
When the EA pin is connected to Vcc, program fetched to addresses 0000H through
0FFFH are directed to the internal ROM and program fetches to addresses 1000H
through FFFFH are Directed to external ROM/EPROM. When the EA pin is grounded,
all addresses fetched by program are directed to the external ROM/EPROM.

5. Explain the 16-bit registers DPTR and SP of 8051.


DPTR stands for data pointer. DPTR consists of a high byte (DPH) and a blow
b yte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-
bit data register or as two independent 8-bit registers. It serves as a base b register
in indirect jumps, lookup table instructions and external data transfer.

SP stands for stack pointer. SP is a 8- bit wide register. It is incremented


before data is stored during PUSH and CALL instructions. The stack array can reside
anywhere in on-chip RAM. The stack pointer is initialized to 07H after a reset. This
causes the stack to begin at location

6. Name the special functions registers available in 8051. (Apr/May 2019)


• Accumulator
• B Register
• Program Status Word.
• Stack Pointer.
• Data Pointer.
• Port 0
• Port 1
• Port 2

7. Name the five interrupt sources of 8051?(Nov/Dec 2010)


The interrupts are:
1) Vector address
2) External interrupt 0
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3) Timer interrupts 0
4) External interrupt 1
5) Timer Interrupt 1
6) Serial Interrupt
7) Receive interrupt:
8) Transmit interrupt:

8. Compare Microprocessor and Microcontroller. (Nov/Dec 2014)


1. Microprocessor: Itcontains the circuitry ALU, general purpose of
microprocessor and Microcontroller registers, stack pointer, has built- in ROM, RAM,
I/O program counter, clock timing devices, timers and counters. Circuit and
interrupt circuit.
2. Microprocessor It has man y instructions to It has one or two instructions to
move data between memory data between memory and CPU. Microcontroller It has
one or two bit handling.It has man y bit handling instructions.
3. Microprocessor Access times for memory and I/O devices are
more.
Microcontroller Less access times for built-in memory and I/O devices.
4. Microprocessor based system requires more hardware Microcontroller
based system requires less hardware reducing PCB size and increasing the
reliability.

9. What is the size of the on-chip program memory and on-chip data memory of 8051
microcontroller? (May /June 2012)
• 4 kb on chip program memory
• 128 bytes on chip data memory

10. List some of the features of 8096 microcontroller.


1) The 8096 is a 16-bit microcontroller.
2) The 8096 is designed to use in applications which require high speed
calculations and fast I/O operations.
3) The high speed I/O section of an 8096 includes a 16-bit timer, a 16-bit
counter, a 4 input programmable edge detector, 4 software timers and a 6-
output programmable event generator. It has 100 instructions, which can
operate on bit, byte, word, and double words.
4) The bit operations are possible and these can be performed on an y bit in
the register file or in the special function register.

11. What are the addressing modes supported by 8051?(ECE M/J 2009)
• Immediate addressing mode.
• Register addressing mode.
• Direct addressing mode.
• Indirect addressing mode.
• Indexed addressing mode

18. List the applications of microcontroller. [MAY/JUNE 2009]


 Stepper motor interfacing
 Length measurement
 Square wave generator

19. Give the alternate functions for the port pins of port3? (April/May17)
• RD – Read data control output.
• WR – Write data control output.
• T1 – Timer / Counter1 external input or test pin.
• T0 – Timer / Counter0 external input or test pin.
• INT1- Interrupt 1 input pin.

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College• INT 0 – Interrupt 0 input pin. Microcontroller
• TXD – Transmit data pin for serial port in UART
mode. RXD- Serial Communication

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20. Define XTAL1 and XTAL2. [MAY/JUNE 2009]
In built oscillator which derives the necessary clock frequency for the
operation of the controller. XTAL1 is the input of amplifier and XTAL2 is the output of
the amplifier.

21. What are the advantages of microcontroller over microprocessor?


The overall system cost is low, as the peripherals are integrated in a single chip.
Size is small. Easy to troubleshoot and maintain. System is more reliable

22. Give the various modes of 8254 timer?


• Mode 0: interrupt or terminal count
• Mode 1: Rate generator
• Mode 3: square wave generator
• Mode 4: software triggered strobe
• Mode 5: hardware triggered strobe

23. What are the functions of the following signals of 8051? ALE/PROG, PSEN. (Nov/Dec
2010)
ALE:The ALE (Address latch enable) is used to latch the lower order address
so that it can be available in T2 and T3 and used for identifying the memory
address. During T1 the ALE goes high. When ALE goes low the lower order address
is latched until the next ALE.
PSEN: PSEN stands for program store enable. In 8051 based system in which
an external ROM holds the program code, this pin is connected to the OE pin of the
ROM.

24. What are the differences between the microprocessor and microcontroller(May/June
2014)

Microprocessor Microcontroller
Microprocessor contains ALU, general
Microcontroller contains the circuitry
purpose registers, stack pointer, of microprocessor and in addition it
program counter, clock timing has built- in ROM, RAM, I/O
circuit and interrupt circuit. devices, timers and counters.

It has many instructions to move It has one or two instructions to


data between memory and CPU move data between memory and
CPU.
It has one or two bit It has many bit handling
handling Instructions instructions.
4 Access times for memory and Less access times for built-in memory
I/O devices are more. and I/O devices
Microprocessor based system Microcontroller based system
requires more hardware. requires less hardware reducing
PCB size and
Increasing the reliability.

25. What are the advantages of using a microcontroller in a place of a microprocessor?


(May/June 2012)
 The overall system cost is low, as the peripherals are integrated in a single chip.
 Size is small.
 Easy to troubleshoot and maintain.
 System is more reliable.

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26. Draw the diagram of processor status word in 8051[MAY/JUN 2015] (Apr/May 2019)

27. What is the significance of EA line of 8051 microcontroller? [MAY/JUN 2014]


EA : EA stands for external access.
When the EA pin is connected to Vcc, program fetched to addresses 0000H
through 0FFFH are directed to the internal ROM and program fetches to addresses
1000H through FFFFH are Directed to external ROM/EPROM. When the EA pin is
grounded, all addresses fetched by program are directed to the external
ROM/EPROM.

28. What is the difference between MOVX and MOV? [NOV/DEC 2013]
 Data transfer instructions move the content of one register to another.
 The register the content of which is moved remains unchanged.
 If they have the suffix “X” (MOVX), the data is exchanged with external memory.

29. What are the different ways of operand addressing in 8051? (May/June 2016)
An Addressing Mode indicates how the data is represented in the
instruction. 8051 supports 6 types of Addressing Modes, those are
 Immediate Addressing mode
 Register Addressing Mode
 Register Indirect Addressing Mode
 Direct Addressing Mode
 Indexed Addressing Mode
 Implicit Addressing Mode

30. Write an 8051 ALP to toggle P1 a total of 200 times. Use RAM location 32H to hold
your counter value instead of registers R0-R7.(May/June2016) (Apr/May 2019)

MOV P1,#55H ;P1=55H


MOV 32H,#200 ;load counter value into RAM loc
32H
LOP1: CPL P1 ;toggle P1
ACALL DELAY
DJNZ P1 32H,LOP1 ;repeat 200 times
31.Illustrate the CJNE instruction.(April/May’17)
Compares immediate data to the accumulator and jumps if not equal. Short Jump.

* ** * *

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Part-B (16 Marks Questions)

1. Bring out the features of special function registers of 8051 microcontroller.


(Ref Sec 4.7) (Nov/Dec 2010) (April/May’17)
2. Draw the pin diagram of 8051 microcontroller and explain the functions of each pin.
(Ref Sec 4.7 ) (Nov/Dec 2011)
3. With a neat sketch of a schematic diagram, explain the functions of
various signals of 8051 (Ref Sec4) (Nov/Dec 2010)
4. Discuss briefly the various registers in 8051 microcontroller.(Ref
Sec 4.8) (Nov/Dec 2011,Apr/May 2011) (Apr/May 2019)
5. Draw the architectural block diagram of 8051 microcontroller and explain.
(Ref Sec 4.5) (May/June 2012)
6. Explain the internal data memory structure of 8051 microcontroller with its SFRs
(Ref Sec 4.6) (May/June 2012)
7. Draw the diagram of 8051 microcontroller and explain the input/output lines in detail
(Ref Sec 4.10) (May/June 2014)
8. Explain instruction sets of8051. (.Ref Sec 4.11) (May/June 2014)
9. Explain about arithmetic and control instruction set of 8051(10)[ JUNE 2015,]
10.Write a program to bring in data in serial form and send it out in parallel form in
8051(6)
[June 2015]
11.Draw the data memory structure of 8051 microcontroller and explain. [8]
[NOV/DEC 2014]
12.Draw the functional block diagram of 8051 microcontroller and explain each block.
[8]
[JUN 2015,NOV/DEC 2014]
13.Draw the pin diagram of 8051 Microcontroller and explain the Input
/Output lines in detail.[8] [MAY/JUN 2014]
14.Explain the architecture of 8051 with its diagram. (16) [MAY/JUN 2016](Nov/Dec’17)
15.Write an 8051ALP to create a square wave of 66 % duty cycle on bit 3 of port 1.
(16)
[MAY/JUN 2016]
16. Explain the types of addressing modes off 8051 with its diagram(April/May’17)
(Apr/May 2019)
17. Discuss the ports and its circuits of 8051.(Nov/Dec’17)

* ** * *

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UNIT 5
INTERFACING MICROCONTROLLER

REFERRED BOOK:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family
- Architecture, Programming and Design”, Second Edition, Prentice Hall of
India, 2007.
2. Mohamed Ali Mazidi, Janice GillispieMazidi, RolinMcKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly
and C”, Second
1. DoughlasV.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH,2012

STAFF IN-CHARGE HOD

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5.1 PROGRAMMING 8051 TIMERS
5.1 8051 Timers
 The 8051 comes equipped with two timers, both of which may be
controlled, set, read, and configured individually.
 The 8051 timers have three general functions:
1) Keeping time and/or calculating the amount of time between events,
2) Counting the events themselves, or
3) Generating baud rates for the serial port.
Timer SFRs:
The 8051 has two timers which each function essentially the same way. One timer
is TIMER0 and the other is TIMER1.
The two timers share two SFRs (TMOD and TCON) which control the timers, and
each timer also has two SFRs dedicated solely to itself (TH0/TL0 and TH1/TL1).
It is often useful to know the numeric address that corresponds to an SFR name.
When you enter the name of an SFR into an assembler, it internally converts it to

a number. The SFRs relating to timers are shown in table 5.1:

SFR Name Description SFR Address


TH0 Timer 0 High Byte 8Ch
TL0 Timer 0 Low Byte 8Ah
TH1 Timer 1 High Byte 8Dh
TL1 Timer 1 Low Byte 8Bh
TCON Timer Control 88h
TMOD Timer Mode 89h
Table 5.1 SFRs relating to timers

TMOD SFR:
 The TMOD SFR is used to control the mode of operation of both timers.
 Each bit of the SFR gives the microcontroller specific information concerning
how to run a timer.
 The high four bits (bits 4 through 7) relate to Timer 1.
 The low four bits (bits 0 through 3) perform the exact same functions, but for
timer 0.
 The individual bits of TMOD have functions are shown in following table 5.2. :

Bit Name Explanation of Function Timer


When this bit is set the timer will only run when
7 GATE1 INT1 (P3.3) is high. When this bit is clear the 1
timer will run
regardless of the state of INT1.
When this bit is set the timer will count events
6 C/T1 on T1 1
(P3.5). When this bit is clear the timer will be
incremented every machine cycle.
5 T1M1 Timer mode bit (see below) 1
4 T1M0 Timer mode bit (see below) 1
When this bit is set the timer will only run when
3 GATE0 INT0 (P3.2) is high. When this bit is clear the timer 0
will run regardless of the state of INT0.
When this bit is set the timer will count events
2 C/T0 on T0 (P3.4). When this bit is clear the timer will be 0
incremented
every machine cycle.
1 T0M1 Timer mode bit (see below) 0
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0 T0M0 Timer mode bit (see below)
Microcontroller 0
TABLE 5.2 TMOD Functions

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Four bits (two for each timer) are used to specify a mode of operation. The modes
of operation are shown in below:
TxM1 TxM0 Timer Mode Description of Mode
0 0 0 13-bit Timer.
0 1 1 16-bit Timer
1 0 2 8-bit auto-reload
1 1 3 Split timer mode
Table 5.3Mode of Operation
13-bit Time Mode (mode 0)
 Timer mode "0" is a 13-bit timer.
 Generally the 13-bit timer mode is not used in new development.
 When the timer is in 13-bit mode, TLx will count from 0 to 31.
 When TLx is incremented from 31, it will "reset" to 0 and increment THx.
 13 bits of the two timer bytes are
being
used: bits 0-4 of TLx and bits 0-7 of THx.

16-bit Time Mode (mode 1)


 Timer mode "1" is a 16-bit timer.
 It functions just like 13-bit mode except that all 16 bits are used.
 TLx is incremented from 0 to 255.
 When TLx is incremented from 255,it resets to 0 and causes THx to be
incremented by 1.

8-bit Time Mode (mode 2)


 Timer mode "2" is an 8-bit auto-reload mode.
 When a timer is in mode 2, THx holds the "reload value" and TLx is the timer
itself.
 When TLx reaches 255 and is subsequently incremented, instead of resetting to
0

Split Timer Mode (mode 3)


 Timer mode "3" is a split-timer mode.
 When Timer 0 is placed in mode 3, it essentially becomes two separate 8-bit
timers.
 Timer 0 is TL0 and Timer 1 is TH0.
 Both timers count from 0 to 255 and overflow back to 0.
 All the bits that are related to Timer 1 will now be tied to TH0.

TCON SFR
 Finally, there’s one more SFR that controls the two timers and provides
valuable information about them. The TCON SFR has the following structure
shown in table :

Bit Name Bit Address Explanation of Function Timer


Timer 1 Overflow. This bit is set by
7 TF1 8Fh 1
the microcontroller when Timer 1
overflows.
Timer 1 Run. When this bit is set
6 TR1 8Eh Timer 1 is turned on. When this bit 1
is clear Timer
1 is off.
Timer 0 Overflow. This bit is set by
5 TF0 8Dh 0
the microcontroller when Timer 0

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Timer 0 Run. When this bit is set
4 TR0 8Ch Timer 0 0
is turned on. When this bit is clear
Timer 0 is off.
Table 5.4 TCON SFR Controls
 A new piece of information in this chart is the column "bit address.”. This is
because this SFR is "bit-addressable."

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 Bit addressable means, if you want to set the bit TF1 which is the highest bit
of TCON you could execute the command: MOV TCON, #80h.
 SETB TF1 has the benefit of setting the high bit of TCON without changing the
value of any of the other bits of the SFR.

Initializing a Timer
 First initialize the TMOD SFR with first two bits, GATE0 and C/T0 are both 0
 16-bit mode is timer mode 1 so we must clear T0M1 and set T0M0.
 Only bit we want to turn on is bit 0 of TMOD.
 Initialize the timer we execute the instruction:
 MOV TMOD,#01h Timer 0 is now in 16-bit timer mode

Reading the Timer


 There are two common ways of reading the value of a 16-bit timer;
which you use depends on your specific application.

Reading the value of a Timer


 If your timer is in an 8-bit mode that is, either 8-bit Auto Reload mode or
in split timer mode then reading the value of the timer is simple.
 Read the low byte of the timer as 255, and then read the high byte of the timer
as 15.
 Executed the next instruction a small amount of time passed but enough for
the timer to increment.
 If the high byte read the second time is not the same as the high byte read
the first time you repeat the cycle. In code, this would appear as:
REPEAT: MOV A, TH0
MOV R0, TL0
CJNE A, TH0, REPEAT

Detecting Timer Overflow


 Whenever a timer overflows from it’s highest value back to 0, the
microcontroller automatically sets the TFx bit in the TCON register.
 If TF0 is set it means that timer 0 has overflowed; if TF1 is set it means that
timer 1 has overflowed.
 The following code to execute a pause of 1/20th of a
second: MOV TH0,#76 ;High byte of 19,457 (76
* 256 = 19,456)
MOV TL0,#01 ;Low byte of 19,457 (19,456 + 1 = 19,457)
MOV TMOD,#01 ;Put Timer 0 in 16-bit mode
SETB TR0 ; Make Timer 0 start
counting
JNB TF0,$ ;If TF0 is not set, jump back to this same instruction
 In the above code the first two lines initialize the Timer 0 starting value to
19,457.
 The next two instructions configure timer 0 and turn it on.
 Finally, the last instruction JNB TF0,$, reads "Jump,
 if TF0 is not set, back to this same instruction."
 The "$" operand means, in most assemblers, the address of the current
instruction.
Timers / Counters

051 has two 16-bit programmable UP timers/counters. T

hey can be configured to operate either as timers or as event counters.

he names of the two counters are T0 and T1 respectively.
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he timer content is available in four 8-bit special function registers, viz,
TL0,TH0,TL1 and TH1 respectively.

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n the "timer" function mode, the counter is incremented in every machine cycle.

he clock rate is 1/12 th of the oscillator frequency.

n the "counter" function mode, the register is incremented in response to a
1 to 0 transition at its corresponding external input pin (T0 or T1).

t requires 2 machine cycles to detect a high to low transition. Hence
maximum count rate is 1/24 th of oscillator frequency.
 The operation of the timers/counters is controlled by two special function
registers, TMOD and TCON respectively
Timer Mode control (TMOD) Special Function Register:
 TMOD register is not bit addressable
 TMODAddress: 89 H

Fig: 5.1 TMOD Functional register


Various bits of TMOD are described as follows
Gate:
This is an OR Gate enabled bit which controls the effect of on START/STOP
of Timer. It is set to one ('1') by the program to enable the interrupt to
start/stop the timer.

 It is used for the selection of Counter/Timer mode.

Mode Select Bits:

Table 5.5 M1 and M0 are mode select bits.

Timer/ Counter control logic:

Figure 5.2 Timer/ Counter control logic

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Timer control (TCON) Special function register: Microcontroller
College

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 TCON is bit addressable.
 The address of TCON is 88H. It is partly related to Timer and partly to interrupt

Figure 5.3 TCON Functional register

The various bits of TCON are as follows


 TF1 : Timer1 overflow flag. It is set when timer rolls from all 1s to 0s.
 TR1 : Timer1 run control bit. Set to 1 to start the timer / counter.
 TF0 : Timer0 overflow flag. (Similar to TF1)
 TR0 : Timer0 run control bit.
 IE1 : Interrupt1 edge flag. IE0 : Interrupt0 edge flag. (Similar to IE1)
 IT1 : Interrupt1 type control bit.
 IT0 : Interrupt0 type control bit. (Similar to IT1)
Timer Mode-0:
 In this mode, the timer is used as a 13-bit UP counter as follows

Fig 5.4. Operation of Timer on Mode-0



he lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count.

pper 3 bits of TLX are ignored.

hen the counter rolls over from all 0's to all 1's, TFX flag is set and an
interrupt is generated.
 If TR1/0 bit is 1 and Gate bit is 0, the counter continues counting up.
 If TR1/0 bit is 1 and Gate bit is 1, then the operation of the counter is
controlled by input.
Timer Mode-1:
 This mode is similar to mode-0 except for the fact that the Timer operates in 16-
bit mode

Fig 5.5. Operation of Timer in Mode 1


Timer Mode-2: (Auto-Reload Mode)
 In this mode when the timer overflows i.e. TLX becomes FFH, it is fed with
the value stored in THX..

Fig 5.6. Operation of Timer in Mode 2


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Timer Mode-3:
 Timer 1 in mode-3 simply holds its count.
 The effect is same as setting TR1=0. Timer0 in mode-3 establishes TL0 and
TH0 as two separate counters.

Fig 5.7. Operation of Timer in Mode 3

5.2 SERIAL PORT PROGRAMMING


5.2.1 Serial Port
 The serial buffer consists of two separate registers:
1. Transmit buffer
2. Receive buffer.
 Writing data to the SFR sbuf sets this data in the serial output buffer and
starts the transmission. Reading from the sbuf register reads data from the
serial receive buffer.
 The serial port can simultaneously transmit and receive data.
 It can also buffer one byte at receive, which prevents the receive data from
being lost
 The serial port can operate in one of four modes.
a) Mode 0
 In this mode, the rxd0i pin receives serial data and the rxd0o pin transmits
serial data. The txd0 pin outputs the shift clock.
 Eight bits are transmitted with LSB first.
 The baud rate is fixed at 1/12 of the crystal (clk input) frequency.
b) Mode 1
 In this mode, the rxd0i pin receives serial data and the txd0 pin transmits serial
data.
 No external shift clock is used, and the following 10 bits are transmitted:
1. One Start Bit (always 0)
2. Eight Data Bits (LSB first)
3. One Stop Bit (always 1)
4. On receive,
c) Mode 2
 The baud rate is fixed at 1/32 or 1/64 of the oscillator (clk input)
frequency, and the following 11 bitsare transmitted or received:
1. One Start Bit (0)
2. Eight Data Bits (LSB first)
3. One Programmable Ninth Bit
4. One Stop Bit (1)
 The ninth bit can be used to control the parity of the serial interface.
d) Mode 3
The only difference between Mode 2 and Mode 3 is that the baud rate is variable in
Mode 3.

5.2.2 Multiprocessor Communication


 The nine-bit reception feature in Modes 2 and 3 can be used for

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Collegemultiprocessor communication. In thisMicrocontroller
case, the SM2 bit in the scan register
is set to logic 1 by the slave processors.
 The slave processors compare the received byte with their network address.
If there is a match, the addressed slave will clear SM2 and receive the rest of
the message,

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 After addressing the slave, the master will output the rest of the message
with the ninth bit set to logic 0,

5.2.3 Serial Port Control Register (SCON)


 The function of the serial port depends on the setting of the Serial Port Control
Register.
 The various register flags, bit descriptions, mode descriptions, and baud
rates are shown in table 5.6 and 5.7
 MSB
LSB
SM0 SM1 SM2 REN TB8 RB8 TI RI
Table 5.6 SCON Register Flags

Bit Symbol Function


7 SM0 Sets baud rate
6 SM1 Sets baud rate
5 SM2 Enables multiprocessor communication feature
If set, enables serial reception. Cleared by software to
4 REN
disable reception.
3 TB8 The ninth transmitted data bit in Modes 2 and 3. Set or
cleared by
the CPU, depending on the function it performs (parity
check, multiprocessor communication, etc.).
2 RB8 In Modes 2 and 3, the ninth data bit received. In Mode 1, if SM2
is '0', RB8 is the stop bit. In Mode 0 this bit is not
used. Must be
cleared by the software.
1 TI Transmits the interrupt flag and is set by the hardware
after completion of a serial transfer. Must be cleared by the
software.
0 RI Receives the interrupt flag and is set by the hardware
after completion of a serial reception. Must be cleared by the
software.
Table 5.7SCON Bit Functions

5.2.4 Generating Variable Baud Rate in Modes 1 and 3


 In Modes 1 and 3, the Timer 1 overflow rate is used to generate baud rates.
 If Timer 1 is configured at auto in auto-reload mode to establish a baud
rate, the followingtables 5.8 and 5.9are useful:
SM0 SM1 Mode Description Baud Rate
0 0 0 Shift register fosc/12
0 1 1 8-bit UART variable
1 0 2 9-bit UART fosc/32 or /64
1 1 3 9-bit UART variable
Table 5.8Serial Port Modes

Mode Baud Rate


Mode 0 fosc12
Mode 1,3 Timer 1 overflow rate
Mode 2 SMOD = 0 fosc/64 SMOD = 1 fosc/32
Table 5.9Serial Port Baud Rates
5.2.5 Generating Variable Baud Rate in Modes 1 and 3
 In Modes 1 and 3, the Timer 1 overflow rate is used to generate baud rates.
 If Timer 1 is configured at auto in auto-reload mode to establish a baud
rate, the following equation is useful:

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Microcontroller
 The serial port of 8051 is full duplex, i.e., it can transmit and receive
simultaneously.
 The register SBUF is used to hold the data.
 The special function register SBUF is physically two registers.

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 One is, write-only and is used to hold data to be transmitted out of the 8051 via
TXD.
 The other is, read-only and holds the received data from external sources via
RXD.
 Both mutually exclusive registers have the same address 099H.

5.2.6 Serial port Registers:


Serial Port Control Register (SCON)
 Register SCON controls serial data communication.
 Address: 098H (Bit addressable)

Fig: 5.8 Serial Port Control Register


Mode select bits

Fig:5.9 Mode select bits


1. SM2:multi-processor
communication bit REN: Receive
enable bit
2. SM2: multi-processor communication bit
3. REN: Receive enable bit
4. TB8: Transmitted bit 8 (Normally we have 0-7 bits transmitted/received)
5. RB8: Received bit 8
6. TI: Transmit interrupt flag
7. RI: Receive interrupt flag

Power Mode control Register


 Register PCON controls processor power down, sleep modes and serial data
baud rate.
 Only one bit of PCON is used with respect to serial communication.
 The seventh bit (b7)(SMOD) is used to generate the baud rate of serial
communication.

Address: 87H

Fig: 5.10 Addresses of 87H


1. SMOD: Serial baud rate modify bit
2. GF1: General purpose user flag bit 1
3. GF0: General purpose user flag bit 0
4. PD: Power down bit
5. IDL: Idle mode bit

5.2.7 Data Transmission


 Transmission of serial data begins at any time when data is written to SBUF.
 TI is set to 1 when data has been transmitted.
 This signifies that SBUF is empty so that another byte can be sent.
5.2.7.1 Data Reception
 Reception of serial data begins if the receive enable bit is set to 1 for all modes.
 Pin P3.0 (Alternate function bit RXD) is used to receive data from the
serial data network.
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5.2.7.2
College Serial Data Transmission Modes Microcontroller
Mode-0:
 A shift register and the data transmission works synchronously with a clock
frequency of fosc /12.

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 Serial data is received and transmitted through RXD. 8 bits are transmitted/
received any a time.
 Pin TXD outputs the shift clock pulses of frequency fosc /12, which is
connected to the external circuitry for synchronization.
 The shift frequency or baud rate is always 1/12 of the oscillator frequency.

Fig 5.11. Data transmission/reception in Mode-0

Mode-1 (standard UART mode) :



he serial port functions as a standard Universal Asynchronous Receiver
Transmitter (UART) mode. 1

bits are transmitted through TXD or received through RXD.

he 10 bits consist of one start bit (which is usually '0'), 8 data bits (LSB is
sent first/received first), and a stop bit (which is usually '1').

nce received, the stop bit goes into RB8 in the special function register SCON.
The baud rate is variable.The following figure 5.12 shows the way the bits are
transmitted/ received.

Fig 5.12. Data transmission format in UART mode


Mode-1 baud rate generation:
 Timer-1 is used to generate baud rate for mode-1 serial communication.
 Timer-1 is used in timer mode-2 as an auto-reload 8-bit timer.
 The data rate is generated by timer-1 using the following formula

 Where, SMOD is the 7th bit of PCON register fosc is the crystal oscillator
frequency
 fosc/ (12 X [256- (TH1)]) is the timer overflow frequency in timer mode-2,
which is the auto-reload mode.
 If timer-1 is not run in mode-2, then the baud rate is,

5.3 INTERRUPTS PROGRAMMING


8051 provides 5 vectored interrupts. They are
1.
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2. TF0
3.
4. TF1
5. RI/TI
 The external interrupts could be negative edge triggered or low level triggered.
 All these interrupt, when activated, set the corresponding interrupt flags.
 Except for serial interrupt, the interrupt flags are cleared when the processor
branches to the Interrupt Service Routine (ISR).
 The external interrupt flags are cleared on branching to Interrupt Service
Routine (ISR),
 The schematic representation of the interrupts is shown in below figure 5.13
5.3.1 Interrupt Vector Location

Fig 5.13 8051 Interrupt Details


 Each of these interrupts can be individually enabled or disabled by 'setting' or
'clearing' the corresponding bit in the IE (Interrupt Enable Register) SFR.
 IE contains a global enable bit EA which enables/disables all interrupts at once.

5.3.2 Interrupt Enable register (IE):


Address: A8H

Where as
EX0 interrupt (External)
enable bit ET0 Timer-0 interrupt
enable bit
EX1 interrupt (External) enable bit
ET1 Timer-1 interrupt enable bit
ES Serial port interrupt enable bit
ET2 Timer-2 interrupt enable bit

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Setting '1' Enable the corresponding interrupt

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Setting '0' Disable the corresponding interrupt

5.3.3 Priority level structure:


Each interrupt source can be have two priority levels by setting (high priority) or
clearing (low priority) a bit in the IP (Interrupt Priority) Register .
A low priority interrupt can itself be interrupted by a high priority interrupt, but not by
another low priority interrupt.
If two interrupts of different priority levels are received simultaneously, the request
of higher priority level is served.

Fig: 5.14 Priority Level

5.3.4 Interrupt Priority register (IP)

'0' low priority


'1' high priority

5.3.5 Interrupt handling:


 The interrupt flags are sampled at P2 of S5 of every instruction cycle
 The polling detects it and the interrupt process generates a long call (LCALL)
 The LCALL is generated provided this hardware generated LCALL is not
blocked by any one of the following conditions.
1. An interrupt of equal or higher priority level is already in progress.
2. The current polling cycle is not the final cycle in the execution of the
instruction in progress.
3. The instruction in progress is RETI or any write to IE or IP registers.

5.4 LCD & KEYBOARD INTERFACING


5.4.1 Interfacing LCD to AT89C51:
LCD:
 16×2 Liquid Crystal Display which will display the 32 characters at a time in
two rows (16 characters in one row).
 Each character in the display of size 5×7 pixel matrix.
 The matrix will not be same for all the 16×2 LCD modules.
 There are 16 pins in the LCD module, the pin configuration us given below

PIN
NAME FUNCTION
NO

1 VSS Ground pin

2 VCC Power supply pin of 5V

3 VEE Used for adjusting the contrast commonly attached


to the potentiometer.

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PIN
NAME FUNCTION
NO

4 RS RS is the register select pin used to write display data


to the LCD (characters), this pin has to be high when
writing the data to the LCD. During the initializing
sequence and other commands this pin should low.

5 R/W Reading and writing data to the LCD for reading the
data R/W pin should be high (R/W=1) to write the data
to LCD R/W pin should be low (R/W=0)

6 E Enable pin is for starting or enabling the module. A high


to low pulse of about 450ns pulse is given to this pin.

7 DB0

8 DB1

9 DB2

10 DB3

11 DB4 DB0-DB7 Data pins for giving data(normal data like


numbers characters or command data) which is meant
to be displayed
12 DB5

13 DB6

14 DB7

15 LED+ Back light of the LCD which should be connected to Vcc

16 LED- Back light of LCD which should be connected to ground.


Table 5.10 PIN Functions
Follow these simple steps for displaying a character or data
 E=1; enable pin should be high
 RS=1; Register select should be high
 R/W=0; Read/Write pin should be low.
To send a command to the LCD just follows these steps:
 E=1; enable pin should be high
 RS=0; Register select should be low
 R/W=1; Read/Write pin should be high.
Commands:
 There are some preset commands which will do a specific task in the LCD.
 These commands are very important for displaying data in LCD.
 The list of commands given below:
Command Function

0F For switching on LCD, blinking the cursor.

1 Clearing the screen

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Command Function

2 Return home.

4 Decrement cursor

6 Increment cursor

E Display on and also cursor on

80 Force cursor to beginning of the first line

C0 Force cursor to beginning of second line

38 Use two lines and 5x7 matrix

83 Cursor line 1 position 3

3C Activate second line

0C3 Jump to second line position 3

0C1 Jump to second line position1


Table 5.11 Functions
Circuit Explanation:
 The crystal oscillator is connected to XTAL1 and XTAL2 which will provide the
system clock to the microcontroller
 The data pins and remaining pins are connected to the microcontroller as
shown in the circuit 5.14.
 The potentiometer is used to adjust the contrast of the LCD.
 The enable, R/W and RS pins are should be connected to the 10, 11

Programming LCD to 8051:


Coming to the programming you should follow these steps:
 STEP1: Initialization of LCD.
 STEP2: Sending command to LCD.
 STEP3: Writing the data to LCD.

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Fig: 5.15 LCD modules to 8051


Initializing LCD:
To initialize LCD to the 8051 the following instruction and commands are to be embed in
to the functions
 0×38 is used for 8-bit data initialization.
 0xFH for making LCD on and initializing the cursor.
 0X6H for incrementing the cursor which will help to display another character in
the LCD
 0x1H for clearing the LCD.
Sending Data to the LCD:
 E=1; enable pin should be high
 RS=1; Register select should be high for writing the data
 Placing the data on the data registers
 R/W=0; Read/Write pin should be low for writing the data.

5.5 ADC (ANALOG TO DIGITAL CONVERTER)


ADC 0804 is the ADC used here and before going through the interfacing procedure,

5.5.1 The features of ADC0804


ADC0804 is an 8 bit successive approximation analogue to digital converter from
National semiconductors.
 differential analogue voltage inputs,
 0-5V input voltage range,
 no zero adjustment,
 built in clock generator,
 reference voltage can be externally adjusted to convert smaller analogue
voltage span to 8 bit resolution
5.5.2 Pin Diagram of ADC0804
The pin out diagram of ADC0804 is shown in the figure 5.15 below.

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Fig: 5.16 Pin Diagram of ADC0804

ADC0804 input:
The voltage at Vref/2 (pin9) of ADC0804 can be externally adjusted to convert
smaller input voltage spans to full 8 bit resolution.
Vref/2 (pin9) left open means input voltage span is 0-5V and step size is 5/255=19.6V.
Have a look at the table below for different Vref/2 voltages and corresponding
analogue input voltage spans.

Vref/2 (pin9) (volts) Input voltage span (volts) Step size (mV)
Left open 0–5 5/255 = 19.6
2 0–4 4/255 = 15.69
1.5 0–3 3/255 = 11.76
1.28 0 – 2.56 2.56/255 = 10.04
1.0 0–2 2/255 = 7.84
0.5 0–1 1/255 = 3.92
Table 5.12 different Vref/2 voltages and corresponding analogue input voltage

Steps for converting the analogue input and reading the output from ADC0804.
 Make CS=0 and send a low to high pulse to WR pin to start the conversion.
 Now keep checking the INTR pin. INTR will be 1 if conversion is not finished
and INTR will be 0 if conversion is finished.
 If conversion is not finished (INTR=1) , poll until it is finished.
 If conversion is finished (INTR=0), go to the next step.
 Make CS=0 and send a high to low pulse to RD pin to read the data from the
ADC.

5.5.3 Circuit diagram of ADC0804

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Fig: 5.17Circuit diagram of ADC0804


Interfacing ADCto 8051
 The figure 5.16above shows the schematic for interfacing ADC0804 to 8051. ]
 The circuit initiates the ADC to convert a given analogue input, then
accepts the corresponding digital data and displays it on the LED array
connected at P0.
 For example, if the analogue input voltage Vin is 5V then all LEDs will glow
indicating 11111111 in binary which is the equivalent of 255 in decimal.
 Data out pins (D0 to D7) of the ADC0804 are connected to the port pins
P1.0 to P1.7 respectively.
 LEDs D1 to D8 are connected to the port pins P0.0 to P0.7 respectively.
 Resistors R1 to R8 are current limiting resistors. I
 Control signals for the ADC (INTR, WR, RD and CS) are available at port pins
P3.4 to P3.7 respectively.
 Resistor R9 and capacitor C1 are associated with the internal clock circuitry of
the ADC.
 Preset resistor R10 forms a voltage divider which can be used to apply a
particular input analogue voltage to the ADC.
 Push button S1, resistor R11 and capacitor C4 forms a de bouncing reset
mechanism. Crystal X1 and capacitors C2, C3 are associated with the clock
circuitry of the microcontroller.
Example Program.
ORG 00H
MOV P1, #11111111B // initiates P1 as the
input port MAIN: CLR P3.7 // makes CS=0
SETB P3.6 // makes RD
high CLR P3.5 // makes WR
low
SETB P3.5 // low to high pulse to WR for starting
conversion WAIT: JB P3.4, WAIT // polls until INTR=0
CLR P3.7 // ensures CS=0
CLR P3.6 // high to low pulse to RD for reading the data from
ADC MOV A,P1 // moves the digital data to accumulator
CPL A // complements the digital data (*see the
notes) MOV P0,A // outputs the data to P0 for
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the MAIN
program
END

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5.6 DAC (DIGITAL TO ANALOGUE CONVERTER)
5.6.1 DAC0800
 DAC0800 series are monolithic 8-bit high-speed current output digital-
to-analog converters (DAC)
 The performance and characteristics of the device are essentially unchanged
over the
±4.5V to ±18V power supply range
 Power consumption at only 33 mW with ±5V supplies is independent of
logic input levels.
 The DAC 0800 consists of a 8 data lines and REF voltage lines figure 5.17 is
shown in below.
 When the DAC is given the digital input it converts the Digital data to
corresponding current, to convert the I to V we use UA 741.

Fig: 5.18 Pin diagrams of 0800

Fig: 5.19. How a DAC works

5.6.2 PIN ASSIGNMENT WITH 8051

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8051 DAC 0800

REF VOLTAGE V+ Line is given to+12V regulator(7812)


LINES
V- Line is given to -12Vregulator(7912)

78 series in the Regulator IC indicates + voltage

79 series in the Regulator IC indicates - voltage

DAC – DATA LINES PA.0 D0

PA.1 D1

PA.2 D2

PA.3 D3

PA.4 D4

Table 5.13 Pin Assignment With 8051


Assembly Program To Interface DAC 0800 With 8051
CNTRL : 4003H
PORTA :

4000CH
MEMORY ADDRESS OPCODE MNEMONICS
8500 74 80 MOV A, #80H
8502 90 FF 0F MOV DPTR, #CNTRL
8505 F0 MOVX @DPTR, A
8506 74 00 START: MOV A, #00H
8508 90 FF 0C L1: MOV DPTR, #PORTA
850B F0 MOVX @DPTR, A
850C 04 INC A
850D 70 F9 CJNE A, #0FF, L1
Table 5.14Memory Addresses of 8051

5.7 SENSOR INTERFACING

5.7.1 Temperature sensor interfacing with


8051 Temperature Measuring
 A temperature sensor LM35 is interfaced to the 8051 by an ADC0804
 The output voltage from the LM35 is linearly proportional to the measuring
temperature
 The ADC0804 converts the output voltages from the LM35 into digital
signals, which correspond to the measured temperature. Handled by the
8051.
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5.7.1.1 LM35 temperature sensor

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 The LM35 series are precision integrated-circuit temperature sensor,
whose output voltage is linearly proportional to the Celsius (Centigrade)
temperature.
 The LM35 thus has an advantage over linear temperature sensoris not
required to subtract a large constant voltage from its output to obtain
convenient Centigrade scaling.
 The LM35 does not require any external calibration or trimming .
 It to provide typical accuracies of ±¼°C at room temperature and ±¾°Cover a
full -55 to
+150°C temperature range.
 The LM35's low output impedance, linear output, and precise inherent
calibration
 It makes interfacing to readout or control circuitry especially easy.
 It can be used with single power supplies, or with plus and minus supplies.
 It draws only 60 µA from its supply.
 It has very low self-heating, less than 0.1°C in still air.
 The LM35 is rated to operate over a -55° to +150°C temperature range.

5.7.1.2 LM35 Pin Outs:


Mainly the LM35 has 3 pins are shown in following figure5.19, which are:

Pin 1: VDD - Supply voltage


Pin 2: Vout - Output analogue voltage, Linear + 10.0 mV/°C
scale factor Pin 3: GND – Ground

Fig: 5.20 LM35 Pin Outs

5.7.1.3 Block Diagram for ADC0804 with 8051

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Fig: 5.21 ADC0804 with 8051

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5.8 INTERFACING WITH EXTERNAL MEMORY WITH 8051
 Require to connect 8051 to external program memory of size 4 KiB starting
at 0000H with EPROM 2716.
 EPROM 2716 is 2K x 8 bit with Pin Diagram shown in Figure 5.21.1.From
requirement, we need 5.21.2 of 2716. The memory map is shown Figure
5.21.
Address Decoder Circuit
There are 11 address lines for each 5 address lines (A[11..15]) which
could be used inaddressdecoder.All address lines (16 in this case have
absolute address decoder.) Consider mapped addresses in Table 5.15

Table 5.15 mapped addresses

Fig: 5.22 EPROM 2716 is 2K x 8 bit with Pin Diagram

 The idea is to use signal(s) in address decode to select the correct 2716 device.
 Using partial address decoder may reduce number of signals used, and
possibly the size of the address decoder circuit.
 From Table 5.15, signal A11 could be used to select each 2716.
 This is because 2716 #0 has no addresses that A11 is 1.
 Therefore, in case of using partial decoder, we can create a select signal Y
with “Y = A11”.
 If Y is 0, Y will select 2716 #0. If Y is 1, Y will select 2716 #1.
 Figure 5.22 shows the designed partial address decoder. Figure 5.23 shows
absolute address decoder case.

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Fig:5.23 Designed Partial Address Decoder

Fig: 5.24 Absolute Address Decoder Case.

5.10 INTERFACING STEPPER MOTOR WITH 8051


 A Stepper Motor is a brushless, synchronous DC Motor.
 It has many applications in the field of robotics and mechatronics.
 The total rotation of the motor is divided into steps.
 The angle of a single step is known as the stepper angle of the motor.
 There are two types of stepper motors Unipolar and Bipolar.
 Unipolar stepper motor is commonly used by electronics hobbyists.
 Stepper Motors can be easily interfaced with a microcontroller using
driver ICs such as L293D or ULN2003.

5.10.1 Driving Unipolar Stepper Motor with 8051

Fig: 5.25 Unipolar Stepper Motor Windings


 Unipolar stepper motors can be used in three modes namely the Wave
Drive, Full Drive and Half Drive mode. Each drive have its own advantages and
disadvantages,
Wave Drive:
 In this mode only one electromagnet is energized at a time.

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 Generated torque will be less when compared to full drive in which two
electromagnets are energized at a time but power consumption is reduced.
 It has same number of steps as in the full drive.
 This drive is preferred when power consumption is more important than
torque. It is rarely used.
Wave Drive Stepping Sequence
Step A B C D
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
Table 5.16 Wave Drive Stepping Sequence
Full Drive
 In this mode two electromagnets are energized at a time.
 The torque generated will be larger when compared to Wave Drive.
 This drive is commonly used than others.
 Power consumption will be higher than other modes.
Full Drive Stepping Sequence
Step

Table 5.17Full Drive Stepping Sequence

 The following circuit diagram fig.5.25 is driving a bipolar stepper


motor using 8051 microcontroller using L293D.
 24MHz crystal is connected to provide the required clock for the microcontroller.
 10μF capacitor and 10KΩ is used to provide Power On Reset (POR) for
the 8051 microcontroller.
 L293D is connected to pins P2.0, P2.1, P2.2, P2.3 of the microcontroller and
two pairs of L293D are enabled by teing EN1, EN2 to 5V.

Fig: 5.26 Bipolar Stepper Motor Using 8051 Microcontroller

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 Logic Voltage (5V) is connected to Vss pin and Motor Supply (12V) is
connected to the Vs pin of L293D.
 Center Tap of each windings of stepper motor is shorted and connected to
the motor supply. Each winding of the motor by making corresponding pin of
L293D LOW

5.11 WAVEFORM GENERATION


5.11.1 Square wave generation using 8051 timer.
 Square waves of any frequency (limited by the controller
specifications) can be generated using the 8051 timer. The technique is very
simple.
 Write up a delay subroutine with delay equal to half the time period of the
square wave.
 After the delay subroutine is finished, make the corresponding port pin low
and call the delay subroutine gain. After the subroutine is finished repeat the
cycle again.
 The result will be a square wave of the desired frequency at the selected port
pin.
 The circuit diagram 5.26 is shown below and it can be used for any square
wave, but the program has to be accordingly.
 Programs for different square waves are shown below the circuit diagram 5.26

Fig: 5.27 Square wave generation using 8051 timer

PIC MICROCONTROLLER:

PIC stands for Peripheral Interface Controller coined by Microchip Technology


to identify its single-chip microcontrollers. These devices have been
phenomenally successful in 8-bit microcontroller mar-ket. The main reason is
that Microchip Technology has constantly upgraded the device architecture
and added needed peripherals to the microcontroller to ’suit customers’
requirements.

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College Architectures:
Low-end Microcontroller

Microchip PIC microcontrollers are available in various types. WhenPIC−M


icroMCU firstbecame available from General Instruments in early 1980’s, the
microcontroller consisted of a verysimple processor executing 12-bit wide
instructions with basic I/O

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functions. These devices are knownas low-end architectures.Some of the
low-end device past numbers are12C5XX, 16C5X, and 16C50.

Mid-range Architectures:
Mid-range Architectures are built by upgrading low-end architecture with
more number of peripherals,more numbers of register and more data
memory. Some of the mid-range devices are16C6X,
16C7X, 16F87X
↑Program memory
type C = EPROM
F=Flash
RC = Mask ROM.
Popularity of PIC microcontrollers is due to the following factors-
1. Speed: Harvard Architecture, RISC Architecture1
instruction Cycle = 4 clock cycles. For 20 MHz clock,
most of the instructions are executed in 0.2μsor five
instructions per mi- crosecond.
2. Instruction Set Simplicity:The instruction set consists of
just 35 instructions (as opposed to 111 instructions for
8051).
3. Power on reset Power-out reset Watch-dog
timerOscillator Options.
4. Programmable timer options on chip ADC.
5. Up to 12 independent interrupt sources
6. Powerful output pin control25mA (max.) current
sourcing capability.
7. EPROM/OTP/ROM/Flash memory options.
8. Free assembler and simulator support.

Basic Architecture of PIC Microcontroller:


CPU Registers: W, the working register, is used by many instructions as the
source of an operand. It may also serveas the destination for the result of
the instructions execution. It works as the accumulator. W working register,

Fig.5.28.PSW of PIC microcontroller.

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Fig.5.29.Architechture of PIC
W→Temporary holding register, often called as an accumulator, cannot be
accessed directly. Instead,contents must be moved to other registers that
can be accessed directly.
BANK ADDRESSING:

Fig.5.30.Bank addressing

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Register File Structure and Addressing Modes:
Register file→locations that an instruction can access via an address.
Register file consists of two components
1. General purpose register file (same as RAM)
2. Special purpose register file.

Fig5.31.Register file & addressing Structue

RPO bit in the Status register detects the bank. 7 bit of direct address TRPO
determines the absolute address of the register. Indirect addressing
modeFSR contains the 8-bit address of the data/register.

Memory Organization;
The PIC 16C7X family has a 13-bit program counter capable of
addressing 8k×14 program memory.PIC16C74A has 4k×14 program
memory. For those devices with less than 8k program memory, accessing a
location above the physically implemented address will cause a wraparound.

ARM PROCESSORS:
ARM, previously Advanced RISC Machine, originally Acorn RISC
Machine, is a family of reduced instruction set computing (RISC)
architectures for computer processors, configured for various environments.
Arm Holdings develops the architecture and licenses it to other companies,
who design their own products that implement one of those architectures.

Processors that have a RISC architecture typically require fewer transistors


than those with a complex instruction set computing (CISC) architecture
(such as the x86 processors found in most personal computers), which
improves cost, power consumption, and heat dissipation.

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This ARM is a family of microcontroller developed by makers like ST
Microelectronics, Motorola, and so on. The ARM architecture comes with
totally different versions like ARMv1, ARMv2, etc., and, each one has its own
advantage and disadvantages.

Fig.5.32.Architecture of ARM Processor

 The ARM cortex is a complicated microcontroller within the ARM


family that has ARMv7 design. There are 3 subfamilies within the
ARM cortex family : ARM Cortex Ax-series
 ARM-Cortex Rx-series
 ARM-Cortex Mx-series
 Arithmetic Logic Unit
 Booth multiplier
 Barrel shifter
 Control unit
 Register file

This article covers the below mentioned components.

The ARM processor conjointly has other components like the Program status
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register, (Z, S, V and C). The modes bits
Microcontroller
conjointly exist

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within the program standing register, in addition to the interrupt and quick
interrupt disable bits; Some special registers: Some registers are used like
the instruction, memory data read and write registers and memory address
register.

Priority encoder: The encoder is used in the multiple load and store
instruction to point which register within the register file to be loaded or kept
.

Multiplexers: several multiplexers are accustomed to the management


operation of the processor buses. Because of the restricted project time, we
tend to implement these components in a very behavioral model. Each
component is described with an entity. Every entity has its own architecture,
which can be optimized for certain necessities depending on its application.
This creates the design easier to construct and maintain.

Fig.5.33.ARM block diagram


Arithmetic Logic Unit (ALU):
The ALU has two 32-bits inputs. The primary comes from the register
file, whereas the other comes from the shifter. Status registers flags
modified by the ALU outputs. The V-bit output goes to the V flag as well as
the Count goes to the C flag. Whereas the foremost significant bit really
represents the S flag, the ALU output operation is done by NORed to get the
Z flag. The ALU has a 4-bit function bus that permits up to 16 opcode to be
implemented.

Booth Multiplier Factor:


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Microcontroller
register file. The multiplier output is barely 32-Least Significant Bits of the
merchandise. The entity representation of the multiplier factor is shown in
the above block diagram. The

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multiplication starts whenever the beginning 04 input goes active. Fin of
the output goes high when finishing.

Booth Algorithm:
Booth algorithm is a noteworthy multiplication algorithmic rule for 2’s
complement numbers. This treats positive and negative numbers uniformly.
Moreover, the runs of 0’s or 1’s within the multiplier factor are skipped over
without any addition or subtraction being performed, thereby creating
possible quicker multiplication. The figure shows the simulation results for
the multiplier test bench. It’s clear that the multiplication finishes only
in16 clock cycle.

Barrel Shifter:

The barrel shifter features a 32-bit input to be shifted. This input is


coming back from the register file or it might be immediate data. The shifter
has different control inputs coming back from the instruction register. The
Shift field within the instruction controls the operation of the barrel shifter.
This field indicates the kind of shift to be performed (logical left or right,
arithmetic right or rotate right). The quantity by which the register ought to
be shifted is contained in an immediate field within the instruction or it
might be the lower 6 bits of a register within the register file.

The shift Value input bus is 6-bits, permitting up to 32 bit shift. The shifttype
indicates the needed shift sort of 00, 01, 10, 11 are corresponding to shift
left, shift right, an arithmetic shift right and rotate right, respectively. The
barrel shifter is especially created with multiplexers.

Control Unit:

For any microprocessor, control unit is the heart of the whole process
and it is responsible for the system operation,so the control unit design is the
most important part within the whole design. The control unit is sometimes a
pure combinational circuit design. Here, the control unit is implemented by
easy state machine. The processor timing is additionally included within the
control unit. Signals from the control unit are connected to each component
within the processor to supervise its operation.

ARM7 Functional Diagram

The final thing that must be explained is how the ARM will be used and the
way in which the chip appear. The various signals that interface with the
processor are input, output or supervisory signals which will be used to
control the ARM operation.

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Fig.5.34.Pin functional digram of ARM processor

ADDITIONAL USES OF THE CORTEX PROCESSOR


It is a reduced instruction set computing Controller
 32-bit high performance central processing unit
 3-stage pipeline and compact
one It has THUMB-2 technology
 Merges optimally with 16/32 bit instructions
 High performance
It supports tools and RTOS and its core Sight debug and trace
 JTAG or 2-pin serial wire debugs connection
 Support for multiple
processors Low power Modes

 It supports sleep modes


 Control the software package
 Multiple power domains

Nested vectored interrupt controller (NVIC)

 Low latency, low noise interrupts response


 No need for assembly programming

ARM Cortex (STM32) based Solar Street Light:


Present days, solar technology has been progressing in many applications like
homes, industries, etc. The main goal of this project is to conserve the
electrical energy:here an Arm-Cortex- based solar street light is implemented
that works on solar energy. Generally, solar street lights are used where
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electricity
College is not available. Microcontroller

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Hardware Components

 STM32 with ARM cortex board


 White LEDs
 MOSFET
 Battery
 Regulator
 Solar Panel

Software

 Keil compiler
 Embedded C Language

This project utilizes an ARM-Cortex processor of the STM32 family and a


battery for power supply. This project uses a solar panel to charge the
battery where charge controller circuit controls the battery charging. ARM-
Cortex processor is interfaced to a set of LEDs with the help of the MOSFET
Switch

Fig.5.35.ARM Cortex (STM32) based Solar Street Light

The intensity control of the LED lights is possible by varying the duty cycle
from a DC source. A programmed ARM-Cortex microcontroller unit is
engaged to afford different intensities at different times of night by using the
Pulse Width Modulation technique. The charge controller circuit is used to
protect the battery from the deep discharge and overload conditions

Therefore, This is all about ARM architecture with an application.


Furthermore, any queries regarding this article or electronic project kits, You
can write to us for developing and programming these projects practically
and for some more latest arm processor based projects.

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Part-A (2 Marks Questions and Answers)
1. List the major components of the keyboard/Display interface.
a. Keyboard section
b. Scan
section
Display
section
d.CPU interface section

2. What is Key bouncing? (Nov 2012)


Mechanical switches are used as keys in most of the keyboards. When a key
is pressed the contact bounce back and forth and settle down only after a small
time delay (about 20ms). Even though a key is actuated once, it will appear to have
been actuated several times. This problem is called Key Bouncing.

3. What is the use of stepper motor?


A stepper motor is a device used to obtain an accurate position control of
rotating shafts. A stepper motor employs rotation of its shaft in terms of steps,
rather than continuous rotation as in case of AC or DC motor.

4. What is TXD?
TXD- Transmitter Data Output .This output pin carries serial stream of the
transmitted data bits along with other information like start bit, stop bits and
priority bit.

5. Compare polling and interrupt. [MAY/JUNE 2016]


 Interrupts vs. Polling
In the Polling method, the microcontroller must "access by himself" the
device and “ask” for the information it needs for processing. In fact we see
that in the Polling method the external devices are not independent systems;
they depend on the microcontroller, and only the micro is entitled to obtain
access to the information it needs.
Interrupt is the signal sent to the micro to mark the event that requires
immediate attention. Interrupt is “requesting" the processor to stop to
perform the current program and to “make time” to execute a special code.
Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal. Upon receiving an interrupt
signal, the microcontroller interrupts whatever it is doing and serves the
device. The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.

6. Define baud rate of 8051 [MAY/JUNE 2016]


In serial communication the data is rate is known as the baud rate, which
simply means the number of bits transmitted per second. In the serial port modes
that allow variable baud rates, this baud rate is set by timer 1.

7. State the function of RS1 and RS0 bits in the flag register of Intel8051
microcontroller? (May 2013)

RS1 , RS0 – Register bank select bits


RS1 RS0 Bank Selection
0 0 Bank 1
0 1 Bank 2
1 0 Bank 3
1 1 Bank 4

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8. What is the necessity to interface DAC with microcontroller?
College Microcontroller [NOV/DEC 2014]
When the DAC is given the digital input it converts the Digital data to
corresponding current, to convert the I to V we use UA 741.

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9. What is difference between watch dog timer and ordinary timer? [NOV/DEC 2013]
Timer is a clock that controls the sequence of an event while counting in fixed
intervals of time. A Timer is used for producing precise time delay. Secondly, it can
be used to repeat or initiate an action after/at a known period of time
The 'watchdog timer' is a timing device such that it is set for a preset time interval
and an event must occur during that interval. On failure to get that event in the
watched time interval, the device generates the timeout signal.

10. Compare Microprocessor and Microcontroller.


1. Microprocessor: Itcontains the circuitry ALU, general purpose of microprocessor
and Microcontroller registers, stack pointer, has built- in ROM, RAM, I/O program
counter, clock timing devices, timers and counters. Circuit and interrupt circuit.
2. Microprocessor It has man y instructions to It has one or two instructions to move
data between memory data between memory and CPU. Microcontroller It has one or
two bit handling.It has man y bit handling instructions.
3. Microprocessor Access times for memory and I/O devices are more.
Microcontroller Less access times for built-in memory and I/O devices.
4. Microprocessor based system requires more hardware Microcontroller based
system requires less hardware reducing PCB size and increasing the reliability.

11. What is the size of the on-chip program memory and on-chip data memory of 8051
microcontroller? (May /June 2012)
 4 kb on chip program memory
 128 bytes on chip data memory

12. What are the different types of ADC(Nov/Dec 2011)


 Successive approximation ADC
 Counter type ADC
 Flash type ADC
 Integrator converters
 Voltage to frequency converters

13. What is the use of Verf pin in the ADC..( Nov/Dec 2012)
This pin used where FSD of input signal is lower than 5 volts.to get digit 255
for 8 bitADC,and 1023 for 10bit ADC.If maximum voltage is 2 volts connect Vref to 2
volt ,to get maximum resolution.If maximum voltage is 2 volts connect Vref to 2.56
volt ,to get maximum resolution

14. What is Baud rate for mode 0 operation of serial port of 8051. (May/June 2013)
 Timer mode "1" is a 16-bit timer.
 It functions just like 13-bit mode except that all 16 bits are used.
 TLx is incremented from 0 to 255.
 When TLx is incremented from 255,it resets 0 and causes THx to be
incremented by 1.

15. List some of the features of 8096 microcontroller.


1) The 8096 is a 16-bit microcontroller.
2) The 8096 is designed to use in applications which require high speed
calculations and fast I/O operations.
3) The high speed I/O section of an 8096 includes a 16-bit timer, a 16-bit
counter, a 4 input programmable edge detector, 4 software timers and a 6-
output programmable event generator. It has 100 instructions, which can
operate on bit, byte, word, and double words.
4) The bit operations are possible and these can be performed on an y bit in the
register file or in the special function register.

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16. What are the addressing modes supported by
College 8051?(ECE M/J 2009)
Microcontroller

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SKR Engineering EC8691 – Microprocessor &
College Microcontroller
 Immediate addressing mode.
 Register addressing mode.
 Direct addressing mode.
 Indirect addressing mode.
 Indexed addressing mode

17. List the applications of microcontroller. [MAY/JUNE 2009]


 Stepper motor interfacing
 Length measurement
 Square wave generator

18. Give the alternate functions for the port pins of port3?
 RD – Read data control output.
 WR – Write data control output.
 T1 – Timer / Counter1 external input or test pin.
 T0 – Timer / Counter0 external input or test pin.
 INT1- Interrupt 1 input pin.
 INT 0 – Interrupt 0 input pin.
 TXD – Transmit data pin for serial port in UART mode.

19. Define XTAL1 and XTAL2. [MAY/JUNE 2009]


Inbuilt oscillator which derives the necessary clock frequency for the
operation of the controller. XTAL1 is the input of amplifier and XTAL2 is the output of
the amplifier.

20. What are the advantages of microcontroller over microprocessor?


The overall system cost is low, as the peripherals are integrated in a single chip.
Size is small. Easy to troubleshoot and maintain. System is more reliable.

21. Give the various modes of 8254 timer?(Apr/May2019)


 Mode 0:interrupt or terminal count
 Mode 1:Rate generator
 Mode 3:square wave generator
 Mode 4:software triggered strobe
 Mode 5:hardware triggered strobe

22. List the major components of 8257 keyboard/display interface?


 Keyboard section
 Bit Select S/R
 Scan section
 Display section
 MPU interface

23. Write down the output control signals used in 8255A PPI?
 OBF Output Buffer Full
 ACK Acknowledgement
 INTR Interrupt request
 INTE Interrupt Enable

24. List the 8251interrupts with its priority.(April/May’17,Nov/Dec’17)

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College Microcontroller

25. What are the types of sensors used for interfacing? (April/May’17, Nov/Dec’17)
8051 Connection to ADC0848 and Temperature Sensor ADC0804 is a very
commonly used 8-bit analog to digital convertor. It is a single channel IC, i.e.,
it can take only one analog signal as input.

26. Define serial to parallel conversion?


In serial reception, the MPU receives a stream of eight bits andit is converted in to 8-bit
parallel word. This is known as serial to parallel conversion.

27. Differentiate between timers and counters. Draw the diagram of TCON IN 8051
[MAY/JUNE 2015]
 The timer content is available in four 8-bit special function registers, viz,
TL0,TH0,TL1 and TH1 respectively. In the "timer" function mode, the counter
is incremented in every machine cycle. The clock rate is 1/12 th of the
oscillator frequency.
 In the "counter" function mode, the register is incremented in response to a 1
to 0 transition at its corresponding external input pin (T0 or T1). It requires 2
machine cycles to detect a high to low transition. Hence maximum count rate
is 1/24 th of oscillator frequency.
The diagram of TCON IN 8051

28. Which register is used for serial programming in 8051, illustrate it. [MAY/JUNE 2015]
Writing data to the SFR sbuf sets this data in the serial output buffer and
starts the transmission. Reading from the sbuf register reads data from the
serial receive buffer.

SBUF 99 Serial Input/Output buffer. Only byte addressing


is possible.
SCON 98 Serial communication control. Both bit addressing
and byte addressing possible.

29. When an external memory access generated in 8051? (Apr/May2019)


Since external data memory is indirectly accessed through a data
pointer register (which must be loaded with an address), it is slower than
access to internal data memory. Several 8051 devices provide on-chip XRAM
space that is accessed with the same instructions as the traditional external
data space.

Part-B (16 Marks Questions)

1. Describe the functional of the signals present in 8051. (Refer Sec 5.1)
(May/June 2013)
2. Explain how an LCD and keyboard is interfaced with 8051.(Refer
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Sec 5.4) (May/June 2013)
College Microcontroller

3. Describe about serial port interface of 8051.(May/June 2013)

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SKR Engineering EC8691 – Microprocessor &
College Microcontroller

4. Explain 8051 serial port programming with example(Refer Sec 5.2) (May/June
2016)

5. Draw the circuit diagram to interface an LCD with microcontroller and


explain how to display the data using LCD. (Refer Sec 5.4) (May/June 2012,
Nov/Dec 2012)

6. Draw the architectural block diagram of 8051 microcontroller and explain.


(Refer Sec 5.1)(May/June 2012)

7. Explain the internal data memory structure of 8051 microcontroller with its
SFRs.
(Refer Sec 5.1) (Nov/Dec 2012)

8. Draw the pin diagram of 8051 microcontroller and explain the functions of
each pin.
(Refer Sec 5.5.2)(Nov/Dec 2011)

9. Discuss briefly the various registers in 8051 microcontroller,(Refer


Sec 5.1) (Nov/Dec 2011)

10.Explain with the help of a neat diagram how DAC is interfaced


with 8051 Microcontrollers
DAC (Refer Sec 5.6)(Apr/May 2011) (Apr/May2019)

11.Describe the various interrupts and their associated


priorities in 8051 microcontroller. (Refer Sec 5.3)(Nov/Dec
2010)

12.Draw a diagram to interface a stepper motor with 8051 microcontroller


and explain. Write a program to make the stepper motor to rotate both
clockwise and anticlockwise directions.[MAY/JUNE 2015, NOV/DEC 2014
MAY/JUNE
2016,April/May’17]

13.How to interface an LCD display with microcontroller? Explain how


to display a character using LCD display. [MAY/JUNE 2015,NOV/DEC
2014,April/May’17] (Apr/May2019).
14.Explain the interrupt structure of 8051 microcontroller
with suitable diagrams.[Nov/Dec’14]
15. Illustrate the serial communication in 8051, with its
special function register(Nov/Dec’17)
16.Interface the ADC converter with 8051 and explain with neat diagram
with assembly language program (Nov/Dec’17).
17. Develop 8051 based system design 8Kbyte RAM to generate the
Triangular waveform and Square waveform using DAC (Nov/Dec’17,
April/May’17) (Apr/May2019)
18.Briefly explain about the various addressing modes of 8051 with one
example.
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(Apr/May2019).
College Microcontroller
19.Explain about the Architecture of ARM processor.
20.Briefly explain about the PIC controller.

*****

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