ASIC Lab Manual

Covering – Incisive, IMC, Genus, Modus, Conformal, Innovus,

Tempus, Voltus

Cadence RTL-to-GDSII Flow

Course Version 2.0

Developed By

University Support Team

Cadence Design Systems, Bangalore

Table of Contents
Cadence RTL-to-GDSII Flow

Module 1: Design Simulation Using the INCISIVE Simulator ............................ 05

Lab 1-1 Simulating a Simple Counter Design ................................................ 05
Getting Started .............................................................................. 05
Steps to Invoke Tools ..................................................................... 05
Verification Using Simulation ............................................................. 06

Module 2: Code Coverage Using Incisive Metrics Center .................................. 12

Lab 2-1 Code Coverage Flow for a Simple Counter Design ............................ 12
What Is Code Coverage? ................................................................ 12
Code Coverage Flow ...................................................................... 13

Module 3: The Synthesis Stage .......................................................................... 19

Lab 3-1 Running the Basic Synthesis Flow .................................................... 19
Getting Started .............................................................................. 19
Steps to Invoke Tools ..................................................................... 20
Running Synthesis (without DFT)……………………………………….……….. 20
Creating the Script for Run ............................................................. 20
Timing Constraints or SDC File............................................................ 22
Starting Genus ............................................................................... 23
Loading Libraries and Designs and Synthesizing the Design ............. 24
Genus Legacy Terminal After Synthesis ............................................. 25
Launching the GUI ......................................................................... 25
Generating Reports........................................................................ 26
Writing Output Files ...................................................................... 27
Exiting the Software ...................................................................... 28
Lab 3-2 Running the Synthesis Flow with DFT .............................................. 29
Understanding the Flow................................................................. 29
Running Scan Insertion .................................................................. 31

Module 4: The Modus Test Stage ...................................................................... 35

Lab 4-1 Running the basic ATPG flow in Modus Test .................................... 35
Getting Started .............................................................................. 36
Steps to Invoke Tools ..................................................................... 36

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 Invoking Modus Test...................................................................... 37
Creating a New Project .................................................................. 38
Build Model ................................................................................... 39
Build Test Mode............................................................................. 43
Build Fault Model .......................................................................... 45
Verifying Test Structures ................................................................ 49
ATPG Vector Generation ................................................................ 51
Scan Test ....................................................................................... 51
Logic Tests ..................................................................................... 53
Write Out Verilog Patterns............................................................. 56
Exiting the Software ...................................................................... 58

Module 5: The Equivalency Checking Stage ....................................................... 59

Lab 5-1 Running the Equivalence Checking Flow in Conformal ..................... 59
Get Started .................................................................................... 59
Steps to Invoke Tools ..................................................................... 60
Invoking Equivalency Checking........................................................... 60
Creating the Script (DOFILE) for Run .................................................. 61
Running Equivalency Checking ........................................................... 63
Loading Libraries and Designs, and Comparing Designs.................... 63
Analyzing Results After Comparison .................................................. 64
Exiting the Software ...................................................................... 65
Lab 5-2 Creating a .v Format File from .lib Format ....................................... 65
Understanding the Flow................................................................. 65
Creating a .v File ............................................................................ 66

Module 6: The Implementation Stage ............................................................... 67

Lab 6-1 Running the Basic Implementation Flow ......................................... 67
Importing the Design ..................................................................... 67
Viewing the Timing Setup and Design Import Results ...................... 72
Viewing the Design Hierarchy ............................................................ 75
Floorplanning the Design ............................................................... 76
Power Planning.............................................................................. 78
Creating Power Rails with Special Route ........................................... 83
Running Placement Optimization ...................................................... 84
Running Clock Tree Synthesis ............................................................. 87
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 Routing the Nets ............................................................................ 88
Extraction and Timing Analysis........................................................... 89
Running Physical Verification ............................................................. 90
Verify Geometry ............................................................................ 90
Verify Connectivity ........................................................................ 90
Running Power Analysis ................................................................. 90
Viewing Power Analysis Results ......................................................... 97
Generating a Stream File................................................................ 99

Module 7: Running Gate Level Simulations on a Simple Counter Design ........ 100
Lab 7-1 Running Gate Level Simulations on a Simple Counter Design ......... 100
What Is Gate Level Simulation?........................................................ 100
SDF Annotation ........................................................................... 101
Simulating the Netlist with the xrun Command .............................. 104

Module 8: Timing Signoff Analysis ................................................................... 108

Lab 8-1 Run Signoff Timing Analysis .......................................................... 108
Running Timing Analysis and Debugging in the Innovus Session.... 109
Running Independent Timing Analysis in Tempus........................... 111
Rerun Innovus to Fix All Violations .................................................. 116
Summary ..................................................................................... 118

© 2017 Cadence Design Systems, Inc. All rights reserved. 4

 Module 1: Design Simulation Using the INCISIVE Simulator
Simulating a Simple Counter Design
Objective: To simulate a simple counter design with a
testbench using the Incisive Enterprise Simulator or IES tool.
Get Started
Directory Structure

Let us understand the directory structure of the counter_database.

 Constraints – Contains SDC file

 lef – Contains lef files

 lib – Contains lib files

 rtl – Contains rtl design files

 QRC_Tech – Contains QRC tech file

 Captable – Contains Cap table

 Gate_level_simulation – Contains Simulation library

 Please save your design (RTL files) inside the RTL directory and keep
both RTL as well as test bench inside the simulation directory.
Libraries, LEF and Constraint files (SDC files) are kept in respective
directories. Simulation, Synthesis, gate_level_simulation,
Equivalence_checking, Physical_design and STA directories are used to
run simulation, synthesis, gate level simulation, logic equivalence
checking, physical design and timing analysis so that all log files,
command files and other tool generated files won’t get mixed up.

Steps to Invoke Tools

 Before invoking any tool, invoke C shell be typing ‘csh’ in terminal.

 Source the cshrc file by typing ‘source <cshrc file>’ e.g.: - source cshrc
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 Verification
IES (Incisive Enterprise Simulator) is the tool used for verification. Navigate to
Simulation directory where you have kept your RTL and test bench (simulation
directory).
 Invoke the tool by typing ‘nclaunch -new’ in the terminal.
NCLaunch window will appear like in the below screen shot and in the
NCLaunch window, select ‘Multiple Step’ option.

 On clicking the ‘Multiple Step’ option, ‘nclaunch: Open Design Directory’

window will appear as shown below

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  Click on ‘Create cds.lib File’ option and a ‘Create a cds.lib file’ window will open. Click
‘Save’ option.

 A ‘New cds.lib File’ window will appear. Click any of the three options available
depending on your RTL and click ‘OK’. As the counter design is in verilog, the third
option is selected.

 Click ‘OK’ in the ‘nclaunch: Open Design Directory’ window.

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  In the NCLaunch window, we will be able to see the design as well as the
testbench that we kept inside the simulation directory.

Compilation

 The next step is to compile (Checks syntax and semantics) the code. For this,
select both the design and testbench and choose the appropriate compilers.

• ncvlog for Verilog designs. (choose ncvlog for counter design as the design is
in verilog)

• ncvhdl for VHDL designs.

Command Entry Window

Any error in the code will be reported in the ‘Command Entry Window’.

© 2017 Cadence Design Systems, Inc. All rights reserved. 8

 Elaboration
After rectifying the errors in the code, the next step is elaboration (constructs design
hierarchy and connects signals). Once the compilation is successfully completed, open
the ‘worklib’ directory on the right side of the window and we can see the design
objects created inside. Elaboration should be performed on the testbench as
testbench is the top module at this stage and design is instantiated inside the
testbench. Select the testbench module and select the ‘launch elaborator’ (ncelab)
key.

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Simulation
 After elaboration, the next step is simulation (executes simulation code). For this we have to
send the snapshot generated during elaboration to the simulator.

 Open the ‘snapshots’ folder and select the snapshot and click on ‘launch simulator’
option.

 Launch simulator’ will open ‘Design Browser’ and ‘console’ windows. ‘Console –
SimVision’ window can be used to perform simulation in command mode and
hence can be minimized while using ‘Design Browser –SimVision’ window to run
simulation in GUI mode.

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  In the Design Browser window, select the testbench module (counter_test) and select the
‘waveform’ option. A ‘waveform –SimVison’ window will appear.
 In the waveform window, we can see different ports in the design. Now click on the Run
simulation key to start the simulation. Use the ‘pause’ key to interrupt or stop the simulation.
Use different options like zoom in, zoom out etc to analyze the plot. There are many different
options available in the ‘Design Browser’ as well as in the ‘Waveform’ window to analyze the
design and debugging.

Run SimulationInterrupt Simulation Zoom in, Zoom out etc..

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  After verifying the design, close the tools. We can now proceed for synthesis.

To know more about tool options, use help or pdfs present inside the doc directory of the tool.

Module 2: Code Coverage Using Incisive Metrics Center

Code Coverage Flow for a Simple Counter Design

Objective: To invoke the Code Coverage Tool, Incisive Metric Center (or
IMC) and analyze the code coverage for a simple counter
design with associated test bench.

In this lab, you use the Incisive® Metrics Center software to analyze your code
coverage.

This lab uses the following software release:

 XCELIUM1704

 MDV1704

What Is Code Coverage?

Coverage is a metric to indicate how well the design is exercised by the test bench.
There are two types of coverage:

 Code coverage

 Functional coverage

Code Coverage assesses how well the tests exercise the design code. It points to areas
that did not meet desired coverage criteria. You can then target these with further
tests. Code coverage in Incisive Coverage is classified as the following:

1. Block Coverage – Monitors all exercisable blocks in the Verilog/VHDL

source code and identifies unexercised code during simulation.

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 2. Branch coverage – Complements block coverage by scoring additional
pieces of code that are not by default considered individual blocks.

3. Statement Coverage – Provides information on number of statements

within a block.

4. Expression Coverage – Provides information on why a conditional piece

of code was executed. It provides statistics for all expressions in the HDL
code.

5. Toggle Coverage – Measures the amount of activity in the design, such as

unused signals, signals that remain constant, or signals that have too few
value changes.

FSM Coverage – Interprets the synthesis semantics of the HDL design and monitors
the coverage of the FSM representation of control logic blocks in the design.

Code Coverage Flow

1. Go to the simulation directory of your counter_design lab package or

database.
cd simulation

You will see two files here: counter. v, which is the design itself and
counter_test. v, which is the testbench, both written in the Verilog language.

Run the following xrun command to compile, elaborate and simulate your
counter design as well as prepare it for coverage analysis by including the –
coverage all option in the command; this will include all coverage types for
analysis.
xrun counter.v counter_test.v -access +rwc –coverage all –gui

The command above, along with simulating the design, will create the cov_work
directory and further creates a scope and test directory with coverage model and
coverage data, .ucm and .ucd files respectively.

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 2. . The SimVision™ tool starts because of the –gui option in the command
and opens up the console and design hierarchy windows.

3. Click on the Run button.

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4. Invoke the IMC tool by either entering imc in your terminal or by clicking the

symbol from the SimVision console window and load the coverage data into the tool
by clicking on the load button.

5. The imc tool starts and will open the following welcome page of the imc tool, if
you launch by typing imc in the console window. Then you need to load the
coverage model dir. into the tool by clicking on the load button and selecting the
path to the coverage model as follows.

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6. The imc tool opens the metric center as shown showing the hierarchy of the design, and the
testbench.

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7. Select the block coverage context from the pull-down menu and as seen this
creates a block coverage context as well as shows the blocks covered/uncovered. In
this case all are covered.

7
.

8. Select the toggle coverage context from the pull-down menu and as seen this
creates a toggle coverage context as well and shows the toggling of the different
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signals covered/uncovered. As you can see rst is not fully toggled for both values of 1
and 0.

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Module 3 The Synthesis Stage
Lab 3.1: Running the Basic Synthesis Flow

Objective: To run the basic synthesis flow for a design.

The tool used for synthesis (converting RTL to gate level netlist) is Genus™ Synthesis
Solution (Genus) in Legacy mode.

This lab uses the following software release:

 GENUS162

Getting Started

Let us understand the directory structure of the counter_database.

 Constraints – Contains SDC file

 lef – Contains lef files

 lib – Contains lib files

 rtl – Contains rtl design files

 QRC_Tech – Contains QRC tech file

 Captable – Contains Cap table

 Gate_level_simulation – Contains Simulation library

Please save your design (RTL files) inside the RTL directory and keep both
RTL as well as test bench inside the simulation directory. Libraries, LEF
and Constraint files (SDC files) are kept in respective directories.
Simulation, Synthesis, Gate_level_simulation, Equivalence checking,
Physical_design and STA directories are used to run simulation, synthesis,
gate level simulation, logic equivalence checking, physical design and
timing analysis so that all log files, command files and other tool
generated files won’t get mixed up.

© 2017 Cadence Design Systems, Inc. All rights reserved. 19

Steps to Invoke Tools

Before invoking any tool, invoke C shell by entering “csh” in terminal.

Source the cshrc file by entering “source <cshrc file>”.

e.g., source cshrc

Running Synthesis (without DFT)

Change the directory to synthesis and write a script file for synthesis.

Below is an example of a script file for synthesis.

Creating the Script for Run

The necessary inputs to perform synthesis are RTL, standard cell library and
constraints.

1. Setting search path for libraries:

set_attribute init_lib_search_path <library path>
This command will set the path for the standard cell library.

2. Setting search path for HDL/RTL:

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 set_attribute init_hdl_search_path <rtl path>
This command will set the path for rtl files.

3. Loading libraries:
set_attribute library <library name>
This command will read the specified standard cell library from the specified
library path.

4. Reading the design:

read_hdl <rtl design>
This command will read the rtl design.
Note: If the design is hierarchical or has multiple modules instantiated
inside the top module, use curly braces “{}” to mention all modules
including the top design.
E.g., - read_hdl {top. v sub1.v sub2.v}

Here top. v is the top module and sub1.v and sub2.v are the sub modules that are instantiated
inside the top module.

5. Elaborating the design:

elaborate
The elaborate command constructs design hierarchy and connects signals.

6. Reading the constraints:

read_sdc < sdc file name with path>
This command reads in the timing constraints file. Here we have to provide
the constraints file name along with the path. Explanation on constraints file
is provided later.

7. Running synthesis:
set_attribute syn_generic_effort <effort level>
set_attribute syn_map_effort <effort level>
set_attribute syn_opt_effort <effort level>

© 2017 Cadence Design Systems, Inc. All rights reserved. 21

 syn_generic
syn_map
syn_opt
These commands will perform synthesis by combining the generic, mapped
and optimization synthesis and attributes specifies the synthesis effort. The
effort can be set to “low”, “medium” or “high” depending upon the scenario.

8. Include all the above commands in the script file.

Note: In counter design, you can see a script file “genus_legacy_script.tcl”
inside the synthesis directory. Please open the script file for further
understanding.

Timing Constraints or SDC File

Now let us understand the content of the Constraints or SDC file.

1. Using SDC, we define clock period, pulse width, rise and fall time,
uncertainty and also input and output delays for different signals. The
snapshot below contains the constraints file used in counter design.

2. Let us see the usage and purpose of each command.

create_clock –name –period 10 –waveform {0 5} {get_port “clk”}
This command will define clock with period 10ns and 50% duty cycle and
signal is high in the first half.
set_clock_transition –rise/fall
This command defines the transition delay for clock.

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 set_clock_uncertainty
This command will set the uncertainty due to (clock skew and jitter).
set_input/output_delay
This command will specify the input and output delay used for timing slack
calculations.

3. Keep the constraints file inside the constraints directory.

Important: Once the script file to run synthesis and the constraints file
are ready, we can initiate synthesis. You can either source
complete script or run commands one by one interactively in
Genus Legacy shell to analyze synthesis log/results at each
stage.

Starting Genus

1. Change to the synthesis directory by entering the following command:

cd synthesis

2. Start the software in Legacy mode by entering:

genus -legacy_ui -f <script file.tcl>
Important: Use the following command to invoke Genus Legacy along
with the script file.
“genus” is the command to invoke Genus Synthesis Solution and
-f option is used to pass the script to Genus at the time of
launching the tool. Genus will execute each commands
mentioned inside the script file one by one.
Note: If the script file is in the current working directory (synthesis
directory), we need not have to provide the path for the script.
In case of the counter design, the command will be the following:
genus –legacy_ui -f rc_script.tcl
Important: If you are moving ahead by sourcing the complete script at
one go, you can skip the next section and continue from the
Genus Legacy Terminal after Synthesis section.

© 2017 Cadence Design Systems, Inc. All rights reserved. 23

 Important: While performing synthesis, always check the Genus
terminal to see whether the tool is reporting any error.

Loading Libraries and Designs and Synthesizing the Design

1. Setting the library and HDL paths:

set_attr init_lib_search_path ../lib/
set_attr init_hdl_search_path ../rtl/

2. Loading the library:

set_attr library slow_vdd1v0_basicCells.lib

3. Reading the design:

read_hdl counter.v

4. Elaborating the design:

elaborate

5. Reading constraints:
read_sdc ../constraints/constraints_top.sdc

6. Synthesize to generic gates, map to technology library and optimize the

design:
set_attribute syn_generic_effort medium
set_attribute syn_map_effort medium
set_attribute syn_opt_effort medium
syn_generic
syn_map
syn_opt

© 2017 Cadence Design Systems, Inc. All rights reserved. 24

Genus Legacy Terminal After Synthesis

The following snapshot shows the Genus Legacy Terminal after Synthesis.

Launching the GUI

When the synthesis is complete, run the following steps to use the graphical interface.

1. View or unhide the graphical interface.

gui_show
The interface displays four main windows:
 Hierarchy window
 HDL window
 Schematic window
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  Layout window (This window is enabled after placement with the
Genus_Physical_Opt license or if you read in a DEF file along with the
LEF files.)
These windows are dynamically refreshed to identify the logical hierarchy
you are currently in.

2. To close the GUI, enter the following command:

gui_hide

Generating Reports

Use the “report_*” command to write out the results.

1. To generate timing report use:

report_timing

2. To dump out the power report use:

report_power

3. To report QOR use:

© 2017 Cadence Design Systems, Inc. All rights reserved. 26

 report_qor

Writing Output Files

After completing synthesis, use the below command to dump out netlist, SDF, SDC etc.
for next stages of the flow.

1. To write out Synthesized netlist:

write_hdl > counter_netlist.v

2. To generate final SDC file run:

write_sdc > counter_sdc.sdc

3. Write out SDF file:

write_sdf -timescale ns -nonegchecks -recrem split -edges check_edge >
delays.sdf
 timescale: Used to mention the time unit
 nonegchecks: Used to ignore the negative timing checks
 recrem: Used to split out the recrem (recovery-removal) timing check
to separate checks for recovery and removal
 edges: Specifies the edges values
 check_edge: Keeps edge specifiers on timing check arcs but does not
add edge specifiers on combinational arcs.

Note: The commands listed above will generate netlist, SDF and SDC in
the synthesis directory. If you want, you can specify required directory to
save the output files.

© 2017 Cadence Design Systems, Inc. All rights reserved. 27

Exiting the Software

1. To close Genus use the following command:

exit
After dumping out the netlist and SDC, we can proceed for Physical Design.
Close the Synthesis tool.
Note: To know more about synthesis, please refer to the pdf available
inside the installation directory of the tool.

© 2017 Cadence Design Systems, Inc. All rights reserved. 28

Lab 3-2: Running the Synthesis Flow with DFT
Objective: To run the synthesis flow with DFT for a design.
In this lab you will insert scan cells in the design using Genus Synthesis
Solution (Genus) in Legacy mode.

Understanding the Flow

Let us look at the files we are working with in this lab.

1. Change directory to synthesis and locate genus_dft_script.tcl. The main

purpose of this script is to set up the variables and other commands that
will be used in the flow.

2. Now let us look at the content of the run script (genus_dft_script.tcl).

Here is a breakdown of the script flow for clarity:
 Load all the design files and elaborate
 Read SDC (from constraints directory)
 Read in DFT setup
Same as
 Synthesize to GENERIC explained in
 Synthesize to MAPPED and Optimize normal
 Run DFT flow
synthesis flow

 Incremental Synthesis
 Write results and database
 Write Modus files and ATPG flow

© 2017 Cadence Design Systems, Inc. All rights reserved. 29

The snapshot below shows genus_dft_script.tcl.

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Running Scan Insertion

3. Change to the synthesis directory (if you are not into this directory) by
entering the following command:
cd synthesis

4. Start the software in Legacy mode by entering:

genus –legacy_ui -f <file.tcl>

5. Run basic setup.

Set search paths, load libraries and design, elaborate design and read
constraints:
set_attr init_lib_search_path ../lib/
set_attr init_hdl_search_path ../rtl/
set_attr library slow_vdd1v0_basicCells.lib
read_hdl counter.v
elaborate
read_sdc ../constraints/constraints_top.sdc

6. Set the DFT Scan flip flop style for scan replacement using the following
command:
set_attr dft_scan_style muxed_scan

7. Prefix is added to the name of DFT logic that is inserted using the
following command:
set_attribute dft_prefix dft_ /

8. Define the test signals using the following command:

define_shift_enable -name SE -active high -create_port SE
Note: Syntax for the command is:
define_shift_enable -name {scan_en} -active {high} -create_port
{scan_en}

© 2017 Cadence Design Systems, Inc. All rights reserved. 31

 9. It is recommended you check DFT rules multiple times during a DFT flow
using the following command:
check_dft_rules
As you can see that there are no registers that fail DFT rules, which means that all
of eight registers are eligible for scan connection.

10. Synthesize the design:

set_attribute syn_generic_effort medium
syn_generic
set_attribute syn_map_effort medium
syn_map
set_attribute syn_opt_effort medium
syn_opt
check_dft_rules

11. Specify the number of scan chains required to connect all FFs using the
following command. Here we have used one scan chain:
set_attr dft_min_number_of_scan_chains 1 /designs/counter

12. Specify the scan-in and scan-out ports of the scan chain using the
following command:
define_scan_chain -name top_chain -sdi scan_in -sdo scan_out \
-create_ports

13. Now connect the scan chains using the connect_scan_chains command.
This will include all original FFs that were mapped to scan flops.
connect_scan_chains -auto_create_chains

14. Run incremental synthesis:

syn_opt -incr

© 2017 Cadence Design Systems, Inc. All rights reserved. 32

 15. View the DFT chains using the following command:
report_scan_chains

16. Write out the final netlist, SDF, ScanDEF and constraints using the
following commands:

write_hdl > counter_netlist_dft.v

write_sdf -timescale ns -nonegchecks -recrem split -edges check_edge \
> dft_delays.sdf
write_sdc > counter_sdc_dft.sdc
write_scandef > counter_scanDEF.scandef

17. We will now run the final ATPG analysis and vector generation. This step
will take the final scan chains and run through the basic ATPG flow. This
flow is implemented by the following command:
write_dft_atpg -library ../lib/slow_vdd1v0_basiccells.v
It will generate a directory “et_scripts” in current working location.

18. Change directory to et_scripts to see the files that are generated by
Genus.
 counter.et_netlist.v (completed Verilog netlist used for ATPG tool)

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  runet.atpg (ATPG run script)
 counter.FULLSCAN.pinassign (File specifying IO test behavior)
 et_check.sh (self error checking file used by runet.atpg)
 run_fullscan_sim (NC-sim script to verify ATPG patterns)

19. View the schematic in GUI.

20. Exit the software:

exit

© 2017 Cadence Design Systems, Inc. All rights reserved. 34

Module 4: The Modus Test Stage
Lab 4.1: Running the basic ATPG flow in Modus Test

Objective: To run the basic ATPG flow for a design in Modus Test.

Modus Test is the tool used to verify test logic inserted in the netlist during the
Synthesis stage.

This lab uses the following software release:

 Modus162

Getting Started

Let us understand the directory structure of the counter_database.

 Constraints – Contains SDC file

 lef – Contains lef files

 lib – Contains lib files

 rtl – Contains rtl design files

 QRC_Tech – Contains QRC tech file

 Captable – Contains Cap table

 Gate_level_simulation – Contains Simulation library

Please save your design (RTL files) inside the RTL directory and keep both
RTL as well as test bench inside the simulation directory. Libraries, LEF
and Constraint files (SDC files) are kept in respective directories.
Simulation, Synthesis, gate_level_simulation, Equivalence checking,
Physical_design and STA directories are used to run simulation, synthesis,
gate level simulation, logic equivalence checking, physical design and
timing analysis so that all log files, command files and other tool
generated files won’t get mixed up.

© 2017 Cadence Design Systems, Inc. All rights reserved. 35

Steps to Invoke Tools

1. Before invoking any tool, invoke C shell be typing ‘csh’ in terminal.

2. Source the cshrc file by entering:

source <cshrc file>
e.g., source cshrc

Invoking Modus Test

1. Change the directory:

cd synthesis/et_scripts

2. Invoke the Modus Test tool inside the et_scripts directory using the
command :
modus –legacy_gui

© 2017 Cadence Design Systems, Inc. All rights reserved. 36

Creating a New Project

This step registers this project and allows you to bring up this design from any directory
with the GUI.

1. Select File -> New as shown below

2. You will get a new project pop-up window.

3. Working Directory = <path>/et_scripts (should be filled in for you).

© 2017 Cadence Design Systems, Inc. All rights reserved. 37
 4. Name Counter (This can be anything and will be a unique name for this
particular project.)

5. Setup and Methodology are blank. If you click on the Methodology tab,
you will see a number of default methodologies for your use. These are
not needed for this exercise since we will be running our commands and
flow from the pull-down menus.

6. Click OK to create a new project.

7. Once the project has been created, the GUI will be modified as shown
below

© 2017 Cadence Design Systems, Inc. All rights reserved. 38

Build Model

This step will read in your netlist and libraries and compile them into Modus Test
binary model to be used for all future steps.

1. Select Verification – Build Models – Model.

2. The Build Model pop-up window appears.

© 2017 Cadence Design Systems, Inc. All rights reserved. 39

 3. Now select the Design Source: counter.et_netlist. v (Click on
counter.et_netlist. v to add to the Design Source pane) and specify the
cell Name as counter (The top module name of your design) as shown
below.

© 2017 Cadence Design Systems, Inc. All rights reserved. 40

 4. Click the Setup button (right side bottom) to add library technology.
Browse the technologies file from the browse folder as shown in the
snapshot shown on the next step:

5. Add the /equivalence_checking/slow_vdd1vo_basiccells.v Library and

click on Update Project to save your edits as shown below.
[Note: To convert slow_vdd1vo_basiccells.lib to slow_vdd1vo_basiccells. v,
refer lab. 5-2.]

© 2017 Cadence Design Systems, Inc. All rights reserved. 41

 6. This will bring you back to the Build Model form; click RUN in the form.

7. Click on the Tasks tab to see the running progress of the command. If you
click on any command in the Task pane, you can view the log file in the
Log tab.

© 2017 Cadence Design Systems, Inc. All rights reserved. 42

Build Test Mode

Creates a “test view” of your circuit based on the pin assignments set in the assignfile.

1. Go to Verification -> Build Models -> Test Mode.

In the Build Test mode window, specify the test mode name as FULLSCAN (a
default mode for an ATPG SI to SO configuration) and browse the Input pin
assignment file counter.FULLSCAN.pinassign from the et_scripts directory as
shown below.

© 2017 Cadence Design Systems, Inc. All rights reserved. 43

 2. Click Run in the Build Test Mode window and verify how many Static faults
are active in this mode.

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Build Fault Model

This step takes the model created in the previous step and applies a fault model to the
circuit by placing faults on the appropriate nodes.

3. Go to Verification – Build Models – Fault Model.

© 2017 Cadence Design Systems, Inc. All rights reserved. 45

 4. Check boxes allow you to turn on/off Dynamic Faults. If selected, the tool
will apply the static and dynamic fault model to the circuit. And after
selection click Run.

5. Verify the log file containing information about the Static Faults present
in the entire design and you can see it in the snapshot below.

© 2017 Cadence Design Systems, Inc. All rights reserved. 46

 6. Click on Report – Test Structures.

This tells the tool to trace the scan chains from SO backwards and SI
forwards.

© 2017 Cadence Design Systems, Inc. All rights reserved. 47

 7. Select Test mode name as FULLSCAN in the form and click Run.

8. Now verify how many Controllable chains and how many Observable
chains we have in the design, you can see it in the snapshot below:

© 2017 Cadence Design Systems, Inc. All rights reserved. 48

Verifying Test Structures

In this section, you verify test structures in the scan mode.

1. Go to Verification -> Verify -> Test Structures.

In the Verify Test Structures window select the Test mode name as FULLSCAN
and then click Run.

© 2017 Cadence Design Systems, Inc. All rights reserved. 49

 2. Verify the log. Informational message TSV-381 identifies how many complete
scan chains were found. Informational messages TSV-384 and TSV-385 identify
chains that are broken.

3. Once you have taken your circuit through the build and verify process. It
is now ready for vector generation.

© 2017 Cadence Design Systems, Inc. All rights reserved. 50

ATPG Vector Generation

Before writing the ATPG vectors, we will perform the scan and logic test to verify how
much test coverage can be achieved using the generated test patterns.

 Scan test

 Logic test

Scan Test

In Scan test, we generate patterns to verify simple shifting through the scan chains.
This is mainly to identify manufacturing bugs and to ensure you can shift safely from
Scan in (SI) to Scan out (SO).

1. Go to ATPG – Create Tests – Specific Static Tests – Scan Chain.

© 2017 Cadence Design Systems, Inc. All rights reserved. 51

 2. In the Create Scan Chain Tests window, select the Test mode name as
FULLSCAN and give Create tests experiment name as scan (or name of
your choice) and click Run.

3. The ATPG engine is now generating test patterns that test the scan chain.
Take a look at the log file and observe the resultant Fault Coverage in the
Testmode, Global Coverage and number of test sequences generated as
shown below.

© 2017 Cadence Design Systems, Inc. All rights reserved. 52

Logic Tests

Now we are going to create the standard Stuck-At model ATPG patterns.

1. Go to the pull-down menu: ATPG – Create Tests – Specific Static Tests –

Logic, as shown below.

© 2017 Cadence Design Systems, Inc. All rights reserved. 53

 2. In the Create Logic Test window select the Test mode name as FULLSCAN
and specify Create tests experiment name as logic (or name of your
choice) and click Run.

© 2017 Cadence Design Systems, Inc. All rights reserved. 54

 3. The ATPG engine is now generating test patterns that will test the
structural integrity of the design. Take a look at the log file, observe
resultant Fault Coverage in the Testmode (FULLSCAN), Global Coverage
and total number of Test Sequences.

© 2017 Cadence Design Systems, Inc. All rights reserved. 55

Write Out Verilog Patterns

1. Go to the pull-down menu: APTG – Write Vectors.

© 2017 Cadence Design Systems, Inc. All rights reserved. 56

 2. In the Write Vectors window specify the Test mode name as FULLSCAN
and select Vectors to write as Uncommitted Vectors input Experiment
name and specify name as logic and specify the Language as Verilog. Click
Run and review the log file.

3. You can view all patterns in the log window and the results will be saved
in the /testresults/Verilog directory.

© 2017 Cadence Design Systems, Inc. All rights reserved. 57

Exiting the Software

To close software, enter the following command:

exit
Note: You can find solution files under. Solution folder under synthesis
directory

© 2017 Cadence Design Systems, Inc. All rights reserved. 58

Module 5: The Equivalency Checking Stage
Lab 5-1: Running the Equivalence Checking Flow in Conformal

Objective: To run the basic logic equivalence checking flow for a design.

The tool used for Equivalence checking (Comparing RTL to gate level netlist) is
Conformal® Logic Equivalence Checker (LEC).

Conformal LEC is a tool used for formal verification of designs at various stages in the
flow. Formal verification is the process of verifying designs using mathematical
methods. Equivalence Checking is the process of verifying the correctness of a
modified or transformed design (revised design) by comparing it with a reference
design (golden design).

This lab uses the following software release:

 CONFRML162

Get Started

Let us understand the directory structure of the counter_database.

 Constraints – Contains SDC file

 lef – Contains lef files

 lib – Contains lib files

 rtl – Contains rtl design files

 QRC_Tech – Contains QRC tech file

 Captable – Contains Cap table

 Gate_level_simulation – Contains Simulation library

Please save your design (RTL files) inside the RTL directory and keep both RTL as well
as test bench inside the simulation directory. Libraries, LEF and Constraint files (SDC
files) are kept in respective directories. Simulation, Synthesis, gate_level_simulation,
© 2017 Cadence Design Systems, Inc. All Rights Reserved. 59
Equivalence_checking, Physical_design and STA directories are used to run
simulation, synthesis, gate level simulation, logic equivalence checking, physical
design and timing analysis so that all log files, command files and other tool
generated files won’t get mixed up.

Steps to Invoke Tools

Before invoking any tool, invoke C shell by entering “csh” in terminal.

Source the cshrc file by typing “source <cshrc file>”:

e.g., source cshrc

Invoking Equivalency Checking

Change the directory to “Equivalence_checking.”

1. Invoke Conformal LEC inside Equivalence checking directory in non-GUI

by using the command:
lec –xl –nogui -color -64 –dofile <filename>
 -xl: Launches Conformal L with Data path and advanced
equivalence checking capabilities
 -nogui: Starts the session in non-GUI mode
 -color: Turns on color-coded messaging when in non-GUI mode
 -64: Runs the Conformal software in 64-bit mode
 -dofile <filename>: Runs the script <filename> after starting LEC

© 2017 Cadence Design Systems, Inc. All rights reserved. 60

Creating the Script (DOFILE) for Run

Let us understand the content of the dofile. Dofile is a script file used to run LEC and
below is an example for the dofile.

1. Save log file.

set log file <filename.log> - replace
Save the log file and replace if any log file exists with same name if any.

2. Read the Verilog library by entering:

read library <filename> -verilog –both
 -verilog: To indicate that library is in Verilog format
 -both: Use same library to model or structure both golden and
revised design
Note: Both Verilog and liberty format can be used but Verilog format is
preferred. Steps to generate.v from .lib using Conformal is
mentioned at the end of this session.

3. Read the Golden Design (RTL)

read design <filename> -verilog –golden
 -verilog: To indicate that RTL is coded in Verilog
 -golden: To input the golden design

© 2017 Cadence Design Systems, Inc. All rights reserved. 61

 4. Read the Revised Design:
read design <filename> -verilog –revised
 -verilog: To indicate that netlist is in Verilog
 -revised: To input the revised design

5. Ignore the scan input (scan_in) and scan output (scan_out) pins (as these
instances are not available in golden design and primary output key point
is compare point)
add ignored inputs scan_in –revised
add ignored outputs scan_out –revised
Ignores scan_in and scan_out pin

6. Constraint the scan enable (SE) pin to zero to keep the revised design in
functional mode.
add pin constraints 0 SE -revised
Important: Tool keeps the design in functional mode and ignore scan_in
pin while compare. Also scan_in is not a compare point.

7. Change the mode of operation from “setup” to “lec.”

set system mode lec
Note: Conformal LEC has two modes of operation, i.e., SETUP mode and
LEC mode. Setup mode is used to prepare the design to be
compared. Any command that affects the way the design is
modeled will need to be issued in this mode. LEC mode is where
the designs will get modeled, key points mapped and where the
compare process takes place.

8. Compare golden vs. revised netlist

add compare points –all
compare

Running Equivalency Checking

1. Change to the Equivalence_checking directory by entering this command:

© 2017 Cadence Design Systems, Inc. All rights reserved. 62

 cd Equivalence_checking

2. Start the software by entering this command:

lec –xl –nogui -color -64
You can enter commands interactively in the LEC shell.
The command shell that starts LEC in non GUI mode.
Important: Use the command shown below to invoke Conformal LEC
along with the script file.
lec –xl –nogui -color -64 -dofile counter.do
“lec” is the command to invoke Conformal LEC and the “-dofile” option
is used to pass the script to LEC at the time of launching the tool. LEC
will execute each command mentioned inside the script file one by
one.
Note: If the script file is in the current working directory
(Equivalence_checking directory), we need not have to provide the
path for the script.
Important: If you are moving ahead by sourcing the complete script at
one go you can skip below section and continue from the
section “Analyzing Results after Comparison”.
Important: While performing synthesis, always check the LEC terminal
to see whether the tool is reporting any error.

Loading Libraries and Designs, and Comparing Designs

1. Set log file and read library:

set log file counter_lec.log -replace
read library ../lib/slow_vdd1v0_basiccells.v -verilog -both

2. Load Golden and Revised designs:

read design ../rtl/counter.v -verilog -golden
read design ../synthesis/counter_netlist_dft.v -verilog -revised

3. Add pin constraints and ignore DFT signals:

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 add pin constraints 0 SE -revised
add ignored inputs scan_in -revised
add ignored outputs scan_out -revised

4. Switch System mode to LEC:

set system mode lec

5. Add Compare points and compare the designs:

add compare point -all
compare

Analyzing Results After Comparison

Once the compare process is completed, Conformal LEC will print a summary report
that tells how many key points are equivalent, non-equivalent, aborted and not
compared.

1. Generate verification report:

report verification
(reports a table of all violated checklist items)

2. To turn on GUI window, enter the following command:

set gui on
In case of mapping issue or comparison issue or non-equivalence, use
mapping manager or debug manager or Schematic viewer options in LEC to
resolve the issue.

© 2017 Cadence Design Systems, Inc. All rights reserved. 64

Exiting the Software

1. To close LEC, enter the following command:

exit
Important: Same is the flow to compare netlist generated at different
stages of physical design. Use proper modelling directives and
constraints to verify designs.

Module 5.1: Creating a.v Format File from .lib Format

Objective: To run LEC to create a.v file from .lib file format.
In this lab you will create output file in .v format from input file .lib format file using
Conformal Logic Equivalence Checker.

Understanding the Flow

1. Invoke LEC by using the following command:

lec -xl -nogui -64

2. Read library in liberty (.lib) format by using the following command:

read library <.lib file> –liberty –both

3. Write out the verilog file by using the following command:

write library <file name*> -verilog
*file name can be any name with extension.v.

© 2017 Cadence Design Systems, Inc. All rights reserved. 65

Creating a .v File

Shown below is an example dofile to generate “.v” from “.lib.”

1. Set the log file and read library in .lib format.

set log file lib_v.log -replace

read library ../lib/slow_vdd1v0_basicCells.lib -liberty
2. Write out library in .v format.

write library slow_vdd1v0_basicCells.v -verilog -replace

3. Exit the software:

exit

© 2017 Cadence Design Systems, Inc. All rights reserved. 66

Module 6 : The Implementation Stage

Lab 6-1: Running the Basic Implementation Flow

Objective: In this lab, you run the implementation flow including floor
planning, placement, power planning, and routing.
You will use Innovus™ Implementation System to implement the floorplanning,
placement, routing etc. for this design. At the end you will also verify your results
before handing-off for signoff.

This lab uses the following software release:

 INNOVUS162

Importing the Design

In this section, you import a gate-level netlist and libraries into the Innovus
Implementation System.

1. Change to the working directory where you will run floor-planning by

entering:
cd physical_design

2. Start the Innovus Implementation System by entering:

innovus

Note: Do not use the window where you started the software for any
windowing or UNIX operations, except to communicate with the tool.

© 2017 Cadence Design Systems, Inc. All rights reserved. 67

 3. To import a gate-level netlist, timing constraints, and libraries, choose
File ‒ Import Design.

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 The Design Import form appears.

4. In a different xterm window than where you brought up the tool, view
the counter.globals file. Notice the design and library files that are
specified.

© 2017 Cadence Design Systems, Inc. All rights reserved. 69

 5. Next, view the counter.view file.
This file specifies the files for timing analysis and extraction.

6. Click the Load button in the Design Import form, the Load Global Variables
window will appear.

7. Select the counter.globals file. Click Open.

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 The Design Import form will be populated by the parameters specified in the
counter.globals file.

© 2017 Cadence Design Systems, Inc. All rights reserved. 71

 When you load the file, it fills in the fields in the Design Import window.
The technology files and the ./counter.view file for the labs are displayed.
The counter.view file contains pointers to the timing library, LEF and the
constraints files.

8. To load the design and libraries, in the Design Import window, click OK.
Here is a brief description of the fields in the Design Import window.

Field Description

Verilog files Contains the names of gate-level Verilog

netlist files.

LEF files Library of components and physical data

for the components in LEF format. Also
contains routing layers and DRC rules.

MMMC View Definition file, Contains pointers to timing libraries,

counter.view technology files for extraction, and SDC
constraints files.

Viewing the Timing Setup and Design Import Results

In this section, you learn how to view the MMMC settings, details about the objects
on the screen, and how to view and interpret what you see in the design window.

1. Select Timing ‒ MMMC Browser.

The MMMC Browser is a useful tool to debug the view file. Often, the view
file is created manually and is therefore prone to errors.
2. Expand the parameters under Analysis View List and MMMC Objects.

© 2017 Cadence Design Systems, Inc. All rights reserved. 72

 Notice that the settings match the ones in the counter.view file.

3. Close the MMMC browser.

4. To enlarge the window, drag the corner of the window until you can see
all the modules in your design, as well as all the Innovus menus.

5. Select the Floorplan view by clicking the Floorplan view icon .

6. Fit the design to the window by pressing the f key.

© 2017 Cadence Design Systems, Inc. All rights reserved. 73

 7. Zoom out by pressing Shift-Z or by clicking the Zoom Out icon .

8. Expand the design window to display all the available pull-down menus.

9. To view more of the objects, click the Zoom Out icon or press Shift-
Z.

10. Move your cursor over the icons and notice that their functions are
displayed in text boxes, as shown here.

© 2017 Cadence Design Systems, Inc. All rights reserved. 74

 11. To zoom to a particular area, press and drag the right mouse button over
a rectangular area.
The window zooms to that area.

Viewing the Design Hierarchy

To view the hierarchical design that you imported, choose Tools ‒ Design Browser.

12. To expand the modules, click the plus sign (+) next to the categories of design
objects.

To view the I/O terminals, click the Terms plus sign (+).

13. When you are finished viewing the hierarchy, close the Design Browser
window.

© 2017 Cadence Design Systems, Inc. All rights reserved. 75

Floorplanning the Design

In this section, you create a floorplan. You become familiar with the floorplanning
forms and icons.

14. Choose Floorplan – Specify Floorplan.

The Specify Floorplan form appears.

a. For aspect ratio, enter 1.

b. Select Core to Die Boundary.

c. Enter 2.5 for Core to Left, Core to Right, Core to Top and Core to
Bottom values.
To display more information about the options, on the Specify Floorplan
form, click Help.

© 2017 Cadence Design Systems, Inc. All rights reserved. 76

 d. To initialize the floorplan, click OK.

The floorplan you will see should look like the above screenshot.

15. To measure the distance between the core area and the I/O boundary,
click the Ruler icon or press k.

16. To delete the ruler, click the Clear All ruler icon or press Shift+K.

17. To deselect ruler mode, click the Select By Box icon or press a.

© 2017 Cadence Design Systems, Inc. All rights reserved. 77

Power Planning

In this section, you create a power plan.

1. Choose Power-Power Planning ‒ Add Ring.

The Add Rings form is displayed. There are 11 metal layers available for
routing in the horizontal and vertical directions and you will be selecting
some of them for creating rings in subsequent steps.

a. To select the VDD and VSS nets, click the icon in the Net(s) field.
The Net Selection form is displayed.

b. In the Possible Nets pane, press Shift and VDD and VSS.

c. Click Add.
The selected nets appear in the Chosen Nets pane.

d. Click OK.

© 2017 Cadence Design Systems, Inc. All rights reserved. 78

 e. Make sure that the Net(s) field contains VDD and VSS.

f. Click Core ring(s) contouring.

g. Select Around core boundary.

h. In the Ring Configuration field, make sure that METAL11 H layer is

selected for Top and Bottom.

i. Use METAL10 V as the layer for Left and Right.

j. For Width, change the default value to 0.7.

k. For Spacing, change the default value to 0.2

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 l. For Offset, change the default value to 0.5

m. To generate the power rings, click Apply.

Notice that the power rings are created.

2. Choose Power-Power Planning ‒ Add Stripe. The Add Stripes form

appears.

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 n. Make sure that the Net(s) field contains VDD and VSS.

o. In the cyclic field, select Metal10.

p. Set width and spacing to 0.22 and 0.2 respectively.

q. Select Vertical, if it is not already selected.

r. Set Set-to-set distance to 5.

s. Select Relative from core or selected area.

t. Set Start to 1.

u. Set Stop to 0.

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 v. Click OK.

Notice the power stripes and the vias connecting the rings to the
stripes are created.

w. Save the floorplan by selecting File – Save – Floorplan.

x. Specify counter.fp for the File Name.

© 2017 Cadence Design Systems, Inc. All rights reserved. 82

Creating Power Rails with Special Route

1. Choose Route ‒ Special Route.

The SRoute form appears.

a. To populate the field with VDD and VSS, click the icon next to the
Net(s) field.

b. Click Add to add the nets to the Chosen Nets field and click OK.

c. Deselect all options except Follow Pins.

d. Click OK.

© 2017 Cadence Design Systems, Inc. All rights reserved. 83

 2. In the Physical view, zoom in to the follow pin routes.

Notice that the power routes have been connected to the power planned
targets with relevant Vias.

© 2017 Cadence Design Systems, Inc. All rights reserved. 84

Running Placement Optimization

1. Load the scan DEF file by running the following command:

defIn counter.scandef

2. Set the scan reordering mode by the running the command:

setScanReorderMode –compLogic true

3. Set the place mode to move unplaced I/O pins, based on the placement
of connected instances by running command:
setPlaceMode –place_global_place_io_pins true

4. Run placement optimization by running the following command:

place_opt_design
The command takes a few minutes to finish. After placement, post-
placement setup optimization is run if the slack is negative.
During the optimization stage of the command, the following operations may
be performed to close timing:
 Adding buffers
 Resizing gates
 Reconstructing the circuit
 Remapping the logic
 Swapping the pins
 Deleting the buffers
 Moving the instances
Notice that the status of the design on the lower-right corner has changed.
After the placement run completes, what is the status of the design
that is displayed?
Answer: _____________________
This field is a convenient way to check where you are in the flow. The
timing summary is output to the log file which contains the Total
Negative Slack (TNS) and the Worst Negative Slack (WNS).

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 What is the Worst Negative Slack (WNS) at this stage?
Answer:
Is it a positive or a negative number?

5. To display the Physical view, click the Physical View button.

You will see the standard cell placements.

Notice that in addition to cell placement, Trial Route has been run on the
design.

6. To save the design, enter:

saveDesign placeOpt

After running placement or pre-CTS optimization, you run clock tree synthesis with
constraints on what buffers to use and the type of clock routing to implement.

© 2017 Cadence Design Systems, Inc. All rights reserved. 86

Running Clock Tree Synthesis

1. To see all possible options for the clock tree synthesis command, run the
following:
set_ccopt_property * -help

2. Generate the remaining clock tree spec file constraints from the .sdc file
by running the command:
create_ccopt_clock_tree_spec

3. Create a clock tree by running the command:

ccopt_design

If you see error message about the clock net being not completely routed.
Ignore this error as later on, when you run the NanoRoute tool for the
remaining nets, this error will be fixed.

4. View the .log file for this session.

Were there any timing violations after this step?
Answer: __________________________

5. Save your design as postCTSopt by entering:

saveDesign postCTSopt

© 2017 Cadence Design Systems, Inc. All rights reserved. 87

Routing the Nets

1. To route the nets, choose Route – NanoRoute – Route.

The NanoRoute™ form is displayed.

a. Make sure that Timing Driven is selected.

b. Select SI Driven.

c. Click OK in the NanoRoute form.

© 2017 Cadence Design Systems, Inc. All rights reserved. 88

Extraction and Timing Analysis

1. Run RC extraction on the routed design by selecting Timing – Extract RC.

2. Unselect all options except Save SPEF to.

3. Click OK.

4. Set the timing analysis mode by running the following commands:

setAnalysisMode –analysisType onChipVariation

5. Run setup and hold timing analysis by running the following commands:
timeDesign –postRoute
Are there any setup violations?
Answer: _________________

© 2017 Cadence Design Systems, Inc. All rights reserved. 89

Running Physical Verification

In this section, you run physical verification commands in the Innovus system.

Verify Geometry

Choose Verify – Verify Geometry

The Verify Geometry form is displayed.

Are there any violations?
Answer:

Verify Connectivity

Choose Verify – Verify Connectivity.

The Verify Connectivity form is displayed.

Are there any violations?
Answer:

Running Power Analysis

1. To display the power analysis setup form, choose Power – Power Analysis
– Setup.

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 a. In the Analysis Method, select Static.

b. Select Analysis View.

c. Select wc.

d. Select max for the corner.

e. Click OK.

2. Source the power.tcl file which contains the rules for global net power
connections by entering the following:
source power.tcl

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 3. To run power analysis, select Power – Power Analysis – Run.

4. Leaving all defaults as is, enter ./run1 in the Results Directory field.

5. Click OK.
This will run power analysis and generate power consumption values.

6. From the log file for this session, determine the following:
What is the total internal power?
Answer:
What is the total switching power?
Answer:
What is the leakage power?
Answer:
What is the total power consumed?
Answer:

© 2017 Cadence Design Systems, Inc. All rights reserved. 92

 7. To run rail analysis, first, select Power – Rail Analysis – Setup Rail Analysis.
This will bring up the Set Rail Analysis Mode form.

a. Select Early for Analysis Stage.

b. Select Analysis View.

c. Select wc for worst case.

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 d. Select Extraction Tech File and enter ../QRC_Tech/gpdk045.tch. or

Browse for Extraction tech file, click button, browse for QRC_Tech
folder using button and choose Filters field with All files(*), select
gpdk045.tch and click Add and close the window.

e. Click OK.

8. Select Power– Rail Analysis – Run Rail Analysis.

This will bring up the Run Rail Analysis form.

In the Run Rail Analysis form:

9. Select Net Based.

10. Enter VDD for the Power Net.

11. Delete VSS if it is in the Ground Net field.

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 12. Enter 0.9 in the Voltage(s) field.

13. Enter 0.81 in the Threshold field.

14. Make sure that Current Files is selected for Power Data.

15. For Power/Current Files, enter run1/static_VDD.ptiavg.

16. To create an XY file for the power sources, select XY File.

17. Click Create.

This will bring up the Edit Pad Location form.

18. In the Edit Pad Location form:

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 a. Enter VDD for the Net Name.

b. Make sure Auto Fetch is selected.

c. At the bottom of the Edit Pad Location form, click Get Coord.

d. The cursor will change into a crosshair.

e. Click on a location in the main Innovus design window.

f. Go back to the Edit Pad Location form.

g. Make sure to change the Layer to Metal10 (By default Metal11 is

selected).

h. Click Add.
Notice that the Pad Location List field is populated with the coordinate
as VDDvsrc1.

i. Add another location for a VDD source.

j. Click Save.

k. Enter Counter.pp for the filename and click Save.

l. Click Cancel to close the Edit Pad Location form.

19. In the Run Rail Analysis form, specify the name of the XY file Counter.pp
you just created in the File field.

20. Enter VDD for the Net Name field.

21. Click Add so that the pane under the fields are populated with the type of
file, net name and file name.

22. Enter./run1 for the Results Directory.

23. Click OK to run rail analysis.

© 2017 Cadence Design Systems, Inc. All rights reserved. 96

Viewing Power Analysis Results

1. To display the results of rail analysis, select Power – Report – Power & Rail
Result.

Notice that the pane on the left of the design window contains options to
run analysis.

2. Select Rail.

3. Select DB Setup.

This will bring up the Power and Rail Setup form. In this form:

a. Navigate and populate the Power Database field with run1/power.db.

b. In the Rail Database field, populate the field with the path to the
directory run1/VDD_25C_avg_* where * indicates a number which
increments every time you rerun the step. For example, this directory
name might be run/VDD_25C_avg_1.

© 2017 Cadence Design Systems, Inc. All rights reserved. 97

 c. Click OK.

4. Select ir – IR Drop from the pick list.

Notice that the Innovus design window display shows the color-coded
voltage ranges that match the range.
Are there any red areas displayed in the main Innovus window?
Answer: _________________________________________

5. Enter the following to save the Innovus database:

saveDesign counter.inn -libs

© 2017 Cadence Design Systems, Inc. All rights reserved. 98

Generating a Stream File

1. Select File-Save-GDS/OASIS.

This will bring up the GDS/OASIS Export form.

a. Enter counter in the Output File field.

b. Click OK.

2. Close the Innovus software.

© 2017 Cadence Design Systems, Inc. All rights reserved. 99

Module 7: Running Gate Level Simulations on a Simple Counter Design
Lab 7.1: Running Gate Level Simulations on a Simple Counter Design
Objective: To run gate level simulations on a simple counter Design
using the Xcelium Simulator tool.
This lab uses the following software:

 XCELIUM1704

What Is Gate Level Simulation?

GLS is a step in the design flow to ensure that the design meets the functionality
after Synthesis or after placement and routing activities. We need a
synthesized/post-routed netlist, a testbench and an SDF (Standard Delay Format)
file. SDF will have all the delay information for the cell and the wire.

Here we will make use of the same test-bench that we used for the functional
simulation with some changes in the testbench. That is, we have to use the
$sdf_annotate system task to call the sdf file inside the testbench.

We will perform gate level simulation inside the “gate_level_simulation” directory

under counter_database.

Files present inside the gate_level_simulation directory are:

 Counter_netlist.v – Netlist after synthesis with DFT (Netlist after

physical design also be used)

 Counter_test.v – Testbench with $sdf_annotate system task to input

SDF file.

 slow_vdd1v0_basicCells.v – Simulation library in .v format

 delays.sdf – SDF file generated during synthesis (SDF can also be

generated after physical design.)

© 2017 Cadence Design Systems, Inc. All rights reserved. 100

SDF Annotation

Modify the testbench to include SDF configuration as shown below. In

counter_test.v available inside the gate_level_simulation directory, SDF
configuration system task is already included.

$sdf_annotate (“sdf_file”
{, module_instance}
{, “config_file”}
{, “log_file”}
{, “mtm_spec”}
{, “scale_factors”}
{, “scale_type”});
Note: We must specify the arguments to the $sdf_annotate system
task in the order shown in the syntax. We can skip an argument
specification, but the number of comma separators must
maintain the argument sequence. For example, to specify only
the first and last arguments, use the following syntax:
$sdf_annotate (“sdf_file”,,,,,, “scale_type”);

© 2017 Cadence Design Systems, Inc. All rights reserved. 101

$sdf_annotate arguments:

 “sdf_file” The full or relative path of the SDF file. This argument is
required and must be in quotation marks. We can specify the file name
with the +sdf_file plus option on the command line.

 module_instance (optional): Specifies the scope in which the

annotation takes place. The names in the SDF file are relative paths to
the module_instance with respect to the entire Verilog HDL
description. The SDF Annotator uses the hierarchy level of the
specified instance for running the annotation. Array indexes
(module_instance [index]) are permitted in the scope. If we do not
specify module_instance, the SDF Annotator uses the module
containing the call to the $sdf_annotate system task as the
module_instance for annotation.

 “config_file” (optional): The name of the configuration file, specified

in quotation marks, that the SDF Annotator reads before annotating
begins. If we do not specify config_file, the SDF Annotator uses the
default settings.

 “log_file” (optional): The name of the log file specified in quotation

marks that the SDF Annotator generates during annotation. Also, you
must specify the +sdf_verbose plus option on the command line to
generate a log file. If we do not specify a log file name, but specify the
+sdf_verbose plus option, the SDF Annotator creates a default log file
called sdf.log.

 “mtm_spec” (optional): One of the following keywords, specified in

quotation marks, indicating the delay values that are annotated to the
Verilog family tool.

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 Keyword Description

MAXIMUM Annotates the maximum delay value

MINIMUM Annotates the minimum delay value

TOOL_CONTROL (default) Annotates the delay value that is

determined by the Verilog-XL and
Verifault-XL command-line options
(+mindelays, +typdelays or +maxdelays);
minimum, typical and maximum values
are always annotated to Veritime. If
none of the TOOL_CONTROL command
line options is specified, then the default
keyword is TYPICAL

TYPICAL Annotates the typical delay value

 “scale_factors” optional: The minimum, typical, and maximum timing

data values, specified in quotation marks, expressed as a set of three
positive real number multipliers (min_mult:typ_mult:max_mult). For
example, 1.6:1.4:1.2. If we do not specify values, the default values are
1.0:1.0:1.0 for minimum, typical, and maximum values. The SDF
Annotator uses these values to scale the minimum, typical, and
maximum timing data from the SDF file before they are annotated to
the Verilog family tool.

 “scale_type” (optional): One of the following keywords, specified in

quotation marks, to scale the timing specifications in SDF, which are
annotated to the Verilog family tool.

Keyword Description

FROM_MAXIMUM Scales from the maximum timing

specification

FROM_MINIMUM Scales from the minimum timing

© 2017 Cadence Design Systems, Inc. All rights reserved. 103

 specification

FROM_MTM Scales from the minimum, typical

(default) and maximum timing
specifications. This is the default

FROM_TYPICAL Scales from the typical timing

specification

Simulating the Netlist with the xrun Command

1. Change to the working directory.

cd gate_level_simulation

2. Execute the following xrun command:

xrun -timescale 1ns/10ps counter_netlist.v counter_test.v -v
slow_vdd1v0_basicCells.v -access +rwc -define SDF_TEST -mess –gui
 -timescale: Used to mention the time unit and time precision
 -access: Passed to the elaborator to provide read access to
simulation objects
 -gui: Used to invoke the xrun in gui mode
 -mess: Used to display all the messages in detail
 -define: Used to provide SDF definition present in the testbench
 -v: Used to provide library in “.v” format

© 2017 Cadence Design Systems, Inc. All rights reserved. 104

© 2017 Cadence Design Systems, Inc. All rights reserved. 105
 2. SimVision™ starts,
with Console and
Design Browser
windows opening as

3. In the console window,

Force DFT signals such as
SE, scan_in and scan_out

4. Click on counter_test
in the design browser
window, and then we will
get all the signals in the

6. Click on run
5. Select all the above signals
button in the
and send those selected objects
console window.
to waveform window by clicking

© 2017 Cadence Design Systems, Inc. All rights reserved. 106

 7. Snapshot showing the
counter waveform results
with back annotated

8. In the Design Browser window,

go to the hierarchy counter_test-
>counter1->Library cells (22) ->
g705 which shows 2 signals A and
Y. Select these two signals and pull

9. In the waveform window if

you look at the timing
between these 2 signals A &
Y, then you will see that the
delay from AY signals is
0.04ns, the back annotated
delay because of sdf

© 2017 Cadence Design Systems, Inc. All rights reserved. 107

Module 8: Timing Signoff Analysis
Lab 8.1: Run Signoff Timing Analysis
Objective: In this lab, you will run timing analysis and fix a couple of
timing violations.
Tempus™ Timing Signoff Solution is a timing sign-off tool which is used to verify
that the design meets your timing goals. In this lab, you will first rerun the previous
session of Place & Route and continue it with running Tempus timing analysis inside
of Innovus™.

This lab uses the following software:

 INV162 and

 SSV162

You will then run Tempus in the Timing Signoff mode.

 You can start the Tempus tool using the command tempus.

 You can start the Tempus TSO software using the command tempus -
tso.

The following are from the Physical design lab and will serve as inputs to Tempus:

 counter_netlist.v – Gate-level netlist output after synthesis

 counter_sdc.sdc – Constraint file generated during synthesis

 counter.view – The implementation view definitions are listed in this

MMMC file

 gsclib045_tech.lef, gsclib045_macro.lef – LEF file used in physical

design

 slow_vdd1v0_basicCells.lib and fast_vdd1v0_basicCells.lib – Timing

libraries

© 2017 Cadence Design Systems, Inc. All rights reserved. 108

There are also a few additional files in the directory that are not listed above.

Running Timing Analysis and Debugging in the Innovus Session

Innovus is a cockpit for a lot of implementation and verification tools front-to-back.

In this section, you will be running Tempus style timing analysis inside of Innovus.

1. Let’s rerun the previous session of Place & Route inside the STA
directory instead of using a saved session.
LINUX# cd STA
LINUX# innovus –files runPnR.tcl
At the end of this session, the design is routed and timing analyzed.

2. Run the following commands:

To check the post route timing and optimization, need to set the
AOCV mode through setAnalysisMode.

setAnalysisMode -analysisType onChipVariation -aocv true

timeDesign –postRoute
timeDesign –postRoute –hold
How many setup violations?
Answer: ________
How many hold violations?
Answer: ________
There are lot of hold violations. It looks like we have not run hold
optimization.

3. Run optimization with the hold option.

optDesign –postRoute –hold
At this point, you should have fewer violations.

© 2017 Cadence Design Systems, Inc. All rights reserved. 109

 4. If the graphical interface is not open, start it using the following
command:
win

5. Run timing analysis using the Timing – Debug Timing menu.

a. Select hold in the Check Type field.

b. Click OK.
The Timing Debug window opens.

c. Right-click on the path #1 in the Path List and select Show Timing
Path Analyzer.
You will see the Timing Path Analyzer window.

© 2017 Cadence Design Systems, Inc. All rights reserved. 110

 From the Timing Path Analyzer, if you want to debug violating
paths, you can right click on any of the signals and you will get
additional options like interactive ECO etc.

6. Save the design including the SPEF, DEF and the libraries.
saveDesign -rc -def -relativePath postRoute

7. Keep this session open if you would like for debugging purposes. You
can close it later.

Running Independent Timing Analysis in Tempus

1. Start Tempus independently.

tempus

2. Load the Innovus database into Tempus using the following command:
read_design –physical_data postRoute.dat/ counter
This loads the entire design along with the physical layout.
Open the Layout tab (click the sign to see other available tabs) to
confirm that the same layout from Innovus is also shown here in Tempus.
 You can also load each individual corresponding files in the Setup
menu.

© 2017 Cadence Design Systems, Inc. All rights reserved. 111

 Browse for the libraries (slow_vdd1v0_basicCells.lib and
fast_vdd1v0_basicCells.lib from lib directory), netlist (counter.v),
constraints (counter_sdc.sdc), SPEF (counter.spef), physical design
(counter.def) etc.

Once the design is loaded successfully, then generate the following reports.

3. Check the analysis coverage using the command:

report_analysis_coverage
It gives out these two Errors :
ERROR: (TCLCMD-1208): AOCV Analysis mode has been selected via
setAnalysisMode -aocv. Since no AOCV libraries have been read, this
analysis cnanot be performed. The analysis will continue without AOCV
based derating applied.AOCV libraries can be loaded via the .conf file or
by including them in an MMMC library set.
To avoid this , set like:
setAnalysisMode -analysisType onChipVariation -aocv false
ERROR: (IMPESI-2017): There is no coupling capacitance found in the
design. Use set_delay_cal_mode -siAware false to perform base delay
analysis. SI analysis requires the SPEF to contain coupling capacitance. To
perform SI analysis, load a SPEF with coupling capacitance and re-run.
To avoid this , set as :

set_delay_cal_mode -SIAware false

4. View the list of all constraint violations using the command:

report_constraint -all_violators

5. Report the worst slack time for setup and hold respectively, using the
commands:
report_timing –late
report_timing –early

© 2017 Cadence Design Systems, Inc. All rights reserved. 112

 6. Generate timing histograms using the following commands:
report_timing –early –max_paths 100 –machine_readable > early.mtarpt
load_timing_debug_report early.mtarpt

7. Open the Analysis tab (click the sign to see other available tabs).
After the timing analysis is done, you can see the histogram for the hold
analysis.

a. Browse through the Path list with Startpoint Pin as SE, right click on
the path and select Show Timing Path Analyzer.
You will see the Timing Path Analyzer window.

From the Timing Path Analyzer, if you want to debug violating paths, you can right
click on any of the signals and you will get additional options like interactive ECO
etc.

8. In the Timing Path Analyzer window, select the SE pin and right-click
and select Interactive ECO/WhatIf – Add Repeater.

© 2017 Cadence Design Systems, Inc. All rights reserved. 113

 The Interactive ECO window opens, which will allow you to add repeaters.

9. In the Interactive ECO window:

a. Click get selected to populate the net information or just enter SE.

b. In the New Cell field, select BUFX2.

c. Click Eval.

d. View the messages by the tempus> prompt.

© 2017 Cadence Design Systems, Inc. All rights reserved. 114

 There is no change in the slack (it is negative), or the change is so
minimal that it cannot be observed. The result should be a positive
slack for you to Apply the repeater addition.

10. Click Apply.

Because the slack improvement is not clearly observable, let’s just see
what happens.

11. Rerun timing analysis.

Why is that no matter what buffer we use, the timing of the path
has no impact?
Answer: _____________
This Interactive ECO process typically has direct observable impact on
setup, but not on hold analysis and therefore you can stop this process
and figure out a better way to fix hold.
For setup fixing, this can be continued until all the ECOs are complete and
no more timing violations are left in the design. But, even that can get
tedious.
Because there are a lot of violations and there is no significant impact
from the ECO to the timing, this Interactive ECO is not the right way.
Tempus TSO provides a faster and better way to fix setup and hold
violations. But, that is for another time.
Therefore, let’s try and find a better way.

12. Compare the two SDC files provided.

diff counter_sdc.sdc counter_postCTS.sdc
What do you think is the problem now?
Answer: ____________
In the tempus.log file, this sdc file gets read:

<work_area>/postRoute.dat/mmmc/modes/sdc_cons/sdc_cons.sdc

© 2017 Cadence Design Systems, Inc. All rights reserved. 115

It has set SE and rst as ideal_networks , thus 0 slew is being propagated

Rerun Innovus to Fix All Violations

Although the clock has automatically been set to propagated, the problem is
caused because of the SE and Reset signals being left as ideal networks. Therefore,
it is important to verify your constraints after each stage.

1. Let’s rerun the Place & Route session using the runPnR2.tcl file.
LINUX# cd STA
LINUX# innovus –files runPnR2.tcl
This runPnR2.tcl uses the counter2.view file, which in turn uses the fixed
counter_postCTS.sdc file.
At the end of this session, the design is routed, optimized for setup and
hold, and timing analyzed.

2. Run the following commands:

setAnalysisMode -analysisType onChipVariation -aocv false
timeDesign –postRoute –hold
How many setup violations?
Answer: ________
How many hold violations?
Answer: ________

© 2017 Cadence Design Systems, Inc. All rights reserved. 116

 3. In the Timing Path Analyzer, now it shows non-zero delay for SE and
rst nets.

4. Now, you can add buffers and click Apply.

At the prompt, this message displays:

© 2017 Cadence Design Systems, Inc. All rights reserved. 117

 5. Re-run the timing report and compare the WNS.
Earlier:

Later:

6. Go on to fix the violations similarly.

Summary

1. You can run timing analysis from within Innovus. You can also evaluate
and create timing-fixing ECOs interactively from within Tempus.

2. You can run independent timing analysis from within Tempus.

Independent analysis frees up Innovus to do other things.

© 2017 Cadence Design Systems, Inc. All rights reserved. 118