SVCE TIRUPATI

COURSE MATERIAL

SUBJECT VLSI DESIGN (EC20APC603)

UNIT 1

COURSE B.TECH

DEPARTMENT ECE

SEMESTER 32

PREPARED BY
Dr. G. Sujatha
(Faculty Name/s) Professor

Version V-2

PREPARED / REVISED DATE 16-03-2023

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TABLE OF CONENTS – UNIT 1

S. NO CONTENTS PAGE NO.
1 COURSE OBJECTIVES 3
2 PREREQUISITES 3
3 SYLLABUS 4
4 COURSE OUTCOMES 4
5 CO - PO/PSO MAPPING 5
6 LESSON PLAN 5
7 ACTIVITY BASED LEARNING 6
8 LECTURE NOTES 6
2.1 THE PASS TRANSISTOR 6
2.2 NMOS INVERTER 7
2.3 PULL UP-PULL DOWN RATIO OF DIFFERENT CASES 9
2.4 THE CMOS INVERTER AND LATCH UP IN CMOS CIRCUITS 16
2.5 LATCH UP IN CMOS CIRCUITS 19
2.6 MOS LAYERS 20
2.7 DESIGN RULES AND LAYOUT 20
2.8 LAMBDA-BASED DESIGN RULES,CONTACT CUTS 24
2.9 2µm DOUBLE METAL,DOUBLE POLY CMOS/BICMOS RULES AND 24
LAYOUT DIAGRAMS
2.10 STICK DIAGRAMS -NMOS AND CMOS DESIGN STYLES 26
9 PRACTICE QUIZ 33

10 ASSIGNMENTS 35

11 PART A QUESTIONS & ANSWERS (2 MARKS QUESTIONS) 36

12 PART B QUESTIONS 38

13 SUPPORTIVE ONLINE CERTIFICATION COURSES 39

14 REAL TIME APPLICATIONS 39

15 CONTENTS BEYOND THE SYLLABUS 39

16 PRESCRIBED TEXT BOOKS & REFERENCE BOOKS 39

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17 MINI PROJECT SUGGESTION 40

Course Objectives

The objectives of this course is to

1. To understand Fabrication process of MOS devices.

2. To Analyze the Ids Versus Vds Relationship.

3. Understand lambda based design rules.

4. To design circuits using stick diagrams and layouts.

2. Prerequisites

Students should have knowledge on

1. Digital Logic Design

2. Electronic Devices & Circuits

3. Fundamentals of electronic circuits

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3. Syllabus

UNIT I

The pass transistor, nMOS Inverter, Pull-up to Pull down Ratio of different cases,
The CMOS Inverter, Latch-up in CMOS circuits, MOS Layers, Stick Diagrams-Nmos
and CMOS design styles, Design Rules and Layout-Lambda –based design rules,
2µm Double Metal , Double poly, CMOS/BiCMOS rules and Layout Diagrams.

4. Course outcomes

The outcome of this course is to

1. Understand the static and dynamic behaviour of MOSFETs (Metal Oxide

Semiconductor Field Effect Transistors) and the secondary effects of the MOS
transistor model.

2. Design digital systems using MOS circuits (Static and Switching characteristics
of inverters)

3. Implement Layout, Stick diagrams, Fabrication steps.

4. Approach the concept behind ASIC (Application Specific Integrated Circuits)

design and the different implementation approaches used in industry Explain
the principles of design of Jigs and fixtures, Types of clamping & work holding
devices and latest UBMTS.

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5. CO-PO / PSO Mapping

COs/
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PSO1 PSO2
POs

2 3
CO1 3

CO2 3 3 3
3
CO3 3
3 3 3
C04 3

6. Lesson Plan
Lecture No. Weeks Topics to be covered References

1 The pass trasistor

T1, T2

2 NMOS inverter
T1, R1

3 Pull up to pull down ratio of different cases T1, R1

4 The CMOS Inverter and Latch up in CMOS circuits T1, R1

5 3 Latch up in CMOS Circuits T1, R1

6 Mos layers T1, R1

7 Design rules and layout T1, R1

8 Lambda-based design rules,contact cuts T1,T2

9 2µm DOUBLE METAL,DOUBLE POLY T1,T2

CMOS/BICMOS RULES AND LAYOUT DIAGRAMS
10 Stick diagrams -nmos and cmos design styles T1, R1

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 7. Activity Based Learning

1. Analyze various methods in fabrication.

2. Understand the concepts of MOS Transistors
3. Design stick diagrams and layouts of Mos Circuits

8. Lecture Notes

2.1 PASS TRANSISTOR:

The nMOS transistors pass '0's well but ‘1’s poorly. Figure 1.19 (a) shows an
nMOS transistor with the gate and drain tied to VDD. Imagine that the
source is initially at Vs = 0. Vgs > Vtn, so the transistor is ON and current
flows. If the voltage on the source rises to Vs = VDD - Vtn, Vgs falls to Vtn
and the transistor cuts itself OFF. Therefore, nMOS transistors attempting
to pass a '1' never pull the source above VDD - Vtn. This loss is sometimes
called a threshold drop. Moreover, when the source of the nMOS
transistor rises, Vsb becomes nonzero and this nonzero source to body
potential introduces the body effect that increases the threshold
voltage. Similarly, pMOS transistors pass ‘1`s well but ‘0’s poorly. If the
pMOS source drops belo w |Vtp|, the transistor cuts off. Hence, pMOS
transistors only pull down to within a threshold above GND, as shown in
Figure 1.19(b). As the source can rise to within a threshold voltage of the
gate, the output of several transistors in series is no more degraded than
that of a single transistor Figure 1.19c. However, if a degraded output
drives the gate of another transistor, the second transistor can produce
an even further degraded output Figure 1.19d.

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 Figure 1.19: Pass transistor

2.2 nMOS INVERTER

An inverter circuit is a very important circuit for producing a complete

range of logic circuits. This is needed for restoring logic levels, for Nand
and Nor gates, and for sequential and memory circuits of various forms.
A simple inverter circuit can be constructed using a transistor with source
connected to ground and a load resistor of connected from the drain to
the positive supply rail VDD. The output is taken from the drain and the
input applied between gate and ground. But, during the fabrication
resistors are not conveniently produced on the silicon substrate and
even small values of resistors occupy excessively large areas. Hence
some other form of load resistance is used. A more convenient way to
solve this problem is to use a depletion mode transistor as the load, as
shown in Figure. 1.17.

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 Figure 1.17: nMOS inverter

The salient features of the n-MOS inverter are

 For the depletion mode transistor the gate is connected to the

source so it is always on.
 In this configuration the depletion mode device is called the pull
up (P.U) and the enhancement mode device the pull down (P.D)
transistor.
 With no current drawn from the output the currents Ids for both
transistors must be equal.

Fig 1.18: nMOS Inverter transfer characteristic

The transfer characteristic is drawn by taking Vds on x-axis and Ids on Y-

axis for both enhancement and depletion mode transistors. So, to obtain
the inverter transfer characteristic for Vgs = 0 depletion mode

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characteristic curve is superimposed on the family of curves for the

enhancement mode device and from the graph it can be seen that ,
maximum voltage across the enhancement mode device corresponds
to minimum voltage across the depletion mode transistor. From the
graph it is clear that as Vin(=Vgs p.d. transistor) exceeds the Pulldown
threshold voltage current begins to flow. The output voltage Vout thus
decreases and the subsequent increases in Vin will cause the Pull down
transistor to come out of saturation and become resistive.

2.3 Pull up to pull down ratio of different cases:

2.3.1 DETERMINATION OF PULL-UP TO PULL –DOWN RATIO (ZP.U} ZP. D.) FOR AN
NMOS INVERTER DRIVEN BY ANOTHER NMOS INVERTER:

Let us consider the arrangement shown in Fig. (a). in which an inverter

is driven from the output of another similar inverter. Consider the
depletion mode transistor for which Vgs = 0 under all conditions, and
also assume that in order to cascade inverters without degradation the
condition

For equal margins around the inverter threshold, we set Vinv = 0.5VDD ·
At this point both transistors are in saturation and we can write that

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where Wp.d, Lp.d , Wp.u. and Lp.u are the widths and lengths of
the pull-down and pull-up transistors respectively.

Substituting these values in the above equation, we get This is the ratio
for pull-up to pull down ratio for an inverter directly driven by another
inverter.

2.3.2 PULL -UP TO PULL-DOWN RATIO FOR AN NMOS INVERTER DRIVEN

THROUGH ONE OR MORE PASS TRANSISTORS:

Let us consider an arrangement in which the input to inverter 2 comes

from the output of inverter 1 but passes through one or more nMOS

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transistors as shown in Fig. below (These transistors are called pass

transistors).

Fig 1.20: Pull -Up to Pull-Down ratio for an nMOS Inverter

The connection of pass transistors in series will degrade the logic 1 level /
into inverter 2 so that the output will not be a proper logic 0 level. The
critical condition is , when point A is at 0 volts and B is thus at VDD but
the voltage into inverter2 at point C is now reduced from VDD by the
threshold voltage of the series pass transistor. With all pass transistor
gates connected to VDD there is a loss of Vtp, however many are
connected in series, since no static current flows through them and
there can be no voltage drop in the channels. Therefore, the input
voltage to inverter 2 is Vin2 = VDD - Vtd where Vtp = threshold voltage for a
pass transistor.
Let us consider the inverter 1 shown in Fig. (a) with input = VDD· If the
input is at VDD, then the Pull-down transistor T2 is conducting but with a
low voltage across it; therefore, it is in its resistive region represented by
R1 in below. Meanwhile, the pull up transistor T1 is in saturation and is
represented as a current source.

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 For the pull down transistor Since Vds is small, Vds/2 can be neglected in
the above expression.

Now, for depletion mode pull-up transistor in saturation with Vgs =0

The product I1R1 = Vout1 So,

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 Let us now consider the inverter 2 Fig. b.

When input = VDD - Vtd.

Hence,

If inverter 2 is to have the same output voltage under these conditions

then Vout1 =Vout2.
That is I 1R1=I 2R2,
therefore Considering the typical values

Therefore

From the above theory it is clear that, for an n-MOS transistor

 An inverter driven directly from the output of another should have a
Zp.u/ Zpd. ratio of ≥ 4/1.

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  An inverter driven through one or more pass transistors should have a
Zp.u./Zp.d ratio of ≥8/1

2.3.1 ALTERNATIVE FORMS OF PULL –UP

Generally the inverter circuit will have a depletion mode pull-up

transistor as its load. But there are also other configurations .Let us
consider four such arrangements.
i. Load resistance RL:

This arrangement consists of a load resistor as a pull-up as shown in the

diagram below. But it is not widely used because of the large space
requirements of resistors produced in a silicon substrate.

ii. nMOS depletion mode transistor pull-up: This arrangement consists of a

depletion mode transistor as pull-up. The arrangement and the transfer
characteristic are shown below. In this type of arrangement we observe

a) Dissipation is high, since rail to rail current flows when Vin = logical 1.

b) Switching of output from 1 to 0 begins when Vin exceeds Vt, of pull-

down device.

c) When switching the output from 1 to 0, the pull-up device is non-

saturated initially and this presents lower resistance through which to
charge capacitive loads.

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 iii. nMOS enhancement mode pull-up: This arrangement consists of a n-MOS
enhancement mode transistor as pull-up. The arrangement and the
transfer characteristic are shown below.

nMOS enhancement mode pull-up and transfer characteristic

The important features of this arrangement are

a) Dissipation is high since current flows when Vin =logical 1 (VGG is
returned to VDD).

b) Vout can never reach VDD (logical I) if VGG = VDD as is normally the
case.

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 c) VGG may be derived from a switching source, for example, one phase
of a clock, so that dissipation can be greatly reduced.

d) If VGG is higher than VDD then an extra supply rail is required.

iv. Complementary transistor pull-up (CMOS): This arrangement consists of

a CMOS arrangement as pull-up. The arrangement and the transfer
characteristic are shown below

The salient features of this arrangement are

a. No current flows either for logical 0 or for logical 1 inputs.

b. Full logical 1 and 0 levels are presented at the output.

c. For devices of similar dimensions the p-channel is slower than the n-

channel device.

2.4 CMOS Inverter

The inverter is the very important part of all digital designs. Once its
operation and properties are clearly understood, Complex structures like
NAND gates, adders, multipliers, and microprocessors can also be easily

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 done. The electrical behavior of these complex circuits can be almost
completely derived by extrapolating the results obtained for inverters. As
shown in the Figure 1.22 the CMOS transistor is designed using p-MOS
and n-MOS transistors.

Fig 1.21: CMOS Inverter circuit

In the inverter circuit, if the input is high .the lower n-MOS device closes
to discharge the capacitive load. Similarly, if the input is low, the top p-
MOS device is turned on to charge the capacitive load. At no time both
the devices are on, which prevents the DC current flowing from positive
power supply to ground. Qualitatively this circuit acts like the switching
circuit, since the p-channel transistor has exactly the opposite
characteristics of the n-channel transistor. In the transition region both
transistors are saturated and the circuit operates with a large voltage
gain. The C-MOS transfer characteristic is shown in Figure 1.21.

Fig 1.22: CMOS transfer characteristics.

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 Considering the static conditions first, it may be Seen that in region 1 for
which Vi,. = logic 0, we have the p-transistor fully turned on while the n-
transistor is fully turned off. Thus no current flows through the inverter and
the output is directly connected to VDD through the p-transistor. Hence
the output voltage is logic 1. In region 5, Vin = logic 1 and the n-transistor
is fully on while the p-transistor is fully off. So, no current flows and a logic
0 appears at the output.
In region 2 the input voltage has increased to a level which just
exceeds the threshold voltage of the n-transistor. The n-transistor
conducts and has a large voltage between source and drain; so it is in
saturation. The p-transistor is also conducting but with only a small
voltage across it, it operates in the unsaturated resistive region. A small
current now flows through the inverter from VDD to VSS. If we wish to
analyze the behavior in this region, we equate the p-device resistive
region current with the n-device saturation current and thus obtain the
voltage and current relationships.
Region 4 is similar to region 2 but with the roles of the p- and n-
transistors reversed. However, the current magnitudes in regions 2 and 4
are small and most of the energy consumed in switching from one state
to the other is due to the larger current which flows in region 3.
Region 3 is the region in which the inverter exhibits gain and in which
both transistors are in saturation. The currents in each device must be
the same, since the transistors are in series. So, we can write that

since both transistors are in saturation, they act as current sources so

that the equivalent circuit in this region is two current sources in series

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 between VDD and Vss with the output voltage coming from their
common point. The region is inherently unstable in consequence and
the changeover from one logic level to the other is rapid.

2.5 LATCH UP IN CMOS CIRCUITS

A latch-up is a type of short circuit which can occur in an integrated

circuit (IC). More specifically it is the inadvertent creation of a low-
impedance path between the power supply rails of a MOSFET circuit,
triggering a parasitic structure which disrupts proper functioning of the
part, possibly even leading to its destruction due to overcurrent.
A power cycle is required to correct this situation.

Fig 1.23: Latch up in CMOS circuits

BICMOS Inverters The latch-up does not have to happen between

the power rails - it can happen at any place where the required
parasitic structure exists. A common cause of latch-up is a positive or
negative voltage spike on an input or output pin of a digital chip that
exceeds the rail voltage by more than a diode drop. Another cause is
the supply voltage exceeding the absolute maximum rating, often from
a transient spike in the power supply. It leads to a breakdown of an
internal junction. This frequently happens in circuits which use multiple
supply voltages that do not come up in the required sequence on
power-up, leading to voltages on data lines exceeding the input rating
of parts that have not yet reached a nominal supply voltage. Latch-ups
can also be caused by an electrostatic discharge event.

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 2.6 MOS LAYERS
MOS circuits are formed on four basic layers:
 N-diffusion
 P-diffusion
 Poly silicon
 Metal
These layers are isolated by one another by thick or thin silicon dioxide
insulating layers. Thin oxide mask region includes n-diffusion / p-
diffusion and transistor channel.

2.7 DESIGN RULES AND LAYOUT

Design rules include width rules and spacing rules. Mead and Conway
developed a set of simplified scalable λ -based design rules, which are
valid for a range of fabrication technologies. In these rules, the
minimum feature size of a technology is characterized as 2 λ . All width
and spacing rules are specified in terms of the parameter λ . Suppose
we have design rules that call for a minimum width of 2 λ , and a
minimum spacing of 3 λ . If we select a 2 um technology (i.e., λ = 1
um), the above rules are translated to a minimum width of 2 um and a
minimum spacing of 3 um. On the other hand, if a 1 um technology
(i.e., λ = 0.5 um) is selected, then the same width and spacing rules are
now specified as 1um nd 1.5 um, respectively Figure 1.28 shows the
design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n and
p diffusion lines are having a minimum width of 2λand a minimum
spacing of 3λ. Similarly we are showing for other layers

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 Fig 1.28: Design Rules for Wires (nMOS and CMOS)

Fig 1.29: Transistor Design Rules (nMOS, pMOS and CMOS)

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 Figure 1.29 shows the design rule for the transistor, and it also shows that
the poly should extend for a minimum of 2λbeyond the diffusion
boundaries.(gate over hang distance)
VIA
It is used to connect higher level metals from metal1 connection. The
cross section and layout view given explain via in a better way.

Fig1.30: Cross section showing the contact and via

Fig1.31: Design rules for contact cuts and vias

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 Figure 1.31 shows the design rules for contact cuts and Vias. The design
rule for contact is minimum 2λx2λand same is applicable for a Via.

Buried contact: The contact cut is made down each layer to be joined
and it is shown in figure 1.32.

Fig 1.32: Buried Contact

Butting contact: The layers are butted together in such a way the two
contact cuts become contiguous. We can better under the butting
contact from figure 1.33

Fig 1.33: Butting Contact

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 2.8 LAMBDA BASED DESIGN RULES, CONTACT CUTS
Till now we have studied the design rules with respect to only
NMOS, what are the rules to be followed if we have the both p and
n transistor on the same chip will be made clear with the diagram.
Figure 1.32 shows the rules to be followed in CMOS well processes to
accommodate both n and p transistors.

Fig1.34: CMOS Design Rules

2.9 2µm CMOS process:

In this process all the spacing between each layers and dimensions will
be in terms micro meter. The 2µm here represents the feature size. All
the design rules whatever we have seen will not have lambda instead
it will have the actual dimension in micro meter. In one way lambda
based design rules are better compared micro meter based design
rules, that is lambda based rules are feature size independent. Figure
1.34 shows the design rule for BiCMOS process using orbit 2um process.

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 Fig 1.35: BiCMOS Design Rules

The following is the example stick and layouts for 2 way selector with enable
(2:1 MUX).

Fig 1.36: Two way selector stick and layout

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 2.10 STICK DIAGRAMS (NMOS AND CMOS DESIGN STYLES) and LAYOUT
DIAGRAMS
Stick diagrams may be used to convey layer information through the
use of a color code.
For example:
 N-diffusion -green poly -- red
 Blue -- metal
 yellow --implant
 Black --contact area

Encodings for NMOS process:

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Fig 1.37: Encodings for a simple metal nMOS process

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 Figure shows the way of representing different layers in stick diagram
notation and mask layout using nmos style.
Figure 1.37 shows when a n-transistor is formed: a transistor is formed
when a green line (n+ diffusion) crosses a red line (poly) completely.
Figure also shows how a depletion mode transistor is represented in the
stick forma

Encodings for MOS process:

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Figure 1.38: Encodings for a double metal CMOS p-well process

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 Figure 1.38 shows when a n-transistor is formed: a transistor is formed
when a green line (n+ diffusion) crosses a red line (poly) completely.
Figure 1.38 also shows when a p-transistor is formed: a transistor is formed
when a yellow line (p+ diffusion) crosses a red line (poly) completely.

Encoding for BJT and MOSFETs:

Fig 1.39: Additional encodings for a double metal double poly. BiCMOS n-well
process

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 There are several layers in an nMOS chip:
Paths of metal (usually aluminum) a further thick layer of silicon
dioxide with contact cuts through the silicon dioxide where connections
are required. The three layers carrying paths can be considered as
independent conductors that only interact where polysilicon crosses
diffusion to form a transistor. These tracks can be drawn as stick
diagrams with
o Diffusion in green

o Polysilicon in red

o Metal in blue

Using black to indicate contacts between layers and yellow to

mark regions of implant in the channels of depletion mode transistors.
With CMOS there are two types of diffusion: n-type is drawn in green and
p-type in brown. These are on the same layers in the chip and must not
meet. In fact, the method of fabrication required that they be kept
relatively far apart. Modern CMOS processes usually support more than
one layer of metal. Two are common and three or more are often
available. Actually, these conventions for colors are not universal; in
particular, industrial (rather than academic) systems tend to use red for
diffusion and green for polysilicon. Moreover, a shortage of colored pens
normally means that both types of diffusion in CMOS are colored green
and the polarity indicated by drawing a circle round p-type transistors or
simply inferred from the context. Colorings for multiple layers of metal
are even less standard. There are three ways that an nMOS inverter
might be drawn:

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 Fig 1.40: nMOS depletion load inverter

Figure 1.40 shows schematic, stick diagram and corresponding layout of

nMOS depletion Load inverter

Fig 1.41: CMOS Inverter

Fig 1.41 shows the schematic, stick diagram and corresponding layout of
CMOS Inverter

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 Fig 1.42: nMOS depletion load NAND and NOR Stick Diagram

Fig 1.43: Stick Diagram of a given function f

Figure 1.43 shows the stick diagram nMOS implementation of the

function f=[(xy)+z]

Fig 1.44: Stick diagram of CMOS NAND and NOR

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 Figure 1.44 shows the stick diagram CMOS NOR and NAND, where we
can see that the p diffusion line never touched the n diffusion directly, it
is always joined using a blue color metal line.

NMOS and CMOS Design style:

In the NMOS style of representing the sticks for the circuit, we
use only NMOS transistor, in CMOS we need to differentiate n and p
transistor, that is usually by the color or in monochrome diagrams we will
have a demarcation line. Above the demarcation line are the p
transistors and below the demarcation are the n transistors. Following
stick shows CMOS circuit example in monochrome where we utilize the
demarcation line.

Fig 1.45: Stick Diagram of Dynamic Shift Register in CMOS style

Figure 1.45 shows the stick diagram of dynamic shift register using CMOS
style. Here the output of the TG is connected as the input to the inverter
and the same chain continues depending on the number of bits.

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9. Practice Quiz
1. The colour of demarcation line is
a) brown
b) yellow
c) black
d) None

2. Large scale integration has_______________

a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates

3. The difficulty in achieving high doping concentration leads to ____________-

a) error in concentration
b) error in variation
c) error in doping
d) distribution error

4. Which provides higher integration density?

a) switch transistor logic
b) transistor buffer logic
c) transistor transistor logic
d) circuit level logic

5. Which is the high level representation of VLSI design?

a) problem statement
b) logic design
c) HDL program
d) functional design

6. The colour of N diffusion is

a) Green
b) yellow
c) black
d) None

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7. what is the value of Metal in lambda based design rules
a) 3 lambda
b) 2 lambda
c) 1lambda
d) None

8. In Pull up to pull down ratio for nMOS inverter driven by another Nmos transitor
is
a) 1:8
b) 4:1
c) 1:4
d) 8:1

8. In Pull up to pull down ratio for nMOS inverter driven by pass transistor
a) 1:8
b) 4:1
c) 1:4
d) 8:1

10. The colour encoding of polysilicon is

a) Green
b) yellow
c) black
d) Red

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10. Assignments

S.No Question BL Co

Design a CMOS inverter circuit and explain about its

1 2 1
various regions of operation in detail with the necessary
diagrams.

2 1 1
Explain the Double metal Mos process rules and
CMOS Lambda based design rules

a. Obtain pull up to pull down ratio for NMOS inverter

3 driven another NMOS inverter 2 1

b. Obtain pull up to pull down ratio through one or

more pass transistors .

a. Explain Lambda based Design Rules and in detail.

4 2 1
b. Draw the stick diagram and Lay out of 𝐴. 𝐵 in Nmos
̅̅̅̅̅

and CMOS design style using lambda based rules.

E xpl a in L am bd a ba se d de s ig n r ul e s .
5 1 2

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11. Part A- Question & Answers

S.No Question & Answers BL CO

What is an Integrated circuit?

An integrated circuit (IC) is an electronic circuit fabricated

on a small semiconductor wafer by building thousands or
millions of resistors, capacitors, diodes and transistors on it.
ICs are the heart and brains of most circuits.

1 The integrated circuits are divided into different categories

1
depending on the number of components that are 1
fabricated in the chip. They are,

Small Scale Integration (SSI)

Medium Scale Integration (MSI)

Large Scale Integration (LSI)

Very Large Scale Integration (VLSI).

Give the basic process for IC fabrication?

Silicon wafer Preparation, Epitaxial Growth

Oxidation , photolithography

Diffusion, Ion implantation

2 1
2
Isolation technique

Metallization

Assembly processing & Packaging

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 What are the steps involved in twin-tub process?

Tub Formation

3 Thin-oxide Construction 1
1
Source & Drain Implantation

Contact cut definition

Metallization

What is pull up device?

4 1
A device connected so as to pull the output voltage to the 1
upper supply voltage usually VDD is called pull up device.

What is pull down device?

5 1
A device connected so as to pull the output voltage to the 1
lower supply voltage usually 0V is called pull down device.
Define Short Channel devices?

Transistors with Channel length less than 3- 5 microns are

6 1
termed as Short channel devices. With short channel devices 1
the ratio between the lateral & vertical dimensions are
reduced.
Define Threshold voltage in CMOS?

The Threshold voltage, VT for a MOS transistor can be defined as

7 1
the voltage applied between the gate and the source ofthe 1
MOS transistor below which the drain to source current,
IDS effectively drops to zero.

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 What is Body effect?

The threshold voltage VT is not a constant w. r. to the voltage

8 1
difference between the substrate and the source of MOS 1

transistor. This effect is called substrate-bias effect or body

effect.

12. Part B- Questions

S.No Question BL C
O
Design a CMOS inverter circuit and explain about its various
1 regions of operation in detail with the necessary diagrams. 3 1

2 2 1
Explain the Double metal Mos process rules and CMOS
Lambda based design rules

3 c. Obtain pull up to pull down ratio for NMOS inverter driven 2 1

another NMOS inverter

d. Obtain pull up to pull down ratio through one or more pass

transistors .

b. Explain Lambda based Design Rules and in detail.

4 b. Draw the stick diagram and Lay out of 𝐴. 𝐵 in Nmos and
̅̅̅̅̅ 3 1

CMOS design style using lambda based rules.

5 E xpl a in L am bd a ba se d de s ig n r ul e s . 2 1

Draw Explain Nmos inverter

6 2 2
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BTECH_ECE-SEM 41
13. Supportive Online Certification Courses
1. Digital circuits By Prof. Santanu Chattopdhayay, conducted by IIT Kharagpur
on NPTEL – 12 weeks
2. Digital Electronic Circuits By Prof. Goutam Saha, conducted IIT Kharagpur on
NPTEL – 12 weeks

14. Real Time Applications

S.No Application CO

3D Lifting based Discrete Wavelet Transform

The main aim of this project is to aid with image coding in order to
1
produce high accurate images without losing any information. To
1
achieve the task, this approach implements a lifting filter based 3D
discrete wavelet transform VLSI architecture.

15. Contents Beyond Syllabus

Low Power Design for safety Critical applications: safe operation constraints vs
low-power techniques, Unsuitable low power design techniques for safety critical
applications, Low-power and safe-operating circuits

16. Prescribed Text Books & Reference Books

Text Books:
1. Kamran Eshraghian, Eshraghian Douglas and A. Pucknell, “Essentials of VLSI
circuits and systems”, PHI, 2013 Edition.

2. K.Lal Kishore and V.S.V. Prabhakar, “VLSI Design”, IK Publishers

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BTECH_ECE-SEM 41
References:

1. Weste and Eshraghian, “Principles of CMOS VLSI Design”, Pearson

Education, 1999.

2. Wayne Wolf, “Modern VLSI Design”, Pearson Education, 3rd Edition, 1997.

3. John P. Uyemura, “Chip Design for Submicron VLSI: CMOS layout and
Simulation”, Thomson Learning.

4. John P. Uyemura, “Introduction to VLSI Circuits and Systems”, John wiley,

2003.

5. John M. Rabaey, “Digital Integrated Circuits”, PHI, EEE, 1997.

17. Mini Project Suggestion

1. An Efficient VLSI Architecture for Removal of Impulse Noise in Image:

This project aims to enhance the visual quality of images and to avoid
chances of being corrupted by impulse noise by implementing an efficient
VLSI architecture using edge preserving filter.

2. VHDL Model of Smart Sensor:

The aim of this project is to build a VHDL model of smart sensor by

implementing algorithm for smart sensor with noise cancellation using IEEE 1451
communication standard. The complete simulation of this project is carried by
VHDL program.

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