DSDV – BEC654A

Module 2
Basic Concepts
Modules and Ports
Contents
Basic Concepts
Learning Objectives
• Understand lexical conventions for operators, comments, whitespace,
numbers, strings, and identifiers.
• Define the logic value set and data types such as nets, registers,
vectors, numbers, simulation time, arrays, parameters, memories,
and strings.
• Identify useful system tasks for displaying and monitoring
information, and for stopping and finishing the simulation.
• Learn basic compiler directives to define macros and include files.
Lexical Conventions
• The basic lexical conventions used by Verilog HDL are similar to those
in the C programming language.
• Verilog contains a stream of tokens. Tokens can be comments,
delimiters, numbers, strings, identifiers, and keywords.
• Verilog HDL is a case-sensitive language.
• All keywords are in lowercase.
Whitespace
• Blank spaces (\b) , tabs (\t) and newlines (\n) comprise the
whitespace.
• Whitespace is ignored by Verilog except when it separates tokens.
• Whitespace is not ignored in strings.
Comments
• Comments can be inserted in the code
for readability and documentation.
• There are two ways to write
comments. A one line comment starts
with "//".
• Verilog skips from that point to the
end of line.
• A multiple- line comment starts with
"/*" and ends with "*/". Multiple-line
comments cannot be nested.
• However, one-line comments can be
embedded in multiple-line comments.
Operators
• Operators are of three types:
unary, binary, and ternary.
• Unary operators precede the
operand.
• Binary operators appear
between two operands.
• Ternary operators have two
separate operators that separate
three operands.
Number Specification

Sized numbers Unsized numbers

X or Z values
• Verilog has two symbols for unknown and high impedance values. An
unknown value is denoted by an x. A high impedance value is
denoted by z.
• An x or z sets four bits for a number in the hexadecimal base, three
bits for a number in the octal base and one bit for a number in the
binary base.
• If the most significant bit of a number is 0, x, or z, the number is
automatically extended to fill the most significant bits, respectively,
with 0, x, or z.
• This makes it easy to assign x or z to whole vector. If the most
significant digit is 1, then it is also zero extended.
Negative numbers
• Negative numbers can be specified by putting a minus sign before the
size for a constant number.
• Size constants are always positive. It is illegal to have a minus sign
between <base format> and <number>.
• An optional signed specifier can be added for signed arithmetic.
Underscore characters and question marks
• An underscore character "_" is allowed anywhere in a number except
the first character.
• Underscore characters are allowed only to improve readability of
numbers and are ignored by Verilog.
• A question mark "?" is the Verilog HDL alternative for z in the context
of numbers.
• The ? is used to enhance readability in the casex and casez
statements.
Strings
• A string is a sequence of characters that are enclosed by double
quotes.
• The restriction on a string is that it must be contained on a single line,
that is, without a carriage return.
• It cannot be on multiple lines. Strings are treated as a sequence of
one-byte ASCII values.
Identifiers and Keywords
• Keywords are special identifiers reserved to define the language
constructs.
• Keywords are in lowercase. Identifiers are names given to objects so
that they can be referenced in the design.
• Identifiers are made up of alphanumeric characters, the underscore (
_ ), or the dollar sign ( $ ).
• Identifiers are case sensitive. Identifiers start with an alphabetic
character or an underscore. They cannot start with a digit or a $ sign
(The $ sign as the first character is reserved for system tasks)
Escaped Identifiers
• Escaped identifiers begin with the backslash ( \ ) character and end
with whitespace (space, tab, or newline).
• All characters between backslash and whitespace are processed
literally. Any printable ASCII character can be included in escaped
identifiers.
• Neither the backslash nor the terminating whitespace is considered
to be a part of the identifier.
Data Types
• If two signals of unequal strengths are driven on a wire, the stronger
signal prevails.
• For example, if two signals of strength strong1 and weak0 contend, the
result is resolved as a strong1.
• If two signals of equal strengths are driven on a wire, the result is
unknown.
• If two signals of strength strong1 and strong0 conflict, the result is an x.
Nets
• Nets represent connections between hardware elements.
• Just as in real circuits, nets have values continuously driven on them
by the outputs of devices that they are connected to.
• In Figure, net a is connected to the output of and gate g1.
• Net a will continuously assume the value computed at the output of
gate g1, which is b & c.
• Nets are declared primarily with the keyword wire.
• Nets are one-bit values by default unless they are declared explicitly
as vectors.
• The terms wire and net are often used interchangeably.
• The default value of a net is z (except the trireg net, which defaults to
x ). Nets get the output value of their drivers.
• If a net has no driver, it gets the value z.
• Note that net is not a keyword but represents a class of data types
such as wire, wand, wor, tri, triand, trior, trireg, etc.
• The wire declaration is used most frequently.
Registers
• Registers represent data storage elements.
• Registers retain value until another value is placed onto them.
• In Verilog, the term register merely means a variable that can hold a value.
• Unlike a net, a register does not need a driver.
• Verilog registers do not need a clock as hardware register do.
• Values of registers can be changed anytime in a simulation by assigning a
new value to the register.
• Register data types are commonly declared by the keyword reg.
• The default value for a reg data type is x.
Registers can also be declared as signed variables. Such registers can be used for signed arithmetic.
Vectors
• Nets or reg data types can be declared as vectors (multiple bit
widths). If bit width is not specified, the default is scalar (1-bit).
• Vectors can be declared at [high# : low#] or [low# : high#]
Vector Part Select
Variable Vector Part Select
Integer , Real, and Time Register Data Types
• An integer is a general purpose register data type used for
manipulating quantities.
• Integers are declared by the keyword integer.
• The default width for an integer is the host- machine word size, which
is implementation specific but is at least 32 bits.
 Real
• Real number constants and real
register data types are declared with
the keyword real.
• They can be specified in decimal
notation (e.g., 3.14) or in scientific
notation (e.g., 3e6, which is 3 x 106 ).
• Real numbers cannot have a range
declaration, and their default value is
0.
• When a real value is assigned to an
integer, the real number is rounded
off to the nearest integer.
Time
• Verilog simulation is done with respect to simulation time.
• A special time register data type is used in Verilog to store simulation
time.
• A time variable is declared with the keyword time.
• The width for time register data types is implementation-specific but
is at least 64 bits.
• The system function $time is invoked to get the current simulation
time.
• Simulation time is measured in terms of simulation seconds. The unit
is denoted by s, the same as real time.
Arrays
• Arrays are allowed in Verilog for reg, integer, time, real, realtime and vector
register data types.
• Multi-dimensional arrays can also be declared with any number of
dimensions.
• Arrays of nets can also be used to connect ports of generated instances.
• Each element of the array can be used in the same fashion as a scalar or
vector net.
• Arrays are accessed by <array_name>[<subscript>].
• For multi-dimensional arrays, indexes need to be provided for each
dimension.
Memories
• In digital simulation, one often needs to model register files, RAMs,
and ROMs.
• Memories are modeled in Verilog simply as a one dimensional array
of registers.
• Each element of the array is known as an element or word and is
addressed by a single array index.
• Each word can be one or more bits. It is important to differentiate
between n 1-bit registers and one n-bit register.
• A particular word in memory is obtained by using the address as a
memory array subscript.
Parameters
• Verilog allows constants to be defined in a module by the keyword
parameter. Parameters cannot be used as variables.
• Parameter types and sizes can also be defined.
Strings
• Strings can be stored in reg. The width of the register variables must be
large enough to hold the string.
• Each character in the string takes up 8 bits (1 byte). If the width of the
register is greater than the size of the string, Verilog fills bits to the left of
the string with zeros.
• If the register width is smaller than the string width, Verilog truncates the
leftmost bits of the string.
• It is always safe to declare a string that is slightly wider than necessary. reg
[8*18:1] string_value; // Declare a variable that is 18 bytes wide initial
• string_value = "Hello Verilog World"; // String can be stored in variable
System Tasks
• Verilog provides standard system tasks for certain routine operations.
All system tasks appear in the form $.
• Operations such as displaying on the screen, monitoring values of
nets, stopping, and finishing are done by system tasks.
Displaying information
• $display is the main system task for displaying values of variables or
strings or expressions. This is one of the most useful tasks in Verilog.
• Usage: $display(p1, p2, p3,....., pn);
• p1, p2, p3,..., pn can be quoted strings or variables or expressions.
• The format of $display is very similar to printf in C.
• A $display inserts a newline at the end of the string by default.
• A $display without any arguments produces a newline.
Monitoring information
• Verilog provides a mechanism to monitor a signal when its value changes.
This facility is provided by the $monitor task.
• Usage: $monitor(p1,p2,p3,....,pn);
• The parameters p1, p2, ... , pn can be variables, signal names, or quoted
strings.
• A format similar to the $display task is used in the $monitor task.
• $monitor continuously monitors the values of the variables or signals
specified in the parameter list and displays all parameters in the list
whenever the value of any one variable or signal changes.
• Unlike $display, $monitor needs to be invoked only once.
• Only one monitoring list can be active at a time.
• If there is more than one $monitor statement in your simulation, the last
$monitor statement will be the active statement. The earlier $monitor
statements will be overridden.
• Two tasks are used to switch monitoring on and off.
• Usage: $monitoron; $monitoroff;
• The $monitoron tasks enables monitoring, and the $monitoroff task
disables monitoring during a simulation.
• Monitoring is turned on by default at the beginning of the simulation
and can be controlled during the simulation with the $monitoron and
$monitoroff tasks.
Compiler Directives
• Compiler directives are provided in Verilog. All compiler directives are
defined by using the ` construct.
• We deal with the two most useful compiler directives.
• `define - The `define directive is used to define text macros in Verilog
• The Verilog compiler substitutes the text of the macro wherever it
encounters a `.
• This is similar to the #define construct in C.
• The defined constants or text macros are used in the Verilog code by
preceding them with a ` (back tick).
`include
• The `include directive allows you to include entire contents of a
Verilog source file in another Verilog file during compilation.
• This works similarly to the #include in the C programming language.
• This directive is typically used to include header files, which typically
contain global or commonly used definitions
Modules and Ports
Learning Objectives
• Identify the components of a Verilog module definition, such as
module names, port lists, parameters, variable declarations, dataflow
statements, behavioral statements, instantiation of other modules,
and tasks or functions.
• Understand how to define the port list for a module and declare it in
Verilog.
• Describe the port connection rules in a module instantiation.
• Understand how to connect ports to external signals, by ordered list,
and by name.
• Explain hierarchical name referencing of Verilog identifiers.
Modules
• A module definition always begins with the keyword module.
• The module name, port list, port declarations, and optional parameters
must come first in a module definition.
• Port list and port declarations are present only if the module has any ports
to interact with the external environment.
• The five components within a module are: variable declarations, dataflow
statements, instantiation of lower modules, behavioral blocks, and tasks or
functions.
• These components can be in any order and at any place in the module
definition.
• The endmodule statement must always come last in a module definition.
• All components except module, module name, and endmodule are
optional and can be mixed and matched as per design needs.
• Verilog allows multiple modules to be defined in a single file.
• The modules can be defined in any order in the file.
Example: SR Latch
• The SR latch has S and R as the input ports and Q and Qbar as the
output ports.
Ports
• Ports provide the interface by which a module can communicate with
its environment.
• For example, the input/output pins of an IC chip are its ports.
• The environment can interact with the module only through its ports.
• The internals of the module are not visible to the environment.
• This provides a very powerful flexibility to the designer. The internals
of the module can be changed without affecting the environment as
long as the interface is not modified.
• Ports are also referred to as terminals.
List of Ports
• A module definition contains an optional list of ports.
• If the module does not exchange any signals with the environment,
there are no ports in the list.
• Consider a 4-bit full adder that is instantiated inside a top-level
module Top.
• In the figure, the module Top is a
top-level module. The module
fulladd4 is instantiated below Top.
• The module fulladd4 takes input on
ports a, b, and c_in and produces an
output on ports sum and c_out.
Thus, module fulladd4 performs an
addition for its environment.
• The module Top is a top-level
module in the simulation and does
not need to pass signals to or
receive signals from the
environment.
• Thus, it does not have a list of ports.
The module names and port lists for
both module declarations in Verilog
Port Declaration
Port Connection Rules
• A port as consisting of two units,
one unit that is internal to the
module and another that is
external to the module.
• The internal and external units are
connected. There are rules
governing port connections when
modules are instantiated within
other modules.
• The Verilog simulator complains if
any port connection rules are
violated.
• Inputs: Internally, input ports must always be of the type net. Externally,
the inputs can be connected to a variable which is a reg or a net.
• Outputs: Internally, outputs ports can be of the type reg or net. Externally,
outputs must always be connected to a net. They cannot be connected to a
reg.
• Inouts: Internally, inout ports must always be of the type net. Externally,
inout ports must always be connected to a net.
• Width matching: It is legal to connect internal and external items of
different sizes when making inter module port connections. However, a
warning is typically issued that the widths do not match.
• Unconnected ports: Verilog allows ports to remain unconnected. For
example, certain output ports might be simply for debugging, and you
might not be interested in connecting them to the external signals. You can
let a port remain unconnected by instantiating a module as shown below.
fulladd4 fa0(SUM, , A, B, C_IN); // Output port c_out is unconnected
Example of illegal port connection
Connecting Ports to External Signals
• There are two methods of making connections between signals
specified in the module instantiation and the ports in a module
definition.
• These two methods cannot be mixed.
• Connecting by ordered list
• Connecting ports by name
Connecting by ordered list
• The signals to be connected must appear in the module instantiation
in the same order as the ports in the port list in the module
definition.
• Consider the module fulladd4.To connect signals in module Top by
ordered list, the Verilog code is shown in below example.
• Notice that the external signals SUM, C_OUT, A, B, and C_IN appear in
exactly the same order as the ports sum, c_out, a, b, and c_in in
module definition of fulladd4.
Connecting ports by name
• For large designs where modules have, say, 50 ports, remembering
the order of the ports in the module definition is impractical and
error-prone.
• Verilog provides the capability to connect external signals to ports by
the port names, rather than by position.
• Another advantage of connecting ports by name is that as long as the
port name is not changed, the order of ports in the port list of a
module can be rearranged without changing the port connections in
module instantiations.
• We could connect the ports by name in above example by
instantiating the module fulladd4
• // Instantiate module fa_byname and connect signals to ports by
name fulladd4 fa_byname(.c_out(C_OUT), .sum(SUM), .b(B),
.c_in(C_IN), .a(A),);
• Note that only those ports that are to be connected to external
signals must be specified in port connection by name.
• Unconnected ports can be dropped.
• For example, if the port c_out were to be kept unconnected, the
instantiation of fulladd4 would look as follows. The port c_out is
simply dropped from the port list.
• // Instantiate module fa_byname and connect signals to ports by
name fulladd4 fa_byname(.sum(SUM), .b(B), .c_in(C_IN), .a(A),);
• Another advantage of connecting ports by name is that as long as the
port name is not changed, the order of ports in the port list of a
module can be rearranged without changing the port connections in
module instantiations.
Hierarchical Names
• Verilog supports a hierarchical design methodology.
• Every module instance, signal, or variable is defined with an identifier.
• A particular identifier has a unique place in the design hierarchy.
• Hierarchical name referencing allows us to denote every identifier in
the design hierarchy with a unique name.
• A hierarchical name is a list of identifiers separated by dots (".") for
each level of hierarchy
• The top-level module is called
the root module because it is
not instantiated anywhere. It is
the starting point.
• To assign a unique name to an
identifier, start from the top-
level module and trace the path
along the design hierarchy to the
desired identifier.
Summary
• Module definitions contain various components. Keywords module and
endmodule are mandatory. Other components?port list, port declarations,
variable and signal declarations, dataflow statements, behavioral blocks,
lower-level module instantiations, and tasks or functions?are optional and
can be added as needed.
• Ports provide the module with a means to communicate with other
modules or its environment. A module can have a port list. Ports in the port
list must be declared as input, output, or inout. When instantiating a
module, port connection rules are enforced by the Verilog simulator. An
ANSI C style embeds the port declarations in the module definition
statement.
• Ports can be connected by name or by ordered list.
• Each identifier in the design has a unique hierarchical name. Hierarchical
names allow us to address any identifier in the design from any other level
of hierarchy in the design.