Microprocessor&Its Applications (CS313)

UNiT 3 Interfacing with Peripheral Devices and Memory

1. Introduction to Interfacing

A microprocessor needs to communicate with external devices, including memory and peripheral
devices like input/output (I/O) devices. The process of connecting these devices to the
microprocessor is called interfacing. Interfacing ensures seamless communication between the
CPU and external components for data transfer and control operations.

2. Types of Interfacing

1. Memory Interfacing – Connecting RAM and ROM to the microprocessor.

2. I/O Interfacing – Connecting input/output devices like keyboards, displays, ADC, DAC,
etc.
3. Memory Interfacing
Memory interfacing allows the microprocessor to read and write data from/to memory. It involves
connecting RAM (for read/write operations) and ROM (for read-only operations).

3.1 Memory Addressing

• A microprocessor uses address lines to specify the location of data.

• The total addressable memory is determined by the number of address lines.
• Example:
◦ 8085 Microprocessor has 16-bit address lines → Can access 64 KB of memory
(2¹⁶ = 65536 bytes).
◦ 8086 Microprocessor has 20-bit address lines → Can access 1 MB of memory (2²⁰
= 1048576 bytes).
3.2 Memory Interfacing Diagram

Below is a basic memory interfacing diagram for the 8085 Microprocessor, showing how the
address and data lines connect to memory.
3.3 Control Signals for Memory Interfacing

1. RD (Read Signal) – Enables reading data from memory.

2. WR (Write Signal) – Enables writing data to memory.
3. CS (Chip Select) – Activates a speci c memory chip.
3.4 Example: Interfacing 8KB ROM and 8KB RAM with 8085

• Address range of ROM: 0000H – 1FFFH (8KB)

• Address range of RAM: 2000H – 3FFFH (8KB)
Address decoding is used to activate the appropriate memory chip when an address falls within its
range.

4. I/O Interfacing (Peripheral Interfacing)

I/O interfacing connects input/output devices to the microprocessor, enabling communication with
peripherals such as keyboards, displays, sensors, etc.

4.1 Types of I/O Addressing

1. Isolated I/O – Separate address space for memory and I/O devices.
2. Memory-Mapped I/O – Treats I/O devices as memory locations.
4.2 I/O Interfacing Diagram

4.3 Control Signals for I/O Interfacing

1. IN – Reads data from an input device.

2. OUT – Sends data to an output device.
3. CS (Chip Select) – Activates a particular I/O device.
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4.4 Common Peripheral Devices and Their Interfacing

Peripheral Device Function Example IC

8279 (Keyboard Display
Keyboard Input device for user commands
Controller)
Display (LED/LCD) Output device to show results 7-segment display, LCD
ADC (Analog to Digital
Converts analog signals to digital ADC0808
Converter)
DAC (Digital to Analog
Converts digital signals to analog DAC0800
Converter)
Rotational device for control
Stepper Motor ULN2003 (Driver IC)
applications

5. Interfacing Examples
5.1 Interfacing 8255 (Programmable Peripheral Interface - PPI) with 8085

The 8255 PPI (Programmable Peripheral Interface) is used to interface input and output devices
with the microprocessor.

Block Diagram of 8255 Interfacing

 • 8255 has 3 ports (Port A, B, and C) for input/output operations.
• Each port can be programmed as input or output.
5.2 Interfacing ADC (Analog to Digital Converter)

ADC is used to convert analog signals (like temperature, pressure, etc.) into digital form.

Example: Interfacing ADC0808 with 8085

┌───────────────┐
│ ADC0808 │
│ (Analog Input) │
├───────────────┤
│ Digital Output │──────▶ 8085 Data Bus
│ Control Signals │──────▶ RD, WR, INTR
└───────────────┘

Types of Transmission in Microprocessors and

Communication Systems
Data transmission refers to the transfer of data from one device to another through a communication
medium. It plays a crucial role in microprocessor-based systems, networking, and embedded
applications.

1. Types of Data Transmission

Data transmission can be categorized based on:

• Direction of Data Flow

• Mode of Transmission
• Synchronization Method
1.1 Based on Direction of Data Flow

There are three types of data transmission based on how data moves between devices.

Type Description Example

Simplex Data ows in only one direction TV Broadcasting, Keyboard to CPU
Half- Data ows in both directions, but only one at a
Walkie-Talkies, Two-Way Radio
Duplex time
Full- Telephone Calls, Internet
Data ows in both directions simultaneously
Duplex Communication

(a) Simplex Transmission

• Data travels in one direction only.

• No return signal or acknowledgment.
• Example: Keyboard to CPU, Radio Transmission.
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 (b) Half-Duplex Transmission

• Data travels in both directions, but one at a time.

• Requires a control mechanism to switch between sending and receiving.
• Example: Walkie-Talkie Communication (Only one person can talk at a time).
(c) Full-Duplex Transmission

• Data ows in both directions at the same time.

• Requires two separate communication channels.
• Example: Telephone Communication, Internet Browsing.

1.2 Based on Transmission Mode

This classi cation depends on how data is structured and sent.

Type Description Example

Parallel Multiple bits are sent at the same Internal Data Transfer in
Transmission time Microprocessors
Serial Transmission Bits are sent one after another USB, Ethernet, IoT Devices

(a) Parallel Transmission

• Multiple bits (usually 8, 16, or 32 bits) are transmitted simultaneously over multiple
channels.
• Faster but prone to crosstalk and signal degradation over long distances.
• Used in RAM, CPU Data Bus, and Printer Communication.
Diagram:

Sender: 10110110 → 8 bits sent at once → Receiver

(b) Serial Transmission

• Bits are transmitted one by one in a sequence over a single channel.

• Used for long-distance communication (less interference).
• Found in USB, Ethernet, and Bluetooth devices.
Types of Serial Transmission:

1. Synchronous Transmission – Data is sent in continuous streams with synchronization.

2. Asynchronous Transmission – Data is sent in small packets with start/stop bits.

1.3 Based on Synchronization

Type Description Example

Synchronous Data is sent as a continuous stream, synchronized Ethernet, Real-Time
Transmission with a clock signal Systems
Asynchronous USB, RS232 Serial
Data is sent in small packets with start/stop bits
Transmission Communication
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 (a) Synchronous Transmission

• Data is transmitted in a continuous stream.

• Requires a clock signal for synchronization.
• Used in high-speed communication like Ethernet, Real-Time Systems.
(b) Asynchronous Transmission

• Data is sent in small chunks with start and stop bits to indicate the beginning and end.
• No clock signal is required.
• Used in USB, RS232 Serial Communication, and IoT Devices.

2. Comparison of Transmission Types

Feature Simplex Half-Duplex Full-Duplex
Data Flow One-way only Both directions (one at a time) Both directions (simultaneous)
Speed Slow Moderate Fast
Ef ciency Low Medium High
Example TV Broadcasting Walkie-Talkies Internet, Telephone
Feature Parallel Transmission Serial Transmission
Speed Faster Slower
Wiring Multiple wires Single wire
Distance Short distance Long distance
Example CPU-RAM Communication USB, Bluetooth

3. Applications of Different Transmission Types

• Simplex: TV broadcasting, keyboards.
• Half-Duplex: Walkie-talkies, two-way radios.
• Full-Duplex: Telephony, computer networks.
• Parallel Transmission: Internal CPU operations, RAM data transfer.
• Serial Transmission: Internet communication, USB, IoT sensors.

Intel 8257 – Direct Memory Access (DMA) Controller

Introduction to 8257 (DMA Controller)
The Intel 8257 is a Direct Memory Access (DMA) controller that allows data to be transferred
directly between memory and I/O devices without involving the CPU. This increases system
ef ciency and speeds up data transfer.

Why is DMA Needed?

• In a normal data transfer, the CPU reads data from an I/O device and then writes it to
memory. This creates a bottleneck.
• DMA allows direct memory access, freeing up the CPU for other tasks.
• Used in high-speed devices like disk drives, sound cards, graphics processors, and
network cards.
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Pin Diagram of 8257 DMA Controller

Features of Intel 8257

1. 4 independent DMA channels (CH0, CH1, CH2, CH3).
2. Transfers data without CPU intervention.
3. Each channel has a 16-bit address and count register.
4. Supports burst mode, cycle stealing mode, and transparent mode.
5. Can transfer up to 64 KB of data per channel.
6. Works with 8-bit microprocessors like 8085, 8086.
7. Signals end of transfer (TC – Terminal Count signal).
8. Prioritization: Channels can be xed or rotating priority.
9. Supports memory-to-memory, memory-to-I/O, and I/O-to-memory transfers.

Pin Description of 8257

8257 has 40 pins, divided into different groups:
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1. Data & Address Pins

Pin Description
D0 – D7 8-bit data bus for communication with CPU.

A0 – A7 8-bit address bus to access memory.

2. Control Signals

Pin Description
HRQ (Hold Request) Requests control of the system bus from CPU.
HLDA (Hold Acknowledge) CPU grants DMA access to the bus.
TC (Terminal Count) Indicates transfer completion.

3. Read/Write Control

Pin Description
MEMR (Memory Read) Reads data from memory.
MEMW (Memory Write) Writes data to memory.
IOR (I/O Read) Reads data from an I/O device.
IOW (I/O Write) Writes data to an I/O device.

4. DMA Channel Control

Pin Description
DRQ0 – DRQ3 (DMA Request) Each I/O device requests DMA transfer via these pins.
DACK0 – DACK3 (DMA Acknowledge) Acknowledges DMA transfer to I/O device.

Working of 8257 DMA Controller

1. DMA Request: An I/O device (e.g., Hard Disk) sends a DMA request (DRQx) to 8257.
2. Bus Request: 8257 sends Hold Request (HRQ) to CPU to gain control of the system bus.
3. CPU Acknowledges: CPU halts its operations and responds with HLDA (Hold
Acknowledge).
4. Data Transfer: 8257 performs direct transfer between memory and I/O.
5. Completion: Once transfer is completed, 8257 releases the system bus.

DMA Transfer Modes in 8257

1. Burst Mode

• Entire block of data is transferred without CPU intervention.

• High-speed transfer but CPU remains idle during transfer.
• Used in disk drives, graphics processing.
 2. Cycle Stealing Mode

• DMA transfers one byte at a time, allowing the CPU to use the bus between transfers.
• Used in sound cards and slow-speed devices.
3. Transparent Mode

• DMA only transfers data when CPU is not using the system bus.
• CPU works continuously without interruptions.
• Used in background data transfer applications.

Example: Interfacing 8257 with 8085 Microprocessor

The 8257 can be interfaced with 8085 microprocessor as follows:

1. Address bus (A0–A7) and data bus (D0–D7) are connected to 8085.
2. Control signals (HRQ, HLDA) manage bus access.
3. DRQ and DACK lines handle DMA requests from I/O devices.
Interfacing Diagram

+-----------+ +--------+
| 8085 CPU | ----| 8257 DMA |
+-----------+ +--------+
| |
(HLDA) (HRQ)
| |
(MEMR) (MEMW)
| |
Memory I/O Devices

Advantages of Using 8257

• Faster data transfer (bypasses CPU bottleneck).
• Ef cient CPU utilization (CPU can execute other tasks).
• Supports multiple I/O devices via 4 channels.
• Reduces system bus contention in multi-tasking systems.

Applications of 8257 DMA Controller

• Hard Disk Controllers (for fast data transfer).
• Graphics & Video Processing (for high-speed data transfer).
• Audio Processing (sound cards use DMA for real-time audio streaming).
• Embedded Systems (microcontroller-based applications).
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Intel 8255 – Programmable Peripheral Interface (PPI)

Introduction to 8255 (PPI)

The Intel 8255 is a Programmable Peripheral Interface (PPI) used to interface microprocessors
(like 8085, 8086) with peripheral devices such as keyboards, displays, ADCs, DACs, and
sensors.

• It has three 8-bit ports (PA, PB, PC), which can be programmed for input or output
operations.
• Supports mode selection for exible communication with peripherals.
• Commonly used in embedded systems, robotics, and industrial automation.

Pin Diagram of 8255

Features of 8255
✔ 3 Programmable Ports:

• Port A (PA0 - PA7)

• Port B (PB0 - PB7)
• Port C (PC0 - PC7)
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 ✔ Modes of Operation:

• Mode 0 (Basic I/O Mode)

• Mode 1 (Strobed I/O Mode)
• Mode 2 (Bi-directional Mode)
✔ Used for interfacing:

• LEDs, LCDs, Relays, Sensors, Keyboards, ADCs, DACs.

✔ Compatible with 8085, 8086, and other microprocessors.

✔ 8-bit Data Bus for communication with the microprocessor.

Pin Description of 8255

Pin Description
PA0 - PA7 8-bit Port A for input/output.
PB0 - PB7 8-bit Port B for input/output.
PC0 - PC7 8-bit Port C (can be split into PC upper/lower).
D0 - D7 8-bit Data Bus (for communication with CPU).
RD Read signal (active low) to read data from 8255.
WR Write signal (active low) to write data into 8255.
CS Chip Select (active low) to enable 8255.
A0, A1 Address pins (selects different registers in 8255).
RESET Resets the 8255 to default state.
Control Word Format (Command Register)
To con gure the 8255 ports, we write a control word to the Control Register.

D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0
--------------------------------------
1 | Mode Selection | PA | PB | PC
Bit Function
D7 Set to 1 for Mode selection.
D6-D5 Select Mode (0,1,2).
D4 Port A direction (1 = Input, 0 = Output).
D3 Port C Upper (1 = Input, 0 = Output).
D2 Port B direction (1 = Input, 0 = Output).
D1 Port C Lower (1 = Input, 0 = Output).
D0 Mode selection (1 = Mode set, 0 = Bit Set/Reset).
Modes of Operation
1. Mode 0 (Basic I/O Mode)

• Simple input/output operation.

• No handshaking signals are required.
• Each port can be programmed as input or output independently.
• Used in LEDs, LCDs, Switches, and Simple Data Transfer.
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2. Mode 1 (Strobed I/O Mode)

• Data is transferred with handshake signals.

• Requires strobe signals for data transfer.
• Used in printers, ADC/DAC communication.
3. Mode 2 (Bi-directional Mode)

• Only available for Port A.

• Port A acts as a bidirectional bus.
• Requires handshaking signals for communication.
• Used in parallel data communication (e.g., between microprocessors).

Interfacing 8255 with 8085 Microprocessor

• 8255 is memory-mapped or I/O-mapped to 8085.
• Data bus (D0-D7) is connected to the CPU's data lines.
• Address lines (A0, A1) select the registers.
• Control signals (RD, WR, CS) manage read/write operations.
Interfacing Diagram

+-----------+ +--------+
| 8085 CPU | ----> | 8255 PPI |
+-----------+ +--------+
| |
(RD) (WR)
| |
(A0, A1) (CS, RESET)
| |
LEDs, LCDs, Switches, Sensors
Example: Controlling LEDs using 8255
If we want Port A to control LEDs (output mode) and Port B to read switches (input mode):

Step 1: Con gure 8255

MVI A, 80H ; Control Word: Port A = Output, Port B = Input,

Port C = Output
OUT 03H ; Send control word to 8255
Step 2: Turn ON LEDs (PA = 11110000)

MVI A, F0H ; Data to turn ON LEDs (PA7-PA4 ON, PA3-PA0 OFF)

OUT 00H ; Send data to Port A
Step 3: Read Switch Status from Port B

IN 01H ; Read switch status from Port B

MOV B, A ; Store value in register B
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Applications of 8255
• LED Display Control
• Interfacing Keyboards and Switches
• Data Communication (Parallel Ports)
• Interfacing ADCs and DACs
• Robotics & Industrial Automation

Intel 8251 – USART (Universal Synchronous Asynchronous

Receiver Transmitter)
The Intel 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter) is a
serial communicationdevice used for interfacing microprocessors (e.g., 8085, 8086) with serial
data communication devices.

• It supports both synchronous and asynchronous data transmission.

• Converts parallel data from the microprocessor into serial data for transmission.
• Receives serial data and converts it into parallel data for the microprocessor.
• Used in modems, RS-232 communication, remote sensing, and industrial automation.

Pin Diagram of 8251 USART

Features of 8251 USART
✔ Supports Synchronous and Asynchronous communication.
✔ Full-Duplex Communication (Simultaneous Transmit and Receive).
✔ Baud Rate Generation using External Clock.
✔ Supports Data Bits (5 to 8), Stop Bits (1, 1.5, or 2), Parity Bits (Even/Odd).
✔ Handshake Signals (RTS, CTS, DSR, DTR).
✔ Status Flags for data transmission and reception monitoring.

Pin Description of 8251 USART

Pin Description
D0 - D7 8-bit data bus (for communication with the microprocessor).
RD Read signal (active low) to read data from 8251.
WR Write signal (active low) to write data into 8251.
CS Chip Select (active low) to enable 8251.
C/D Control/Data select (1 = Control, 0 = Data).
RESET Resets 8251 to default state.
CLK Clock input for baud rate generation.
TXD Transmit Data (Serial Output).
RXD Receive Data (Serial Input).
RTS Request to Send (Handshake signal).
CTS Clear to Send (Handshake signal).
DSR Data Set Ready (Handshake signal).
DTR Data Terminal Ready (Handshake signal).
SYNDET Synchronous Detect (Used in Sync mode).

Modes of Operation in 8251

The 8251 USART operates in two main modes:

1. Asynchronous Mode

• Data transmitted without a clock signal.

• Uses start and stop bits to frame data.
• Used in RS-232, UART communication.
• Supports baud rates (e.g., 9600, 115200).
• Example: PC-to-PC communication via serial port.
2. Synchronous Mode

• Data transmitted with a clock signal.

• Requires sync characters for data framing.
• Used in high-speed data communication (e.g., Modems, Ethernet).
• No start/stop bits, making it more ef cient.

Control Word Format (Command Register)

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The Control Register is used to con gure USART mode, baud rate, parity, and stop bits.

D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0
--------------------------------------
Mode | Parity | Stop Bits | Data Bits
Bit Function
D7-D6 Mode selection (Sync/Async).
D5 Parity Enable (1 = Enable, 0 = Disable).
D4 Parity Type (1 = Odd, 0 = Even).
D3 Stop Bits (1 = 1 bit, 2 = 2 bits).
D2-D1 Character Length (Data Bits: 5, 6, 7, 8).
D0 Baud Rate Factor (1 = x16, 0 = x1).
Interfacing 8251 with 8085 Microprocessor
• 8251 is memory-mapped or I/O-mapped to 8085.
• Data bus (D0-D7) is connected to CPU data lines.
• Control signals (RD, WR, CS, C/D) manage data ow.
• TXD and RXD are connected to serial devices.
Interfacing Diagram

+-----------+ +---------+
| 8085 CPU | ----> | 8251 USART |
+-----------+ +---------+
| |
(RD) (WR)
| |
(A0, A1) (CS, RESET)
| |
TXD → Serial Output (To Modem)
RXD ← Serial Input (From Modem)
Programming 8251 USART
Step 1: Initialize USART (Asynchronous Mode, 8-bit, 1 Stop Bit)

MVI A, 11000000B ; Control Word: 8-bit, 1 Stop Bit, No

Parity
OUT 03H ; Send control word to 8251
Step 2: Load Data to Transmit

MVI A, 'A' ; Load ASCII value of 'A'

OUT 02H ; Send data to 8251 (TXD)
Step 3: Receive Data from Serial Input

IN 02H ; Read data from RXD

MOV B, A ; Store received data in register B
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Applications of 8251 USART
✔ Serial Communication (RS-232, UART, USB)
✔ Data Transfer Between Computers and Microcontrollers
✔ Modem Communication for Internet & Networking
✔ Interfacing with GSM, GPS, RFID, and Bluetooth Modules
✔ Industrial Automation & Robotics

Intel 8279 – Keyboard/Display Controller

The Intel 8279 is a programmable keyboard and display interface designed to interface a
microprocessor (e.g., 8085, 8086) with a keyboard and display unit.

• Keyboard Section: Scans and debounces keypresses, supports multiple keypress detection.
• Display Section: Controls multiplexed 7-segment displays or alphanumeric displays.
• FIFO Buffer: Stores keypress data before sending it to the CPU.

Pin Diagram of 8279

Features of 8279
✔ Interfacing for up to 64-key keyboards and 16-digit displays.
✔ FIFO buffer for storing keypress data before the CPU reads it.
✔ Supports 7-segment, alphanumeric, and LED displays.
✔ Debouncing and auto-repeat for key detection.
✔ Supports single and multi-key mode.
✔ Interrupt-based keyboard input handling.
✔ Programmable scan timing and display intensity control.

Pin Description of 8279

Pin Description
D0 - D7 8-bit data bus (for communication with the microprocessor).
CS Chip Select (active low) to enable 8279.
RD Read signal (active low) to read data from 8279.
WR Write signal (active low) to write data into 8279.
C/D Control/Data select (1 = Control, 0 = Data).
RESET Resets 8279 to default state.
CLK Clock input for scanning and timing control.
IRQ Interrupt Request for keypress noti cation.
SL0 - SL3 Scan Lines (Used to scan rows of the keyboard).
RL0 - RL7 Return Lines (Used to detect key presses).
OUT0 - OUT3 Display Segment Control (Drives display segments).
BD Blank Display Control (Turns display off).
Internal Architecture of 8279
The 8279 consists of the following main functional blocks:

1. Keyboard Interface
◦ Scans a matrix keyboard (8×8 or 4×4 con guration).
◦ Provides debouncing and auto-repeat functions.
◦ Supports FIFO buffer (8-byte queue) for keypress storage.
◦ Supports single-key, multi-key, and encoded modes.
2. Display Interface

◦ Controls multiplexed 7-segment or LED displays.

◦ Supports 16-character display control.
◦ Provides intensity control and blanking features.
3. Control and Timing Logic

◦ Synchronizes operations with system clock.

◦ Generates interrupts for keypress detection.

Modes of Operation in 8279

The 8279 operates in two major sections:
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1. Keyboard Section Modes

• Scanned Keyboard Mode: Detects keypresses in a row-column format (8×8 matrix).

• Scanned Sensor Mode: Reads digital sensors instead of keypresses.
• Encoded Mode: Directly provides ASCII code for keypresses.
2. Display Section Modes

• Left Entry Mode: Data displayed from left to right.

• Right Entry Mode: Data displayed from right to left.

Control Word Format (Command Register)

The Control Register is used to con gure 8279's keyboard and display settings.

D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0
--------------------------------------
Mode | Scan Rate | Keyboard | Display
Bit Function
D7-D6 Keyboard mode (Scanned/Encoded).
D5-D4 Scan Rate (Determines scanning speed).
D3 Auto-repeat enable (1 = Enable, 0 = Disable).
D2 Key debounce (1 = Enable, 0 = Disable).
D1-D0 Display Mode (Left/Right Entry).

Interfacing 8279 with 8085 Microprocessor

• 8279 is memory-mapped or I/O-mapped to 8085.
• Data bus (D0-D7) is connected to CPU data lines.
• Control signals (RD, WR, CS, C/D) manage data ow.
• Scan and Return lines connect to the keyboard.
• Display output lines drive LED/7-segment displays.
Interfacing Diagram

+-----------+ +---------+
| 8085 CPU | ----> | 8279 |
+-----------+ +---------+
| |
(RD) (WR)
| |
(A0, A1) (CS, RESET)
| |
SL0-SL3 → Keyboard Scan Rows
RL0-RL7 ← Keyboard Return Lines
OUT0-OUT3 → Display Segments
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Programming 8279
Step 1: Initialize 8279 (Keyboard & Display Mode)

MVI A, 10011000B ; Keyboard mode: Scanned keyboard, auto-

repeat enabled
OUT 08H ; Send control word to 8279
Step 2: Set Display Mode

MVI A, 00000001B ; Display Mode: Right Entry

OUT 09H ; Send display mode command
Step 3: Load Data to Display

MVI A, 'H' ; Load ASCII value of 'H'

OUT 0AH ; Send data to display buffer
Step 4: Read Keypress from Keyboard

IN 0BH ; Read key from FIFO buffer

MOV B, A ; Store received keypress in register B
Applications of 8279
✔ Keyboards for Embedded Systems (Digital Keypads, ATMs, POS systems)
✔ LED Display Systems (7-segment, Alphanumeric, LED matrix)
✔ Industrial Automation (Process control panels, sensor interfaces)
✔ Medical Instruments (Input panels for monitoring devices)
✔ Point-of-Sale (POS) terminals and cash registers

Intel 8259 – Priority Interrupt Controller (PIC)

The Intel 8259 is a programmable interrupt controller (PIC) that manages hardware
interrupts and prioritizes them before sending them to the microprocessor. It is commonly used
with 8085 and 8086 microprocessors to handle multiple interrupt requests ef ciently.

Why is 8259 Needed?

• The 8085 has only ve interrupt lines (TRAP, RST7.5, RST6.5, RST5.5, and INTR),
which are not suf cient for complex systems.
• The 8086 supports only two hardware interrupts (NMI & INTR).
• 8259 allows up to 8 interrupts to be managed and can be cascaded to handle up to 64
interrupts.
• It assigns priority to interrupts and sends them to the processor in the correct order.
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Pin Diagram of 8259

Features of 8259
✔ Handles up to 8 interrupt requests (IR0-IR7).
✔ Can be cascaded to support up to 64 interrupts.
✔ Allows priority assignment to interrupts.
✔ Supports edge-triggered and level-triggered interrupts.
✔ Supports maskable and non-maskable interrupts.
✔ Communicates with the CPU using an interrupt vector.
✔ Fast interrupt handling using a priority resolver.

Pin Description of 8259

Pin Description
D0 - D7 8-bit data bus (for communication with the microprocessor).
CS Chip Select (active low) to enable 8259.
RD Read signal (active low) to read data from 8259.
WR Write signal (active low) to write data into 8259.
A0 Address line (selects command/data register).
INT Interrupt output signal to CPU (high when an interrupt is pending).
INTA Interrupt Acknowledge signal from CPU.
IR0 - IR7 Interrupt Request Lines (inputs for external devices).
CAS0 - CAS2 Cascade lines for multiple 8259s (used in multi-controller mode).
SP/EN Single Processor (SP) or Enable (EN) mode selection.
 Internal Architecture of 8259
The 8259 consists of the following major functional blocks:

1. Interrupt Request Register (IRR)

◦ Stores all incoming interrupt requests (IR0-IR7).
◦ Keeps track of which interrupts are pending.
2. Interrupt Mask Register (IMR)

◦ Allows masking (disabling) of speci c interrupts.

◦ If a bit is set, the corresponding interrupt is ignored.
3. In-Service Register (ISR)

◦ Stores the interrupt currently being serviced.

◦ Prevents the same interrupt from being processed again.
4. Priority Resolver

◦ Determines which interrupt has the highest priority.

◦ Sends the interrupt request to the CPU.
5. Control Logic

◦ Handles communication between CPU and 8259.

◦ Supports interrupt acknowledge (INTA) cycles.

Operating Modes of 8259

1. Fully Nested Mode
◦ Highest priority is assigned to IR0, lowest to IR7.
◦ When an interrupt is being serviced, lower-priority interrupts are blocked.
2. Special Fully Nested Mode

◦ Used when multiple 8259s are cascaded.

3. Automatic End of Interrupt (AEOI) Mode
◦ Automatically clears the ISR after the CPU acknowledges the interrupt.
4. Speci c Rotation Mode
◦ Allows changing the priority dynamically.
5. Buffered Mode
◦ Used when multiple 8259s share the data bus.

Interfacing 8259 with 8085 Microprocessor

• The 8259 is connected to the 8085 through the data bus and control signals.
• The INT output of 8259 is connected to INTR of 8085.
• The INTA (Interrupt Acknowledge) from 8085 is connected to INTA input of 8259.
• Interrupt Request (IR0-IR7) lines are connected to external devices.
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Programming 8259
Step 1: Initialize 8259 (ICW1)

MVI A, 00010011B ; ICW1: Edge-triggered, Single 8259, ICW4

needed
OUT 08H ; Send to 8259 command register
Step 2: Set Base Interrupt Vector (ICW2)

MVI A, 00001000B ; ICW2: Interrupt vector address

OUT 09H ; Send to 8259
Step 3: Con gure Interrupt Mode (ICW3 & ICW4)

MVI A, 00000000B ; ICW3: Single 8259 (Not cascaded)

OUT 0AH ; Send to 8259
MVI A, 00000001B ; ICW4: Normal mode, Non-buffered
OUT 0BH ; Send to 8259
Step 4: Enable Speci c Interrupts (OCW1)

MVI A, 11111101B ; OCW1: Enable IR1, disable others

OUT 0CH ; Send to 8259 mask register

Interrupt Handling Process

1. A device raises an interrupt request (IR0-IR7).
2. The 8259 checks priority and sends INT to the CPU.
3. The CPU acknowledges the interrupt using INTA.
4. The 8259 sends the interrupt vector address.
5. The CPU jumps to the corresponding Interrupt Service Routine (ISR).
6. Once the ISR is completed, the interrupt is cleared.

Applications of 8259
✔ Embedded Systems (Microcontroller-based devices)
✔ Computer Systems (PCs, Servers, and Embedded Processors)
✔ Real-Time Systems (Industrial automation, medical devices)
✔ Communication Systems (Network interface cards, routers)
✔ Defense & Aerospace (Radar systems, military communication)
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