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Verilog Program

The document provides Verilog code for a Half Adder and a Full Adder, including Gate Level, Dataflow, and Behavioral modeling for both. It also includes test bench programs to simulate the functionality of these adders. Each section demonstrates how to implement and test the logic for summing binary inputs and generating carry outputs.

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Varsha Varsha
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4 views

Verilog Program

The document provides Verilog code for a Half Adder and a Full Adder, including Gate Level, Dataflow, and Behavioral modeling for both. It also includes test bench programs to simulate the functionality of these adders. Each section demonstrates how to implement and test the logic for summing binary inputs and generating carry outputs.

Uploaded by

Varsha Varsha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Half Adder

Verilog Program:
Gate Level Modelling:
module half_adder_structural (
input a, // Input 'a'
input b, // Input 'b'
output s, // Output 's' (Sum)
output c // Output 'c' (Carry)
);
xor gate_xor (s, a, b); // XOR gate for sum
and gate_and (c, a, b); // AND gate for carry
endmodule

Dataflow Modelling:
module half_adder_dataflow (
input a, // Input 'a'
input b, // Input 'b'
output s, // Output 's' (Sum)
output c // Output 'c' (Carry)
);

assign s = a ^ b; // Dataflow expression for sum


assign c = a & b; // Dataflow expression for carry
endmodule

Behavioural Modelling:
module half_adder_behavioural (
input a, // Input 'a'
input b, // Input 'b'
output s, // Output 's' (Sum)
output c // Output 'c' (Carry)
);
// Combinational logic equations for sum and carry
always @(a,b)
s = a ^ b; // XOR operation for sum
c = a & b; // AND operation for carry
endmodule

Test Bench Program:


module half1_adder;
// Declare registers
reg d; // Register 'd' for input 'a'
reg e; // Register 'e' for input 'b'
// Declare wires
wire f; // Wire 'f' for output 's' (Sum)
wire g; // Wire 'g' for output 'c' (Carry)

// Instantiate half_adder module


half_adder half2_adder (.a(d), .b(e), .s(f), .c(g));

// Initial block for simulation


initial begin
$dumpvars(1, half1_adder); // Enable waveform dumping for simulation

// Test case 1
d = 1'b1; // Assign input 'a' as 1
$display("a=%b", d); // Display value of input 'a'
e = 1'b1; // Assign input 'b' as 1
$display("b=%b", e); // Display value of input 'b'
#10; // Wait for 10 time units
$display("s=%b", f); // Display value of output 's' (Sum)
$display("c=%b", g); // Display value of output 'c' (Carry)

// Test case 2
d = 1'b0; // Assign input 'a' as 0
$display("a=%b", d); // Display value of input 'a'
e = 1'b1; // Assign input 'b' as 1
$display("b=%b", e); // Display value of input 'b'
#10; // Wait for 10 time units
$display("s=%b", f); // Display value of output 's' (Sum)
$display("c=%b", g); // Display value of output 'c' (Carry)

// Test case 3
d = 1'b1; // Assign input 'a' as 1
$display("a=%b", d); // Display value of input 'a'
e = 1'b0; // Assign input 'b' as 0
$display("b=%b", e); // Display value of input 'b'
#10; // Wait for 10 time units
$display("s=%b", f); // Display value of output 's' (Sum)
$display("c=%b", g); // Display value of output 'c' (Carry)

// Test case 4
d = 1'b0; // Assign input 'a' as 0
$display("a=%b", d); // Display value of input 'a'
e = 1'b0; // Assign input 'b' as 0
$display("b=%b", e); // Display value of input 'b'
#10; // Wait for 10 time units
$display("s=%b", f); // Display value of output 's' (Sum)
$display("c=%b", g); // Display value of output 'c' (Carry)
end
endmodule
Full Adder
Verilog Program:
Gate Level Modelling:
module full_adder_s (
input a,b, Cin,
output sum,carry
);
wire w1,w2,w3,w4; //Internal connections
xor(w1,a,b);
xor(sum,w1, Cin); //Sum output
and(w2,a,b);
and(w3,b, Cin);
and(w4, Cin,a);
or(carry,w2,w3,w4); //carry output
endmodule

Dataflow Modelling:
module full_adder_d (
input a,b, Cin,
output sum,carry
);
assign sum = a ^ b ^ Cin;
assign carry = (a & b) | (b & Cin) | (Cin & a) ;
endmodule

Behavioural Modelling:
module full_adder_d (
input a,b, Cin,
output sum,carry
);
always @(a, b, Cin)
sum = a ^ b ^ Cin;
carry = (a & b) | (b & Cin) | (Cin & a) ;
endmodule

Test Bench Program:


module tb_top;
reg a, b, Cin;
wire s, c_out;
full_adder fa(a, b, c, s, c_out);
initial begin
$monitor("At time %0t: a=%b b=%b, cin=%b, sum=%b, carry=%b",$time,
a,b,c,s,c_out);
a = 0; b = 0; Cin = 0; #1;
a = 0; b = 0; Cin = 1; #1;
a = 0; b = 1; Cin = 0; #1;
a = 0; b = 1; Cin = 1; #1;
a = 1; b = 0; Cin = 0; #1;
a = 1; b = 0; Cin = 1; #1;
a = 1; b = 1; Cin = 0; #1;
a = 1; b = 1; Cin = 1;
end
endmodule

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