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DLD_Labaratory_Task_1

The document is a laboratory report from Addis Ababa Science and Technology University focusing on Digital Logic Design. It includes activities on basic gates (NOT, AND, OR), derived gates (NAND, NOR, X-OR, X-NOR), and universal gates using NAND. Each section presents input-output results and discussions for various logic gate configurations.

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4 views

DLD_Labaratory_Task_1

The document is a laboratory report from Addis Ababa Science and Technology University focusing on Digital Logic Design. It includes activities on basic gates (NOT, AND, OR), derived gates (NAND, NOR, X-OR, X-NOR), and universal gates using NAND. Each section presents input-output results and discussions for various logic gate configurations.

Uploaded by

hawiguteta96
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Addis Ababa Science and Technology University

College of Engineering; Department of Electrical & Computer Engineering


Digital Logic Design Laboratory Report 1

No Name Id Section
1
2
3
4
5
6
7
8

Activity One: Basic gates


1- NOT gates
Results: Discuss
Input Output
0/LOW/FALSE/
1/HIGH/TRUE/

2- AND gates
Results:
INPUT 1 INPUT 2 OUTPUT Discuss
0 0
0 1
1 0
1 1

3- OR gates
Results:
INPUT 1 INPUT 2 OUTPUT Discuss
0 0
0 1
1 0
1 1

August 27, 2023 1


Addis Ababa Science and Technology University
College of Engineering; Department of Electrical & Computer Engineering
Digital Logic Design Laboratory Report 1

Activity Two: Derived gates


1- NAND
Results:
INPUT 1 INPUT 2 OUTPUT Discuss
0 0
0 1
1 0
1 1

2- NOR
Results:
INPUT 1 INPUT 2 OUTPUT Discuss
0 0
0 1
1 0
1 1

3- X-OR
Results:
INPUT 1 INPUT 2 OUTPUT Discuss
0 0
0 1
1 0
1 1

4- X-NOR
Results:
INPUT 1 INPUT 2 OUTPUT Discuss
0 0
0 1
1 0
1 1

August 27, 2023 2


Addis Ababa Science and Technology University
College of Engineering; Department of Electrical & Computer Engineering
Digital Logic Design Laboratory Report 1

Activity Three: Universal Gates- NAND


1- NOT gate:

Design Results and Discussion


Input Output
0/LOW/FALSE/
1/HIGH/TRUE/

2- AND Gate

Design Results and Discussion


INPUT 1 INPUT 2 OUTPUT
0 0
0 1
1 0
1 1

3- OR Gate:

Design Results and Discussion


INPUT 1 INPUT 2 OUTPUT

0 0
0 1
1 0
1 1

August 27, 2023 3

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