Module 4 Ppt
Module 4 Ppt
Memory Management
• Logical address:It is a virtual address generated
by the CPU that can be viewed by the user
• Logical address is generated by the CPU during a
program execution
• The logical address is virtual as it does not exist
physically.Hence it is also called virtual address
• This address is used as a reference to access the
physical memory location(physical address)
• Logical address space:set of all logical address
generated by the CPU in reference to a program is
referred as logical address space
• Physical address is a location in a memory unit
• The user can never view the physical address of
program
• The user cannot directly access the physical
address.Instead the physical address is accessed
by its corresponding logical address.
• Physical address space:Set of physical address
corresponding to the logical address is called
physical address space
Address binding
• The Address Binding refers to the mapping of computer
instructions and data to physical memory locations.
• Both logical and physical addresses are used in
computer memory.
• It assigns a physical memory region to a logical pointer
by mapping a physical address to a logical address
known as a virtual address.
• The Memory Management Unit (MMU) translates
logical addresses into physical (RAM) addresses.
Mapping a logical address to a physical address is
called address binding or address mapping.
• There are mainly three types of an address
binding in the OS.
• Compile Time Address Binding
• Load Time Address Binding
• Execution Time or Dynamic Address Binding
Compile Time Address Binding
• It is the first type of address binding.
• It occurs when the compiler is responsible for
performing address binding, and the compiler interacts
with the operating system to perform the address
binding.
• when a program is executed, it allocates memory to
the system code of the computer.
• It will be done before loading the program into
memory.
• The compiler requires interacts with an OS memory
manager to perform compile-time address binding.
• The address binding assigns a logical address
to the beginning of the memory segment to
store the object code.
Load Time Address Binding
m =???
2 m = 64 × 1024
m 6 10
2 =2 ×2
m 16
2 =2
»» m=16
b)How many bits are there in the
physical address?
Let (x) is number of bits in the physical address
x =???
Size of physical address space 2x= No of frames × frame size (frame size =
page size )
2 x =25 × 210
2 x = 215
P1(15 KB)
20 KB
10 KB
750 KB
125 KB
• First Fit Algorithm :
• 115 KB is put in 300 KB partition, leaving (185
KB, 600 KB, 350 KB,200 KB, 750 KB, 125 KB)
• 500 KB is put in 600 KB partition, leaving (185 KB,
100 KB, 350 KB,200 KB, 750 KB, 125 KB)
• 358 KB is put in 750 KB partition, leaving (185
KB, 100 KB, 350 KB,200 KB, 392 KB, 125 KB)
• 200 KB is put in 350 KB partition, leaving (185 KB,
100 KB, 150 KB,200 KB, 392 KB, 125 KB)
• 375 KB is put in 392 KB partition, leaving (185
KB, 100 KB, 150 KB,200 KB, 17 KB, 125 KB)
Memory size PROCESS Process size Internal
fragmentation
300 kb p1 115kb 185 kb
600 kb p2 500 kb 100 kb
350 kb p4 200 kb 150 kb
200 kb
750 kb P3,p5 (358),375 (392),17 kb
125 kb
• Best Fit Algorithm :
• 115 KB is put in 125 KB partition, leaving (300 KB, 600
KB, 350 KB,200 KB, 750 KB, 10 KB)
• 500 KB is put in 600 KB partition, leaving (300 KB, 100
KB, 350 KB,200 KB, 750 KB, 10 KB)
• 358 KB is put in 750 KB partition, leaving (300 KB, 100
KB, 350 KB,200 KB, 392 KB, 10 KB)
• 200 KB is put in 200 KB partition, leaving (300 KB, 100
KB, 350 KB, 0KB, 392 KB, 10 KB)
• 375 KB is put in 392 KB partition, leaving (300 KB, 100
KB, 350 KB, 0KB, 17 KB, 10 KB)
• 115 KB is put in 750 KB partition, leaving (300 KB,
600 KB, 350 KB,200 KB, 635 KB, 125 KB)
• 500 KB is put in 635 KB partition, leaving (300 KB,
600 KB, 350 KB,200 KB, 135 KB, 125 KB)
• 358 KB is put in 600 KB partition, leaving (300 KB,
242 KB, 350 KB,200 KB, 135 KB, 125 KB)
• 200 KB is put in 350 KB partition, leaving (300 KB,
242 KB, 150 KB,200 KB, 135 KB, 125 KB)
• 375 KB has to wait as no space is available which
is having 375KB of Free Memory
Memory partitioning
1. Fixed Partitioning : (Multiple Partitioning)
• Multi-programming with fixed partitioning is a
contiguous memory management technique in which
the main memory is divided into fixed sized partitions
which can be of equal or unequal size.
• Whenever we have to allocate a process memory then
a free partition that is big enough to hold the process
is found.
• Then the memory is allocated to the process.If there is
no free space available then the process waits in the
queue to be allocated memory. It is one of the most
oldest memory management technique which is easy
to implement.
2. Variable Partitioning :
• Multi-programming with variable partitioning is a
contiguous memory management technique in
which the main memory is not divided into
partitions and the process is allocated a chunk of
free memory that is big enough for it to fit.
• The space which is left is considered as the free
space which can be further used by other
processes. It also provides the concept of
compaction.
• In compaction the spaces that are free and the
spaces which not allocated to the process are
combined and single large memory space is
made.
S.NO. Fixed partitioning Variable partitioning
In multi-programming with
In multi-programming with fixed partitioning
variable partitioning the
1. the main memory is divided into fixed sized
main memory is not divided
partitions.
into fixed sized partitions.
It does not utilize the main memory It utilizes the main memory
3.
effectively. effectively.
Degree of multi-
5. Degree of multi-programming is less.
programming is higher.
It is less easier to
6. It is more easier to implement.
implement.
Paging
• Paging is a memory management scheme that
eliminates the need for contiguous allocation
of physical memory.
• The process of retrieving processes in the
form of pages from the secondary storage into
the main memory is known as paging.
• For implementing paging ,the physical and logical
memory spaces are divided into the same fixed-
sized blocks.
• These fixed-sized blocks of physical memory are
called frames, and the fixed-sized blocks of logical
memory are called pages.
• One page of the process is to be stored in one of
the frames of the memory. The pages can be
stored at the different locations of the memory
but the priority is always to find the contiguous
frames or holes.
• The address generated by CPU for accessing
the frame is divided into two parts i.e. page
number and page offset.
Page Table
• Page table is a data structure.
• It maps the page number referenced by the CPU
to the frame number where that page is stored.
• Page table is stored in the main memory.
• Number of entries in a page table = Number of
pages in which the process is divided.
• Page Table Base Register (PTBR) contains the base
address of page table.
• Each process has its own independent page table.
• Page Table Base Register (PTBR) provides the
base address of the page table.
• The base address of the page table is added
with the page number referenced by the CPU.
• It gives the entry of the page table containing
the frame number where the referenced page
is stored.
• Page Table Entry
1. Segment Base
• A segment's base address is also referred to as the
segment base. The memory segments' starting physical
addresses are contained in the segment base.
2. Segment Limit
• Another name for the segment limit is segment offset.
The segment's precise length is contained within it.
• Segment Table Base Register is referred to as STBR. The
segment table's base address is kept in the STBR.
• Segment Table Length Register, also known as STLR. The
number of segments a programme uses is stored in STLR.
The segment table itself is kept in the main memory as a
separate segment. If there are many segments, the
segment table may occasionally use a lot of memory.
TLB(Translation Lookaside Buffer)
• It is a memory cache which is closer to the CPU and the time taken
by CPU to access TLB is lesser then that taken to access main
memory.
• In other words, we can say that TLB is faster and smaller than the
main memory but cheaper and bigger than the register.