International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 11 Issue: 04 | Apr 2024 www.irjet.net p-ISSN: 2395-0072

HDL implementation for real-time image properties adjustments

Sri Lakshmi [1], Mery Lavanya [2], Nikhilesh Mohan [3], Naga Pavan [4], Kavya Reddy [5]

1Associate Professor, Dept. Electronics & Communication Engineering, SR Gudlavalleru Engineering College,
Gudlavalleru, Andhra Pradesh, India.
2,3,4,5Undergraduate Students in, Dept. Electronics & Communication Engineering, SR Gudlavalleru Engineering

College, Gudlavalleru, Andhra Pradesh, India.

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Abstract - areas. First, it enhances human understanding by improving
the interpretation and clarity of visual information in images.
Real-time image processing demands high performance that Second, it optimizes image data representation for efficient
surpasses the capacity of conventional software-based storage, transmission, or tailored use in automated machine
techniques. This paper explores the utilization of Field- perception systems. The basic principle behind any
Programmable Gate Arrays (FPGAs) with Verilog HDL to enhancement method is to generate a demonstrably superior
achieve hardware-accelerated image enhancement. Verilog result compared to the original image, specifically catering to
implementation for fundamental image processing operations, the requirements of a particular application [3].
including thresholding, contrast adjustment, brightness
There are two main image enhancement methods: spatial
manipulation, and inversion is being implemented. These
domain and frequency domain methods. [4,5] Spatial domain
operations are fulfilled by performing logical operations on
methods directly manipulate the pixels within an image
the pixels of the subject image. Compared to software-based
plane, leveraging the image's inherent pixel structure.
approaches, this hardware design offers significant speed
Frequency domain methods, on the other hand, utilize
advantages due to the parallel processing capabilities of
mathematical transforms to induce enhancements within the
FPGAs. This approach is particularly well-suited for real-time
image's frequency domain using techniques like the Fourier
applications where immediate image processing is critical .
transform. Some of the earliest and most effective spatial
Key Words: Image Processing, Verilog HDL, Image domain techniques involve adjustments to an image's
Operations brightness, contrast, or color. These adjustments are often
employed to address limitations encountered during image
1. INTRODUCTION acquisition. For instance, image processing can increase the
overall brightness of a target object, revealing previously
The ever-increasing demand for high-performance digital obscured details, or magnify subtle variations in contrast,
signal processing (DSP) applications necessitates the search allowing for clearer interpretation. As established in various
for efficient scheduling methods. Hardware design languages studies, each pixel value is determined solely by its
(HDLs) have emerged as a powerful tool for hardware corresponding value at the same position within the image,
designers, offering a unique blend of simulation capabilities independent of its neighbors. A function is applied to map
and real-world hardware implementation [1]. This paper the original pixel values to their enhanced counterparts, with
explores the benefits of HDLs, particularly their ability to functions operating independently of image coordinates
carefully simulate and test digital circuits, also and being classified as global or homogeneous operations.
incorporates important timing considerations how this
1.2 Significance of FPGA
functionality translates seamlessly into the DSP field,
enabling designers to optimize productivity and maintain This paper addresses the limitations of software-based
hardware availability. In addition, the paper explores the use image processing, MATLAB especially its struggle to achieve
of Field-Programmable Gate Arrays (FPGAs) in conjunction real-time performance due to sequential processing. Field-
with HDLs. Using conventional HDLs and traditionally Programmable Gate Arrays (FPGAs) are used and
configured, FPGAs provide a flexible, cost-effective hardware programmed with Verilog HDL to overcome this constraint
platform for implementing DSP algorithms [2]. Verilog HDL and obtain the actual evolution time of the image. [6] An
and Very High-Speed Integrated Circuits (VHSIC) HDL, the alternative approach I being put forward as FPGAs provide
two primary HDLs used for FPGA design, will be covered greater efficiency by implementing parallel hardware
along with their key characteristics and how they help to operations, resulting in significant performance gains
streamline the DSP design process. compared to traditional software approaches Furthermore,
Verilog HDL optimization also provides a potentially cost-
1.1 Image Enhancement Operations effective solution. This research paves the way for significant
advances in real-time imaging, opening the doors for
Image enhancement remains a cornerstone of digital image applications in critical areas such as medical imaging,
processing, providing significant value in two key application autonomous vehicles and security systems.

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2. Point Operations consumption. This experiment is expected to show the

superiority of System Generator for FPGA algorithm design,
Point functions provide a powerful way to manipulate highlighting its great processing power in real-time image
individual pixel values in an image. [7] This operation processing tasks [2].
modifies the characteristics of individual pixels without
affecting the size, form, or local relationships between 4. Approach
adjacent pixels of the image as a whole. The new value of
each pixel, denoted by a = I (u, v), is determined by its initial Bitmap image format has been utilized for this process. BMP
value, a = I (u, v), at the same location. This independence is a simple, uncompressed format developed by Microsoft. It
from the surrounding pixels allows for precise control of produces very huge file sizes since it stores every pixel in the
individual intensities. Each pixel in the image (represented image without any compression. BMP can be useful for
by coordinates (u, v)) has a function, f(a), applied to it in storing raw image data for further processing or in
order to convert the original values to their improved situations where preserving every detail is crucial.
counterparts.

a' ← f (a) I' (u, v) ← f (I (u, v))

Equation 1: Point operations for the proposed approach

From the above Equation 1, f () is a function that represents

the coordinates of the image, the operation is classified as
global or unitary. Common examples of such homogeneous
point operations include optimized intensity conversion
("curve"), image quantization (or "posterization"), global
thresholding, gamma correction, and various color Fig. 1: Block Diagram of the suggested methodology
conversions
Although Verilog provides a powerful file format, its primary
3. Previous Work functionality is limited to ASCII characters. This presents a
challenge when working with common models such as BMP,
Image conversions often introduce quality degradation. To which cannot be directly read by Xilinx software. To
counteract this, image enhancement techniques are overcome this limitation, as an alternative approach to
employed to improve visual quality. These techniques image preprocessing in MATLAB. Here, as shown in the Fig.
include contrast stretching, brightness control, inversion, 1, the BMP file is converted from its original format to a
thresholding, and more. While both software and hardware standard hex file containing only the necessary information:
implementations exist for image enhancement, hardware RGB vectors for each pixel.
offers superior performance. This project focuses on utilizing
a reconfigurable hardware system, specifically Field- 4.1 Image Data
Programmable Gate Arrays (FPGAs), to achieve real-time
image enhancement. This approach leverages Hardware An image's red, green, and blue (RGB) elements are stored in
Description Languages (HDLs) for programming, offering a different memory blocks. These memory blocks can be
novel technique within the digital system design domain implemented using either external memory chips or internal
using Very-Large-Scale Integration (VLSI) [1]. memory built into the processing unit, depending on factors
like cost and processing speed. To access the color
Field-programmable gate arrays (FPGAs) have emerged as a information for a specific pixel, the code reads data from a
powerful platform for real-time image processing. Compared designated memory address for each color channel. The
to programmable digital signal processors (DSPs), FPGAs value retrieved from this address corresponds to the
offer much higher performance due to their application- intensity of that color component for that particular pixel.
specific hardware implementation. This work delves into The original image is as shown in the Fig. 2.
image enhancement algorithms implemented on FPGAs,
focusing on techniques such as brightness control, contrast
propagation, negative transformation, thresholding, filtering
and more. The program uses the System Generator tool in
MATLAB to develop a modular image algorithm platform.
This platform facilitates the development and
implementation of image processing algorithms on FPGAs.
After installing the algorithms on the Spartan-3E
development board, subsequent experiments are conducted
to evaluate the impact on display image quality and resource

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Fig. 2: Original Image Fig. 4: Inverted Image

5. Results 5.3 Threshold Operation

5.1 YUV Conversion Conditional thresholding operation within an image

processing framework is implemented by calculating
Weighted sum of the red, green, and blue components for average pixel intensity and comparing it to a predefined
each color (red, green, blue) of the output YUV image is threshold. If the average intensity exceeds the threshold, the
performed. These weights are specific to the YUV conversion pixel is set to white (maximum intensity = 255) for all color
and determine how each color contributes to the luminance channels (red, green, blue). Conversely, if the intensity falls
(brightness) and chrominance (color) information. These are below the threshold, the pixel is set to black (minimum
then added with offset value 128 and then divided by 256 for intensity = 0). Fig. 5 represents threshold converted image.
scaling. An additional offset (16 or 128) is added to the final
values to ensure the output falls within the expected range
for YUV components. Fig. 3 represents the YUV converted
image.

Fig. 5: Result for Threshold Operation

5.4 Contrast Adjustment

A pixel's average RGB value is first compared to a
Fig. 3: YUV converted image predetermined threshold value. Each color channel is
brightened by the code if the average intensity is higher than
5.2 Image Inversion the threshold. To prevent overflow and maintain valid color
value, the code checks if the temporary value exceeds the
Intensity of the pixel is calculated by summing its red, green, maximum intensity (255). If it does, the color value is set to
and blue components. Assuming that the original color the maximum value (255). Otherwise, the adjusted intensity
values range from 0 (darkest) to 255 (brightest), the code from the temporary variable is assigned back to the value.
then inverts each color by subtracting the intensity from the Conversely, if the average intensity falls below the threshold,
maximum value (255). This basically makes the color detail the code performs a darkening operation by subtracting the
float on the color, making bright areas appear darker, and same fixed value (Value) from the original intensity of each
vice versa. Finally, the converted colors are stored back into color channel and storing the result in temporary variables.
the pixel’s data, possibly for use in updating the image. This This could be used for improving image quality and for
operation can aid in edge detection. Fig. 4 shows the better analysis. The image after contrast adjustments is
inverted image for the give original input. shown in Fig. 6.

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Volume: 11 Issue: 04 | Apr 2024 www.irjet.net p-ISSN: 2395-0072

Fig. 6: Result for Contrast Adjustment Fig. 8: Brightness enhanced Image

5.5 HSV Conversion

The image's color scheme is now HSV (hue, saturation,
value) instead of RGB (red, green, and blue). The RGB values
of a pixel are extracted and find the most dominant (highest
intensity) and least dominant (lowest intensity) colors. Hue
is calculated based on the primary color and the contrast
between color components.

Fig. 9: Brightness degraded image

5.7 Gray Level Slicing

Changing pixel intensity based on a specific brightness range
is called gray level slicing. The average intensity is calculated
by combining its red, green, and blue values. If the average
intensity falls within a specific range (based on
requirement), the code sets all those color values (red, green,
Fig. 7: Result for HSV Conversion and blue) to their maximum value (typically 255), effectively
making the pixel white. Otherwise, the original color values
Saturation reflects color purity and is determined by the are left as they are. This method selectively brightens pixels
change in intensity relative to maximum intensity. Finally, within a certain intensity range. For the result which is
value represents the brightness, and is set to the maximum shown in Fig. 10, the pixels in between 50 and 90 will
intensity as shown in Fig. 7. become 255(white) and remaining will be as it is.

5.6 Brightness Manipulation

Intensity values of each color (red, green, and blue) are
retrieved from the memory. This value is then incremented
by adding a default constant. The process ensures that the
final value does not exceed a maximum limit (255). If the
combination pushes the temporary value beyond this limit, it
is lowered back to the maximum value to remove invalid
character data. Otherwise, the incremented value is used as
the final output. Decrementing of the value is performed for
brightness degradation with similar steps as enhancement. Fig. 10: Result for Gray level slicing

5.8 Grayscale Image

Obtained by calculating weighted sum of the red, green, and
blue components. The selection of these weights is intended
to mimic the sensitivity of the human eye to various hues.
Later divided by 256 to scale the value down to gray scale
intensity range. The resulting weighted average represents
the grayscale intensity of the pixel. By setting all color
channels to the same value, the pixel loses its color
information and becomes a shade of gray. This could be
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used to create artistic effects as shown in Fig. 11 and modify 5. Contrast operation
image for specific purposes. 6. Gray level slicing operation
7. HSV conversion operation
8. Gray scale operation
9. YUV conversion operation

Table 1: Timing and Device Utilization Summary

1 2 3 4 5 6 7 8 9
Slice Logic Utilization
Numbe 0% 0% 0% 0% 0% 0% 0 0% 0%
r of %
Fig. 11: Grayscale Image Slice
Registe
6. Power Analysis rs
Numbe 0% 0% 0% 0% 0% 0% 3 0% 0%
With the image transferred to memory, the processed data
r of %
containing RGB components is now saved as a hex file and is Slice
converted into a bmp file to acquire the output image. LUTs
Power analysis in circuit design, especially with Field-
Programmable Gate Arrays (FPGAs) from Xilinx, is the Numbe 0% 0% 0% 0% 0% 0% 3 0% 0%
process of determining how much power the digital circuit r used %
as Logic
will use in the design stage. Utilizing software that examines
the hardware description—which is frequently written in Slice Logic Distribution
Verilog—and takes into account variables like operation
Numbe 12 12 13 11 22 13 63 94 16
frequency and logic gate usage, this assessment is r of LUT 7 4 7 3 6 9 50 0
accomplished. A truly efficient system sets a balance Flip
between high performance and low energy usage. Flop
pairs
So, the power observed after performing the above used
operation were obtained as shown in the Fig. 12.
Numbe 59 58 73 74 76 62 99 70 67
r with % % % % % % % % %
an
unused
Flip
Flop
Numbe 7% 8% 7% 8% 4% 7% 0 10 17
r with % % %
an
unused
Fig. 12: Power Supply Summary LUT
6.1 Device Utilization and Timing Summary: Numbe 33 33 18 16 18 30 0 19 15
r of % % % % % % % % %
The percentage of resources, such as logic components and fully
memory blocks, used by the design on the selected device is used
disclosed in the Device Utilization report. This aids in LUT-FF
pairs
determining whether the gadget can manage the
incorporated functions. Timing Summary analyzes the Numbe 4 4 4 4 7 4 6 4 4
timing properties, examines flip-flop data setup and hold r of
times, clock frequencies, and signal delays in logic routes. unique
The operations are represented in the below order control
sets
respectively.
IO Utilization
1. Brightness enhancement operation
2. Brightness degradation operation Numbe 25 25 25 25 25 25 25 25 25
r of IOs
3. Invert operation
4. Threshold operation Numbe 4% 4% 4% 4% 4% 4% 4 4% 4%

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r of % REFERENCES
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 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 11 Issue: 04 | Apr 2024 www.irjet.net p-ISSN: 2395-0072

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