MODERN INSTITUTE OF TECHNOLOGY AND RESEARCH CENTRE, ALWAR

Name of Faculty: Dr. Neeraj Jain

Subject: Microprocessor & Interfaces
Semester: IV Session: 2023-24 (Even Sem.)
Branch: CSE Batch: A
Unit: 1 Date of Submission: 12/2/2024

Lecture
Topics Covered Page No. Total Page
No.

1 Introduction 1-3 3

2 8085 MP Architecture 4-7 4

3 Memory & I/O Operation 8-10 3

4 Bus System 11-12 2

5 Pin diagram & Functions 13-17 5

Multiplexing & Demultiplexing

6 18-19 2
of Buses

7 Generation of Control Signals 20-21 2

Instruction Cycle, Machine

8 22-25 4
Cycle & T State

References:
1. R. Gaonkar, Microprocessor Architecture Programming, Penram International Publishing
2. Hall D.V., microprocessor & Interfacing-Programming & hardware, TMH, 2008

1
2
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

UNIT-1 (Introduction and Architecture of 8085)

Introduction & Evolution of Microprocessor
Lecture No.-1
A Microprocessor is an important part of computer architecture without which not possible to
perform anything on computer. It is a programmable device that takes in input perform some
arithmetic and logical operations over it and produce desired output

In simple words, a Microprocessor is a digital device on a chip which can fetch instruction from
memory, decode and execute them and give results.

Evolution of Microprocessor
Transistor was invented in 1948 (23 December 1947 in Bell lab).
IC was invented in 1958 (Fair Child Semiconductors) By Texas Instruments J Kilby.
The first microprocessor was invented by INTEL(INTegratedELectronics).
Name Year of Invention Clock Speed Size of MP

INTEL 4004/4040 1971 INTEL 4004/4040 4 Bit

8008 1972 500 kHz 8 Bit

8080 1974 2 MHz 8 Bit

8085 1976 (16-bit address bus) 3 MHz 8 Bit

1978 (16-bit data bus and 20-bit 4.77 MHz, 8 MHz, 10 16 Bit
8086
address bus) MHz
1979 (cheaper version of 8086 and
8088
8-bit external bus) 16 Bit
1982 (80188 cheaper version of
80186, and additional components
80186/80188 like interrupt controller, clock 6 MHz 16 Bit
generator, local bus controller,
counters)
1982 (data bus 16bit and address 16 Bit
80286 8 MHz
bus 24 bit)
1986 ,data bus 32-bit address bus 32 32 Bit
INTEL 80386 16 MHz – 33 MHz
bit
1986 (other versions 80486DX, 32 Bit
INTEL 80486 16 MHz – 100 MHz
80486SX, 80486DX2, 80486DX4)
PENTIUM 1993 66 MHz 32 Bit

1
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

2006 (other versions core2 duo,

INTEL core 2 1.2 GHz to 3 GHz
core2 quad, core2 extreme) 64 Bit
2.2GHz – 3.3GHz, 64 Bit
i3, i5, i7 2007, 2009, 2010 2.4GHz – 3.6GHz,
2.93GHz – 3.33GHz

Features of Microprocessor :

Clock speed: One of the earliest features of microprocessors was the clock speed, which refers to
the speed at which the processor can execute instructions. Over time, clock speeds have
increased, with modern processors capable of speeds in the billions of cycles per second (GHz).

Instruction set architecture: Microprocessors have evolved to support different instruction set
architectures, including CISC (complex instruction set computer) and RISC (reduced instruction
set computer), which affect the efficiency and complexity of processing.

Cache memory: Microprocessors now include a cache memory, which is a small amount of high-
speed memory that stores frequently used data for quicker access.

Multi-core processors: Modern microprocessors have multiple cores, allowing for multiple tasks
to be executed simultaneously, increasing performance and multitasking capabilities.

Virtualization: Microprocessors now support virtualization, which enables multiple operating systems to
run on the same physical hardware.

Power management: Modern processors include power management features, which reduce
power consumption and improve energy efficiency.

Graphics processing: Many modern microprocessors include integrated graphics processing units
(GPUs), which allow for faster and more efficient handling of graphics-intensive tasks.

Security features: Microprocessors now include security features, such as hardware-level

encryption and secure boot, to protect against malware and hacking.

Internet connectivity: Microprocessors now include built-in networking capabilities, such as Wi-
Fi and Ethernet, which allow for seamless internet connectivity.
2
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Machine learning capabilities: Some modern microprocessors include specialized processing

units for machine learning and artificial intelligence tasks, allowing for faster and more efficient
processing of these tasks

3
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

8085 MP Architecture
Lecture-2

8085 Microprocessor Architecture & Operations

It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology.

It has the following configuration −

 8-bit data bus

 16-bit address bus, which can address upto 64KB
 A 16-bit program counter
 A 16-bit stack pointer
 Six 8-bit registers arranged in pairs: BC, DE, HL
 Requires +5V supply to operate at 3.2 MHZ single phase clock

It is used in washing machines, microwave ovens, mobile phones, etc.

8085 Microprocessor – Functional Units

4
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

8085 consists of the following functional units :

Accumulator

It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is
connected to internal data bus & ALU.

Arithmetic and logic unit

As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction,
AND, OR, etc. on 8-bit data.

General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H& L. Each register can
hold 8-bit data.

These registers can work in pair to hold 16-bit data and their pairing combination is like B-C, D-E
& H-L.

Program counter

It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being executed, so
that the program counter points to the memory address of the next instruction that is going to
be executed.

Stack pointer

It is also a 16-bit register works like stack, which is always incremented/decremented by 2 during
push & pop operations.

Temporary register

It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.

Flag register
5
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.

These are the set of 5 flip-flops −

 Sign (S)
 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the Instruction
register.

Timing and control unit

It provides timing and control signal to the microprocessor to perform operations. Following are
the timing and control signals, which control external and internal circuits −

 Control Signals: READY, RD’, WR’, ALE

 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT

Interrupt control

As the name suggests it controls the interrupts during a process. When a microprocessor is
executing a main program and whenever an interrupt occurs, the microprocessor shifts the
control from the main program to process the incoming request. After the request is completed,
the control goes back to the main program.

There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP.
6
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Serial Input/output control

It controls the serial data communication by using these two instructions: SID (Serial input data)
and SOD (Serial output data).

Address buffer and address-data buffer

The content stored in the stack pointer and program counter is loaded into the address buffer
and address-data buffer to communicate with the CPU. The memory and I/O chips are connected
to these buses; the CPU can exchange the desired data with the memory and I/O chips.

Address bus and data bus

Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location
to where it should be stored and it is unidirectional. It is used to transfer the data & Address I/O
devices.

7
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Memory and I/O Operation

Lecture-3

Interfacing the 8085 microprocessor:

A microprocessor is the CPU of a computer. A microprocessor can perform some operation on a

data and give the output. But to perform the operation we need an input to enter the data and
an output to display the results of the operation. So we are using a keyboard and monitor as
Input and output along with the processor. Microprocessors engineering involves a lot of other
concepts and we also interface memory elements like ROM, EPROM to access the memory.

8
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Interfacing Types:

There are two types of interfacing in context of the 8085 Microprocessor. Memory Interfacing &
I/O Interfacing.

1. Memory Interfacing:

Memory is an integral part of a microprocessor system, and in this section, we will discuss how to
interface a memory device with the microprocessor. The Memory Interfacing in 8085 is used to
access memory quite frequently to read instruction codes and data stored in memory. This
read/write operations are monitored by control signals. The microprocessor activates these
signals when it wants to read from and write into memory.

In the last section we have already seen the memory read and memory write machine cycles, and
status of the RD, WR and IO/M status signals for read/write operation. In the following section
we will see memory structure and its requirements, concepts in Memory Interfacing in 8085 and
interfacing examples.

Memory Structure and its Requirements

As mentioned earlier, read/write memories consist of an array of registers, in which each register
has unique address. The size of the memory is N x M as shown in Figure below where N is the
number of registers and M is the word length, in number of bits.

9
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Basic Concepts in Memory Interfacing:

For Memory Interfacing in 8085, following important points are to be kept in mind.

1. Microprocessor 8085 can access 64Kbytes memory since address bus is 16-bit. But it
is not always necessary to use full 64Kbytes address space. The total memory size depends upon
the application.

2. Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as
a data memory. When both, EPROM and RAM are used, the total address space 64Kbytes is
shared by them.

3. The capacity of program memory and data memory depends on the application.

4. It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple
EPROMs and multiple RAMs as per the requirement of application.

5. We can place EPROM/RAM anywhere in full 64 Kbytes address space

But program memory (EPROM) should be located from address 0000H since reset address of
8085 microprocessor is 0000H.

6. It is not always necessary to locate EPROM and RAM in consecutive memory For
example: If the mapping of EPROM is from 0000H to OFFFH, it is not must to locate RAM from
1000H. We can locate itanywhere between 1000H and FFFFH. Where to locate memory
component totally depends on the application.

10
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Bus System
Lecture-4

There are three buses in Microprocessor:

1. Address Bus
2. Data Bus
3. Control Bus
1. Address Bus:- Generally, the Microprocessor has a 16-bit address bus. The bus over which
the CPU sends out the address of the memory location is known as the Address bus. The
address bus carries the address of the memory location to be written or to be read from.
The address bus is unidirectional. It means bits flowing occurs only in one direction, only from
microprocessor to peripheral devices.

We can find how much memory location it can use the formula 2^N. where N is the number of bits
used for address lines.

here, 2^16 = 65536bytes or 64Kb

So we can say that it can access up to 64 kb memory location.

Q.>If a processor has 4 GB memory then how many address lines are required to access this
memory?
Ans: 4GB= 4 * 1GB
4 = 2^2
11
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

1GB = 2^30

4GB = 2^2 * 2^30 = 2^32

So 32 address lines are required to access the 4 GB memory.

2. Data Bus:- 8085 Microprocessor has an 8-bit data bus. So it can be used to carry the 8-bit data
starting from 00000000H(00H) to 11111111H(FFH). Here ‘H’ tells the Hexadecimal Number. It is
bidirectional. These lines are used for data flowing in both directions means data can be
transferred or received through these lines. The data bus also connects the I/O ports and CPU. The
largest number that can appear on the data bus is 11111111.
It has 8 parallel lines of data bus. So it can access up to 2^8 = 256 data bus lines.

3. Control Bus:- The control bus is used for sending control signals to the memory and I/O
devices. The CPU sends a control signal on the control bus to enable the outputs of
addressed memory devices or I/O port devices.
Some of the control bus signals are as follows:

1. Memory read
2. Memory write

3.I/O read

4.I/O writ

12
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Pin Diagram & Functions

Lecture-5

Figure:8085PinDiagram

Figure: 8085 Pin Diagram

Allsignalscanbeclassifiedintosixgroups:

1. AddressBus
2. DataBus
3. Control&StatusSignals
4. PowerSupply&Frequencysignals
5. Externallyinitiatedsignals

13
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

6. SerialI/OPorts

1) AddressBus (pin 12to28)

 16signallinesareusedasaddressbus.
 Howevertheselinesaresplitintotwosegments:A15-A8andAD7-AD0
 A15-A8areunidirectionalandareusedtocarryhigh-orderaddressof16-bitaddress.
 AD7 -AD0areusedfordualpurpose.

2) DataBus/Multiplexed Address (pin 12to19)

 SignallinesAD7-AD0arebidirectionalandservedualpurpose.
 Theyareusedaslow-orderaddressbusaswellasdatabus.
 Theloworderaddressbuscanbeseparatefromthesesignalsbyusingalatch.

3) Control&StatusSignals
 Toidentifynatureofoperation
 TwoControlSignals
1) RD’(Read-pin32)
 Thisisareadcontrolsignal(activelow)
 ThissignalindicatesthattheselectedI/OorMemorydeviceistoberead&dat
aareavailableondatabus.
2) WR’(Write-pin31)
 Thisisawritecontrolsignal(activelow)
 ThissignalindicatesthattheselectedI/OorMemorydeviceistobewrite.
 ThreeS
tatusSi
gnals
1) S1
(pin
33)
2)S0(pin29)

 S1andS0statussignalscanidentifyvariousoperations,buttheyarerarelyusedinsm
all systems.

S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
1 1 OPCODEFET
CH

14
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

3) IO/M’(pin34)
 ThisisastatussignalusedtodifferentiateI/Oandmemoryoperation

15
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

 Whenitishigh,itindicatesanI/Ooperation
 Whenitislow,itindicatesamemoryoperation
 ThissignaliscombinedwithRD’andWR’togenerateI/O&memorycontrolsignals
 Toindicatebeginningofoperation
o OneSpecialSignalcalledALE(AddressLatchEnable-Pin 30)
o Thisispositivegoingpulsegeneratedeverytimethe8085beginsanoperation(machinec
ycle)
o ItindicatesthatthebitsonAD7-AD0areaddressbits
o Thissignalisusedprimarilytolatchthelow-
addressfrommultiplexedbus&generateaseparatesetofaddresslinesA7-A0.

4) PowerSupply&FrequencySignal
 VccPinno.40,+5VSupply
 VssPinno.20,GroundReference
 X1,X2Pinno.1&2,CrystalOscillatorisconnectedatthesetwopins.Thefrequencyisi
nternallydividedbytwo;Therefore,to operate a system
at3MHz,thecrystalshouldhaveafrequencyof6MHz.
 CLK(OUT)
Clockoutput.PinNo.37:Thissignalcanbeusedasthesystemclockforotherd
evices.

5) ExternallyInitiatedSignalsincludingInterrupts
 INTR(Input) InterruptRequest.Itisusedasgeneralpurposeinterrupt
 INTA’(Output) InterruptAcknowledge.Itisusedtoacknowledgeaninterrupt.
 RST7.5,RST6.5,RST5.5(Input) RestartInterrupts.
o Thesearevectorinterruptsthattransfertheprogramcontroltospecificmemorylocations.
o TheyhavehigherprioritiesthanINTRinterrupt.
o Amongthese3interrupts,thepriorityorderisRST7.5,RST6.5,RST5.5
 TRAP(Input) Thisisanonmaskableinterrupt&hasthehighestpriority.
 HOLD(Input)
ThissignalindicatesthataperipheralsuchasDMAContro
llerisrequestingtheuseofaddress&databuses
 HLDA(Output) HoldAcknowledge.ThissignalacknowledgestheHOLDrequest
 READY (Input)This signal is used to delay the microprocessor read or
writecycles until as low- responding peripheral is ready to send or accept data.
Whenthe signal goes low, the microprocessor waits for an integral no. of clock
cyclesuntilitgoeshigh.
 RESETIN’(Input)Whenthesignalonthispingoeslow,theProgramCounterissettozero
,thebusesaretri-stated&microprocessorisreset.
 RESETOUT(Output) This signalindicatesthatmicroprocessorisbeing

16
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

reset.Thesignalcanbeusedtoresetotherdevices.

6) SerialI/O Ports
 Twopinsforserialtransmission
1) SID(SerialInputData-pin5)
2) SOD(SerialOutputData-pin4)
 Inserialtransmission,databitsaresentoverasingleline,onebitatatime.

17
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Multiplexing & Demultiplexing of Buses

Lecture-6
For economic use of pins of microprocessor 8085, the lower order address bus is multiplexed
with the data bus. this is known as multiplexed Address/Data Bus (AD0 – AD7). the
microprocessor 8085 provides an address during the earlier part of the execution of an
instruction on the multiplexed bus (AD0 – AD7). data is also available on the same bus during
the later part of the execution of an instruction. but for proper memory or input/output
operation, the microprocessor requires the lower order address as well as data separately.

Address latch enables (ALE) signal is used to demultiplex the address/data bus. the below figure
shows the schematic of demultiplexing of address/data bus (AD0 – AD7) using a latch IC
(74LS373). the multiplexed address/data bus (AD0 – AD7) is connected as the input to the 8-bit
latch IC (74LS373). the enable input (G) of latch IC is connected to the ALE pin of the
microprocessor whereas the output control (OC) pin is grounded.

18
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

19
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Generation of Control Signals

Lecture-7

Functions of Control Pins: IO/M’ – It is a status signal which determines whether the
address is for input-output or memory. When it is high (Logic 1) the address on the address
bus is for input-output devices. When it is low (Logic 0) the address on the address bus is
for the memory. • RD’ – It is a signal to control READ operation. When it is low the selected
memory or input-output device is read. • WR’ – It is a signal to control WRITE operation.
When it goes low the data on the data bus is written into the selected memory or I/O
location.

3:8 Decoder A 3 to 8 line decoder IC 74138 is used. It has 3-inputs and 8-outputs. Three
signals from the 8085 microprocessor namely read (RD’), write (WR’) and Input
Output/Memory (IO/M’) are connected as input to the decoder. Four output signals are
taken from output pins of decoder.

Control Signals The table list input conditions required or different inputs. • S1, S0 – These
are status signals. They distinguish the various types of operations such as halt, reading,
instructions fetching or writing. • RD’, WR’ – Read and write are two basic control signals for
reading and writing operations respectively.

20
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Functions of the control signals

• MEMR’ – It indicates Memory Read operation • MEMW’ – It indicates Memory Write

operation • IOR’ – It indicates Input Read operation • IOW’ – It indicates Output Write
operation

21
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Instruction Cycle, Machine Cycle & T State

Lecture-8

Instruction Cycle in Microprocessor

The time required for the completion or execution of one instruction is

known as the Instruction Cycle in Microprocessor. The instruction cycle
consists of a –

 Fetch Instruction Cycle in Microprocessor

 Decoding Instruction Cycle in Microprocessor
 Reading effective address Instruction Cycle in Microprocessor
 Execution Instruction Cycle in Microprocessor

22
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

Fetch Instruction Cycle in Microprocessor

The next instruction is fetched by the address stored in the program counter
(PC) and then stored in the instruction register.

Decode Instruction Cycle in Microprocessor

Decoder interprets the encoded instruction from the instruction register.

Reading effective address Instruction Cycle in Microprocessor

The address given in the instruction is read from the main memory and the
required data is fetched. It depends on the direct addressing mode or the
indirect addressing mode.

Execution Instruction Cycle in Microprocessor

It consists of the memory read (MR), memory write (MW), input-output read
(IOR) and input-output write (IOW).

Machine Cycles in Microprocessor

 The time which is required for accessing the memory or input/output

devices is called a machine cycle in Microprocessor.
 One to four machine cycles are used.
 For example, memory reading, memory writing, opcode fetches, etc.
 One machine cycle is equal to 12 clocks.
 One machine cycle consists of 6 states.

T states in Microprocessor

 It is one subdivision of the operation performed in one clock period.

 It is part of the machine cycle.

23
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

 One clock period is equal to one t state.

 One machine cycle is equal to 12 t states.

Timing Diagram in Microprocessor

The timing diagram in Microprocessor is a graphical representation. It is used

for the representation of the execution time taken by each instruction in a
graphical format. The t states represent the timing diagrams.

1. CLOCK – It is the clock pulse provided to the user.

2. AD0-AD7 – These are used to carry data and addresses. It is the

lower address bus. The decision of when it will carry an address and
when it will carry data is made by ALE.

3. A8-A15– It is used to carry the address bits.

4. ALE – It provides the signal for multiplexed addresses and data buses.
If the signal is high or 1, a multiplexed address and data bus will be
24
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)
Unit-1 B. Tech. IV Sem CSE Introduction & Architecture of 8085

used as an address bus. To fetch a lower bit of address, the signal is 1

so that the multiplexed bus can act as an address bus. If the signal is
low or 0, the multiplexed bus will be used as the data bus. When a
lower bit of address is fetched then it will act as a data bus as the
signal is low.

5. RD (low active) – If the signal is high or 1, no data is read by the

microprocessor. If the signal is low or 0, data is read by the
microprocessor.

6. WR (low active) – If the signal is high or 1, no data is written by the

microprocessor. If the signal is low or 0, data is written by the
microprocessor.

7. IO/M (low active) and S1, S0 – If the signal is high or 1, the

operation is performed on input-output. If the signal is low or 0, the
operation is performed on memory.

25
Notes By: Dr. Neeraj Jain (Dean Exam & Associate Professor CSE)