What is exception?

List different ARM processor exceptions and

associated modes.
An exception is any condition that needs to halt the normal sequential
execution of instructions.
Example for exceptions are:
ARM core reset,
instruction fetch or memory access failure,
an undefined instruction fetch,
execution of a software interrupt instruction,
when an external interrupt has been raised.

Each exception causes the core to enter a specific mode.

In addition, any of the ARM processor modes can be entered manually by
changing the cpsr. User and system mode are the only two modes that are not
entered by a
corresponding exception, in other words, to enter these modes you must modify
the cpsr.
When an exception causes a mode change, the core automatically
■ saves the cpsr to the spsr of the exception mode
■ saves the pc to the lr of the exception mode
■ sets the cpsr to the exception mode
■ sets pc to the address of the exception handler
Explain ARM processors exception and modes with neat diagram.
Each exception causes the core to enter a specific mode.
In addition, any of the ARM processor modes can be entered manually by
changing the cpsr. User and system mode are the only two modes that are not
entered by a
corresponding exception, in other words, to enter these modes you must modify
the cpsr.

When an exception causes a mode change, the core automatically

■ saves the cpsr to the spsr of the exception mode
■ saves the pc to the lr of the exception mode
■ sets the cpsr to the exception mode
■ sets pc to the address of the exception handler
Explain exception Priorities and link register offset.
Exceptions can occur simultaneously, so the processor has to adopt a
priority mechanism.Each exception is dealt with according to the priority
level

 Reset Exception: Highest priority; occurs at power-up, initializes system

and sets up stack pointers.
 Software Interrupt & Undefined Instruction: Lowest priority
exceptions.
 Interrupt Disabling: Some exceptions disable interrupts via CPSR bits
(I/F).
 Handler Safety: Avoid exceptions/interrupts in the first few handler
instructions.
 Data Abort: Triggered by invalid memory access; second-highest priority
after Reset.
 FIQ (Fast Interrupt): Highest-priority interrupt; disables IRQ/FIQ on entry.
 IRQ (Interrupt Request): Second-highest interrupt; disables IRQ until
handled.
 Prefetch Abort: Occurs on faulty instruction fetch; IRQ disabled, FIQ
remains active.
 Software Interrupt (SWI): Triggered by SWI instruction; switches to
supervisor mode.
 Undefined Instruction: Raised when an unknown instruction executes;
same priority as SWI.

 Link Register Offsets

 

 When an exception occurs, the link register is set to a specific address

 based on the current pc.
 For example when an IRQ exception is raised, the link register lr points to
 the last executed instruction plus 8 because of three stage pipeline. Care
 has to be taken to make sure the exception handler does not corrupt lr
 because lr is used to return from an exception handler. The IRQ exception

address has to point to the next instruction, or lr − 4.

 is taken only after the current instruction is executed, so the return


What is interrupt latency? Explain briefly.

Interrupt latencyis the interval of time between from an external interrupt signal
being raised to the first fetch of an instruction of the ISR of the raised interrupt
signal.
System architects must balance between two things, first is to handle multiple
interrupts simultaneously, second is to minimize the interrupt latency.
Minimization of the interrupt latency is achieved by software handlers by two
main methods, the first one is to allow nested interrupt handling so the system
can respond to new interrupts during handling an older interrupt. This is
achieved by enabling interrupts immediately after the interrupt source has been
serviced but before finishing the interrupt handling.
The second one is the possibility to give priorities to different interrupt sources;
this is achieved by programming the interrupt controller to ignore interrupts of
the same or lower priority than the interrupt being handled if there is one.
List ARM firmware suite features. Explain firmware execution flow and
Red Hat Boot.
ARM has developed a firmware package called the ARM Firmware Suite (AFS).
AFS is designed purely for ARM-based embedded systems.
It provides support for a number of boards and processors including the Intel
XScale and StrongARM processors.
The package includes two major pieces of technology, a Hardware Abstraction
Layer called μHAL and a debug monitor called Angel.
μHAL provides a low-level device driver framework that allows it to operate over
different
communication devices
Main Features:
 System Initialization – Sets up processor and hardware when the
system starts.
 Serial Driver (Polled) – Allows basic communication through serial port.
 LED Support – Lets software control LEDs (e.g., for status).
 Timer Support – Sets up timers for operating systems that need regular
interrupts.
 Interrupt Controllers – Supports different ways hardware sends alerts
(interrupts).
  Boot Monitor with CLI – Offers a basic command-line interface during
startup.

The second technology, Angel, allows communication between a host debugger

and
a target platform. It allows you to inspect and modify memory, download and
execute
images, set breakpoints, and display processor register contents.
RED HAT REDBOOT
RedBoot is a firmware tool developed by Red Hat.
It provides both debug capability through GNU Debugger (GDB), as well as a
bootloader.
RedBoot supports these main features:
 Communication:
Works over serial (using X-Modem) or Ethernet (using TCP) to connect with
the GNU Debugger (GDB). Supports network tools like bootp, telnet, and tftp.
 Flash Memory Management:
Can download, update, and erase files in flash memory. Supports both
compressed and uncompressed images.
 Operating System Support:
Can load and boot systems like Embedded Linux and Red Hat eCos. It also
lets you pass startup settings to the OS.
Explain IRQ and FIQ exception. Write an ALP to enable and disable IRQ
and FIQ interrupts.
 Lower priority than Reset, Data Abort, and FIQ.
 Switches to IRQ mode (banked r13_irq, r14_irq, spsr_irq).
 Disables further IRQs (sets I-bit in CPSR).
 FIQ remains enabled (can preempt IRQ).
 Return address: lr_irq - 4 (pipeline adjustment).
 Used for general-purpose interrupts (e.g., timers, UART).
 It occurs due to external peripherals.
FIQ Exception
 Triggered by high-priority events via nFIQ pin.
 Higher priority than IRQ (3rd after Reset & Data Abort).
 Switches to FIQ mode (extra banked registers r8–r14_fiq).
 Disables both IRQ & FIQ (sets I & F bits in CPSR).
  Minimal latency (fewer register saves).
 Return address: lr_fiq - 4.
 Used for time-critical tasks (e.g., DMA, real-time systems).

Module-5

What is Cache memory? Explain Memory Hierarchy with neat block

diagram.
• A cache is a small, fast array of memory placed between the processor core
and main
memory that stores portions of recently referenced main memory.
• The processor uses cache memory instead of main memory whenever possible
to increase
system performance.
• cache is a write buffer—a very small first-in-first-out (FIFO) memory placed
between the
processor core and main memory.

The issue is the cache is filled quickly and needs to be replaced with most
important data.
The largest data that is stored is for longer time which is storedin bottom most
layer. It includes Disk, tape and network storage.