1a.

Design a 4-Bit Adder

1. Write a Verilog description
2. Verify the Functionality using Test-bench
3. Synthesize the design by setting proper constraints and generate the gate level netlist.
4. From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required.
1b. Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of
inverter with Wn = Wp, and length at selected technology. Carry out the following: 1. Set the input
signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and the time period of 20ns and
plot the input voltage and output voltage of designed inverter?
1. From the simulation result compute tpHL, tpLH and td for all three geometrical settings of width?
2. Tabulate the results of delay and find the best geometry for minimum delay for CMOS inverter.

2a. 4-Bit Shift and add Multiplier

1. Write Verilog Code
2. Verify the Functionality using Test-bench
3. Synthesize the design by setting proper constraints and obtain the gate level netlist.
4. From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required.
2b. Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of
inverter with Wn = 2Wp, and length at selected technology. Carry out the following:
1. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and the
period of 20ns and plot the input voltage and output voltage of designed inverter?
2. From the simulation result compute tpHL, tpLH and td for all three geometrical settings of width?
3. Tabulate the results of delay and find the best geometry for minimum delay for CMOS inverter.

3a. 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case statement for
1. ALU Behavioural Modelling
2. Write Verilog description
3. Verify functionality using Test-bench
4. Synthesize the design targeting suitable library and by setting area and timing constraints
5. Tabulate the Area, Power and Delay for the Synthesized netlist
6. Identify Critical path
3b. Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of
inverter with Wn = 1/2Wp, and length at selected technology. Carry out the following:
1. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and the
period of 20ns and plot the input voltage and output voltage of designed inverter?
2. From the simulation result compute tpHL, tpLH and td for all three geometrical settings of width?
3. Tabulate the results of delay and find the best geometry for minimum delay for CMOS inverter.
4a. Flip-Flops - D
1. Write the Verilog description
2. Verify the Functionality using Test-bench
3. Synthesize the design by setting proper constraints and obtain the gate level netlist.
4. From the report gate level netlist identify Critical path, Maximum delay, Total number of cells,
5. Power requirement and Total area required.
6. Verify the functionality using Gate level netlist and compare the results at RTL and gate level
netlist.
4b. Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and
LVS, extract parasites

5a. Flip-Flops - SR
1. Write the Verilog description
2. Verify the Functionality using Test-bench
3. Synthesize the design by setting proper constraints and obtain the gate level netlist.
4. From the report gate level netlist identify Critical path, Maximum delay, Total number of cells,
5. Power requirement and Total area required.
6. Verify the functionality using Gate level netlist and compare the results at RTL and gate level
netlist.
5b. Capture the schematic of 2-input CMOS NOR gate having 1x drive strength. Verify the functionality
of NOR gate and also find out the delay td for all four possible combinations of input vectors.

6a. Flip-Flops - JK
1. Write the Verilog description
2. Verify the Functionality using Test-bench
3. Synthesize the design by setting proper constraints and obtain the gate level netlist.
4. From the report gate level netlist identify Critical path, Maximum delay, Total number of cells,
5. Power requirement and Total area required.
6. Verify the functionality using Gate level netlist and compare the results at RTL and gate level
netlist.
6b. Capture the schematic of 2-input CMOS NOR gate having 2x drive strength. Verify the functionality
of NOR gate and also find out the delay td for all four possible combinations of input vectors.
7a. 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using if statement for
1. ALU Behavioral Modeling
2. Write Verilog description
3. Verify functionality using Test-bench
4. Synthesize the design targeting suitable library and by setting area and timing constraints
5. Tabulate the Area, Power and Delay for the Synthesized netlist
6. Identify Critical path
7b. Capture the schematic of 2-input CMOS NOR gate having 4x drive strength. Verify the functionality
of NOR gate and also find out the delay td for all four possible combinations of input vectors.

8a. Four-bit Synchronous MOD-N counter with Asynchronous reset

1. Write Verilog Code
2. Verify functionality using Test-bench
3. Synthesize the design targeting suitable library and by setting area and timing constraints
4. Tabulate the Area, Power and Delay for the Synthesized netlist
5. Identify Critical path
6. Verify the functionality using Gate level netlist and compare the results at RTL and gate level
netlist.

8b. Construct the schematic of the Boolean Expression Y= 𝐴𝐵 ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅

+ 𝐶𝐷 + 𝐸 using CMOS Logic. Verify
the functionality of the expression find out the delay td for some combination of input vectors. Tabulate
the results.

9a. Design a 4-Bit Adder

1. Write a Verilog description
2. Verify the Functionality using Test-bench
3. Synthesize the design by setting proper constraints and generate the gate level netlist.
4. From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required.
9b. Construct the schematic of Common Source Amplifier with PMOS Current Mirror Load and find
its transient response and AC response? Measure the Unit Gain Bandwidth (UGB).
10a. 4-Bit Shift and add Multiplier
1. Write Verilog Code
2. Verify the Functionality using Test-bench
3. Synthesize the design by setting proper constraints and obtain the gate level netlist.
4. From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required.
10b. Construct the schematic of two-stage operational amplifier, configure it as voltage follower,
measure the following:
1. Gain
2. Phase difference between input and output signal.

11a. 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case statement for
1. ALU Behavioral Modeling
2. Write Verilog description
3. Verify functionality using Test-bench
4. Synthesize the design targeting suitable library and by setting area and timing constraints
5. Tabulate the Area, Power and Delay for the Synthesized netlist
6. Identify Critical path
11b. Draw Layout of common source amplifier, use optimum layout methods. Verify for DRC & LVS,
extract parasites.

12a. Flip-Flops - D
1. Write the Verilog description
2. Verify the Functionality using Test-bench
3. Synthesize the design by setting proper constraints and obtain the gate level netlist.
4. From the report gate level netlist identify Critical path, Maximum delay, Total number of cells,
5. Power requirement and Total area required.
6. Verify the functionality using Gate level netlist and compare the results at RTL and gate level
netlist.
12 b. Draw layout of inverter with Wp=Wn, use optimum layout methods. Verify for DRC and LVS,
extract parasites.
13a. Flip-Flops - SR
1. Write the Verilog description
2. Verify the Functionality using Test-bench
3. Synthesize the design by setting proper constraints and obtain the gate level netlist.
4. From the report gate level netlist identify Critical path, Maximum delay, Total number of cells,
5. Power requirement and Total area required.
6. Verify the functionality using Gate level netlist and compare the results at RTL and gate level
netlist.
13b. Draw layout of inverter with Wp=2Wn, use optimum layout methods. Verify for DRC and LVS,
extract parasites.

14a. Flip-Flops - JK
1. Write the Verilog description
2. Verify the Functionality using Test-bench
3. Synthesize the design by setting proper constraints and obtain the gate level netlist.
4. From the report gate level netlist identify Critical path, Maximum delay, Total number of cells,
5. Power requirement and Total area required.
6. Verify the functionality using Gate level netlist and compare the results at RTL and gate level
netlist.
14b. Draw layout of inverter with Wp=1/2(Wn), use optimum layout methods. Verify for DRC and
LVS, extract parasites.

15a. 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using if statement for
1. ALU Behavioral Modeling
2. Write Verilog description
3. Verify functionality using Test-bench
4. Synthesize the design targeting suitable library and by setting area and timing constraints
5. Tabulate the Area, Power and Delay for the Synthesized netlist
6. Identify Critical path
15b. Draw layout of inverter with Wp=4µm Wn=2µm, use optimum layout methods. Verify for DRC
and LVS, extract parasites.