Verilog Programs

1. // Reduce Four Variable Function as given F(A, B, C, D) =Sigma[

m(0,1,3,4,8,9,15)] into SOP form.
module sop4(out,A,B,C,D);
output out;
input A,B,C,D;
wire abar,bbar,cbar,dbar,p1,p2,p3,p4;
not(abar,A);
not(bbar,B);
not(cbar,C);
not(dbar,D);
and(p1,abar,cbar,dbar);
and(p2,abar,bbar,D);
and(p3,A,bbar,cbar);
and(p4,A,B,C,D);
or(out,p1,p2,p3,p4);
endmodule

2. module decoder3to8( in,en,y);

input [2:0] in;
input en;
output [7:0] y;
reg [7:0] y;

always @( in or en)
begin

if (en)
begin
y=8'd0;
case (in)
3'b000: y= 8'b0000_0001;
3'b001: y= 8'b0000_0010;
3'b010: y= 8'b0000_0100;
3'b011: y= 8'b0000_1000;
3'b100: y= 8'b0001_0000;
3'b101: y= 8'b0010_0000;
3'b110: y= 8'b0100_0000;
3'b111: y= 8'b1000_0000;
default: y=8'd0;
endcase
end
else
y=8'd0;
end
endmodule

3. // Designing 8:1 Multiplexer using Four Variable Function as given

F(A, B, C, D) =Sigma[ m(0,1,3,4,8,9,15)].
module m81(out,A,B,C,D);
output out;
input A,B,C,D;
wire D0,D1,D2,D3,D4,D5,D6,D7,S2bar,S1bar,S0bar,Abar;
assign S2bar=~B;
assign S1bar=~C;
assign S0bar=~D;
assign Abar=~A;
assign D0=1;
assign D1=1;
assign D2=0;
assign D3=Abar;
assign D4=Abar;
assign D5= 0;
assign D6=0;
assign D7=A;

assign out = (D0 & S2bar & S1bar & S0bar) | (D1 & S2bar & S1bar & D) |
(D2 & S2bar & C & S0bar) + (D3 & S2bar & C & D) + (D4 & B & S1bar &
S0bar) + (D5 & B & S1bar & D) + (D6 & B & C & S0bar) + (D7 & B & C &
D);
endmodule

4. module full_adder_d (a,b,cin,sum,carry);

input a,b,cin;
output sum,carry;
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (b & cin) | (cin & a) ;
endmodule

/*module full_adder_tb;
reg a,b,cin;
wire sum,carry;

full_adder_d uut(a,b,cin,sum,carry);

initial begin
a = 0; b = 0; cin = 0;
#10 a = 0; b = 0; cin = 1;
#10 a = 0; b = 1; cin = 0;
#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 0;
#10 a = 1; b = 0; cin = 1;
#10 a = 1; b = 1; cin = 0;
#10 a = 1; b = 1; cin = 1;
#10 $stop();
$monitor(" time=%0d a=%b b=%b cin=%b sum=%b carry=%b",
$time,a,b,cin,sum,cout);
end
endmodule*/
module tb_top;
reg a, b, cin;
wire sum, carry;

full_adder_d fa(a, b, cin, sum, carry);

initial begin
$monitor("At time %0t: a=%b b=%b, cin=%b, sum=%b, carry=%b",$time,
a,b,cin,sum,carry);
a = 0; b = 0; cin = 0; #1;
a = 0; b = 0; cin = 1; #1;
a = 0; b = 1; cin = 0; #1;
a = 0; b = 1; cin = 1; #1;
a = 1; b = 0; cin = 0; #1;
a = 1; b = 0; cin = 1; #1;
a = 1; b = 1; cin = 0; #1;
a = 1; b = 1; cin = 1;
end
endmodule

5. module ring_count(q,clk,clr);
input clk,clr;
output [3:0]q;
reg [3:0]q;
always @(posedge clk)
if(clr==1)
q<=4'b1000;
else
begin
q[3]<=q[0];
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule

`timescale 1ns/1ps
module ring_count_test();
reg clk_tb,clr_tb;
wire [3:0]q_tb;
ring_count dut1(q_tb,clk_tb,clr_tb);
initial
begin
clr_tb=1'b0;
#50 clr_tb=1'b1;
#100 clr_tb=1'b0;
#10000 $finish;
end
always
begin
#50 clk_tb=1'b1;
#50 clk_tb=1'b0;
 end
initial
begin
$display("time,\t clk_tb,\t clr_tb,\t q_tb");
$monitor("%g,\t %h,\t %h,\t %h",$time,clk_tb,clr_tb,q_tb);
end
endmodule

6. module Johnson_Counter( out,reset,clk);

input clk,reset;
output [3:0] out;

reg [3:0] q;

always @(posedge clk)

begin

if(reset)
q<=4'd0;
else
begin
q[3]<=q[2];
q[2]<=q[1];
q[1]<=q[0];
q[0]<=(~q[3]);
end
end

assign out=q;
endmodule

`timescale 1ns/1ps
module Johnson_count_test();
reg clk_tb,reset_tb;
wire [3:0]q_tb;
Johnson_Counter dut1(q_tb,reset_tb,clk_tb);
initial
begin
$display("time,\t clk_tb,\t reset_tb,\t q_tb");
$monitor("%g,\t %h,\t %h,\t %h",$time,clk_tb,reset_tb,q_tb);
reset_tb=1'b0;
#50 reset_tb=1'b1;
#100 reset_tb=1'b0;
#10000 $finish;
end
always
begin
#50 clk_tb=1'b1;
#50 clk_tb=1'b0;
end
endmodule
7. module universal_shift_reg( clk, rst_n,select,p_din,
s_left_din,s_right_din,p_dout,s_left_dout,s_right_dout );
input clk, rst_n;
input [1:0] select; // select operation
input [3:0] p_din; // parallel data in
input s_left_din; // serial left data in
input s_right_din; // serial right data in
output [3:0] p_dout; //parallel data out
output s_left_dout; // serial left data out
output s_right_dout; // serial right data out
reg [3:0] p_dout;
always@(posedge clk)
begin
if(!rst_n)
p_dout <= 0;
else
begin
case(select)
2'h1: p_dout <= {s_right_din,p_dout[3:1]}; // Right Shift
2'h2: p_dout <= {p_dout[2:0],s_left_din}; // Left Shift
2'h3: p_dout <= p_din; // Parallel in - Parallel out
default: p_dout <= p_dout; // Do nothing
endcase
end
end
assign s_left_dout = p_dout[0];
assign s_right_dout = p_dout[3];
endmodule

module TB;
reg clk, rst_n;
reg [1:0] select;
reg [3:0] p_din;
reg s_left_din, s_right_din;
wire [3:0] p_dout; //parallel data out
wire s_left_dout, s_right_dout;

universal_shift_reg usr(clk, rst_n, select, p_din, s_left_din,

s_right_din, p_dout, s_left_dout, s_right_dout);

always #2 clk = ~clk;

initial begin
$monitor("select=%b, p_din=%b, s_left_din=%b, s_right_din=%b -->
p_dout = %b, s_left_dout = %b, s_right_dout = %b",select, p_din,
s_left_din, s_right_din, p_dout, s_left_dout, s_right_dout);
clk = 0; rst_n = 0;
#3 rst_n = 1;

p_din = 4'b1101;
s_left_din = 1'b1;
s_right_din = 1'b0;
 select = 2'h3; #10;
select = 2'h1; #20;
p_din = 4'b1101;
select = 2'h3; #10;
select = 2'h2; #20;
select = 2'h0; #20;

$finish;
end
// To enable waveform
/*initial begin
$dumpfile("dump.vcd"); $dumpvars;
end*/

endmodule

8. module up_counter(clk,reset,counter);
input clk, reset;
output[3:0] counter;
//reg [3:0] counter_up;
reg [3:0] counter;

// up counter
always @(posedge clk or posedge reset)
begin
if(reset) counter
<= 4'd0;
else
counter <= counter + 4'd1;
end
//assign counter = counter_up;
endmodule

module upcounter_testbench();
reg clk, reset;
wire [3:0] counter;

up_counter dut(clk, reset, counter);

initial begin
clk=0;
forever #10 clk=~clk;
end
initial
begin
$display("time,\t clk,\t reset,\t counter");
$monitor("%g,\t %h,\t %h,\t %h",$time,clk,reset,counter);
reset=1;
#20;
reset=0;
#10000 $finish;
end
endmodule

9. module synchronous_counter (clk, rst_n,up,cnt);

input clk, rst_n;
input up;
output [3:0] cnt;
reg [3:0] cnt;

always@(posedge clk) begin

if(!rst_n) begin
cnt <= 4'h0;
end
else begin
if(up) cnt <= cnt + 1'b1;
else cnt <= cnt - 1'b1;
end
end
endmodule

module tb;
reg clk, rst_n;
reg up;
wire [3:0] cnt;
synchronous_counter dut(clk, rst_n, up, cnt);

initial
begin
$display("time,\t clk,\t rst_n,\t up,\t cnt");
$monitor("%g,\t %h,\t %h,\t %h,\t %h",$time,clk,rst_n,up,cnt);
clk = 0; rst_n = 0;
clk = 0; rst_n = 0;
up = 1;
#4;
rst_n = 1;
#80;
rst_n = 0;
#4;
rst_n = 1;
#4
up = 0;
#1000;
$finish;
end
always #2 clk = ~clk;

endmodule
10a. module b_comp1 (a, b, L, E,G);
input a, b;
output L, E, G;
wire s1, s2;
not (s1, a);
not (s2, b);
and (L,s1, b);
and (G,s2, a);
xnor (E, a, b);
endmodule

10b. module segment7(bcd,seg);

//Declare inputs,outputs and internal variables.

input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;

//always block for converting bcd digit into 7 segment format

always @(bcd)
begin
case (bcd) //case statement
0 : seg = 7'b0000001;
1 : seg = 7'b1001111;
2 : seg = 7'b0010010;
3 : seg = 7'b0000110;
4 : seg = 7'b1001100;
5 : seg = 7'b0100100;
6 : seg = 7'b0100000;
7 : seg = 7'b0001111;
8 : seg = 7'b0000000;
9 : seg = 7'b0000100;
//switch off 7 segment character when the bcd digit is not
a decimal number.
default : seg = 7'b1111111;
endcase
end

endmodule

module tb_segment7;

reg [3:0] bcd;

wire [6:0] seg;
integer i;

// Instantiate the Unit Under Test (UUT)

segment7 uut ( .bcd(bcd),.seg(seg));

//Apply inputs
initial
begin
 for(i = 0;i < 16;i = i+1) //run loop for 0 to 15.
begin
bcd = i;
#10; //wait for 10 ns
end
end
initial
begin

$display("time,\t bcd,\t seg");

$monitor("%g,\t %h,\t %h",$time,bcd,seg);
end

endmodule

11. module bin2gray (bin,G );

input [3:0] bin; //binary input
output [3:0] G; //gray code output

//xor gates.
assign G[3] = bin[3];
assign G[2] = bin[3] ^ bin[2];
assign G[1] = bin[2] ^ bin[1];
assign G[0] = bin[1] ^ bin[0];
endmodule

module gray2bin (G,bin);

input [3:0] G;
output [3:0] bin;

assign bin[3] = G[3];

assign bin[2] = G[3] ^ G[2];
assign bin[1] = G[3] ^ G[2] ^ G[1];
assign bin[0] = G[3] ^ G[2] ^ G[1] ^ G[0];
endmodule

module tb();

reg [3:0] bin;

wire [3:0] G,bin_out;

// instantiate the unit under test's (uut)

bin2gray uut1(bin,G);
gray2bin uut2(G,bin_out);

// stimulus
always
begin
bin <= 0; #10;
bin <= 1; #10;
 bin <= 2; #10;
bin <= 3; #10;
bin <= 4; #10;
bin <= 5; #10;
bin <= 6; #10;
bin <= 7; #10;
bin <= 8; #10;
bin <= 9; #10;
bin <= 10; #10;
bin <= 11; #10;
bin <= 12; #10;
bin <= 13; #10;
bin <= 14; #10;
bin <= 15; #10;
#100;
$stop;
end

initial
begin

$display("time,\t bin,\t G,\t bin_out");

$monitor("%g,\t %h,\t %h,\t %h",$time,bin,G,bin_out);
end

endmodule