MICROPROCESSORS AND INTERFACING (5131)

MODULE –I
Basic 80x86 Architecture
Role of Microprocessor in Micro Computer
A microprocessor is a programmable electronics chip that has computing and decision making
capabilities similar to central processing unit of a computer.

Any microprocessor-based systems having limited number of resources are called microcomputers. A
microprocessor is used as the CPU in a microcomputer.

Nowadays, microprocessor can be seen in almost all types of electronics devices like mobile phones,
printers, washing machines etc. Microprocessors are also used in advanced applications like radars, satellites
and flights. Due to the rapid advancements in electronic industry and large scale integration of devices results in
a significant cost reduction and increase application of microprocessors and their derivatives.

Important Terms
 Bit: A bit is a single binary digit.
 Word: A word refers to the basic data size or bit size that can be processed by the arithmetic and logic
unit of the processor. A 16-bit binary number is called a word in a 16-bit processor.
 Bus: A bus is a group of wires/lines that carry similar information.
 System Bus: The system bus is a group of wires/lines used for communication between the
microprocessor and peripherals.
 Memory Word: The number of bits that can be stored in a register or memory element is called a
memory word.

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 Address Bus: It carries the address, which is a unique binary pattern used to identify a memory location
or an I/O port. For example, an eight bit address bus has eight lines and thus it can address 2^8 = 256
different locations. The locations in hexadecimal format can be written as 00H – FFH.
 Data Bus: The data bus is used to transfer data between memory and processor or between I/O device
and processor. For example, an 8-bit processor will generally have an 8-bit data bus and a 16-bit
processor will have 16-bit data bus.
 Control Bus: The control bus carry control signals, which consists of signals for selection of memory or
I/O device from the given address, direction of data transfer and synchronization of data transfer in case
of slow devices

Classification of Microprocessors:
Based on their specification, application and architecture microprocessors are classified.

Based on size of data bus:

4-bit microprocessor
8-bit microprocessor
16-bit microprocessor
32-bit microprocessor

Examples for 4/ 8 / 16 / 32 bit Microprocessors:

4-Bit processor – 4004/4040
8-bit Processor - 8085 / Z80 / 6800
16-bit Processor - 8086 / 68000 / Z8000
32-bit Processor - 80386 / 80486

Based on application:
 General-purpose microprocessor- used in general computer system and can be used by programmer for
any application. Examples, 8085 to Intel Pentium.
 Microcontroller- microprocessor with built-in memory and ports and can be programmed for any
generic control application. Example, 8051.
 Special-purpose processors- designed to handle special functions required for an application. Examples,
digital signal processors and application-specific integrated circuit (ASIC) chips.

Based on architecture:

Reduced Instruction Set Computer (RISC) processors

Complex Instruction Set Computer (CISC) processors

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Brief history of Microprocessors

Generations of microprocessors:
1. First-generation –
 From 1971 to 1972
 4 bit MicroProcessors
 First MicroProcessor: INTEL 4004 (In 1971)
 Eg:INTEL 4004, Rockwell international PPS-4, INTEL 8008 etc.
 All these were not TTL compatible processors.

2. Second generation –
 from 1973 to 1978
 8-bit microprocessors
 Eg: INTEL 8085, Motorola 6800 and 6801
 Owing to their super fast speed, they were costly as they were based on NMOS
technology fabrication.

3. Third generation –
 16-bit processors
 Eg: INTEL 8086/80186/80286, Motorola 68000/68010 etc.
 From 1979 to 1980
 Used the HMOS technology.

4. Fourth generation –
 From 1981 to 1995.
 The 32-bit processors
 Using HCMOS fabrication.
 Eg: INTEL 80386 and Motorola 68020

5. Fifth-generation –
 From 1995 till now
 64-bit processors
 Eg: PENTIUM, Celeron, dual, quad, and octa-core processors.

Features of 8086
1. It is a 16 bit μp.
2. 8086 has a 20 bit address bus can access upto 220 memory locations ( 1 MB) .
3. It can support upto 64K I/O ports.
4. It provides 14, 16-bit registers.
5. It has multiplexed address and data bus AD0- AD15 and A16 – A19.
6. It requires single phase clock with 33% duty cycle to provide internal timing.
7. 8086 is designed to operate in two modes, Minimum and Maximum.
8. It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up
instruction execution.
9. It requires +5V power supply.
10. A 40 pin dual in line package.

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Internal Block Diagram of 8086 / Internal Architecture of 8086 / Functional Block

diagram of 8086

 8086 has two blocks BIU(Bus Interface Unit) and EU(Execution Unit).
The BIU performs all bus operations such as instruction fetching, reading and writing operands
for memory and calculating the addresses of the memory operands. The instruction bytes are transferred
to the instruction queue. EU executes instructions from the instruction system byte queue. Both units
operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism
which is called as Pipelining. This results in efficient use of the system bus and system performance.
BIU contains Instruction queue (Prefetch-Queue), Segment registers, Instruction pointer, Address adder.
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.

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Bus Interface Unit:

 It provides a full 16 bit bidirectional data bus and 20 bit address bus.
 The bus interface unit is responsible for performing all external bus operations. Specifically it has the
following functions: Instruction fetch, Instruction queuing, Operand fetch and storage, Address
relocation and Bus control.
 The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.

This queue (Prefetch-Queue) permits prefetch of up to six bytes of instruction code. Whenever
the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not
requesting it to read or write operands from memory, the BIU is free to look ahead in the program by
prefetching the next sequential instruction. These prefetching instructions are held in its FIFO queue. With its
16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. After a byte is loaded at the
input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output. The
EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the
queue. If the queue is full and the EU is not requesting access to operand in memory. These intervals of no bus
activity, which may occur between bus cycles, are known as Idle state. If the BIU is already in the process of
fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first
completes the instruction fetch bus cycle before initiating the operand read / write cycle. The BIU also contains
a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus. This
address is formed by adding an appended 16 bit segment address and a 16 bit offset address. For example, the
physical address of the next instruction to be fetched is formed by combining the current contents of the code
segment CS register and the current contents of the instruction pointer IP register. The BIU is also responsible
for generating bus control signals such as those for memory read or write and I/O read or write.

What is the advantage of using pre-fetch queue in 8086?

Improve The 8086/8088 instruction queue is a buffer that holds opcode bytes that have been prefetched by the
bus interface unit. This speed up operations of the processor by helping to reduce fetches latency, i.e. to
improve the probability that an opcode byte fetched by the processor is already available.

Execution Unit :
 The Execution unit is responsible for decoding and executing all instructions.

The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if
necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O
and perform the operation specified by the instruction on the operands. During the execution of the
instruction, the EU tests the status and control flags and updates them based on the results of executing the
instruction. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top
of the queue. When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions. Whenever this happens, the BIU automatically resets
the queue and then begins to fetch instructions from this new location to refill the queue.

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Internal Registers of 8086 / Register Organization of 8086

 The 8086 has four groups of the user accessible internal registers.
They are
1. the Instruction Pointer - IP
2. four General Purpose Registers - GPRs(Data Registers)
3. four Pointers and Index registers
4. four Segment Registers.

 The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status register
(Flag Register), with 9 of bits implemented for status and control flags.
 Most of the registers contain data/instruction offsets within 64 KB memory segment.

GENERAL PURPOSE REGISTERS

 All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The use
of general-purpose registers is to store temporary data.
 There are 4 general-purpose registers of 16-bit length each.
 Each of them is further divided into two subparts of 8-bit length each: one high, which stores the higher-
order bits and another low which stores the lower order bits.
 AX = [AH:AL]
 BX = [BH:BL]
 CX = [CH:CL]
 DX = [DH:DL]

 The general purpose registers are:

 Accumulator(AX) register consists of two 8-bit registers AL and AH, which can be combined together
and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH
contains the high-order byte.
 Accumulator can be used for I/O operations and string manipulation.

 Base Register(BX) consists of two 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains
the high-order byte.

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 BX register usually contains a data pointer used for based, based indexed or register
indirect addressing.

 Count Rgister(CX) consists of two 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and
CH contains the high-order byte.
 Count register can be used in Loop, shift/rotate instructions and as a counter in string
manipulation,.

 Data register(DX) consists of two 8-bit registers DL and DH, which can be combined together and used
as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH
contains the high- order byte.
 Data register can be used as a port number in I/O operations. In integer 32-bit multiply
and divide instruction the DX register contains high-order word of the initial or resulting
number.

The following registers are both general and index registers

INDEX or POINTER REGISTERS

The pointers will always store some address or memory location. In 8086 Microprocessor, they usually store the
offset through which the actual address is calculated.

 Stack Pointer (SP) is a 16-bit register pointing to program stack. Also, it acts as an offset for Stack
Segment (SS).
 Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for
based, based indexed or register indirect addressing. Also, it acts as an offset for Stack Segment (SS).
 Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data address in string manipulation instructions.
 Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect
addressing, as well as a destination data address in string manipulation instructions.

Instruction Pointer (IP) is a 16-bit register. The instruction pointer usually stores the address of the next
instruction that is to be executed. Apart from this, it also acts as an offset for CS register.

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SEGMENT REGISTERS.
What is segmentation?
Memory segmentation is nothing which is the methods where whole memory is divided into the smaller
parts. The total memory size is divided into segments of various sizes. A segment is just an area in memory. The
process of dividing memory this way is called Segmentation
In the 8086 memory, data is stored as bytes. Each byte has a specific address. Intel 8086 has 20 lines
address bus. With 20 address lines, the memory that can be addressed is 2 power 20 bytes. 2 power 20 =
1,048,576 bytes (1 MB). 8086 can access memory with address ranges from 00000 H t o FFFFF H
In 8086 microprocessor memory are divided into four parts which is known as the segments. These
segments are data segment, code segment, stack segment and extra segment.

segment registers
Each of these segments are addressed by an address stored in corresponding segment register. These
registers are of 16-bit in size. Each register stores the base address (starting address) of the corresponding
segment. Because the segment registers cannot store 20 bits, they only store the upper 16 bits.

1. Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions.
The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP)
register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far
call and far return instructions.

2. Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack.
By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP)
registers is located in the stack segment. SS register can be changed directly using POP instruction.

3. Data segment (DS) is a 16-bit register containing address of 64KB segment with program data.
By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and
index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and
LDS instructions.

4. Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data.

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By default, the processor assumes that the DI register references the ES segment in string manipulation
instructions. ES register can be changed directly using POP and LES instructions. It is possible to change
default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES
prefix.

Physical Address Calculation

How is a 20-bit address obtained if there are only 16- bit registers?
The 20-bit address of a byte is called its physical Address (Effective Address). But, it is specified as a
Logical Address. Logical address is in the form of:
Base Address : Offset
Offset is the displacement of the memory location from the starting location of the segment.

Physical Address (Effective address) = Base address X 10H + Offset Value

The 8086 addresses a segmented memory. The complete physical address which is 20-bits long is
generated using segment and offset registers each of the size 16-bit. The content of a segment register also
called as Base Address (segment address), and content of an offset register also called as offset address. To
get total physical address, put the lower nibble 0H to segment address and add offset address. The figure shows
the formation of 20-bit physical address.

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Q1) The value of Code Segment (CS) Register is 4042H and the value of different offsets is as follows:
BX:2025H IP:0580H DI:4247H
Calculate the effective address of the memory location pointed by the CS register.

Ans:
The offset of the CS Register is the IP register.
Effective address= Base address of CS register X 10H + Address of IP
= 4042H X 10H + 0580H
= (40420 + 0580)H
= 41000H

Q2) Calculate the effective address for the following register:

SS: 3860H, SP: 1735H, BP: 4826H
Ans:
Both SP and BP are the offsets for Stack Register (SS). The address calculated when BP is taken as the offset
gives the starting address of the stack. The address when SP is taken as the offset denotes the memory location
where the top of the stack lies.
Therefore, the effective address for both these cases is:
(SS X 10H) + SP = 3640H X 10H + 1735H
= 36400H + 1735H
= 38135H
(SS X 10H) + BP = 3640H X 10H + 4826H
= 36400H + 4826H
= 41226H

FLAG REGISTERS or STATUS REGISTER

Flags is a 16-bit register containing 9 one bit flags.

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It contains a group of status bits called flags that indicate the status of the CPU or the result of arithmetic
operations or logical operation. There are two types of flags:

1. The status flags (condition flags) which reflect the result of executing an instruction. The programmer
cannot set/reset these flags directly. The programmer can set/reset. This category consists of the following 6
flags:

2. The control flags enable or disable certain CPU operations. The control flags are used to navigate the
microprocessor for certain operations. There are 3 types of control flags:

The remaining 7 are not used.

A flag can only take on the values 0 and 1. We say a flag is set if it has the value 1.The status flags are used to
record specific characteristics of arithmetic and of logical instructions.

STATUS FLAGS: There are six status flags

1. The Carry Flag (C): This flag is set when the result of an unsigned arithmetic operation is too large to
fit in the destination register. This happens when there is an end carry in an addition operation or there
an end borrows in a subtraction operation. A value of 1 = carry and 0 = no carry.
2. The Overflow Flag (O): This flag is set when the result of a signed arithmetic operation is too large to
fit in the destination register (i.e. when an overflow occurs). Overflow can occur when adding two
numbers with the same sign (i.e. both positive or both negative). A value of 1 = overflow and 0 = no
overflow.
3. The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is negative. This
flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1 means negative and 0 = positive.
4. The Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is equal to zero. A
value of 1 means the result is zero and a value of 0 means the result is not zero.
5. The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from bit 3 to bit 4 (or a
borrow from bit 4 to bit 3) of an operand. A value of 1 = carry and 0 = no carry.
6. The Parity Flag (P): This flags reflects the number of 1s in the result of an operation. If the number of
1s is even its value = 1 and if the number of 1s is odd then its value = 0.

CONTROL FLAGS: There are three control flags

1. The Direction Flag (D): Affects the direction of moving data blocks by such instructions as MOVS,
CMPS and SCAS. The flag values are 0 = up and 1 = down and can be set/reset by the STD (set D) and
CLD (clear D) instructions.
2. The Interrupt Flag (I): Dictates whether or not system interrupts can occur. Interrupts are actions
initiated by hardware block such as input devices that will interrupt the normal execution of programs.

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The flag values are 0 = disable interrupts or 1 = enable interrupts and can be manipulated by the CLI
(clear I) and STI (set I) instructions.
3. The Trap Flag (T): Determines whether or not the CPU is halted after the execution of each
instruction. When this flag is set (i.e. = 1), the programmer can single step through his program to debug
any errors. When this flag = 0 this feature is off. This flag can be set by the INT 3 instruction.

Addressing Modes of 8086:

Addressing mode indicates a way of locating data or operands.

The addressing mode describes the types of operands and the way they are accessed for executing an
instruction.
According to the flow of instruction execution, the instructions may be categorized as
1. Sequential control flow instructions and
2. Control transfer instructions.

Sequential control flow instructions are the instructions which after execution, transfer control to the next
instruction appearing immediately after it (in the sequence) in the program. For example the arithmetic, logic,
data transfer and processor control instructions are Sequential control flow instructions.
The control transfer instructions on the other hand transfer control to some predefined address or the address
somehow specified in the instruction, after their execution. For example INT, CALL, RET & JUMP instructions
fall under this category.
The addressing modes for Sequential and control flow instructions are explained as follows.

1. Immediate addressing mode:

In this type of addressing, immediate data is a part of instruction, and appears in the form of successive byte or
bytes.
Example: MOV AX, 0005H.
In the above example, 0005H is the immediate data. The immediate data may be 8- bit or 16-bit in size.
2. Direct addressing mode:
In the direct addressing mode, a 16-bit memory address (offset) directly specified in the instruction as a part of
it.
Example: MOV AX, [5000H].
3. Register addressing mode:
In the register addressing mode, the data is stored in a register and it is referred using the particular register. All
the registers, except IP, may be used in this mode.
Example: MOV BX, AX
4. Register indirect addressing mode:
Sometimes, the address of the memory location which contains data or operands is determined in an indirect
way, using the offset registers. The mode of addressing is known as register indirect mode.

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In this addressing mode, the offset address of data is in either BX or SI or DI Register. The default segment is
either DS or ES.
Example: MOV AX, [BX].
5. Indexed addressing mode:
In this addressing mode, offset of the operand is stored one of the index registers. DS & ES are the default
segments for index registers SI & DI respectively.
Example: MOV AX, [SI]
Here, data is available at an offset address stored in SI in DS.
6. Register relative addressing mode:
In this addressing mode, the data is available at an effective address formed by adding an 8-bit or 16-bit
displacement with the content of any one of the register BX, BP, SI & DI in the default (either in DS & ES)
segment.
Example: MOV AX, 50H [BX]
7. Based indexed addressing mode:
The effective address of data is formed in this addressing mode, by adding content of a base register (any one of
BX or BP) to the content of an index register (any one of SI or DI). The default segment register may be ES or
DS.
Example: MOV AX, [BX][SI]
8. Relative based indexed / Based Indexed with Displacement:
The effective address is formed by adding an 8 or 16-bit displacement with the sum of contents of any of the
base registers (BX or BP) and any one of the index registers, in a default segment.
Example: MOV AX, 50H [BX] [SI]
9. Implicit addressing mode:
In this addressing mode the instruction contains only the opcode
Eg: HLT – Halt
CMC – Compliment Carry

For the control transfer instructions, the addressing modes depend upon whether the destination location is
within the same segment or in a different one. It also depends upon the method of passing the destination
address to the processor. Basically, there are two addressing modes for the control transfer instructions, viz.
intersegment and intrasegment addressing modes.
If the location to which the control is to be transferred lies in a different segment other than the current one, the
mode is called intersegment mode. If the destination location lies in the same segment, the mode is called
intrasegment mode.
Addressing Modes for control transfer instructions:
1. Intersegment
 Intersegment direct
 Intersegment indirect

2. Intrasegment
 Intrasegment direct
 Intrasegment indirect
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1. Intersegment direct:
In this mode, the address to which the control is to be transferred is in a different segment. This addressing
mode provides a means of branching from one code segment to another code segment. Here, the CS and IP of
the destination address are specified directly in the instruction.
Example: JMP 5000H, 2000H;
Jump to effective address 2000H in segment 5000H.

2. Intersegment indirect:
In this mode, the address to which the control is to be transferred lies in a different segment and it is passed to
the instruction indirectly, i.e. contents of a memory block containing four bytes, i.e. IP(LSB), IP(MSB),
CS(LSB) and CS(MSB) sequentially. The starting address of the memory block may be referred using any of
the addressing modes, except immediate mode.
Example: JMP [2000H].
Jump to an address in the other segment specified at effective address 2000H in DS.

3. Intrasegment direct mode:

In this mode, the address to which the control is to be transferred lies in the same segment in which the control
transfers instruction lies and appears directly in the instruction as an immediate displacement value. In this
addressing mode, the displacement is computed relative to the content of the instruction pointer.
The effective address to which the control will be transferred is given by the sum of 8 or 16 bit displacement
and current content of IP. In case of jump instruction, if the signed displacement (d) is of 8-bits (i.e. -
128<d<+127), it as short jump and if it is of 16 bits (i.e. -32768<d<+32767), it is termed as long jump.
Example: JMP SHORT LABEL.

4. Intrasegment indirect mode: In this mode, the displacement to which the control is to be transferred is in
the same segment in which the control transfer instruction lies, but it is passed to the instruction directly. Here,
the branch address is found as the content of a register or a memory location.
This addressing mode may be used in unconditional branch instructions.
Example: JMP [BX]; Jump to effective address stored in BX.

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Hardware Structure Of 8086

Pin Configuration

(MIN MODE) (MAX MODE)

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Clock
CLK- Clock Input: The clock input provides the basic timing for processor operation and bus control
activity. It’s an asymmetric square wave with 33% duty cycle.

Operating Modes of 8086

8086 has two operating Modes:

1. Minimum mode
2. Maximum mode

There are two modes of the 8086 microprocessor. The pin 33 decides whether the processor will work
in minimum mode or maximum mode. If the pin is set, then the minimum mode is followed, else the
processor works in maximum mode.

Minimum mode:

The pins from 24 to 31 are multiplexed in such a way that they work differently in these two modes. Let us first
discuss the working of these pins in minimum mode.

 In this 8086 is the only processor in the system . In a minimum mode 8086 system.
 8086 is operated in minimum mode when MN/MX’ pin to logic 1.
 In this mode, all the control signals are given out by the 8086 itself.

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Maximum mode:

The pins form 24 to 31 are dedicated to these modes. Let us have a look at how these pins function in
the maximum mode of the 8086 microprocessor.

 In this we can connect more processors to 8086 (8087/8089).

 8086 max mode is basically for implementation of allocation of global resources and passing bus control
to other coprocessor(i.e. second processor in the system), because two processors cannot access system
bus at same instant.
 All processors execute their own program.
 The resources which are common to all processors are known as global resources.
 The resources which are allocated to a particular processor are known as local or private resources.

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Differentiate between Minimum mode and Maximum mode

Instruction Cycle:

It is the time taken by the processor to complete the execution of an instruction. An instruction cycle consists of
one to six machine cycles.
Machine Cycle: The time required to complete one operation; accessing either the memory or I/O device. A
machine cycle consists of three to six T-states.
T-State: Time corresponding to one clock period. It is the basic unit to calculate execution of instructions or
programs in a processor.

In a basic computer, each instruction cycle consists of the following phases:

1. Fetch instruction from memory.

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2. Decode the instruction.

3. Read the effective address from memory.
4. Execute the instruction.

Assembly Process

Microprocessor communicates and operates in binary numbers 0 and 1. The set of instructions in the form of
binary patterns is called a machine language and it is difficult for us to understand. Therefore, the binary
patterns are given abbreviated names, called mnemonics, which forms the assembly language. The conversion
of assembly-level language into binary machine-level language is done by using an application called
assembler.Eg: MASM, TASM

It generates instructions by evaluating the mnemonics (symbols) in operation field and find the value of symbol
and literals to produce machine code. Now, if assembler do all this work in one scan then it is called single pass
assembler, otherwise if it does in multiple scans then called multiple pass assembler. Here assembler divides
these tasks in two passes:
 Pass-1:
1. Define symbols and literals and remember them in symbol table and literal table respectively.
2. Keep track of location counter
3. Process pseudo-operations
 Pass-2:
1. Generate object code by converting symbolic op-code into respective numeric op-code
2. Generate data for literals and look for values of symbols

Assemblers for x86

For 8086 processor a large set of assemblers are available, but the code running on one assembler will not run
on another assembler.
A86 was the 1st assembler run only under DOS operating system.
The names of few popular assemblers are:
MASM, NASM, TASM, FASM, HLA
NASM & FASM can run in all operating systems
2 popular assemblers are TASM & MASM. TASM is a Borland’s Turbo assembler. MASM is
Microsoft’s Macro Assembler. The code written in TASM is runs on MASM. But the reverse is not possible.
HLA is High Level Assembler, we can use high level control structures such as if, while, for, etc. which
make programming easy.

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Assembler Directives

There are some instructions in the assembly language program which are not a part of processor
instruction set. These instructions are instructions to the assembler, linker and loader. These are referred to as
pseudo-operations or as assembler directives.
The assembler directives enable us to control the way in which a program assembles and lists. They act
during the assembly of a program and do not generate any executable machine code.
There are many specialized assembler directives. Let us see the commonly used assembler directive in 8086
assembly language programming.

ASSUME:
It is used to tell the name of the logical segment the assembler to use for a specified segment.
E.g.: ASSUME CS: CODE
tells that the instructions for a program are in a logical segment named CODE.

Allocating Storage Space for Initialized Data

The syntax for storage allocation statement for initialized data is:
[variable-name] DEFINE initial-value [,initial-value]...

Where, variable-name is the identifier for each storage space. The assembler associates an
offset value for each variable name defined in the data segment. There are five basic forms of
the define directive:
Data Defining Directives

Eg:
RANKS DB 01H,02H,03H,04H
This statement directs the assembler to reserve four memory locations for a list named RANKS and
initialize them with the above specified four values.

MESSAGE DB “GOOD MORNING‟

This makes the assembler reserve the number of bytes of memory equal to the number of characters in
the string named MESSAGE and initializes those locations by the ASCII equivalent of these characters.
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VALUE DB 50H
This statement directs the assembler to reserve 50H memory bytes and leave them uninitialized for the
variable named VALUE.

Allocating Storage Space for Uninitialized Data

The reserve directives are used for reserving space for uninitialized data. It take a single
operand that specifies the number of units of space to be reserved. Each define directive has a
related reserve directive.
There are five basic forms of the reserve directive:

Defining Constants
The EQU Directive
The EQU directive is used for defining constants. The syntax is as follows:

CONSTANT_NAME EQU expression

END -End of Program:

The END directive marks the end of an assembly language program. When the assembler comes across
this END directive, it ignores the source lines available later on. Hence, it should be ensured that the END
statement should be the last statement in the file and should not appear in between. Also, no useful program
statement should lie in the file, after the END statement

ENDS-End of Segment:
This directive marks the end of a logical segment. The logical segments are assigned with the names
using the ASSUME directive. The names appear with the ENDS directive as prefixes to mark the end of those
particular segments. Whatever are the contents of the segments, they should appear in the program before
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ENDS. Any statement appearing after ENDS will be neglected from the segment. The structure shown below
explains the fact more clearly.
DATA SEGMENT
---------------------
---------------------
DATA ENDS

ASSUME CS: CODE, DS: DATA

CODE SEGMENT
---------------------
---------------------
CODE ENDS

LABEL-
Used to give a name to the current value in the location counter.
This directive is followed by a term that specifies the type you want associated with that name.
E.g: ENTRY_POINT LABEL FAR
NEXT: MOV AL, BL

SEGMENT-
Used to indicate the start of a logical segment.
E.g.: CODE SEGMENT
indicates to the assembler the start of a logical segment called CODE

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