100 RTL Design and Verification

Projects

A Curated Project Book for RTL/Verification Entry

Prepared by Kittu K Patel

VeriCore Initiative
t el
Pa
K
u
itt
K

Empowering Students Freshers into VLSI Design

May 18, 2025

RTL Verification VeriCore Premium Projects

Contents

Introduction 2

1 Project List – RTL Design & Verification 3

t el
Pa
K
u
itt
K

1
RTL Verification VeriCore Premium Projects

Introduction
The world of VLSI design demands a strong grip on both RTL Design and Verification.
To gain expertise, real-world project-based learning is the most effective path. This
document provides 100 hands-on projects to help you build a strong foundation in digital
design using Verilog/SystemVerilog, testbenches, and assertions.
Pro Tip
Start from beginner-level FSMs, then progress to memory controllers, protocol im-
plementations, and bus verifications. Try to simulate every design with timing and
waveform analysis.

t el
Pa
K
u
itt
K

2
RTL Verification VeriCore Premium Projects

1 Project List – RTL Design & Verification

Legend
Domain: [Design / Verification / Both]
Complexity: [Beginner / Intermediate / Advanced]

No. Project Title Description

1 4-bit Ripple Carry Adder RTL design of a basic ripple carry adder us-
ing structural modeling. Verify using test-
bench and waveform analysis.
2 4-bit Carry Lookahead Adder Implements fast addition using carry looka-
head logic. Verification involves random test-
cases and delay checks.
3 8-bit Up/Down Counter Synchronous counter with control signal to
toggle up/down. Verify with directed stimu-
lus.
4 Traffic Light Controller
t el
FSM-based design for 4-way traffic signals.
Pa
Verification includes timing sequence valida-
tion.
5 Sequence Detector (1011) FSM design to detect binary sequence. In-
K

cludes both Mealy and Moore implementa-

tion.
u

6 UART Protocol (Tx + Rx) Universal Asynchronous Receiver Transmit-

itt

ter core. Includes frame structure, start/stop

bits.
K

7 SPI Master-Slave Serial Peripheral Interface between master

and slave. Verification includes burst mode
testing.
8 I2C Controller Implements start, stop, ACK, and data
transfer conditions. Use self-checking test-
bench.
9 ALU with 8 Operations Arithmetic and logic operations controlled by
opcode. Add assertion-based checks.
10 Memory Controller Read/Write logic, address decoder and en-
able signals. Test memory access latency and
correctness.

3
RTL Verification VeriCore Premium Projects

Pro Tip
While working on protocol projects like UART, SPI, or AXI, always create sepa-
rate modules for transmitter, receiver, and control. This helps in modular testbench
development too.

No. Project Title Description

11 AXI4-Lite Master Interface RTL design of AXI4-lite master with address,
write, and read channels. Verification in-
cludes burst and handshake testing.
12 AXI4-Slave Protocol Checker SV-based monitor and scoreboard to verify
AXI4-slave response under back-pressure.
13 APB to AXI Bridge Design protocol converter between APB and
AXI. Validate timing translation with asser-
tions.
14 Round Robin Arbiter Arbitration logic for 4 masters. Verify fair

cases.
t el
grant distribution using randomized test-
Pa
15 LFSR-based Random Number Linear Feedback Shift Register for pseudo-
Generator random bit generation. Verify period and
seed behavior.
K

16 Priority Encoder (8:3) RTL design with enable and valid signals.
u

Write testbench with edge case priority tests.

itt

17 Wallace Tree Multiplier High-speed multiplier using tree structure.

Simulation and gate-delay analysis recom-
K

mended.
18 Pipelined Multiplier 3-stage pipelined architecture with stall and
flush conditions. Verify latency vs through-
put.
19 Booth Multiplier Signed multiplier using Booth’s algorithm.
Functional correctness via scoreboard.
20 ALU with Flag Outputs ALU design with zero, carry, negative, and
overflow flags. Assertion checks for edge
cases.
21 DMA Controller (2 channels) Direct Memory Access controller with source
and destination handshaking. Use FSM-
based design.
22 AXI Write Channel UVM Se- Create a reusable write sequence with con-
quence straints and callbacks for AXI verification.

4
RTL Verification VeriCore Premium Projects

No. Project Title Description

23 SPI UVM Testbench Develop agent, monitor, and scoreboard for
SPI. Include reset, corner, and burst scenar-
ios.
24 FSM Lock-Unlock Mechanism Secure lock mechanism using FSM. Include
test scenarios for wrong inputs and resets.
25 Parity Generator-Checker Generate and validate even/odd parity bits.
Use assertions to catch errors.
26 UART Frame Checker Create checker that validates start/stop,
data and parity bits using assertions.
27 Gray Code Counter Design and verify binary to Gray and Gray to
binary logic. Focus on glitch-free transitions.
28 Clock Divider Divide input clock by N. Testbench with
pulse counting and frequency verification.
29 Watchdog Timer Reset system if no activity in defined cycles.

30 Configurable FIFO (Sync) el

Use assertions to check timeouts.
t
RTL of synchronous FIFO with parameteri-
Pa
zable width and depth. Verify overflow and
underflow conditions.
K

Pro Tip
u

Always parameterize your designs like counters, FIFOs, and ALUs. It allows you to
itt

write scalable verification environments and reuse testbenches effectively.

K

No. Project Title Description

51 Configurable Counter with Load RTL of a universal counter with pro-
and Hold grammable load, hold, reset. Verify using
corner case tests.
52 Traffic Light Controller with FSM-based system supporting auto/manual
Pedestrian Override pedestrian signals. Add reset and flash
modes.
53 UART VIP with Protocol Score- Create reusable VIP for UART. Include
board golden model and scoreboard comparisons
for verification.
54 Time-Multiplexed Display Driver RTL design for 7-segment LED driver us-
ing time-division multiplexing. Verify using
waveform checking.

5
RTL Verification VeriCore Premium Projects

No. Project Title Description

55 Coverage-Driven Verification Write a coverage plan and implement cover-
Plan for SPI age bins for SPI protocol items.
56 UVM Factory Override Demon- Show base-to-derived class override in a test-
stration bench using UVM factory methods.
57 Reset Synchronizer Design RTL for synchronizing async reset into the
system clock domain. Verify using metasta-
bility simulations.
58 Formal Property Verification for Write SVA to check illegal transitions in FSM
FSM design using cover and assume-assert proper-
ties.
59 UVM RAL Model for Control Build Register Abstraction Layer (RAL)
Register Set model for DUT with read/write mirror
checking.
60 AMBA AHB-Lite Verification IP Develop lightweight VIP for AHB-Lite in-
cluding assertion-based protocol checker.
61 SystemVerilog Queue-Based el
Use dynamic queues to track push/pop be-
t
Pa
FIFO Monitor havior and validate ordering.
62 OTP Generation Logic RTL for generating and validating One-Time
Passwords. Use SVA to check uniqueness and
K

validity.
u

63 Handshake Protocol Checker Create assertions to check timing and de-

(Ready/Valid) pendency of ready-valid handshake-based de-
itt

sign.
K

64 Clock Gating Cell Verification Verify functionality of RTL clock gating cir-
cuit using coverage and assertions.
65 Bus Arbiter Coverage Plan Build functional coverage bins to track access
patterns and fairness in bus arbitration logic.
66 Sequence Layered Protocol Gen- UVM sequences layered with headers, pay-
erator loads, CRC fields. Include constrained ran-
dom generation.
67 Interrupt Controller (RTL + Design and verify priority-based interrupt
Testbench) handler with masking, vector table.
68 Bus Matrix Switch (4x4) Crossbar switch design for routing inputs to
outputs. Validate conflict and simultaneous
access.
69 BCD to Binary Converter RTL RTL of BCD to Binary converter. Include
input filtering and verification through asser-
tions.

6
RTL Verification VeriCore Premium Projects

No. Project Title Description

70 Dual Clock FIFO Design FIFO operating across two asyn-
chronous clock domains. Verify using test-
bench and metastability checks.

Pro Tip
To stand out, show at least one project where you’ve applied SystemVerilog Assertions
(SVA) or written a complete UVM agent. These are recruiter favorites!

No. Project Title Description

71 Low Power Finite State Machine Design FSM with clock gating and low power
techniques. Validate with SDF-aware simu-
lation.
72 Watchdog Timer with Window- RTL of watchdog with reset, timeout, and
ing Feature configurable windowing. Include coverage

73 Reusable Delay Line Module el

and negative tests.
t
Build a parameterized delay element useful
Pa
in SoC interfacing or bit alignment.
74 Latch and Flop Identification Verify latch vs flop behavior using SVA to
K

Checker flag latches in unintended logic.

75 Configurable Priority Encoder RTL module with variable input width and
u

one-hot encoded output.

itt

76 Arbiter Using Round Robin + Dual-mode arbiter RTL with configurable ar-
Priority Modes bitration policy. Include UVM coverage for
K

fairness.
77 Clock Divider by N RTL + Parameterized divider with clean duty cy-
Checker cle output. Add assertion-based glitch de-
tection.
78 Basic TLM Interface Modeling Implement TLM abstraction for memory
transaction verification in UVM.
79 Memory BIST Controller (Sim- RTL of Built-In Self Test controller with
plified) memory access patterns. Include testbench
for stuck-at testing.
80 Static Hazard Detector for Logic RTL module that identifies hazards. Verify
Circuit correctness using waveform snapshots.
81 Multicycle Path Annotator (Tim- Annotate timing-critical path RTL. Run
ing RTL) testbench and report slacks using delays.

7
RTL Verification VeriCore Premium Projects

No. Project Title Description

82 FSM with Illegal State Detector Include illegal state detector logic inside
FSM. Verify entry into valid states only.
83 Reset Generator Logic (POR) Power-On-Reset generation circuit with de-
lay counter. Simulate power glitch scenarios.
84 Power-Aware Verification Exam- Simulate power shut-down of block and as-
ple sert inactive interface using SVA.
85 Protocol Monitor with Error In- Create UVM monitor for packet protocol
jection and inject CRC/sequence errors to check re-
silience.
86 Dual Clock Synchronizer Checker Assertions to validate safe crossing be-
tween async clock domains using synchro-
nizer stages.
87 SVA for Bus Deadlock Detection Use SVA to monitor for deadlock on shared
bus (e.g., no grant for extended cycles).
88 Lint + CDC Report Analyzer
Script el
Build a Python + SV interface to parse CDC
and lint reports and generate dashboards.
t
Pa
89 Universal Pattern Generator for Build parameterized stimulus generator
Testbench (PRBS, toggle, ramp) for reuse in test-
benches.
K

90 Bus Functional Model (BFM) for Model BFM interface to drive and respond
u

APB to APB transactions.

itt

91 Interrupt Latency Checker Build RTL logic and assertions to measure

cycles from interrupt request to acknowledg-
K

ment.
92 Built-in Loopback Test Logic Add loopback logic to DUT and self-check
using testbench or formal.
93 Memory Map Decoder RTL + Address decoder logic with support for block
Test enable, error region, and mirroring.
94 Spec-to-Code Flow Verification Build project showing complete flow from
spec to RTL to testbench to coverage to re-
port.
95 Watchpoint Generator in UVM Extend monitor to trigger flags when specific
Monitor sequence or data seen. Add callback or log.
96 CRC Generator RTL + Polyno- Configurable CRC RTL supporting various
mial Config standard polynomials. Include testbench
with golden CRC check.
97 Command/Response Packet Track packet sequences in UVM monitor and
Tracker assert correct response timing.

8
No. Project Title Description
98 Parametrized N-bit RTL supporting both addition/subtraction
Adder/Subtractor based on select line. Verify overflow, under-
flow.
99 Multi-Threaded Testbench Use fork-join, mailboxes to create multi-
Framework threaded testbench for load testing.
100 Final Project: Mini UVM SoC Integrate mini SoC (UART + Memory +
Verification Environment Timer). Build complete UVM env with
scoreboard, coverage, assertions.

Pro Tip
Final Tip: Group your top 5–10 projects into a portfolio PDF and publish it on
LinkedIn or your GitHub. Use QR codes to link to code repositories or waveforms.

t el
Pa

Thank You for Reading!

K
u
itt

Vision Ahead
This document is not just a list — it is your launchpad into the world
K

of digital design and functional verification. Whether you are a

student, fresher, or professional, mastering even 50 of these projects will
sharpen your RTL and UVM skills like never before.

Words from Kittu K Patel

I hope this curated roadmap fuels your learning journey and inspires you
to build more. Remember: Every great chip starts with a small line of
RTL code.
For more guidance, connect with me on LinkedIn or explore content on
my technical platform. Keep learning, keep verifying!