ME6702 -Mechatronics Unit II - MICROPROCESSOR & MICROCONTROLLer

ME6702- MECHATRONICS

UNIT II 8085 MICROPROCESSOR AND 8051 MICROCONTROLLER

Introduction – Architecture of 8085 – Pin Configuration – Addressing Modes –Instruction set, Timing diagram
of 8085 – Concepts of 8051 microcontroller – Block diagram,.
1. Introduction
Programmable Logic Devices (PLD) are programmable systems and are generally used in manufacturing automation
to perform different control functions, according to the programs written in its memory, using low level languages of
commands. There are following three types of PLDs are being employed in mechatronics systems.

A Microprocessor
It is a digital integrated circuit which carries out necessary digital functions to process the information
obtained from measurement system.
B Microcomputer
It uses microprocessor as its central processing unit and contains all functions of a computer.
C Programmable Logic Controller (PLC)
It is used to control the operations of electro-mechanical devices especially in tough and
hazardous industrial environments.
A typical programmable machine has basic three components as shown in Figure 2.1.1:

Processor, which processes the information collected from measurement system and takes logical
decisions based on the information. Then it sends this information to actuators or output devices.
Memory, it stores
The input data collected from sensors
The programs to process the information and to take necessary decisions or actions. Program is a set of
instructions written for the processor to perform a task. A group of programs is called software.
Input/output devices: these are used to communicate with the outside world/operator.

Figure 2.1.1 Components of a programmable logic device

2. Microprocessor

It is a multi-purpose, programmable device that reads binary instructions from a storage device called memory,
processes the data according to the instructions, and then provides results as output. In common practice it is also
known as CPU (central processing unit). CPU can be referred as complete computational engine on a single chip.

Applications of microprocessors are classified primarily in two categories:

Reprogrammable Systems: Micro computers

Embedded Systems: photocopying machine, Digital camera

Microprocessor works or operates in binary digits i.e. 0 and 1, bits. These bits are nothing but electrical voltages in
the machine, generally 0 - low voltage level, and 1 - high voltage level.
A group of bits form a ‘word’. In general, the word length is about 8 bits. This is called as a ‘byte’. A word with a
length of 4 bits is called as a ‘Nibble’

Microprocessor processes the ‘commands in binary form’ to accomplish a task. These are called as ‘instructions’.
Instructions are generally entered through input devices and can be stored in a storage device called memory.

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Figure 2.1.2 Schematic of configuration of a micro processor

Figure 2.1.2 and 2.1.3 show the configuration and basic blocks of a microprocessor. The functions of each element are
as follows.

Figure 2.1.3 Working of a microprocessor

1. ALU: ALU stands for Arithmetical Logical Unit. As name indicates it has two parts:
a. Arithmetical unit which is responsible for mathematical operations like addition, subtraction, multiplication and
division,
b. Logical unit which is dedicated to take logical decisions like greater than, less than, equal to, not equal to etc.
(Basically AND/OR/NOT Operations)
2. Register Array: Registers are small storage devices that are available to CPU or processors. They act as temporary
storage for processing of intermediate data by mathematical or logical operations.

3. Control: This part of CPU is dedicated to coordinate data flow and signal flow through various types of buses i.e.
Data Bus, Control Bus, and Address Bus etc. It directs data flow between CPU and storage and I/O devices.

4. Memory: There are two different types of memory segments being used by the CPU. First is the ROM which stands
for Read Only Memory while other is R/W which stands for Read and Write Memory or Random Access Memory
(RAM).
a. ROM: From this memory unit, CPU can only read the stored data. No writing operations can be done in this
part of memory. Thus it is used to store the programs that need no alteration or changes like Monitor Program
or Keyboard driver etc.
b. R/W: As name indicates it is opposite to ROM and used for both reading and writing operations. In general
User’s program and instruction are stored in this segment of memory unit.

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5. Input Devices: Input devices are used to enter input data to microprocessor from Keyboard or from ADC which
receives data from sensors/signal conditioning systems.

6. Output Devices: These devices display the results/conclusions coming out from ALUs either in soft copy (Monitor)
or in Hard Copy (Printer).

2.1 Functions of microprocessor

Various functions of microprocessor are as follows:
 Microprocessor performs a variety of logical and mathematical operations using its ALU.
 It controls data flow in a system and hence can transfer data from one location to another based on the instructions
given to it.
 A microprocessor can take necessary decisions and jump to a new set of instructions based on those decisions.
A Elements of microprocessor
A simple microprocessor consists of following basic elements
Data Bus: Through data bus, the data flow between various storage units,ALU and memory units
Address Bus: It controls the flow of memory addresses between ALU and memory unit.
RD (read) and WR (write) lines set or obtain the addressed locations in the memory.
Clock line transfers the clock pulse sequence to the processor.
Reset Line is used to restart execution and reset the processor to zero.
Address Latch is a register which stores the addresses in the memory.
Program Counter: It is a register which can increment its value by 1 and keeps the record of number of instructions
executed. It can be set to zero when instructed.
Test Register: It is a register which stores intermediate or in-process data of ALU operations. For example it is
required to hold the ‘carry’ while ALU is performing ‘addition’ operation. It also stores the data which can be
accessed by Instruction decoder to make any decision.
State Buffers: These are tri-state buffers. A tri-state buffer can go to a third state in addition to the states of 1 and 0.
The instruction register and instruction decoder are responsible for controlling the operations of all other
components of a microprocessor.
Microcomputer
Microcomputer is a microprocessor based system. It is a data processing system that employs a microprocessor as its
central unit. Based on the input it takes decisions. These decisions are further used to control a system or to actuate an action
or operation.

3.1 Microprocessor based programmable controller

Schematic of microcontroller.

It is a microprocessor-based system. It implements the functions of a computer and a controller on a single chip. Generally
microcontroller is programmed for one specific application and it is dedicated to a specific control function.

Microcontrollers find applications in automobiles, aircraft, medical electronics and home appliances. They are small in size
and can be embedded in an electromechanical system without taking up much space. Thus we can have a system with its
functions completely designed into a chip. However microcontrollers have very little user programmable memory. Various
types of microcontroller chips available in market are: Motorola 68HC11, Zilog Z8 and Intel MCS51 and 96 series.

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Architecture of 8085

This is the functional block diagram of the 8085 Microprocessor.

Accumulator - It is a 8-bit register which is used to perform arithmetical and logical operation. It stores the
output of any operation. It also works as registers for I/O accesses.
Temporary Register- It is a 8-bit register which is used to hold the data on which the acumulator is computing
operation. It is also called as operand register because it provides operands to ALU.
Registers - These are general purposes registers. Microprocessor consists 6 general purpose registers of 8-bit each
named as B, C, D, E, H and L. Generally theses registers are not used for storing the data permanently. It carries
the 8-bits data. These are used only during the execution of the instructions.
These registers can also be used to carry the 16 bits data by making the pair of 2 registers. The valid register pairs
available are BC,DE HL. We can not use other pairs except BC,D,E and H,L. These registers are programmed by
user.
ALU - ALU performs the arithmetic operations and logical operation.

Flag Registers

It consists of 5 flip flops which changes its status according to the result stored in an accumulator. It is also known
as status registers. It is connected to the ALU.
There are five flip-flops in the flag register are as follows:

1. Sign(S)
2. zero(z) D7 D6 D5 D4 D3 D2 D1 D0
3. Auxiliary carry(AC)
4. Parity(P) S Z AC P CY
5. Carry(C)

All of the three flip flop set and reset according to the stored result in the accumulator.
1. Sign- If D7 of the result is 1 then sign flag is set otherwise reset. As we know that a number on the D7 always
decides the sign of the number. if D7 is 1: the number is negative. if D7 is 0: the number is positive.
2. Zeros (Z) - If the result stored in an accumulator is zero then this flip flop is set otherwise it is reset.
3. Auxiliary carry (AC) - If any carry goes from D3 to D4 in the output then it is set otherwise it is reset.
4. Parity (P) - If the no of 1's is even in the output stored in the accumulator then it is set otherwise it is reset for
the odd.
5. Carry(C) - If the result stored in an accumulator generates a carry in its final output then it is set otherwise it is
reset.
Instruction registers (IR) - It is a 8-bit register. When an instruction is fetched from memory then it is stored in
this register.

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Instruction Decoder - Instruction decoder identifies the instructions. It takes the information from instruction
register and decodes the instruction to be performed.
Program Counter - It is a 16 bit register used as memory pointer. It stores the memory address of the next
instruction to be executed.
Stack Pointer - It is also a 16 bit register used as memory pointer. It points to the memory location called stack.
Timing and Control Unit - It provides timing and control signal to the microprocessor to perform the various
operation. It has three control signals.
 ALE-Arithmetic Latch Enable, It provides control signal to synchronize the components of
microprocessor.
 RD- This is active low used for reading operation.
 WR-This is active low used for writing operation.
There are three status signal used in microprocessor S0, S1 and IO/M. It changes its status according the provided
input to these pins.
Serial Input Output Control - There are two pins in this unit. This unit is used for serial data communication.
Interrupt Unit - There are 6 interrupt pins in this unit. Generally an external hardware is connected to these pins.
Register Section - Many registers has been used in microprocessor. It consists of PIPO(Parallel Input Parallel
Output) register.

Pin Diagram and Pin description of 8085

8085 is a 40 pin IC, The signals from the pins can be grouped as follows

1. Power supply and clock signals

2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports

1. Power supply and Clock frequency signals:

Vcc: + 5 volt power supply

Vss: Ground
X1, X2 : internal clock generator. CLK (output)-Clock Output is used as the system clock for peripheral
and devices interfaced with the microprocessor.

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2. Address Bus:
A8 - A15: (output; 3-state)
It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address.

3. Data bus:
AD0 - AD7 (input/output; 3-state)
These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order address A0 -
A7.In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.
The CPU may read or write out data through these lines.

4. Control and Status signals:

ALE (output) - Address Latch Enable.
It is an output signal used to give information of AD0-AD7 contents.
It is a positive going pulse generated when a new operation is started by uP.
When pulse goes high it indicates that AD0-AD7 are address.
When it is low it indicates that the contents are data.

RD (output 3-state, active low)

Read memory or IO device.
This indicates that the selected memory location or I/O device is to be read and that the data bus is ready
for accepting data from the memory or I/O device

WR (output 3-state, active low)

Write memory or IO device.
This indicates that the data on the data bus is to be written into the selected memory location or I/O
device.

IO/M (output) - Select memory or an IO device.

This status signal indicates that the read / write operation relates to whether the memory or I/O device.
It goes high to indicate an I/O operation.
It goes low for memory operations.

5. Status Signals:

S1: S2:
It is used to know the type of current operation of the microprocessor.

IO/M S1 S0 OPERATION
0 1 1 Opcode fetch
0 1 0 Memory read
0 0 1 Memory write
1 1 0 I/O read
1 0 1 I/O write
1 1 0 Interrupt acknowledge
Z 0 1 Halt
Z x x Hold
Z x x Reset

6. Interrupts and externally initiated operations:

They are the signals initiated by an external device to request the microprocessor to do a particular task or
work.

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There are five hardware interrupts

TRAP, RST 7.5, RST 6.5, RST 5.5 & INTA

1.On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low INTA
(Interrupt Acknowledge) signal.
2. Reset In (input, active low)
3.This signal is used to reset the microprocessor.
4. The program counter inside the microprocessor is set to zero.
5. The buses are tri-stated. Reset Out (Output)
6.It indicates CPU is being reset.
7. Used to reset all the connected devices when the microprocessor is reset.

7. Direct Memory Access (DMA): Tri state devices:

 When 2 or more devices are connected to a common bus, to prevent the devices from interfering
with each other, the tristate gates are used to disconnect all devices except the one that is
communicating at a given instant.
 The CPU controls the data transfer operation between memory and I/O device. Direct Memory
Access operation is used for large volume data transfer between memory and an I/O device
directly.
 The CPU is disabled by tri-stating its buses and the transfer is effected directly by external control
circuits.
 HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the
microprocessor acknowledges the request by sending out HLDA signal and leaves out the control
of the buses. After the HLDA signal the DMA controller starts the direct transfer of data.
READY(input)
Memory and I/O devices will have slower response compared to microprocessors.
 Before completing the present job such a slow peripheral may not be able to handle further data
or control signal from CPU.
 The processor sets the READY signal after completing the present job to access the data.
 The microprocessor enters into WAIT state while the READY pin is disabled.
8. Single Bit Serial I/O ports:
8. SID (input) Serial input data line/SOD (output) Serial output data line these signals are used for serial
communication.

Addressing Modes in 8085

1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Indirect Addressing Mode
5. Implied/implicit Addressing Mode

Immediate Addressing Mode:

An immediate is transferred directly to the register.
Eg: -MVI A, 30H (30H is copied into the register A) MVI B,40H(40H is copied into the register B).

Register Addressing Mode:

Data is copied from one register to another register.
Eg: -MOV B, A (the content of A is copied into the register B)MOV A, C (the content of C is copied into the
register A).

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Direct Addressing Mode:

Data is directly copied from the given address to the register.
Eg: -LDA 3000H (The content at the location 3000H is copied to the register A).

Indirect Addressing Mode:

The data is transferred from the address pointed by the data in a register to other register.
Eg: - MOV A, M (data is transferred from the memory location pointed by the register to the accumulator).

Implied Addressing Mode:

This mode doesn't require any operand. The data is specified by opcode itself.
Eg: -RALCMP

Bus Structure in 8085

There are three buses in Microprocessor:

1. Address Bus
2. Data Bus
3. Control Bus

Interrupts In 8085
What is Interrupt?
Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of processor
and get itself serviced. Generally, a particular task is assigned to that interrupt signal. In the microprocessor based
system the interrupts are used for data transfer between the peripheral devices and the microprocessor.

Interrupt Service Routine (ISR)

A small program or a routine that when executed services the corresponding interrupting source is called
as an ISR.

Mask able/Non-Mask able Interrupt

An interrupt that can be disabled by writing some instruction is known as Maskable Interrupt otherwise it
is called Non-Mask able Interrupt.
There are 6 pins available in 8085 for interrupt: TRAP,RST 7.5,RST6.5,RST5.5,INTR & INTA

TRAP
It is non maskable edge and level triggered interrupt. TRAP has the highest priority ,TRAP interrupts can only be
masked by resetting the microprocessor. There is no other way to mask it.

RST7.5
It has the second highest priority. It is maskable and edge level triggered interrupt. It can also be reset or masked
by resetting microprocessor. It can also be resetted by DI instruction.

RST6.5 and RST5.5

These are level triggered and maskable interrupts. When RST6.5 pin is at logic 1, INTE flip-flop is set. RST 6.5
has third highest priority and RST 5.5 has fourth highest priority.
It can be masked by giving DI and SIM instructions or by resetting microprocessor.

INTR
It is level triggered and maskable interrupt. The following sequence of events occurs when INTR signal goes
high:
The 8085 checks the status of INTR signal during execution of each instruction.
If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt acknowledge
signal, if the interrupt is enabled.
On receiving the instruction, the 8085 save the address of next instruction on stack and execute received
instruction.
It has the lowest priority. It can be disabled by resetting the microprocessor.

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Instruction Set 8085

I. Control
II. Logical
III. Branching
IV. Arithmetic
V. Data Transfer

Control Instructions

Opcode Operand Explanation Description

NOP none No operation No operation is performed. The instruction is fetched and

decoded. However no operation is executed. Example: NOP

HLT none Halt and enter wait The CPU finishes executing the current instruction and halts
state any further execution. An interrupt or reset is necessary to
exit from the halt state. Example: HLT

DI none Disable interrupts The interrupt enable flip-flop is reset and all the interrupts
except the TRAP are disabled. No flags are affected.
Example: DI

EI none Enable interrupts The interrupt enable flip-flop is set and all interrupts are
enabled. No flags are affected. After a system reset or the
acknowledgement of an interrupt, the interrupt enable flip-
flop is reset, thus disabling the interrupts. This instruction is
necessary to re enable the interrupts (except TRAP).
Example: EI

RIM none Read interrupt mas This is a multipurpose instruction used to read the status of
interrupts 7.5, 6.5, 5.5 and read serial data input bit. The
instruction loads eight bits in the accumulator with the
following interpretations. Example: RIM

SIM none Set interrupt mask This is a multipurpose instruction and used to implement the
8085 interrupts 7.5, 6.5, 5.5, and serial data output. The
instruction interprets the accumulator contents as follows.
Example: SIM

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LOGICAL INSTRUCTIONS
Opcode Operand Explanation of Instruction Description

CMP RM Compare register or memory The contents of the operand (register or memory) are M
with accumulator compared with the contents of the accumulator. Both
contents are preserved. The result of the comparison is
shown by setting the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset Example:
CMP B or CMP M

CPI 8-bit data Compare immediate with The second byte (8-bit data) is compared with the contents
accumulator of the accumulator. The values being compared remain
unchanged. The result of the comparison is shown by
setting the flags of the PSW as follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset Example: CPI
89H

ANA R Logical AND register or The contents of the accumulator are logically ANDed with
M memory with accumulator M the contents of the operand (register or memory), and
the result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set. Example: ANA B or ANA
M

ANI 8-bit Logical AND immediate with The contents of the accumulator are logically ANDed
data accumulator withthe8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set. Example: ANI 86H

XRA R Exclusive OR register or The contents of the accumulator are Exclusive ORed with M
M memory with accumulator the contents of the operand (register or memory), and the
result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset. Example: XRA B or XRA M

XRI 8-bit Exclusive OR immediate with The contents of the accumulator are Exclusive ORed with
data accumulator the 8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset. Example: XRI 86H

ORA R Logical OR register or The contents of the accumulator are logically ORed with M
M memory with accumulator the contents of the operand (register or memory), and the
result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset. Example: ORA B or ORA M

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ORI 8-bit Logical OR immediate with The contents of the accumulator are logically ORed with
data accumulator the 8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset. Example: ORI 86H

RLC none Rotate accumulator left Each binary bit of the accumulator is rotated left by one
position. Bit D7 is placed in the position of D0 as well as in
the Carry flag. CY is modified according to bit D7. S, Z, P, AC
are not affected. Example: RLC

RRC none Rotate accumulator right Each binary bit of the accumulator is rotated right by one
position. Bit D0 is placed in the position of D7 as well as in
the Carry flag. CY is modified according to bit D0. S, Z, P, AC
are not affected. Example: RRC

RAL none Rotate accumulator left Each binary bit of the accumulator is rotated left by one
through carry position through the Carry flag. Bit D7 is placed in the Carry
flag, and the Carry flag is placed in the least significant
position D0. CY is modified according to bit D7. S, Z, P, AC
are not affected. Example: RAL

RAR none Rotate accumulator right Each binary bit of the accumulator is rotated right by one
through carry position through the Carry flag. Bit D0 is placed in the Carry
flag, and the Carry flag is placed in the most significant
position D7. CY is modified according to bit D0. S, Z, P, AC
are not affected. Example: RAR

CMA none Complement accumulator The contents of the accumulator are complemented. No
flags are affected. Example: CMA

CMC none Complement carry The Carry flag is complemented. No other flags are
affected. Example: CMC

STC none Set Carry Set Carry Example: STC

RANCHING INSTRUCTIONS
Opcode Operand Explanation of Description
Instruction

JMP 16-bit address Jump The program sequence is

unconditionally transferred to the memory
location specified by the
16-bit address given in the
operand. Example: JMP
2034H or JMP XYZ

Opcode Description Flag Status 16-bit address Jump conditionally The program sequence is
transferred to the memory
JC Jump on Carry CY = 1 location specified by the
JNC Jump on no Carry CY = 0 16-bit address given in the
operand based on the
JP Jump on positive S=0
specified flag of the PSW
JM Jump on minus S=1 as described below.
JZ Jump on zero Z=1 Example: JZ 2034H or JZ
XYZ
JNZ Jump on no zero Z=0

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JPE Jump on parity even P=1

JPO Jump on parity odd P=0

Opcode Description Flag Status 16-bit address Unconditional The program sequence is
subroutine call transferred to the memory
CC Call on Carry CY = 1 location specified by the
CNC Call on no Carry CY = 0 16-bit address given in the
operand. Before the
CP Call on positive S=0 transfer, the address of the
CM Call on minus S=1 next instruction after CALL
CZ Call on zero Z=1 (the contents of the
CNZ Call on no zero Z=0 program counter) is
CPE Call on parity even P=1 pushed onto the stack.
Example: CALL 2034H or
CPO Call on parity odd P=0 CALL XYZ

RET none Return from The program sequence is

subroutine transferred from the
unconditionally subroutine to the calling
program. The two bytes
from the top of the stack
are copied into the
program counter,and
program execution begins
at the new address.
Example: RET

Opcode Description Flag Status none Return from The program sequence is
subroutine transferred from the
RC Return on Carry CY = 1 conditionally subroutine to the calling
RNC Return on no Carry CY = 0 program based on the
specified flag of the PSW
RP Return on positive S=0
as described below. The
RM Return on minus S=1 two bytes from the top of
RZ Return on zero Z=1 the stack are copied into
the program counter, and
RNZ Return on no zero Z=0 program execution begins
RPE Return on parity even P = 1 at the new address.
Example: RZ
RPO Return on parity odd P=0

PCHL none Load program The contents of registers

counter with HL H and L are copied into the
contents program counter. The
contents of H are placed as
the high-order byte and
the contents of L as the
low-order byte. Example:
PCHL

RST 0-7 Restart The RST instruction is

equivalent to a 1-byte call
instruction to one of eight
memory locations
depending upon the
number. The instructions
are generally used in
conjunction with interrupts

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and inserted using external

hardware. However these
can be used as software
instructions in a program
to transfer program
execution to one of the
eight locations. The
addresses are:
Restart
Instruction
Address
RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
The 8085 has four
additional interrupts and
these interrupts generate
RST instructions internally
and thus do not require
any external hardware.
These instructions and
their Restart addresses
are:
Restart
Interrupt
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

Arithmetic Instructions

Opcode Operand Explanation of Instruction Description

ADD RM Add register or memory, to The contents of the operand (register or memory) are
accumulator added to the contents of the accumulator and the result
is stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the
HL registers. All flags are modified to reflect the result
of the addition. Example: ADD B or ADD M

ADC RM Add register to accumulator The contents of the operand (register or memory) and M
with carry the Carry flag are added to the contents of the
accumulator and the result is stored in the accumulator.
If the operand is a memory location, its location is
specified by the contents of the HL registers. All flags
are modified to reflect the result of the addition.
Example: ADC B or ADC M

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ADI 8-bit data Add immediate to The 8-bit data (operand) is added to the contents of the
accumulator accumulator and the result is stored in the accumulator.
All flags are modified to reflect the result of the
addition. Example: ADI 45H

ACI 8-bit data Add immediate to The 8-bit data (operand) and the Carry flag are added to
accumulator with carry the contents of the accumulator and the result is stored
in the accumulator. All flags are modified to reflect the
result of the addition. Example: ACI 45H

LXI Reg. pair, Load register pair The instruction loads 16-bit data in the register pair
16-bit data immediate designated in the operand. Example: LXI H, 2034H or
LXI H, XYZ

DAD Reg. pair Add register pair to H and The 16-bit contents of the specified register pair are
L registers added to the contents of the HL register and the sum is
stored in the HL register. The contents of the source
register pair are not altered. If the result is larger than 16
bits, the CY flag is set. No other flags are affected.
Example: DAD H

SUB R Subtract register or The contents of the operand (register or memory ) are
M memory from accumulator subtracted from the contents of the accumulator, and the
result is stored in the accumulator. If the operand is a
memory location, its location is specified by the
contents of the HL registers. All flags are modified to
reflect the result of the subtraction. Example: SUB B or
SUB M

SBB R Subtract source and borrow The contents of the operand (register or memory ) and
M from accumulator M the Borrow flag are subtracted from the contents of
the accumulator and the result is placed in the
accumulator. If the operand is a memory location, its
location is specified by the contents of the HL registers.
All flags are modified to reflect the result of the
subtraction. Example: SBB B or SBB M

SUI 8-bit data Subtract immediate from The 8-bit data (operand) is subtracted from the contents
accumulator of the accumulator and the result is stored in the
accumulator. All flags are modified to reflect the result
of the subtraction. Example: SUI 45H

SBI 8-bit data Subtract immediate from The contents of register H are exchanged with the
accumulator with borrow contents of register D, and the contents of register L are
exchanged with the contents of register E. Example:
XCHG

INR R Increment register or The contents of the designated register or memory) are
M memory by 1 incremented by 1 and the result is stored in the same
place. If the operand is a memory location, its location is
specified by the contents of the HL registers.
Example: INR B or INR M

INX R Increment register pair by 1 The contents of the designated register pair are
incremented by 1 and the result is stored in the same
place. Example: INX H

DCR R Decrement register or The contents of the designated register or memory are
M memory by 1 M decremented by 1 and the result is stored in the same
place. If the operand is a memory location, its location is
specified by the contents of the HL registers.
Example: DCR B or DCR M

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DCX R Decrement register pair by The contents of the designated register pair are
1 decremented by 1 and the result is stored in the same
place. Example: DCX H

DAA none Decimal adjust accumulator The contents of the accumulator are changed from a
binary value to two 4-bit binary coded decimal (BCD)
digits. This is the only instruction that uses the auxiliary
flag to perform the binary to BCD conversion, and the
conversion procedure is described below. S, Z, AC, P,
CY flags are altered to reflect the results of the
operation. If the value of the low-order 4-bits in the
accumulator is greater than 9 or if AC flag is set, the
instruction adds 6 to the low-order four bits. If the value
of the high-order 4-bits in the accumulator is greater
than 9 or if the Carry flag is set, the instruction adds 6 to
the high-order four bits. Example: DAA

Data Transfer Instructions

Opcode Operand Explanation of Instruction Description

MOV Rd, Rs Copy from source(Rs) to This instruction copies the contents of the source
M, Rs detination(Rd) register into the destination register; the contents of
Rd, M the source register are not altered. If one of the
operands is a memory location, its location is
specified by the contents of the HL registers.
Example: MOV B, C or MOV B, M

MVI Rd, data Move immediate 8-bit The 8-bit data is stored in the destination register or
M, data memory. If the operand is a memory location, its
location is specified by the contents of the HL
registers. Example: MVI B, 57H or MVI M, 57H

LDA 16-bit Load accumulator The contents of a memory location, specified by a

address 16-bit address in the operand, are copied to the
accumulator. The contents of the source are not
altered. Example: LDA 2034H

LDAX B/D Reg. Load accumulator indirect The contents of the designated register pair point to a
pair memory location. This instruction copies the
contents of that memory location into the
accumulator. The contents of either the register pair
or the memory location are not altered. Example:
LDAX B

LXI Reg. pair, Load register pair immediate The instruction loads 16-bit data in the register pair
16-bit data designated in the operand. Example: LXI H, 2034H
or LXI H, XYZ

LHLD 16-bit Load H and L registers direct The instruction copies the contents of the memory
address location pointed out by the 16-bit address into
register L and copies the contents of the next
memory location into register H. The contents of
source memory locations are not altered. Example:
LHLD 2040H

STA 16-bit 16-bit address The contents of the accumulator are copied into the
address memory location specified by the operand. This is a
3-byte instruction, the second byte specifies the low-
order address and the third byte specifies the high-
order address. Example: STA 4350H

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STAX Reg. pair Store accumulator indirect The contents of the accumulator are copied into the
memory location specified by the contents of the
operand (register pair). The contents of the
accumulator are not altered. Example: STAX B

SHLD 16-bit Store H and L registers direct The contents of register L are stored into the memory
address location specified by the 16-bit address in the
operand and the contents of H register are stored into
the next memory location by incrementing the
operand. The contents of registers HL are not altered.
This is a 3-byte instruction, the second byte specifies
the low-order address and the third byte specifies the
high-order address. Example: SHLD 2470H

XCHG none Exchange H and L with D and The contents of register H are exchanged with the
E contents of register D, and the contents of register L
are exchanged with the contents of register E.
Example: XCHG

SPHL none Copy H and L registers to the The instruction loads the contents of the H and L
stack pointer registers into
the stack pointer register, the contents of the H
register provide the high-order address and the
contents of the L register provide the low-order
address. The contents of the H
and L registers are not altered. Example: SPHL

XTHL none Exchange H and L with top of The contents of the L register are exchanged with the
stack stack location pointed out by the contents of the
stack pointer register. The contents of the H register
are exchanged with the next stack location (SP+1);
however, the contents of the stack pointer register
are not altered. Example: XTHL

PUSH Reg. pair Push register pair onto stack The contents of the register pair designated in the
operand are copied onto the stack in the following
sequence. The stack pointer register is decremented
and the contents of the highorder register (B, D, H,
A) are copied into that location. The stack pointer
register is decremented again and the contents of the
low-order register (C, E, L, flags) are copied to that
location. Example: PUSH B or PUSH A

POP Reg. pair Pop off stack to register pair The contents of the memory location pointed out by
the stack pointer register are copied to the low-order
register (C, E, L, status flags) of the operand. The
stack pointer is incremented by 1 and the contents of
that memory location are copied to the high-order
register (B, D, H, A) of the operand. The stack
pointer register is again incremented by 1.
Example: POP H or POP A

OUT 8-bit port Output data from accumulator The contents of the accumulator are copied into the
address to a port with 8-bit address I/O port specified by the operand. Example:
OUT F8H

IN 8-bit port Input data to accumulator from The contents of the input port designated in the
address a port with 8-bit address operand are read and loaded into the accumulator.
Example: IN 8CH

Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a
graphical format. The execution time is represented in T-states.
Instruction Cycle: The time required to execute an instruction is called instruction cycle.

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Machine Cycle: The time required to access the memory or input/output devices is called machine cycle.
T-State: The machine cycle and instruction cycle takes multiple clock periods.
A portion of an operation carried out in one system clock period is called as T-state.

MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 basic machine cycles. They are

Opcode fetch cycle (4T)

Memory read cycle (3 T)
Memory write cycle (3 T)
I/O read cycle (3 T)
I/O write cycle (3 T)

Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085 processor
executes an instruction, it will execute some of the machine cycles in a specific order.

The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a
machine cycle is expressed in T-states. One T-state is equal to the time period of the internal clock signal of the
processor. The T-state starts at the falling edge of a clock.

Opcode fetch machine cycle of 8085 :

Each instruction of the processor has one byte opcode. The opcodes are stored in memory. So, the
processor executes the opcode fetch machine cycle to fetch the opcode from memory.Hence, every instruction
starts with opcode fetch machine cycle.The time taken by the processor to execute the opcode fetch cycle is 4T.
In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are
used for internal operations by the processor.

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Fig – Timing Diagram for Opcode Fetch Machine Cycle

Memory Read Machine Cycle of 8085:

The memory read machine cycle is executed by the processor to read a data byte from memory.
The processor takes 3T states to execute this cycle.The instructions which have more than one byte word
size will use the machine cycle after the opcode fetch machine cycle

Timing Diagram for Memory Read Machine Cycle Timing Diagram for Memory Write Machine Cycle

Memory Write Machine Cycle of 8085:

The memory write machine cycle is executed by the processor to write a data byte in a memory location.
The processor takes,3T states to execute this machine cycle..

I/O Read Cycle of 8085:

The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral,
which is I/O, mapped in the system.The processor takes 3T states to execute this machine cycle.
The IN instruction uses this machine cycle during the execution

Timing Diagram for I/O Read Machine Cycle Timing Diagram for I/O Write Machine Cycle

I/O Write Cycle of 8085:

The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a
peripheral, which is I/O, mapped in the system.
The processor takes, 3T states to execute this machine cycle

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8051 MICROCONTROLLER

A micro controller is an integrated circuit or a chip with a processor and other support devices like
program memory, data memory, I/O ports, serial communication interface etc integrated together. Unlike a
microprocessor (ex: Intel 8085), a microcontroller does not require any external interfacing of support devices.

The 8051 Microcontroller is one of the basic types of microcontroller, designed by Intel in 1980’s.

This microcontroller was based on Harvard Architecture and developed primarily for use in embedded
systems technology. Normally, this microcontroller was developed using NMOS technology, which requires more
power to operate. Therefore, Intel redesigned Microcontroller 8051 using CMOS technology and their updated
versions came with a letter C in their name, for instance an 80C51 it is an 8 bit microcontroller. These
latest Microcontrollers requires less power to operate as compared to their previous versions.

The 8051 Microcontroller has two buses and two memory spaces of 64K X 8 size for program and data units. It
has an 8 bit processing unit and 8 bit accumulator units.

8051 Microcontroller Architecture

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Central Processor Unit (CPU) As we know that the CPU is the brain of any processing device of the
microcontroller. It monitors and controls all operations that are performed on the Microcontroller units. The User
has no control over the work of the CPU directly . It reads program written in ROM memory and executes them
and do the expected task of that application.

Interrupts As its name suggests, Interrupt is a subroutine call that interrupts of the microcontrollers main
operations or work and causes it to execute any other program, which is more important at the time of operation.
The feature of Interrupt is very useful as it helps in case of emergency operations. An Interrupts gives us a
mechanism to put on hold the ongoing operations, execute a subroutine and then again resumes to another type of
operations.

The Microcontroller 8051 can be configured in such a way that it temporarily terminates or pause the main
program at the occurrence of interrupts. When a subroutine is completed, Then the execution of main program
starts. Generally five interrupt sources are there in 8051 Microcontroller. There are 5 vectored interrupts are
shown in below

 INTO
 TFO
 INT1
 TF1
 R1/T1

Out of these, (INT0) ̅ and (INT1) ̅ are external interrupts that could be negative edge triggered or low level
triggered. When All these interrupts are activated, set the corresponding flogs except for serial interrupt,.The
interrupt flags are cleared when the processor branches to the interrupt service routine (ISR). The external
interrupt flags are cleared when the processor branches to the interrupt service routine, provides the interrupt is a
negative edge triggered whereas the timers and serial port interrupts two of them are external interrupts, two of
them are timer interrupts and one serial port interrupt terminal in general.

Memory

Microcontroller requires a program which is a collection of instructions. This program tells microcontroller to do
specific tasks. These programs require a memory on which these can be saved and read by Microcontroller to
perform specific operations of a particular task. The memory which is used to store the program is known as code
memory or Program memory of applications. It is known as ROM memory of microcontroller also requires a
memory to store data or operands temporarily of the micro controller. The data memory of the 8051 is used to
store data temporarily for operation is known RAM. 8051 microcontroller has 4K of code memory or program
memory, that has 4KB ROM and also 128 bytes of data memory of RAM.

BUS

Basically Bus is a collection of wires which work as a communication channel or medium for transfer of Data.
These buses consists of 8, 16 or more wires of the microcontroller. Thus, these can carry 8 bits,16 bits
simultaneously. Hire two types of buses that are shown in below

 Address Bus
 Data Bus

Address Bus: Microcontroller 8051 has a 16 bit address bus for transferring the data. It is used to address
memory locations and to transfer the address from CPU to Memory of the microcontroller. It has four addressing
modes that are

 Immediate addressing modes.

 Bank address (or) Register addressing mode.
 Direct Addressing mode.
 Register indirect addressing mode.

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Data Bus: Microcontroller 8051 has 8 bits of the data bus, which is used to carry data of particular applications.

Oscillator
Generally, we know that the microcontroller is a device, therefore it requires clock pulses for its operation of
microcontroller applications. For this purpose, microcontroller 8051 has an on-chip oscillator which works as a
clock source for Central Processing Unit of the microcontroller. The output pulses of oscillator are stable.
Therefore, it enables synchronized work of all parts of the 8051 Microcontroller.
Input/Output Port
Normally microcontroller is used in embedded systems to control the operation of machines in the
microcontroller. Therefore, to connect it to other machines, devices or peripherals we require I/O interfacing
ports in the microcontroller interface. For this purpose microcontroller 8051 has 4 input, output ports to connect
it to the other peripherals
Timers/Counters
8051 microcontroller has two 16 bit timers and counters. These counters are again divided into a 8 bit register.
The timers are used for measurement of intervals to determine the pulse width of pulses.

8051 Pin Diagram & Description

For describing pin diagram and pin configuration of 8051, we are taking into consideration a 40 pin DIP (Dual
inline package). Now let’s go through pin configuration in detail.

Pin-40 : Named as Vcc is the main power source. Usually its +5V DC.
You may note some pins are designated with two signals (shown in brackets).
Pins 32-39: Known as Port 0 (P0.0 to P0.7) – In addition to serving as I/O port, lower order address and data bus
signals are multiplexed with this port (to serve the purpose of external memory interfacing). This is a bi
directional I/O port (the only one in 8051) and external pull up resistors are required to function this port as I/O.
Pin-31:- ALE aka Address Latch Enable is used to demultiplex the address-data signal of port 0 (for external
memory interfacing.) 2 ALE pulses are available for each machine cycle.
Pin-30:- EA/ External Access input is used to enable or disallow external memory interfacing. If there is no
external memory requirement, this pin is pulled high by connecting it to Vcc.

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Pin- 29:- PSEN or Program Store Enable is used to read signal from external program memory.
Pins- 21-28:- Known as Port 2 (P 2.0 to P 2.7) – in addition to serving as I/O port, higher order address bus
signals are multiplexed with this quasi bi directional port.
Pin 20:- Named as Vss – it represents ground (0 V) connection.
Pins 18 and 19:- Used for interfacing an external crystal to provide system clock.
Pins 10 – 17:- Known as Port 3. This port also serves some other functions like interrupts, timer input, control
signals for external memory interfacing RD and WR , serial communication signals RxD and TxD etc. This is a
quasi bi directional port with internal pull up.
Pin 9:- As explained before RESET pin is used to set the 8051 microcontroller to its initial values, while the
microcontroller is working or at the initial start of application. The RESET pin must be set high for 2 machine
cycles.
Pins 1 – 8:- Known as Port 1. Unlike other ports, this port does not serve any other functions. Port 1 is an
internally pulled up, quasi bi directional I/O port.

Applications of 8051 Microcontroller

Light sensing and controlling devices

Temperature sensing and controlling devices

Fire detections and safety devices
Automobile applications
Defense applications
Some industrial applications of micro controller and its applications
Industrial instrumentation devices
Process control devices
Some of 8051 microcontroller devices are used in measurement applications
Voltmeter applications
Measuring and revolving objects
Current meter objects
Hand held metering system

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