Floating Point Arithmetic Unit with Multi-Precision

for DSP Applications

2021 Fourth International Conference on Electrical, Computer and Communication Technologies (ICECCT) | 978-1-6654-1480-7/21/$31.00 ©2021 IEEE | DOI: 10.1109/ICECCT52121.2021.9616759

M. VishnuPriya#, B. Nancharaiah*
#
Dept of ECE, Usha Rama Collage of Engineering and Technology, Telaprolu-521109, Andhra Pradesh, India,
[email protected]
*
Dept of ECE, Usha Rama Collage of Engineering and Technology, Telaprolu-521109, Andhra Pradesh, India,
[email protected]

Abstract— In digital signal processing, the arithmetic of density, high performance, low value and low value
floats is very significant. The arithmetic float point unit, solutions have now become the most powerful options for
which is normally selectable for various precision floating implementing floating point hardware arithmetic units
point numbers, is able to work at different precision floating Versatile prime precious operation applications include two
point numbers among various types of engineering entirely separate floating point format are presented in the
application. Flexible architecture of floating point arithmetic IEEE 754 standard, binary exchange and decimal exchange
is provided by the accelerated growth of the FPGA
formats. This section only focus on the regular binary
technologies. This paper explains how a common floating
format IEEE 754 representation with a single-precision,
point arithmetic method based on FPGA is constructed using
Verilog HDL. The arithmetic floating point unit is capable of consisting of a one bit (S) symbol an eight-bit (E) and a
supplementing and subtracting a few double precision float twenty-three-bit (M) or Mantissa.
point numbers or two singles. The floating point arithmetic
unit will execute a pair of double-precision floating point II. LITERATURE SURVEY
numbers or two single-precision floating point numbers. At A. A VARIABLE PRECISION FIXED AND FLOATING POINT LIBRARY
the conclusion of this article, simulation and hardware test FOR RECONFIGURABLE HARDWARE
illustrate functionality and measurement correctness.
Floating point library with variable precision (VFloat)
that supports both standard IEEE and general floating point
Keywords— Floating point; FPGA; Single-precision; Double-
formats. The use of arbitrary floating-point formats which
precision, DSP Applications
do not essentially adjust to standard IEEE sizes may be
I. INTRODUCTION appropriate to optimally reconfigure hardware
A vast volume of information with various precisions and implementation. Any of the floating point formats
high real time demands has to be processed in optical signal historically printed to be used for reconfigurable square
processing, image processing, speech communications, hardware calculation subsets of our format. The VFloat
wireless communications and many other areas. The library's variable precision hardware modules can be
arithmetic of the floating point has high precision properties. maltreated to allow for a better similarity with optimized
But arithmetic from floating points occupies more hardware data paths with optimal bit widths for each service. There
resources compared to integers, so it is used in many systems are three different formats in the VFloat library. Converts
by software. The running speed is also very slow for this between fixed- point and floating-point formats arithmetic
floating arithmetic. And while arithmetical hardware can operations and administration. The format transformations
improve compute speed, the arithmetic of floating points include a single type of hybrid fixed and floating point
demands several floating point units for multiple precision operations [1].
that takes up a lot of hardware resources. There is also a
B. FLOATING POINT ADDERS AND FPGA MULTIPLIERS
decrease in hardware costs when floating point unit is
For the implementation of the IEEE-754 floating point
constructed that can reach a different computing precision.
adder multiplier for FPGA and FPU applications, an
And it is possible to build FPGA rapidly.
increasing trend in the FPGA community is being created. As
In floating point high languages, the
such, the formation of FPGA technology optimized floating
implementation of the floating point arithmetic was
point units is important. The FPGA style zone varies entirely
suitable, but hardware implementation of the arithmetic is
from the VLSI space; thus, FPGA optimizations would have a
difficult with VLSI technology extension, high integration

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major effect on VLSI optimizations. FPGA setting in E. A DUAL-MODE FLOATING POINT DIVIDER EXACT DUAL-
particular the planning area will effectively be used to scale MODE
back latency to such only minimal similarities. It can be Many scientific implementation require more than double-
especially difficult for FPGAs to find the right balance precision or double-extension floating point arithmetic,
between clock speed, latency and space. The styles listed here additional proper computations. The concept of a dual-mode
change the Xilinx Virtex4 FPGA (-11 Speed Grade) to floating precision divisor that is also suitable for two double
achieve a DPD compliant 270 MHz IEEE with a 9-stage adder precision division in parallel for the implementation of a dual
and a 14-stage pipeline. The global market for the adder is mode, quadruple precision floating point divider a radix-4
nearly 500 slices and under 750 multiplier slices [2]. SRT algorithm with marginal redundancy is used. A double,
four-point, dual and four-point divisions for estimate of the
C. MULTIPLIERS SPEED-UP IN BASED FPGA BIT PARALLEL region and a poor wait in the case Units are deployed and
The technological optimizations for a fixed- point synthesized in VHDL. The synthesis results indicate a 22
bit/parallel multiplier are taken into consideration by this percent improvement in the region of the double-mode four-
methodology their implementation by taking into account the precision divider than the four-price precise, and a 1 percent
use of incubator primitive and macro support in modern increase in bad case delay. 59 cycles is needed for a four- fold
FPGAs. ASIC is largely due to low Non-Recurrent precision division, and 2 double-precision two parallel cycles
Engineering (NRE) costs for FPGA systems. FPGAs are the are necessary. The double mode dual precision adder can be
ideal choice for replacing application specific integrated produced using a technology and adjustment to plan a dual
circuits (ASIC). In this way, FPGA suppliers have expanded mode quadruple precision adder that supports a double precise
the potential of the simple rudimentary material and have adder and two identical individual precision operations. The
integrated in their offering advanced material service and standard and the dual-mode double and quadruple precision
material possession (IP) cores. However, much of the work additives are applied and synthesized in VHDL to
related to the introduction of FPGA is not completely approximate the region and the worst case delay. In addition,
exploited. The three fully separate FPGA families are detailed modeling is used to assess the performance of all the
targeting their deployment.Virtex-4, Spartan-6, Virtex-5. The designs [5].
findings from the deployment show that these embedded
FPGA tools can accelerate dramatically in performance. The
rapid growth of reconfigurable data processing puts great
III. SYSTEM EXISTING
pressure on floating multipliers that serve a wide range of
In order to accomplish one or two precision calculation
applications from science computers to multimedia systems. with minimal resources of hardware, the multi-precision
In the latter case, Single Instruction Multiple Information floating point arithmetic unit, suggested in that article, is able
(SIMD) feature in Single Excellence (SP) mode [3] is (when operation) to adjust the internal circuit configuration
intended for support of high precise formats such as Double according to calculation accuracy.
Precision (DP)/ Expanded Precision (EP).
The floating-point multi-precision arithmetic essentially
D. FLOATING POINT DIVIDER ACCURACY DUAL-MODE transforms a floating-point circuit to a pair of floating-point
This segment includes a floating multi-mode Point single-precision circuits [1]. Figure.1 The block diagram is
shown as figure1, DA, DB, and DC representing two accuracy
multiplier that operates reliably for all IEEE standard 754-
numbers, respectively a1, a2, b1, b2, c1 and c2.
2008 accuracy formats. A single precision multiplication or
two simultaneous double accuracy multiplications or four
single accuracy multiplications is done in parallel by this
design. The suggested multiplier is piped in order to perform a
quadruple multiplication in three cycles, with either two dual
accuracy operations in similar operations or four single
accuracies in similar operations in just two cycles. The
proposed architecture increases performance by two compared
to a double accuracy multiplier and four compared to a single
accuracy multiplier. A case in point A schedule is tested on
VLSI and the optimum operational frequency is reached at
505 MHz [4]. Fig.1 Function schematic of multi-precision floating point arithmetic

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Either of the following two operations is carried out with the V. IMPLEMENTATION OF FLOATING POINT ARITHMETIC
floating arithmetic multi- precision unit The detailed process of adding and subtracting
(1) DC=DA±DB two floating point numbers is divided into five steps, the
(2) c1=a1±b1,c2=a2±b2 matching of exponents, the calculation of mantissa, the
normalization of mantissa, the rounding of mantissa and
overflow judgment[6]-[8].
IV. PROPOSED SYSTEM FLOATING POINT REPRESENTATION The function of matching of exponents is to align
IEEE754 is the most commonly used the decimal points of two floating-point numbers; it
representation of floating-point number [6], and its means aligning the smaller exponent to the larger
32-bit single precision and 64-bit double precision exponent and moving the mantissa of the floating-point
data format are shown in figure 2 (a) and (b). number with the smaller exponent to the right by E step,
in which E is the order difference of the two exponents.
As shown in figure 2, the sign, the exponent, and The calculation of mantissas is to add or subtract the
the mantissa of the floating-point number need to be mantissas according to the input control signal. The
stored in order to represent a floating-point number. normalization of mantissa means that the mantissa of the
The true-value of a floating-point number N is operation result should meet the requirements of the
represented by Eq. (1).A floating-point number is floating- point normalization, that the integer part should
actually represented by a normalized real number be 1.Otherwise the exponent need to be done the
which is composed of the sign(S), the exponent(E), corresponding addition and subtraction when the mantissa
and the mantissa(M). is moved to the right or the left. The rounding of mantissa
is to round off the data after being moved to the right
according the rounding principle. The overflow judgment
is to process the exponent of the operation result when the
exponent overflows or underflows. It outputs the infinite
number form if the exponent overflows or outputs
Machine zero form of the floating-point number if the
exponent underflows[9]-[10].
To design a floating-point arithmetic unit, saving
hardware resource and improving the operation speed
Fig.2 Representation of a floating-point number should be considered in addition to follow the rules of
floating point arithmetic [11]. The internal structure of
the multi- precision floating-point arithmetic unit
N = (-1)s X 2E-BiasX(1.0+M) (1)
designed in this paper is shown in figure 3.As shown in
figure3, the arithmetic unit mainly consists of six
Note that the M in the Eq.(1) represents the normalized
modules which are the data pre-processing module,
mantissa(the integer part of the normalized mantissa must
exponent comparison module, mantissa stitching module,
be 1, and this 1 is implicit and non-storage).Similarly, the
addition module, normalization and rounding processing
arithmetic result of the floating-point arithmetic needs to be
module and overflow processing module. Before
converted into the normalized format of Eq.(1),which
introducing the functions of each module, the two control
means that the integer of the normalized mantissa must be
signals in the system, Double and Op should be
1. IEEE754 also stipulates the representations of
illustrated. Double is a selective signal of data precision.
several special data as shown in table I.
When Double=1, double precision arithmetic should be
TABLE I done and the two 64-bit input data DA and DB are two
REPRESENTATION OF SPECIAL DATA
double precision floating- point numbers. When Double=
E M DATA 0, it performs single-precisionarithmeticandthetwo64-bit
0 0 0
data as input A and B are four single- precision floating-
0 0 Un normalized
number point numbers, which represent the a1, a2, b1 and b2.Op
ALL1 0 INF is the operation control signal. When Op=00 add
1 0 NAN operation done, while Op=01 subtract operation done.

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 B. EXPONENT COMPARING MODULE
The exponent comparison module compares a set
of input exponents. The exponents are imported through
the ports, ia and ib. And there are three output signals
which are OS, Of_ex and oN_R. OS is the bigger one
between ia and ib, namely the larger one of the output
exponents. oN_R is the absolute value of the difference
between two exponents, and provides the step number of
the right shift of the mantissas for the subsequent module.
Of_ex is the swap flag. If Of_ex equals 1, which shows
ia<ib the mantissas of the two operands of a pair of
operation numbers will be exchange in the subsequent
computations. On the contrary, if Of_ex equals 0, the
mantissa need not to be exchanged and the purpose of
producing this signal is to make the mantissa,
corresponding to the bigger exponent of each pair of data,
Fig.3 Internal structure of the multi-precision floating-point always be put in DA/a1/a2. Therefore, to move the
arithmetic unit
mantissa to the right only need to deal with DB/b1/b2 in
the mantissa stitching module.
As shown in figure 3, there are two exponent
comparison module, exponent comparer 1and 2.And the
A. PRE-PROCESSING MODULE data inputted in exponent comparer 1 come from two data
The preprocessing module provides data for selectors. When Double equals 0, the data are the
subsequent modules, and mainly realizes the three exponents of a1 and b1.When Double equals 1, data are
following functions. Partition the data field. According to the exponents of DA and DB. And exponent comparer 2
the floating-point format in figure 1, the 64-bit input data outputs the result of comparing a2 and b2 [13].
A should be divided into three parts, the sign, the
exponent and the mantissa of two single-precision
floating-point number (a1 and a2) and disassemble the C. MANTISSA STITCHING MODULE
64-bit input data B into three parts, the sign, the exponent As shown in figure 3,there are many input signals to
and the mantissa of two single-precision floating-point the mantissa stitching module which include Double,
number (b1 and b2). At the same time, disassemble A mantissa swap flag, the step number of small exponent
into three parts, the sign, the exponent and the mantissa of mantissa, the signs and mantissas of four single- precision
one double-precision floating-point number DA [12]. data or two double-precision data. And the output of this
Similarly, disassemble B into three parts, the sign, the module is two 56-bits data. This module realizes splicing
exponent and the mantissa of another double-precision the mantissa of four single-precision data or two double-
floating-point number DB. It should be stated that the ‘1’, precision data into two 56-bit data according to Double
integer part of the mantissa has been restored and signal. In order to simplify the operation circuit, the data
unhidden setting the special data flags. To determine the after splicing are the complement form with two signs bits.
type of the two 64-bit input data according to 0, Plus or According to the size of exponent, the bigger exponent
minus infinity and NAN in table1,andset up three flags, mantissa is placed in DA/a1/a2 while the smaller exponent
NAN, INF and ZERO (all 4 bits) of four single-precision mantissa is in DB/b1/ b2.The reason why the mantissa is
floating- point numbers or two double--precision floating- 56 bits is that when Double equals 1, the 53-bit mantissa is
point numbers. Pre-processing for subtract operation. changed to a new 56-bit mantissa after added one integer
When Op=01, operation of a bitwise NOT (negation) to bit and two sign bit[14]. On the other hand, the 24-bit
the sign bits of b1, b2 and DB should be done in order mantissa of one single- precision data is changed to 28-bit
that only add operation executed in subsequent modules after added one integer bit 2 sign bits and 2 isolation bits
in the case of no special data. (00). In the way, two different precision data can share one
arithmetic unit. Furthermore, figure 4 is the composition
of the mantissas with different operation precision.

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 Fig.5 The prefix operation of the 56-bit mixed Han-Carlson
adder
Fig.4 Mantissa stitching under different precision
D. MANTISSA NORMALIZATION MODULE
The mantissa normalization module changes the
Due to the mantissa needed to be summed is 56-bit sum
output mantissa of the addition module to a 64-bit or two
algorithm effect on the arithmetic speed mostly.
32-bit floating- point numbers according to the accuracy
The sum of mantissa adopted mixed Han–Carlson requirement. The input and output signals of this module
algorithm which trades space for time and its tree structure are shown in table II. This module consists of three sub-
has an advantage compared with serial carry and look- modules which are the mantissa judgment sub-module, the
ahead carry in logical series, the wiring channel and the leading 0 detection sub-module and the normalization
maximum sectorial area. The core of the Han-Carlson
processing sub-module.
algorithm is the prefix parallel addition, and its three main
calculation steps are as follows. The mantissa judgment sub-module pre-judges the
56-bit complement mantissa before being normalized
Calculate the Pi and Gi of each bit of the augend and according to the dual signs and the highest numerical bit,
addend. And the formula of Pi and Gi is shown in Eq. (2) and gets the sign bit(of floating-point number) and the
and (3). expdlt which is the initial value of add operation to
exponent and then to simplify the circuit, subsequent
Pi = Ai.Bi (i=0-55) (2)
processing will be done after mantissa has been transform
Gi = Ai+Bi (i=0-55) (3)
into the Sign-Magnitude representation. The mantissa
Generate Carry signal in parallel and the rule is shown in
judgment sub-module mainly realizes the following three
Eq.(4)-Eq.(6), in which “.” is the prefix operator.
functions.
Ci = Gi…0+ Pi….0C0 (4)
(Gi…0,Pi…0)=(Gi-1,Pi-1).(Gi-2,Pi-2)….(G0,P0) (5) According to the dual sign-bits and the highest numerical
(Gi,Pi).(Gj,Pj) = (Gi + Pi.Gj,Pi.Pj) (6) bit of 56-bit complement mantissa, set the add operation
offset, expdlt when exponent need not be shifted to left.
calculate the sum of each bit and it is shown in Eq.(7) When expdlt=00, it represents that the mantissa has already
Si = Pi+ Ci (7) been a normalized number. When expdlt=01, it represents
the operation of adding exponent with 1 (the equivalent of
the mantissa moves 1 bit to the right).
The A and B in Eq.(2) and Eq.(7) represent two 56-bit
Input data respectively. The Ai and Bi represent the ith bit TABLE II
PORT SIGNAL OF MANTISSA NORMALIZATION MODULE
of input data respectively. And the Si and Ci represents ith
bit summation of the results. NAME PARAMETER WIDTH MEANS
As shown in Fig.5, the internal structure of a 56-bit mixed (bits)
Han-carlson adder, an algorithm which trades space for Double 1 bit Precision control
input
time. Each input dot represents one (Gi,Pi), the process of
Iexp1 11 Exponent 1
binary addition is divided into nine stages. The black dots
in the figure5 represent a carry operation and the carry bits I exp2 11 Exponent 2
of each bit are calculated in parallel at every stage.
I mantissa 56 Sum of mantissa
Eventually, to calculate the results of each bit is calculated
by full adder [15]. output O data 64 Operation Result
.

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When expdlt=11, it represents that the mantissa needs be
shifted to the right for several bits, but the numbers are
determined by the first 1 testing and coding module.
Setting the sign bit of floating-point Numbers. Converting
mantissa to the absolute value. Leading zero detection sub-
module is the most time-consuming sub-module in
mantissa normalization. The ways of detection is that
firstly, to determine which byte contains the highest bit “1”
and then to encode the position of the first 1 by the priority
encoder to provide the left-shift numbers to mantissa when
it is normalized [16].
The normalization processing sub-module moves
the mantissa to the left or right according to the value of
expdlt and at the same time, does addition or subtraction to
the exponents.
Fig. 6 Simulation waveform of 64-bit floating point Adder

E. ROUNDING OFF AND OVERFLOW JUDGEMENT MODULE

Due to adding two numerical value bits in earlier for
mantissa processing in this module, the mantissa is
rounded off according to the principle of the nearest-even-
number, at the same time, in the case of exponent
overflow, the result of exponent and mantissa are set
accordingly. Namely, if exponent underflows, the mantissa
and exponent are set to 0 (representing floating- point 0),
if exponent overflows, the exponent is set to all ‘1' and the
mantissa is set to 0 (representing infinity).

VI. SIMULATION RESULTS

A. 64-BIT FLOATING POINT ADDER Fig. 7 RTL block diagram of 64-bit floating point Adder
Consider the data as shown in the figure.6,
Simulation results of existing system.
A=(4028C00000000000)16 & B=(405FC00000000000)16;
Op-00 for 64-bit floating point number addition is performed.
The approximate result is (40616C0000000000)16 for 64-bit
floating point Adder (the input and output values are taken in
the form of hexadecimal format).

RTL block diagram shown in figure 7, the two 64-bit

inputs are op-a and op-b, clk, enable and reset are given to the
floating point number Adder. The addition operation is
performed between two inputs a and b. The Fig.7, shows
RTL block diagram of existing system of 64-bit floating point
adder, which consists of input and output signals.
Fig. 8, shows RTL schematic Design of 64-bit floating point
Adder, click on view RTL schematic. The RTL schematic
Diagram of 64-bit floating point Adder which consists of Fig 8. RTL schematic of 64-bit floating point Adder
internal modules.

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B. 64-BIT FLOATING POINT SUBTRACTOR
Consider the data as shown in the fig.9, Simulation
results of existing system. A=(406F900000000000)16 &
B=(405F666666666666)16; Op-01 for 64-bit floating point
number subtraction is performed. The approximate result is
(405FB9999999999A)16 for 64- bit floating point Subtractor
(the input and output values are taken in the form of
hexadecimal format).RTL block diagram shown in figure 10,
the two 64-bit inputs are op-a and op-b, clk, enable and reset
are given to the floating point number subtractor. The
subtraction operation is performed between two inputs a and
b. The fig.10 shows RTL block diagram of existing system
of 64-bit floating point subtractor, which consists of input
and output signals. Fig.11 shows RTL schematic Design of Fig.11 RTL schematic of 64-bit floating point Subtractor
64-bit floating point Subtactor, click on view RTL schematic.
The RTL schematic Diagram of 64-bit floating point
Subtractor which consists of internal modules.
C. 64-BIT FLOATING POINT MULTIPLIER
Consider the data as shown in the figure 12, Simulation
results of proposed system. A=(405ED9999999999A)16 and
B=(406F900000000000)16; Op-10 for 64-bit floating point
number multiplication is performed. The approximate result
is (40DE6DA000000000)16 for 64-bit floating point
Multiplier (the input and output values are taken in the form
of hexadecimal format). RTL block diagram shown in fig.13,
the two 64-bit inputs are op-a and op-b, clk, enable and reset
are given to the floating point number Multiplier. The
multiplication operation is performed between two inputs a
and b. The fig.13 shows RTL block diagram of proposed
system of 64-bit floating point Multiplier, which consists of
input and output signals. The fig.14 shows, RTL schematic
Design of 64-bit floating point Multiplier, click on the view
Fig.9 Simulation waveform of 64-bit floating point Subtractor RTL schematic. The RTL schematic Diagram of 64-bit
floating point Multiplier which consists of internal modules.

Fig.10. RTL block diagram of 64-bit floating point Subtractor Fig12 Simulation waveform of 64-bit floating point Multiplier

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 VII. CONCLUSION
In this paper proposed the design of a multi-precision
floating-point arithmetic unit which can realize the
multiplication double precision floating-point data with the
input of the control signal. The proposed system of multi-
precision floating point arithmetic unit which results the
multiplication operation for both single-precision and double-
precision floating point data. The proposed system which is
used in the applications of Digital Signal Processing (DSP),
Green Computing and Data Mining.

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