0% found this document useful (0 votes)
6 views3 pages

Decomposition of Boolean Function

This paper presents a novel decomposition method for Boolean functions, specifically targeting multiple-output, partially specified functions represented by cubes. The proposed approach enhances logic synthesis by reducing run-time and improving solution quality, particularly for FPGA designs. It introduces a new calculus based on generalized set systems, allowing for efficient processing of complex Boolean functions.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
6 views3 pages

Decomposition of Boolean Function

This paper presents a novel decomposition method for Boolean functions, specifically targeting multiple-output, partially specified functions represented by cubes. The proposed approach enhances logic synthesis by reducing run-time and improving solution quality, particularly for FPGA designs. It introduces a new calculus based on generalized set systems, allowing for efficient processing of complex Boolean functions.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

Decomposition of Boolean Functions Specified by

Cubes
Ugwuogor, N.E
MENG/SEET/2022/13618

Department of Electrical Electronics Engineering,


Federal University of Technology, Minna, Nigeria.

Abstract - This paper introduces a type of FPGA cells can only accommodate functions with very
decomposition of Boolean functions, whereby few inputs and outputs. Consequently, decomposition
partitioning the original function into disjoint chains methods are increasingly in today's logic synthesis
of cubes. We use this type of decomposition as a pre- systems [17]. Mathematically, decomposition is the
processing step in logic synthesis algorithms which process of expressing a function of n variables as a
lead to a considerable reduction in the run-time thus function of functions of fewer variables [7]. For
allowing to process larger functions, which otherwise example, a function F (X) is decomposable if it can be
cannot be handled due to the time limit. Very Large expressed as F = H(U; G(V )), where U and V are
Scale Integration is of a practical importance. For proper subsets of the set X of input variables, and G
example, for digital circuits designed with field- and H have fewer input variables than F . Ashen Hurst,
programmable gate arrays, it is necessary to express in his fundamental paper [1], stated the disjunctive
Boolean functions in terms of `smaller' functions that decomposition theorem based on decomposition
the cells of the array. The decomposition problem charts. Curtis extended Ashen Hurst’s results to
understood when the functions to be decomposed are multiple decompositions [7], of the form F = H(U;
specified by the truth table. However, modern design G1(V ); : : : ; Gk(V )).
tools handle functions with many outputs and To improve on that, Roth and Karp used a more
represent them by Boolean cubes rather than the representation of a function in the form of a cover of
minterms, for reasons of efficiency. In this paper, we the on-set and of the offset [15]. However, their
develop a decomposition theory for multiple-output, method does not deal directly with multiple-output
partially specified Boolean functions represented by functions. A function can be decomposed in different
cubes. The theory uses ternary algebra and set ways, depending on the criteria chosen. For example, a
systems. classical type of decomposition is the simple
Keywords: blanket, Boolean function, cube, disjunctive decomposition, where the original function
decomposition, disjunctive, don't care," multiple- is replaced by two functions, which are disjoint in
output, set system, ternary algebra. variables [1], [2]. Functional decomposition methods
has less attention because of the rapid development of
I. INTRODUCTION synthesis techniques for multilevel logic. The algebraic
Decomposition is a fundamental problem in modern division of sum-of-product expressions represented by
logic synthesis. Its aim is to break a logic circuit into a sets of cubes has been a basic operation in the
set of smaller interacting components. Such an procedures of so-called kernel extraction widely used
implementation is desirable for a number of reasons. in multi-level synthesis of Boolean functions [3].
This paper shows how a similar type of decomposition
is defined for logic functioned and demonstrates its 2. NOTATIONS
application to logic synthesis. The problem of We use the standard definitions and notation in the
functional decomposition can be formulated. A given area of logic synthesis ([4]). The most important
function f, express it as a composite function of some notations summarized in this section.
set of new functions. Often a composite expression can
be found in which the new functions are significantly Let f(x1, x2,… xn) be a completely specified Boolean
simpler than f. function of type F : {0,1}n, of the variables X1,…,Xn.
The designs using field-programmable gate arrays A point in the domain {0,1} n of the function f is called
(FPGAs), particularly those with lookup table a minterm. The on-set and the off-set are the sets of
structures [4], decomposition is a necessity, since minterms that are mapped by 1 and 0, respectively.
A product-term is a Boolean product (AND) of one or relevant to G. The relationship between Bv and the
more variables X1,…,Xn or their complements. A minterm G are shown below.
convenient representation for a product-term is cube
[5]. We use the terms cube and product-term
interchangeably. A sum-of-products is a Boolean sum
(OR) of product terms.
Let Px and Py be cubes of f. The distance between Px Table 2
and Py denoted by distance (Px, Py), is the number of Function F
empty fields in the intersection of Px and Py. When the
distance is zero, then the cubes intersect, otherwise Block of Bv Cubes of F Minterms of G
they are disjoint. B1 {7, 8} {0000, 0100}
B2 {3, 4, 8} {0001, 0101}
3. DEFINITION OF DECOMPOSITION B3 {8} {0010, 0110, 1110, 1111}
The decomposition of a function F is completed when B4 {4, 8} {0011, 0111}
truth tables for components G and H have been found. B5 {1, 5, 8} {1000}
For convenience and simplicity, we used minterms to B6 {3, 5, 8} {1001, 1101}
construct the tables. Thus, we considered {0, 1}n and B7 {6, 8} {1010, 1011}
{0, 1}n+p as inputs to G and H, respectively. However, B8 {1, 2, 5, 8} {1100}
F is specified by cubes and it would be desirable to
have a method that handles all functions uniformly as 4. APPLICATION TO LOGIC SYNTHESIS.
cubes. We now present such a method. To demonstrate the application of the new
The table below shows a function F to be decomposed
decomposition to logic synthesis, we take an algorithm
with respect to U = {x1, x2} and V = {x3, x4, x5, for three-level AND-OR-XOR minimization,
x6}. presented in [3], and added clustering as a pre-
processing step of the algorithm. First, we briefly
Bv= describe the basic idea of the algorithm, and then give
B1 B2 B3 B4 B5 B6 B7 B 8 the experimental results showing the effect of
{7 , 8 ! 3 , 4 ,8 ! 8 ! 4 , 8! 1, 5 , 8 ! 3 , 5 ,8 ! 6 ,8 ! 1 , 2 ,5 , 8clustering
} on its run-time and the quality of its
solutions.
Assume that we have found a blanket σG, in the case
4.1 ALGORITHM AOXMIN-MV
of a set system, that satisfies the conditions. Assume
that the blocks of σG are encoded as shown below. In this section, we briefly describe the basic idea of the
algorithm for three-level AND-OR-XOR minimization
00 01 10 11 AOXMIN-MV, presented. The target of the algorithm
σG= {3 , 4 ,7 , 8 ! 3 , 5 , 8 ! 6 , 8 ! 1 ,2 , 5 , 8} is a three-level logic expression, which is a XOR of
two sum-of-products.
To define a function G by a set G of function cubes, in The core of AOXMIN-MV is a group migration
this case 6-tuples, algorithm, which is an extension of iterative
improvement algorithm. Group migration algorithm
Table 1 repeats the following: given an initial partitioning of
objects into two groups, for each object determine the
Χ1 X2 X3 X4 X5 X6 Y1 Y2 Y3 decrease in cost if the object is moved to the other
1 x 0 1 x 0 0 1 x x group. Then, move the object that produces the
2 0 x 1 1 0 0 1 x x greatest decrease or smallest increase in cost and mark
3 1 x x x 0 1 x 1 x
it as moved. After all objects has been moved, the
4 0 x 0 x x 1 x 1 x
5 1 x 1 x 0 x x x 1 lowest-cost partitioning is selected. If the partitioning
6 x x 1 0 1 x 0 0 0 has a higher cost then the algorithm stops. Hence, it
7 x x 0 x 0 0 x x 0 iterates taking the new partitioning for the initial
8 1 1 x x x x 0 x x partitioning.

All the minterms relevant to G are represented. These CONCLUSION.


are all the binary 4-tuples that are covered by the V This paper introduces a new type of decomposition of
columns of F. Because of row 8, all 16 minterms are Boolean functions. Our experiments show that using
this type of decomposition as a pre-processing step
may considerably reduce the run-time of the algorithm M. Rawski, “Decomposition of Boolean Function Sets,”
for three-level AND-OR-XOR minimization Electronics and Telecommunications
AOXMIN-MV, as well as improve the quality of its Quarterly, Vol. 53, No. 3, 2022, pp. 231-249.
solutions. A distinguishing feature of this method is an J. A. Brzozowski and T. Łuba, “Logic Decomposition
original calculus based on the representation of a Aimed at Programmable Cell Arrays,”
function using generalized set systems, which permit International Conference of Microelectronics:
to derive functional dependencies. The proposed serial Microelectronics, Vol. 1783, 2018, pp. 77-88.
decomposition procedure has already been partly
Y. T. Lai, M. Pedram, and B. K. Vrudhula,
included in the logic synthesis tool DEMAIN
Algorithms for Integer Linear Programming,
dedicated to FPGA-based logic synthesis.
and Function Decomposition, IEEE Trans. on
Perhaps the most important feature of is that it permits
Computer Aided Design, Vol. 13, No. 8, pp.
to process incompletely specified multiple-output
959-975, 2020.
functions specified by sets of on and off cubes, as a
R. Murgai, N. Shenoy, and R. K. Brayton Improved
single n-input, m-output object, for which the result is
Logic Synthesis Algorithm for Table Look Up
represented in the same form. Although existing
Architectures, Proc. IEEE International Conf.
methods [14, 15, 17, 20] deal with multiple-output
on Computer Aided Design, pp. 564-567,
functions, they do not process them as single objects
2019.
represented by a matrix.
J. P. Roth and R. M. Karp, Minimization over Boolean
Graphs, IBM Journal of Research and
References
Development, Vol. 6, pp. 227-238, April 2019.
R. L. Ashenhurst, The Decomposition of Switching
A. Saldanha, T. Villa, R. K. Brayton, and A. L.
Functions, Proc. Theory of Switching
SangiovanniVincentelli, Satisfaction of Input
Functions, 2019.
and Output Encoding Constraints, IEEE
R. K. Brayton, G. D. Hachtel, and C. T. McMullen,
Trans. on Computer Aided Design,, Vol. 13,
Logic Minimization Algorithms for VLSI
No. 5, pp. 589-602, May 2021.
Synthesis, Kluwer Academic Publishers,
A. Sangiovanni-Vincentelli, A. Gamal, and J. Rose,
Boston, MA, 2021.
Synthesis Methods for Field Programmable
R. K. Brayton, R. Rudell, A. Sangiovanni-
Gate Arrays, Proc. IEEE, Vol. 81, No. 7, pp.
Vincentelli, and A. R. Wang, MIS: Multiple-
1057-1083, 2019.
Level Logic Minimization System, Vol. CAD-
T. Sasao, Logic Synthesis and Optimization, Kluwer
6, No. 6, pp. 1062-1081, November 2021.
Academic Publishers, 2018.
D. Brown, Field Programmable Gate Arrays, Kluwer
T. Stanion and C. Sechen, A Method for Finding Good
Academic Publishers, Boston, MA, 2019.
Ashenhurst Decomposition and Its Application
T. H. Cormen, C. E. Leiserson, R. L. Rivest, Revised
to FPGA Synthesis, 32 Design Automation
Introduction to Algorithms, The MIT Press,
Conference, pp. 60-64, San Francisco, 2019.
Cambridge, England, 2022.
E. V. Dubrova, D. M. Miller, J. C. Muzio,”AOXMIN-
H. A. Curtis, A New Approach to the Design of
MV: Algorithm for AND-OR-XOR
Switching Circuits, D. Van Nostrand Co. Inc.,
Minimization”, International Workshop on the
Princeton, NJ, 2023.
Applications of the Reed-Muller Expansion in
R.K. Brayton, G. Hachtel, C. McMullen, A.
Circuit Design, 2018.
Sangiovanni-Vincentelli, Logic Minimization
Algorithms for VLSI Synthesis, Kluwer, 2021.
G. De Micheli, Synthesis and Optimization of Digital
Circuits, McGraw-Hill, 2023.
W. A. Shen, J. D. Huang, and S. M. Chao, Lambda Set
Selection in Roth-Karp Decomposition for
LUT-Based FPGA Technology Mapping, 32
Design Automation Conference, pp. 65-69,
San Francisco, 2021.
W. Wan and M. A. Perkowski, A New Approach to the
Decomposition of Incompletely Specified
Multi-Output Function Based on Graph
Colouring and Local Transformations and Its
Application to FPGA Mapping, Proc.
European Design Automation Conf., pp. 230-
235, 2022.

You might also like