MODULE -2

( MEMORY)

DEBKANTA MAITY
Q. What is Memory Hierarchy ?
The memory hierarchy in computer systems is a structured arrangement of storage types based on speed, cost, and capacity. It is designed to optimize
the performance of the system by placing frequently accessed data in faster, smaller memory and less frequently accessed data in slower, larger memory
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Q. Discuss di erent techniques to reduce miss rate . [WBUT 2010,2018,2019]

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Q. What is the cache coherence problem ? Discuss the techniques used to reduce it .[WBUT 2011,2013,2016,2017,2023]
✅ What is Cache Coherence Problem? 2012,2014,2018
1.De nition:
The cache coherence problem arises in multiprocessor systems when multiple processors cache the same memory location and at least one writes to it, leading to
inconsistent values across caches.
2.Cause:
◦ Each processor maintains its own cache.
◦ If one processor updates a value, other caches may still hold the stale (old) value.
3.Result:
◦ Processors read different values for the same memory location.
◦ Leads to incorrect program behavior.
4.Example:
◦ Shared variable X = 5
◦ Processor P1 caches X and updates it to 10.
◦ Processor P2 still sees X = 5 from its cache → Inconsistency
🛠 Techniques to Reduce Cache Coherence Problem

🔹 1. Write-Invalidate Protocol
• How it works:
◦ When a processor writes to a cached block, it invalidates that block in all other processors' caches.
• Effect:
◦ Ensures no other processor can read stale data.
• Example: MESI protocol uses this method.
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🔹 2. Write-Update (Write-Broadcast) Protocol
• How it works:
◦ When a processor writes data, it broadcasts the updated value to all other caches.
• Effect:
◦ All processors immediately see the updated value. 🔹 5. Directory-Based Coherence

🔹 3. MESI Protocol (Modi ed, Exclusive, Shared, Invalid) • How it works:

• How it works: ◦ A centralized directory keeps track of which processors cache which memory blocks.
◦ A state-based protocol that controls how a cache line is shared/updated. ◦ On updates, the directory ensures all relevant caches are informed.
◦ States: • Effect:
▪ Modi ed: Cache has the latest value, not in memory. ◦ Reduces unnecessary broadcasts (better for large systems).
▪ Exclusive: Cache has the same as memory, not shared. • Used in: Scalable multiprocessor systems.

▪ Shared: Value is in multiple caches.

▪ Invalid: Value is outdated.
• Effect:
◦ Provides strong control over how data is shared and updated.

🔹 4. MOESI / MSI / MESIF Protocols

• Variants of MESI with different levels of control and ef ciency.
• Add states like Owned (O) or Forward (F) to optimize sharing and data forwarding.
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✅ Limitations of Cache Coherence Reducing Techniques

🔹 1. Scalability Issues
• Techniques like snooping protocols do not scale well with increasing numbers of processors.
• Broadcast traf c grows rapidly, leading to bus contention and performance bottlenecks.

🔹 2. Increased Communication Overhead

• Write-update protocols and directory-based methods require frequent data sharing or control messages.
• This increases network/bus traf c and can reduce system performance.

🔹 3. Higher Latency
• Write-invalidate protocols delay write operations until all other caches invalidate their copies.
• Directory protocols introduce latency due to directory lookup and management delays.

🔹 4. False Sharing
• Occurs when multiple processors use different variables within the same cache block.
• Leads to unnecessary coherence actions, reducing ef ciency.

🔹 5. Storage Overhead
• Directory-based protocols require extra memory to store the state of each cache block (e.g., who has it, status).
• This grows with the number of cores and memory blocks.

🔹 6. Complex Hardware Design

• Advanced coherence protocols (like MESI, MOESI) require complex state machines.
• Increases the design time, veri cation effort, and cost of hardware.
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🔹 7. Energy Consumption
• Constant monitoring (snooping), updates, and invalidations consume extra power.
• Signi cant issue in mobile or embedded systems where power is limited.

🔹 8. Debugging and Veri cation Dif culty

• Coherence mechanisms introduce asynchronous interactions and race conditions.
• Makes systems harder to debug, test, and verify during development.

🔹 9. Limited Flexibility
• Some protocols assume speci c architectures (like shared-bus systems).
• May not work ef ciently with non-uniform memory access (NUMA) or heterogeneous cores.
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Q. Short notes on Cache Memory .[WBUT 2010,2019,2018,2023]
🔹 1. What is Cache Memory?
• Cache memory is a small, high-speed memory located close to the CPU.
• It stores frequently accessed data and instructions to reduce the time the CPU takes to access memory.
• Acts as a buffer between main memory (RAM) and the CPU.
🔹 2. Purpose
• To improve processing speed by minimizing memory access delays.
• It stores copies of the most recent or frequently used data from main memory.
🔹 3. Types f Cache Memory
1. L1 (Level 1) Cache – Smallest and fastest, located within the CPU core.
2. L2 (Level 2) Cache – Larger than L1, slightly slower, but still faster than RAM.
3. L3 (Level 3) Cache – Shared across cores, larger and slower than L2, but faster than RAM.

🔹 4. Working Principle
• When the CPU needs data:
◦ It rst checks L1 cache, then L2, then L3.
◦ If the data is not found (called a cache miss), it is fetched from the main memory and stored in the cache for future access.
✅ Advantages of Cache Memory

🔸 1. Faster Data Access

• Provides much faster access to data compared to main memory.
🔸 2. Improved CPU Performance
• Reduces CPU waiting time, allowing it to execute instructions more ef ciently.
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🔸 3. Reduces Memory Bottleneck
• Less frequent access to main memory helps avoid memory bandwidth congestion.
🔸 4. Automatic Data Management
• Cache controllers automatically manage which data is stored and evicted.
🔸 5. Transparency to Users
• The use of cache is invisible to programmers and users – handled by hardware.
❌ Disadvantages of Cache Memory

🔸 1. Expensive
• Built using SRAM (Static RAM), which is costlier than DRAM (used in main memory).
🔸 2. Limited Size
• Due to high cost, cache size is much smaller than main memory.
🔸 3. Complex Design
• Managing cache (replacement policies, coherence, etc.) requires complex logic.
🔸 4. Cache Misses Still Occur
• If required data isn't in cache, CPU still needs to fetch from slower memory.
🔸 5. Energy Consumption
• High-speed operation and constant access increase power usage.
Q. Short note on Virtual memory. [2019]
🔹 1. What is Virtual Memory?
• Virtual memory is a memory management technique that gives an illusion of a large main memory.
• It allows the system to use more memory than physically available RAM by using a portion of the hard disk (or SSD) as temporary memory.
• Used in modern operating systems to enable multitasking and memory protection.
🔹 2. How It Works
• Programs are given a virtual address space.
• The MMU (Memory Management Unit) maps virtual addresses to physical addresses.
• When data is not in RAM, it's loaded from disk (paging/swapping).
🔹 3. Key Concepts
• Paging: Dividing memory into xed-size pages and swapping them in/out of RAM.
• Page Table: Maintains mapping between virtual and physical pages.
• Page Fault: Occurs when required data is not in RAM; OS loads it from disk.
✅ Advantages of Virtual Memory

🔸 1. Larger Effective Memory

• Programs can use more memory than physically available RAM.
🔸 2. Isolation and Protection
• Each process gets its own memory space, preventing interference.
🔸 3. Multitasking Support
• Multiple programs can run simultaneously without memory con icts.
🔸 4. Ef cient Use of RAM
• Only actively used data is kept in RAM; inactive data stays on disk.
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🔸 5. Simpli es Programming
• Programmers don't need to manage memory limitations manually.
❌ Disadvantages of Virtual Memory

🔸 1. Slower Performance
• Accessing data from disk is much slower than accessing RAM.
🔸 2. Thrashing
• Excessive paging (constant swapping in/out of memory) can lead to very poor performance.
🔸 3. Increased Complexity
• Requires complex OS support and hardware (MMU).
🔸 4. Storage Overhead
• Needs disk space for the page le/swap space, reducing available disk storage.
🔸 5. Latency on Page Faults
• When a page fault occurs, the system may pause while loading data from disk, causing delays.
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Q. Short note on Main Memory .
🔹 1. What is Main Memory?
• Main memory refers to the primary storage or RAM (Random Access Memory) in a computer.
• It is the working memory used by the CPU to store data and instructions temporarily during execution.
• It is volatile, meaning data is lost when power is turned off.
🔹 2. Purpose of Main Memory
• Stores the operating system, application programs, and currently processed data.
• Provides fast access to the CPU compared to secondary storage (e.g., hard drives).
• Acts as the interface between the CPU and slower memory (like disk).
🔹 3. Types of Main Memory
1.RAM (Random Access Memory)
◦ Read-write memory, volatile, fast.
◦ Includes DRAM (Dynamic RAM) and SRAM (Static RAM).
2.ROM (Read-Only Memory)
◦ Non-volatile, used for boot instructions.
✅ Advantages of Main Memory

🔸 1. High Speed
• Much faster than secondary memory (like hard drives or SSDs).
🔸 2. Direct Access by CPU
• CPU can directly read/write data in main memory without delay.
🔸 3. Essential for Program Execution
• Stores running programs and data, making multitasking possible.
🔸 4. Improves System Performance
• More RAM reduces the need for disk-based virtual memory, improving speed.
🔸 5. Simple Addressing
• Uses linear or segmented addressing, simplifying memory management.
• Disadvantages of Main Memory
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🔸 1. Volatile
• Loses all data when the power is turned off.
🔸 2. Limited Size
• Compared to secondary storage, RAM is relatively small in capacity.
🔸 3. Expensive
• Cost per GB is higher than that of secondary memory (e.g., HDD/SSD).
🔸 4. Cannot Store Data Permanently
• Needs additional non-volatile storage for long-term data storage.
🔸 5. Dependent on Virtual Memory
• If RAM is insuf cient, the system uses slower virtual memory, reducing performance.
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Q. Short note on Associative memory.
🔹 1. What is Associative Memory?
• Also called Content-Addressable Memory (CAM).
• A type of memory that is accessed by content, not by a speci c address.
• It returns the data location (or data itself) based on a search key or part of the content.
🔹 2. How It Works
• Instead of using an address to fetch data, the memory hardware compares input data against all stored entries simultaneously.
• When a match is found, the corresponding data or address is returned.
🔹 3. Types of Associative Memory
• Binary CAM: Matches exact bit patterns.
• Ternary CAM: Can also store “don’t care” bits, allowing partial matches.

✅ Advantages of Associative Memory

🔸 1. Fast Search
• Provides very fast data retrieval since all entries are compared in parallel.
🔸 2. Ef cient for Lookup Operations
• Ideal for applications like cache tags, translation lookaside buffers (TLBs), and networking (routing tables).
🔸 3. Simpli es Programming
• No need for address calculation; data is retrieved by content match.
🔸 4. Flexible Matching
• Ternary CAMs allow for wildcard searches, improving versatility.
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❌ Disadvantages of Associative Memory

🔸 1. High Cost
• Complex circuitry makes associative memory expensive to build compared to regular RAM.
🔸 2. Limited Size
• Due to cost and complexity, associative memories are generally small in size.
🔸 3. High Power Consumption
• Parallel comparisons require signi cant power, leading to higher energy use.
🔸 4. Complex Design
• Designing associative memory is more complex than traditional memory systems.
🔸 5. Slower Write Operations
• Writing/updating data can be slower due to the need to update multiple comparison circuits.
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Q. What is Inclusion , Cache Coherence and Locality of reference of reference Property ?
📘 1. Inclusion (In Memory Hierarchy)
🔹 De nition:
• Inclusion refers to the relationship between multiple levels of cache (e.g., L1, L2, L3).
• A cache hierarchy is inclusive if all the data in a lower-level cache (like L1) is also present in the higher-level cache (like L2 or L3).
🔹 Purpose:
• Simpli es cache coherence management.
• Allows higher-level caches to easily invalidate or update data in lower levels.
🔹 Example:
• If a block exists in L1 cache, it must also exist in L2 cache in an inclusive system.
📘 2. Cache Coherence
🔹 De nition:
• Cache coherence ensures that multiple copies of data in different caches (multi-core systems) remain consistent.
🔹 Problem:
• When multiple processors have their own cache, and one processor updates a memory location, the other caches might have stale (old) data.
🔹 Solution (Protocols):
• Write-invalidate: Invalidate other copies when one is written.
• Write-update: Broadcast the new value to all caches.
• Common protocols: MESI, MOESI, Directory-based protocols.
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📘 3. Locality of Reference (Memory Access Pattern)
🔹 De nition:
• Refers to the tendency of a program to access the same set of memory locations repeatedly over short periods.
🔹 Types:
1. Temporal Locality: Recently accessed data is likely to be accessed again soon.
2. Spatial Locality: Data near recently accessed memory locations is likely to be accessed soon.
🔹 Importance:
• Helps optimize cache design.
• Basis for prefetching and ef cient memory management.
🔹 Example:
• Accessing an array in a loop shows both spatial and temporal locality.
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Q. Di erence between Physical address and Logical address .
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Q. Di erence between Associative mapping and Direct mapping .
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Q. Short note on Paging .[2019]
🔹 1. Introduction
• Paging is a memory management technique used to implement virtual memory.
• It allows non-contiguous memory allocation, solving problems of fragmentation.
• In paging, both logical memory and physical memory are divided into xed-size blocks.

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❌ Drawbacks of Paging

🔹 1. Internal Fragmentation
• Each page has a xed size (e.g., 4 KB), and not all of it may be used.
• If a process doesn't fully use a page, the remaining space is wasted.
• This is called internal fragmentation.

🔹 2. Page Table Overhead

• Each process has its own page table.
• For large address spaces, the page table can become very large, consuming signi cant memory.

🔹 3. Slower Memory Access

• Every memory access requires two steps:
1. Access the page table to get the frame number
2. Access the actual memory location
• This can cause a performance hit unless assisted by a TLB (Translation Lookaside Buffer).

🔹 4. Increased Context Switch Time

• During a context switch, the operating system must switch the page tables.
• This adds overhead, especially in systems with many processes.

🔹 5. Page Faults
• If a required page is not in memory, it triggers a page fault.
• The OS must load it from disk, which is very slow and can signi cantly degrade performance.
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🔹 6. TLB Miss Penalty
• If a page table entry is not found in the TLB, a full page table lookup in memory is required.
• This increases the effective memory access time.

🔹 7. Hardware Support Required

• Ef cient paging needs hardware support (MMU, TLB).
• Increases the design complexity and cost of the system.

🔹 8. Memory Overhead for Multi-Level Paging

• To reduce large page table sizes, multi-level paging is used.
• But it increases memory accesses and adds extra levels of lookup, which can slow performance.
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Q. Short note on TLB .[2019]
🔹 De nition:
• TLB stands for Translation Lookaside Buffer.
• It is a special cache used by the Memory Management Unit (MMU) to speed up virtual-to-physical address translation.
• It stores recently used page table entries.
🔹 Purpose:
• Avoids repeated access to the page table in main memory.
• Improves memory access speed in a paged memory system.
🔹 How It Works:
1. CPU generates a virtual (logical) address.
2. The page number is searched in the TLB.
3. If found (TLB hit), the corresponding frame number is returned instantly.
4. If not found (TLB miss), the MMU accesses the page table in memory, and updates the TLB.
🔹 Types of TLB:
• Fully associative: Any entry can go in any slot.
• Set-associative: Limited group of slots per entry.
• Direct-mapped: Each entry has only one possible place.
🔹 Advantages: 🔹 Disadvantages: 🔹 Example:

✅ Speeds up address translation ❌ Limited in size • Suppose 90% of address translations are TLB hits.
✅ Reduces page table access time ❌ Needs hardware support • If memory access takes 100 ns, and TLB access takes 10 ns:
✅ Improves overall CPU performance ❌ TLB misses still require memory access ◦ Effective Access Time (EAT) = (0.9 × 10) + (0.1 × (10 + 100)) = 10 + 11 = 21 ns
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Q. Short note on memory replacement policies .
🔹 De nition:
Memory replacement policies are techniques used to select which cache block or memory page to remove when new data needs to be loaded into memory or cache, and it is
already full.
These policies are essential for ef cient cache and virtual memory management.
🔹 Purpose:
🔹 In Cache Memory:
• Optimize memory access performance
• These policies determine which cache line to evict when a cache miss occurs.
• Reduce cache misses or page faults
• Common in set-associative and fully-associative caches.
• Maintain ef cient use of limited memory resources
🔹 Advantages:
✅ Improves memory utilization
✅ Reduces access time and cache misses
✅ Supports better system performance
🔹 Disadvantages:
❌ Some policies like LRU and LFU require additional hardware or tracking
overhead
❌ Optimal policy is not practically implementable
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Q. What is MMU ?
🔹 De nition:
The Memory Management Unit (MMU) is a hardware component in a computer system that handles all memory and address translation operations. It converts logical
(virtual) addresses generated by the CPU into physical addresses in RAM.

🔹 Key Functions of MMU:

1.✅ Address Translation
◦ Converts virtual addresses to physical addresses using page tables.
2.✅ Memory Protection
◦ Prevents processes from accessing unauthorized memory areas.
3.✅ Virtual Memory Support
◦ Enables execution of programs larger than physical memory using techniques like paging or segmentation.
4.✅ Caching and TLB Handling
◦ Uses TLB (Translation Lookaside Buffer) to speed up address translation.
🔹 How It Works:
• The CPU sends a virtual address.
• The MMU uses the page table (and possibly TLB) to nd the corresponding physical address.
• The physical address is then used to access RAM.
🔹 Components of MMU:
🔹 Advantages:
• Page Table Base Register (PTBR)
✅ Simpli es memory allocation for programs
• Translation Lookaside Buffer (TLB) ✅ Enables multitasking and isolation between processes
• Page tables ✅ Supports large programs via virtual memory
• Protection bits
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Q. What is the Direct Mapping function of Cache Memory ? It’s limitation and how it can be improve ?
🔹 What is Direct Mapping?
• Direct mapping is a simple and fast technique to map main memory blocks to cache lines.
• Each block from main memory maps to exactly one cache line using a formula:
Cache Line =(Block Address) mod (Number of Cache Lines)
🔹 How It Works:
• The main memory address is divided into:
◦ Tag: Identi es whether the stored block matches the required one.
◦ Index: Determines the speci c cache line.
◦ Offset: Locates the exact byte within a block.
• During a memory access:
◦ The index points to the cache line.
◦ The tag is compared to check for a cache hit or miss.
✅ Advantages of Direct Mapping:
1. Simple hardware design
2. Fast access time
3. Low cost and ef cient implementation
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