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Exp3 Cadet

The document outlines an experiment focused on implementing and examining data storage elements, specifically latches and flip-flops. It includes instructions for four parts of the experiment, detailing the use of various integrated circuits and equipment, as well as the expected outcomes and reporting requirements. Additionally, it provides a list of necessary components and their function tables in the appendix.

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Ali Huseynov
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6 views10 pages

Exp3 Cadet

The document outlines an experiment focused on implementing and examining data storage elements, specifically latches and flip-flops. It includes instructions for four parts of the experiment, detailing the use of various integrated circuits and equipment, as well as the expected outcomes and reporting requirements. Additionally, it provides a list of necessary components and their function tables in the appendix.

Uploaded by

Ali Huseynov
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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3

Latches and Flip-flops

3.1 Introduction
In this experiment, you will implement and examine data storage elements:
latches and flip-flops.

3.2 Preliminary
• Refresh your knowledge on how latches and flip-flops work.
• Design and draw the circuit to implement in each experiment part.
• Decide which input data must be loaded to the shift register for each case
in 3.4.4.

3.3 Equipments and Integrated Circuits (ICs)


Following equipment and ICs are going to be used in the experiment.
• C.A.D.E.T. (Complete Analogue Digital Electronic Trainer)
• 74000 series ICs
– 74xx00 - Quadruple 2-input Positive NAND Gates
– 74xx02 - Quadruple 2-input Positive NOR Gates
– 74xx04 - Hex Inverters
– 74xx75 - Quadruple Bistable D Type Latches
– 74xx165 - 8-Bit Parallel Input/Serial Output Shift Register
• Oscilloscope
Fundamental information (function tables and pin configurations) of the
ICs listed above are given in the Appendix A. You should also examine the
data-sheets in order to acquire further information about these ICs.

3.4 Experiment
3.4.1 Experiment - Part 1

Implement a SR type latch without an enable input. Use only NOR gates. Use
switches for S and R inputs and LEDs for Q and QN outputs. Create a truth
table for the latch by testing all possible input combinations. Using this truth
table, write the characteristic function of the latch as Q(t+1) = f (S, R, Q(t)).
Note how the latch behaves for disallowed inputs.
8 3 Latches and Flip-flops

3.4.2 Experiment - Part 2

Implement a SR type latch with an enable input, C. Use only NAND gates.
Use switches for S, R and C inputs and LEDs for Q and QN outputs. Create
a truth table for the latch by testing all possible input combinations. Note
how the latch behaves for disallowed inputs and how enable input e!ects the
output.

3.4.3 Experiment - Part 3

Implement a negative edge triggered D type flip-flop using two D type latches
and one inverter. Use a debounced pushbutton for the clock input, a switch
for D and LEDs for Q and QN outputs. Show that the clock is only e!ective
at falling edge.

3.4.4 Experiment - Part 4

Implement a pulse generator using a shift register. It should support variable


pulse frequencies and durations. Build the circuit below and generate given
signals. For each signal, observe both input and output using the oscilloscope
and draw.

• with the 1/2 frequency of input


• with the 1/4 frequency of input
• with the 1/8 frequency of input
• with 1/3 pulse–gap duration rate
• with 1/7 pulse–gap duration rate

3.5 Report
Prepare your report by using the guidelines and the report template which
are posted on Ninova e-Learning System. Your report should also include the
following materials:
• Circuits diagrams of the circuits which were implemented during this ex-
periment.
• Your results as truth tables and discussions for the first 3 parts of the
experiment.
• Your signal drawings and input values for the last part of the experiment.
A
Appendix - Data Sheets

A.1 7400 - Quadruple 2-input Positive-NAND Gates


Pin Configuration Function Table

A.2 7402 - Quad 2-input Positive-NOR Gates


Pin Configuration Function Table
12 A Appendix - Data Sheets

A.3 7404 - Hex Inverters


Pin Configuration Function Table

A.4 7405 - Hex Inverters with Open-Collector Outputs


Pin Configuration Function Table

A.5 7408 - Quadruple 2-input Positive-AND Gates


Pin Configuration Function Table
VCC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8
Inputs Output

A B Y
L L L
L H L
H L L
1 2 3 4 5 6 7
H H H
A1 B1 Y1 A2 B2 Y2 GND
A.9 7432 - Quadruple 2-input Positive-OR Gates 13

A.6 7410 - Triple 3-input NAND Gates


Pin Configuration

A.7 7411 - Triple 3-input AND Gates


Pin Configuration

A.8 7427 - Triple 3-input NOR Gates


Pin Configuration

A.9 7432 - Quadruple 2-input Positive-OR Gates


Pin Configuration Function Table
VCC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8
Inputs Output

A B Y
L L L
L H H
H L H
1 2 3 4 5 6 7 H H H
A1 B1 Y1 A2 B2 Y2 GND
14 A Appendix - Data Sheets

A.10 7475 - Quadruple Bistable Latches


Pin Configuration Function Table

A.11 7483 - 4-Bit Binary Full Adder with Fast Carry


Pin Configuration Function Table

A.12 7486 - Quad 2-Input Exclusive Or Gate


Pin Configuration Function Table
A.15 74161 - BCD Decade Counter / 4-Bit Binary Counter 15

A.13 74138 - 3-to-8 decoder/demultiplexer

Pin Configuration Function Table

A.14 74151 - 8-Input Multiplexer


Pin Configuration Function Table

A.15 74161 - BCD Decade Counter / 4-Bit Binary


Counter
Pin Configuration Function Table
16 A Appendix - Data Sheets

A.16 74165 - 8-Bit Parallel-Load Shift Register


Pin Configuration Function Table

A.17 74174 - Hex D-Type Flip-Flop with Reset


Pin Configuration Function Table
A.19 74241 - Octal 3-State Bu!er/ Line Driver/ Line Receiver 17

A.18 74181 - 4-Bit Arithmetic Logic Unit


Pin Configuration & Function Table

A.19 74241 - Octal 3-State Bu!er/ Line Driver/ Line


Receiver
Pin Configuration Function Table
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
18 A Appendix - Data Sheets

A.20 4011 - Quad 2-Input NAND Gate


Pin Configuration

A1 1 14 VDD

B1 2 13 A4

Q1 3 12 B4

Q2 4 11 Q4

B2 5 10 Q3

A2 6 9 B3

VSS 7 8 A3

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