COCHINE UNIVERSITY OF SCIENCE AND

TECHNOLOGY

Department Of Electronics

Lab Report- Exercise 2

Date: November 23, 2024

Submitted by:
SANDRA P : 30523027
 Lab Report November 23, 2024

1. Use 90nm unless mentioned. Use 1V as VDD.

Draw the schematic of a Complementary CMOS inverter with minimum width for
PMOS and NMOS. Perform DC analysis and plot VTC (Vout vs Vin). Measure Vih,
Voh, Vil and Vol and noise margins. Calculate the switching threshold VM. Refer
the plot given in the below link. After plotting VTC, open calculator in ADE and
select the derivative function and plot the derivative. The points were derivative
is -1 is Vih, Voh, Vil and Vol

Vin vs vout

calculation

NML= Vil-Vol/VDD=(329.968-125.396)mv=204.572
NMH=Voh-Vih/VDD=(837.446-470.027)mv=367.419
vm=410

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 Lab Report November 23, 2024

Derivation

2. For the above inverter, perform transient analysis with a input square pulse of 2ns
period and 1 percentage (of period) rise and fall time. Measure tPHL and tPLH. You
can measure the delays.
.

delay

tphl=11.1554ps tplh=5.06149ps

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output graph

3. Double the width of PMOS and measure tPHL and tPLH. Double the width of NMOS
and measure tPHL and tPLH. This is unloaded delay. Observe how it varies with
width.
.

Doubled the width of pmos

Width of pmos is 240n and nmos with width of 120n

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 Lab Report November 23, 2024

Delay and output graph:

Doubled the width of nmos

Width of nmos is 240n and pmos with width of 120n

circuit

Delay and output graph:

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 Lab Report November 23, 2024

4.Consider the inverter with minimum NMOS and PMOS widths. Add a load capaci-
tance of 10fF and measure tPHL and tPLH. Observe the variation in delay with the
unloaded case. Increase the capacitance to 20nf and 40nf and observe the delays.

Minimum width of PMOS AND NMOS :120n

10fF load capacitance

output graph and measure tPHL and tPLH

When we added the capacitance the propagation delays increased as the presence of
load capacitance increases the time it takes for the output to charge or discharge.
20fF load capacitance

output graph

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 Lab Report November 23, 2024

40fF load capacitance

output graph: When we increase the load capacitance the tplh delay
increases rapidly

5.Use the unloaded inverter and increase the width of the PMOS and identify the
width for which tpHL and tPLH are equal.
It is observed that the value of tphl and tphl becomes almost equal when the
width of the pmos is increased to 300n

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 Lab Report November 23, 2024

6.Parametrize the width of PMOS as a variable multiplied by the minimum width.

Plot VM vs this parameter. For plotting VM short input and output of the inverter.
Calculate the width of PMOS at which VM is VDD/2. This is the width which
maximizes both noise margins.
Width of pmos = s *120nm
Width of nmos = 120nm.

Explanation
vm= vdd/2=500mv.
x=3.4390
Pmos width = 120nm * 3.4390= 412.68 nm.

7.Change the width of the PMOS as obtained in Qn. 5 so that output rise and fall
delays are equal. Use a 25fF load capacitance. Increase both NMOS and PMOS width
together by a factor (S) ranging from 1 to 5 and estimate the delay.
Circuit:
Width of pmos = s * 295nm (295 nm is the width which tphl and tplh are equal).
Width of nmos = s * 120nm.

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 Lab Report November 23, 2024

S=1

S=2

S=3

S=4

S=5

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8.An inverter with size S=1 and symmetric transient response(tpHL = tpLH) is loaded
by an identical inverter. Measure the delays. Now increase the PMOS and NMOS
width of second inverter and estimate delays.

Circuit diagram

output

width of the second pmos changed from s*295 to s*300 and from s*120 and s*140
Circuit:

Output: Delay after width changed

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 Lab Report November 23, 2024

9. Estimate dynamic and leakage power for inverter with S varying from 1 to 2. Use a
square input of period 1ns. Also increase VDD to 1.1V and estimate power. Add a
load capacitance of 10fF and estimate the power dissipation.

Circuit diagram: Dynamic power of the inverters varying s from 1 to 2 Vdd = 1

output

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Estimated dynamic power when vdd = 1

Leakage power when vdd =1

Output:

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Dynamic power when vdd = 1.1

Graph of 1.1

Circuit diagram: leakage power vdd=1.1

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 Lab Report November 23, 2024

Leakage power when vdd =1.1

10.Summarize all your findings based on this exercise as a one

page report.

1.The DC analysis and voltage transfer characteristics (VTC) of a CMOS

inverter were studied using minimum-width PMOS and NMOS transistors.
During this analysis, the key parameters of the inverter were measured:
a. Vih: The input voltage at which the output begins to transition from
high to low.
b. Voh: The output voltage corresponding to a logic high level.
c. Vil: The input voltage at which the output begins to transition from low
to high.
d. Vol: The output voltage corresponding to a logic low level.
switching threshold vm was calculated at the point where the derivative of
voltage transfer characteristics becomes -1.
• NMH : The difference between VOH and VIH, representing the noise
tolerance in the high state.
• NML : The difference between VIL and VOL, representing the noise
tolerance in the low state.
The switching threshold voltage (Vm) of the inverter :410mv
2. A transient analysis was performed on a CMOS inverter using an input
square pulse with a 2 ns period and a 1% rise and fall time (20 ps). This test
simulated the dynamic behavior of the inverter during switching.
The propagation delays were calculated to analyze the inverter's
performance:
• Tphl (high-to-low delay): The time it takes for the output to transition
from high to low after the input changes.
• Tplh (low-to-high delay): The time it takes for the output to transition
from low to high after the input changes.
The delays were measured using the calculator tool and the delay function
in the ADE-L simulation window. A graph of the output voltage versus time
was plotted, showing the inverter's switching behavior. This helped
visualize the transition points and measure the delays accurately.
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 Lab Report November 23, 2024

3. The widths of the PMOS and NMOS transistors were doubled, and the
propagation delays were measured individually. From this experiment, it
was observed that the propagation delay is influenced by the size of the
transistors. Increasing the transistor width reduces their resistance,
thereby affecting the charging and discharging times of the load
capacitance, which directly impacts the delay.
4. When a load capacitance was added to the CMOS inverter with
minimum-width NMOS and PMOS transistors, it was observed that the
propagation delay increased. The delay became more pronounced as the
value of the load capacitance was varied from 10 fF to 40 nF. This behavior
occurs because larger capacitance values take more time to charge and
discharge, leading to slower transitions in the inverter's output.
5. By practicing with various PMOS width values, it was observed that at a
specific width, both Tphl (high-to-low delay) and Tplh (low-to-high delay)
became nearly equal. In this case, the optimal PMOS width was found to
be 300 nm.
6. Parametrized the width of PMOS as a variable multiplied by the
minimum width(eg. s*120). Plotted VM vs this parameter. The width which
maximizes both noise margins is calculated at which vm is vdd/2. Got the
pmos width as 412.68n.
7. When we Increase both NMOS and PMOS width together by a factor (S)
ranging from 1 to 5 and the estimated delay from each case seems to
decrease from s varying from 1 to 5. When the variable parameter that is
multiplied to the width increases the delay decreases even if there is load
capacitance present.
8. An inverter with a size =1 and a symmetric transient response
(Tphl=Tplh) was connected to an identical inverter as its load. The
propagation delays of the first inverter were measured. Then, the PMOS
and NMOS widths of the second inverter were increased, and the delays
were measured again. It was observed that the delays remained
unchanged.
This is due to the load effect. The output of the first inverter serves as the
input to the second inverter and has a specific load capacitance associated
with it. Increasing the transistor widths in the second inverter primarily
enhances its ability to charge or discharge the load faster. However, it does
not significantly affect the propagation delay of the overall chain, as the
dominant factor is the load capacitance already present at the output of
the first inverter.
9. Estimated the dynamic power and leakage power for inverter with S
varying from 1 to 2.we took levels such as 1,1.25,1.50,1.75,2. And found
the dynamic power and leakage power for vdd = 1 and vdd = 1.1

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