1 2 3 4 5 6 7 8

FM9 XXXX Intel Discrete GFX VER : 1A

PWA:
A A

PWB:
FAN & THERMAL POWER
SMSC1422
PG 38
REGULATOR CPU VR
POWER +1.5V_SUS/+0.75V_DDR_VTT
PG 51
SYSTEM PG 47
CLOCK DC/DC
RESET CIRCUIT PG 42 +1.05V +3.3V_ALW/+5V_ALW/
SLG8SP585VTR PG 48
+15V_ALW PG 46
BATT (QFN-32)
Auburndale/ PG 15 +1.1V_DDR_VTT PG 49
AC/BATT CHARGER PG 45 VGA Core
Clarksfield PG 50
CONNECTOR
RUN POWER SW
PG 53 +3.3V_SUS/+5V_SUS LVDS
+5V/+3.3V/+1.8V
Panel Connector
PG 52 PG 24
PCIEx16
ATI M92-XT
B
HDMI B

DDR3-SODIMM1 PCI EXPRESS GFX HDMI CONN.

DDR3 x 4 PG 24
PG 13 Dual Channel DDR3 (512M 64bits)
800/1067/1333 1.5V PG 20 VGA
( rPGA 989 ) PG 16,17,18,19,21,22 CRT CONN.
DDR3-SODIMM2 PG 25
PG 14 PG 3,4,5,6
SATA-ODD SATA
FDI DMI X 4
PG 35 LAN
USB conn x 3
USB2.0 x 3 PG 33, 34 RTL8111DL\RJ45\Transformer
SATA-HDD SATA PG 41
PCIEx1
& Fall Sensor PG 35
PCIEx1
PCH EXPRESS/Card Reader CONN.
PI2EQX3211BHE
USB2.0
E-SATA Combo SATA PG 28
C with USB CONN PG 33 PG 33 C

PCIEx2 MINI-CARD
IHDA
WLAN
USB2.0 USB2.0 PG 32
AUDIO/AMP
MINI-CARD
92HD73C Camera + D-MIC
USB2.0 WWAN
PG 40 PG 7,8,9,10,11,12 PG 31
PG 39
Bluetooth BTB Conn
LPC
Audio Audio
PG 32
SPK conn Jacks x3
PG 39 PG 40
KBC
ITE8502
17X8
PG 29 Keyboard
D D

SPI PS/2 PG 36
USER QUANTA
FLASH
INTERFACE
2Mbyts
Touchpad
Title
COMPUTER
PG 37 Schematic Block Diagram1
PG 30 PG 36 Size Document Number Rev
FM9 1A

Date: Wednesday, March 04, 2009 Sheet 1 of 64

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 1 2 3 4 5 6 7 8

Table of Contents Power States

CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE PAGE DESCRIPTION ACTIVE IN
SIGNAL
1 Schematic Block Diagram
2 Front Page +PWR_SRC 10V~+19V 24,30,45,46,47,48,49,50,51 MAIN POWER S0~S5
3-6 Clarksfield/Auburndale
+RTC_CELL +3.0V~+3.3V 08,11,29,30 RTC S0~S5
7-12 PCH
A 13-14 DDRIII SO-DIMM(204P) +3.3V_ALW +3.3V 08,29,30,35,36,37,42,44,45,46,47,52,53 8051 POWER ALWON S0~S5 A

15 Clock Generator
+5V_ALW2 +5V 37,46,53 LARGE POWER RUN_ON S0~S5
16-22 M92-S2-XT
23 BLANK PAGE +3.3V_LAN +3.3V 41 LAN POWER AUX_ON
24 LCD CONN / HDMI CONN
+5V_SUS +5V 11,33,34,35,37,51,52 SLP_S5# CTRLD POWER SUS_ON
25 CRT CONN
7,09,10,11,13,14,19,24,26,28,29,37,41,42,44
26 OZ888GS0L3N +3.3V_SUS +3.3V ,48,49,50,51,52 SLP_S5# CTRLD POWER SUS_ON
27 BLANK PAGE
+1.5V_SUS +1.8V 03,05,13,14,47,50,52 SODIMM POWER SUS_ON
28 Express/CRard/1394
29 SIO (ITE8512) +0.75V_DDR_VTT +0.9V 13,14,47,52 SODIMM POWER RUN_ON
30 FLASH / RTC
+5V_RUN +5V 11,18,24,25,35,36,38,39,40,52 SLP_S3# CTRLD POWER RUN_ON
31 MINI-Card (WWAN)
3,7,8,9,10,11,13,14,15,17,24,25,26,28,29,30
32 MINI-Card (WLAN\WPAN) +3.3V_RUN +3.3V ,31,32,33,35,37,38,39,40,41,42,46,51,52,59 SLP_S3# CTRLD POWER RUN_ON
33 Left PUSB/ESATA
+1.8V_RUN +1.8V 05,11,26,44,52 SDVO POWER RUN_ON
34 Right USB
B 35 SATA (HDD & CD_ROM) +1.5V_RUN +1.5V 11,18,19,20,28,31,32,52 CALISTOGA/ICH9 POWER RUN_ON B

36 TP / KEYBOARD
+1.8V_RUN_GFX +1.25V 17,18,21,22,44,52 VGA POWER RUN_ON
37 SWITCH / /LED
38 FAN / THERMAL +VCC_GFX_CORE +0.9V~+1.2V 18,21,50 VGA POWER RUN_ON
39 Azelia CODEC
+1.05V_PCH +1.05V 08,09,11,15,48 CPU/CALISTOGA/ICH8 POWER 1.05V_RUN_ON
40 AUDIO CONN
41 LAN(RTL8111DL/RJ-45) +VCC_CORE +0.7V~+1.77V 05,51 CPU CORE POWER IMVP_VR_ON
42 System Reset Circuit LCDVCC_TST_EN
+LCDVCC +3.3V 26 LCD Power & ENVDD
43 Blank Page
44 1.8V_RUN(RT9018/RT9024) +5V_MOD +5V 36 Module Power MODC_EN
45 Charger (ISL88731)
+5V_HDD +5V 36 HDD Power HDDC_EN
46 3V/5V (TPS51427A)
47 1.5_DDR/0.75(TPS51116) +1.1V_VTT +1.1V 03,05,10,11,49,59
48 1.05V_PCH(TPS51218)
+1.1V_GFX_PCIE +1.1V 18,50
49 1.1_VTT(TPS51218)
C C
50 VGA_M92-XT(MAX8792)
51 V_CORE(ISL62882) GND PLANE PAGE DESCRIPTION
52 Run Power Switch
GND_CHG
53 DCin & Batt 46
54 PAD & SCREW GND_1.05V
47
55 EMI CAP
GND_VGA
56 SMBUS BLOCK 50
57 THERMAL MAP GND_SIGNAL
51
58 Power Block Diagram
AGND_DC/DC
59 XDP 52

GND ALL

D D

QUANTA
Title
COMPUTER
Index & Power Status

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 2 of 64

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 5 4 3 2 1

AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

SC(V1.0),P11: Should be shorted at the pins
and then routed to one end of the 49.9-Ω ±1%
resistor, pulled-down to GND on the board.

U34A
B26 PEG_ICOMPI R412 49.9/F U34B
PEG_ICOMPI H_COMP3
PEG_ICOMPO A26 AT23 COMP3
7 DMI_TXN0 A24 DMI_RX#[0] PEG_RCOMPO B27 SC(V1.0),P17: BCLK A16 CLK_CPU_BCLK 10

MISC
C23 A25 R413 750/F SKTOCC# H_COMP2 AT24 B16 CLK_CPU_BCLK# 10
D 7 DMI_TXN1 DMI_RX#[1] PEG_RBIAS COMP2 BCLK# D
7 DMI_TXN2 B22 DMI_RX#[2] PCIE_MRX_GTX_N[0..15] 16 Can be left No Connect
PCIE_MRX_GTX_N15 H_COMP1

CLOCKS
7 DMI_TXN3 A21 DMI_RX#[3] PEG_RX#[0] K35 or tied to GND G16 COMP1 BCLK_ITP AR30 BCLK_ITP 60
J34 PCIE_MRX_GTX_N14 AT30 BCLK_ITP# 60
PEG_RX#[1] PCIE_MRX_GTX_N13 H_COMP0 BCLK_ITP#
7 DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33 AT26 COMP0
D23 G35 PCIE_MRX_GTX_N12 E16 CLK_PCIE_3GPLL 9
7 DMI_TXP1 DMI_RX[1] PEG_RX#[3] PEG_CLK

DMI
B23 G32 PCIE_MRX_GTX_N11 D16 CLK_PCIE_3GPLL# 9
7 DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_CLK#
A22 F34 PCIE_MRX_GTX_N10 T16 TP_SKT0CC# AH24
7 DMI_TXP3 DMI_RX[3] PEG_RX#[5] SKTOCC#
F31 PCIE_MRX_GTX_N9 A18
PEG_RX#[6] PCIE_MRX_GTX_N8 DPLL_REF_SSCLK DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND
7 DMI_RXN0 D24 DMI_TX#[0] PEG_RX#[7] D35 DPLL_REF_SSCLK# A17
G24 E33 PCIE_MRX_GTX_N7 H_CATERR# AK14 on Auburndale directly if motherboard
7 DMI_RXN1 DMI_TX#[1] PEG_RX#[8] CATERR#

THERMAL
F23 C33 PCIE_MRX_GTX_N6 only supports discrete graphics.
7 DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
H23 D32 PCIE_MRX_GTX_N5
7 DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
B32 PCIE_MRX_GTX_N4 F6 DDR3_DRAMRST# 13,14
PEG_RX#[11] PCIE_MRX_GTX_N3 R131 0 H_PECI_ISO SM_DRAMRST#
7 DMI_RXP0 D25 DMI_TX[0] PEG_RX#[12] C31 10 H_PECI AT15 PECI
F24 B28 PCIE_MRX_GTX_N2 AL1 SM_RCOMP_0
7 DMI_RXP1 DMI_TX[1] PEG_RX#[13] SM_RCOMP[0]
E23 B30 PCIE_MRX_GTX_N1 AM1 SM_RCOMP_1
7 DMI_RXP2 DMI_TX[2] PEG_RX#[14] SM_RCOMP[1]
G23 A31 PCIE_MRX_GTX_N0 AN1 SM_RCOMP_2 +1.1V_VTT
7 DMI_RXP3 DMI_TX[3] PEG_RX#[15] SM_RCOMP[2]
PCIE_MRX_GTX_P[0..15] 16 H_PROCHOT#_D AN26
PCIE_MRX_GTX_P15 PROCHOT# R135 10K/F
PEG_RX[0] J35 PM_EXT_TS#[0] AN15

DDR3
MISC
H34 PCIE_MRX_GTX_P14 AP15 R134 10K/F
PEG_RX[1] PCIE_MRX_GTX_P13 PM_EXT_TS#[1] R136 0
PEG_RX[2] H33 PM_EXTTS#0 13
E22 F35 PCIE_MRX_GTX_P12 10 H_THERM R137 0 AK15 R133 0 PM_EXTTS#1 14
FDI_TX#[0] PEG_RX[3] PCIE_MRX_GTX_P11 THERMTRIP#
D21 FDI_TX#[1] PEG_RX[4] G33
D19 E34 PCIE_MRX_GTX_P10
FDI_TX#[2] PEG_RX[5] PCIE_MRX_GTX_P9
D18 FDI_TX#[3] PEG_RX[6] F32 PRDY# AT28 XDP_PRDY# 60 CRB(v0.71) P.11
G21 D34 PCIE_MRX_GTX_P8 AP27 XDP_PREQ# XDP_PREQ# 60 R132
FDI_TX#[4] PEG_RX[7] PCIE_MRX_GTX_P7 PREQ# *12.4K/F_NC
PCI EXPRESS -- GRAPHICS
E19 FDI_TX#[5] PEG_RX[8] F33
F21 B33 PCIE_MRX_GTX_P6 AN28 XDP_TCLK XDP_TCLK 60
FDI_TX#[6] PEG_RX[9] TCK
Intel(R) FDI

G18 D31 PCIE_MRX_GTX_P5 60 H_CPURST# H_CPURST# AP26 AP28 XDP_TMS XDP_TMS 60

FDI_TX#[7] PEG_RX[10] RESET_OBS# TMS

PWR MANAGEMENT
A32 PCIE_MRX_GTX_P4 AT27 XDP_TRST# XDP_TRST# 60
PEG_RX[11] PCIE_MRX_GTX_P3 TRST# T19

JTAG & BPM

PEG_RX[12] C30
D22 A28 PCIE_MRX_GTX_P2 7 PM_SYNC AL15 AT29 XDP_TDI_R T50
FDI_TX[0] PEG_RX[13] PCIE_MRX_GTX_P1 PM_SYNC TDI XDP_TDO_R T51
C21 FDI_TX[1] PEG_RX[14] B29 TDO AR27
D20 A30 PCIE_MRX_GTX_P0 SC(V1.0),P17,35: AR29 XDP_TDI_M
C C18
FDI_TX[2]
FDI_TX[3]
PEG_RX[15]
This signal should be connected to AN14 VCCPWRGOOD_1
TDI_M
TDO_M AP29 XDP_TDO_M 2 C
G22 L33 PCIE_MTX_GRX_C_N15 the processor's VCCPWRGOOD_1
FDI_TX[4] PEG_TX#[0] PCIE_MTX_GRX_C_N14 H_DBR#_R R147 0
E20 FDI_TX[5] PEG_TX#[1] M35 and VCCPWRGOOD_0 input to DBR# AN25 XDP_DBRESET# 7,60
F20 M33 PCIE_MTX_GRX_C_N13 10,60 H_PWRGOOD AN27
FDI_TX[6] PEG_TX#[2] PCIE_MTX_GRX_C_N12 indicate when the VCCPWRGOOD_0
G19 FDI_TX[7] PEG_TX#[3] M30 XDP_OBS[0:7] 60
L31 PCIE_MTX_GRX_C_N11 processor power is valid. AJ22 XDP_OBS0_R R128 0 XDP_OBS0
PEG_TX#[4] PCIE_MTX_GRX_C_N10 PM_DRAM_PWRGD BPM#[0] XDP_OBS1_R R146 0 XDP_OBS1
F17 FDI_FSYNC[0] PEG_TX#[5] K32 7 PM_DRAM_PWRGD AK13 SM_DRAMPWROK BPM#[1] AK22
E17 M29 PCIE_MTX_GRX_C_N9 AK24 XDP_OBS2_R R126 0 XDP_OBS2
FDI_FSYNC[1] PEG_TX#[6] PCIE_MTX_GRX_C_N8 BPM#[2] XDP_OBS3_R R148 0 XDP_OBS3
PEG_TX#[7] J31 BPM#[3] AJ24
C17 K29 PCIE_MTX_GRX_C_N7 VTTPWRGOOD AM15 AJ25 XDP_OBS4_R R129 0 XDP_OBS4
FDI_INT PEG_TX#[8] 42 H_VTTPWRGD VTTPWRGOOD BPM#[4]
H30 PCIE_MTX_GRX_C_N6 SC(V1.0)P18: AH22 XDP_OBS5_R R149 0 XDP_OBS5
PEG_TX#[9] PCIE_MTX_GRX_C_N5 VTT_1.1 VR power good signal BPM#[5] XDP_OBS6_R R127 0 XDP_OBS6
F18 FDI_LSYNC[0] PEG_TX#[10] H29 BPM#[6] AK23
D17 F29 PCIE_MTX_GRX_C_N4 to processor. Signal voltage level AM26 AH23 XDP_OBS7_R R130 0 XDP_OBS7
FDI_LSYNC[1] PEG_TX#[11] is 1.1 V. 60 H_PWRGD_XDP TAPPWRGOOD BPM#[7]
E28 PCIE_MTX_GRX_C_N3
PEG_TX#[12] PCIE_MTX_GRX_C_N2
PEG_TX#[13] D29
R71 D27 PCIE_MTX_GRX_C_N1 R164 1.5K/F AL14 DBR#:
PEG_TX#[14] PCIE_MTX_GRX_C_N0 9,16,26,28,29,31,32,41 PLTRST# RSTIN# SC(V1.0) P22:Connected to the DBR# pin of the Processor.50-Ω to 5-kΩ pull-up to 3.3VS
1K PEG_TX#[15] C26
CRB(V1.0) P11,P71:CRB uses a 1-kΩ pull-up to 3.3VS.
PEG_TX[0] L34 PCIE_MTX_GRX_C_P15 1 R163 On the CRB this signal is ANDed with Master Reset to generate SYS_RESET.
0214 M34 PCIE_MTX_GRX_C_P14 +1.5V_SUS RSTIN#: Clarksfield/Auburndale
750/F
PEG_TX[1] PCIE_MTX_GRX_C_P13 DBR#:(Intell feedback)
PEG_TX[2] M32 DG(V1.11)(Doc.# 414044),P10:
L30 PCIE_MTX_GRX_C_P12 0214 Nothing wrong w/ CRB design. If you want to
PEG_TX[3] Need a voltage divider connect it to PCH directly, make sure pull high
M31 PCIE_MTX_GRX_C_P11
PEG_TX[4] PCIE_MTX_GRX_C_P10
network to scale down from to 3.3V (S0) main power.
PEG_TX[5] K31
DG(V1.0),P79: should be tied to GND M28 PCIE_MTX_GRX_C_P9 3.3V (PCH driven) to 1.05V/1.1V (Clarksfield/Auburndale)
PEG_TX[6] PCIE_MTX_GRX_C_P8 R171
(through 1K ±5% resistors), PEG_TX[7] H31
if these signals are left floating, K28 PCIE_MTX_GRX_C_P7 4.75K/F SM_DRAMPWROK:
PEG_TX[8] PCIE_MTX_GRX_C_P6
there are nofunctional impacts PEG_TX[9] G30 DG(V1.0) P311&SC(V1.0) P18:recommend 4.75-kΩ
G29 PCIE_MTX_GRX_C_P5 PM_DRAM_PWRGD +3.3V_RUN
but a small amount of power (~15 mW) PEG_TX[10] pull-up to DDR3 Power Rail (VDDQ) of +V1.5U PM_THRMTRIP# 46
F28 PCIE_MTX_GRX_C_P4
maybe wasted. PEG_TX[11] PCIE_MTX_GRX_C_P3
and a 12-kΩ pull-down to ground to convert
PEG_TX[12] E27
DG(V1.1) P83: D28 PCIE_MTX_GRX_C_P2 to processor’s VTT level.
PEG_TX[13] PCIE_MTX_GRX_C_P1 R97 CRB(V1.0) P11:CRB uses a 3.3V (always ON) rail
FDI_FSYNC[0], FDI_FSYNC[1], PEG_TX[14] C27 JTAG MAPPING
FDI_LSYNC[0],FDI_LSYNC[1] C25 PCIE_MTX_GRX_C_P0 12K/F with 2K and 1K combination. CRB Implementation R144
PEG_TX[15]

3
B is different for the Calpella Platform Design Guide. 10M Q29 B
can be ganged together
Customers to 2 2N7002W-7-F XDP_TDI_R XDP_TDI 60
with one resistor.

3
follow the latest Calpella Platform Design R494 0

1
Clarksfield/Auburndale H_THERM 2 XDP_TDO_M XDP_TDO 60
Guide for DRAMPWROK Implementation.

1
C313 R497 *0_NC
Q28 0.1U XDP_TRST#

2
MMST3904-7-F 16 R496
PCIE_MTX_GRX_N[0..15] 16 PCIE_MTX_GRX_P[0..15] 16 R499
PCIE_MTX_GRX_C_N0 16 C554 0.1U PCIE_MTX_GRX_N0 PCIE_MTX_GRX_C_P0 16 C553 0.1U PCIE_MTX_GRX_P0 0 51
PCIE_MTX_GRX_C_N1 16 C557 0.1U PCIE_MTX_GRX_N1 PCIE_MTX_GRX_C_P1 16 C555 0.1U PCIE_MTX_GRX_P1 SM_DRAMPWROK:(Intell Feedback)
PCIE_MTX_GRX_C_N2 16 C559 0.1U PCIE_MTX_GRX_N2 PCIE_MTX_GRX_C_P2 16 C558 0.1U PCIE_MTX_GRX_P2 Either way works. XDP_TDI_M
PCIE_MTX_GRX_C_N3 16 C562 0.1U PCIE_MTX_GRX_N3 PCIE_MTX_GRX_C_P3 16 C560 0.1U PCIE_MTX_GRX_P3 R495 *0_NC
PCIE_MTX_GRX_C_N4 16 C566 0.1U PCIE_MTX_GRX_N4 PCIE_MTX_GRX_C_P4 16 C563 0.1U PCIE_MTX_GRX_P4 XDP_TDO_R
PCIE_MTX_GRX_C_N5 16 C575 0.1U PCIE_MTX_GRX_N5 PCIE_MTX_GRX_C_P5 16 C568 0.1U PCIE_MTX_GRX_P5 R498 0
PCIE_MTX_GRX_C_N6 16 C579 0.1U PCIE_MTX_GRX_N6 PCIE_MTX_GRX_C_P6 16 C576 0.1U PCIE_MTX_GRX_P6
PCIE_MTX_GRX_C_N7 16 C584 0.1U PCIE_MTX_GRX_N7 PCIE_MTX_GRX_C_P7 16 C580 0.1U PCIE_MTX_GRX_P7 T18 +1.1V_VTT
PCIE_MTX_GRX_C_N8 16 C587 0.1U PCIE_MTX_GRX_N8 PCIE_MTX_GRX_C_P8 16 C585 0.1U PCIE_MTX_GRX_P8
PCIE_MTX_GRX_C_N9 16 C595 0.1U PCIE_MTX_GRX_N9 PCIE_MTX_GRX_C_P9 16 C588 0.1U PCIE_MTX_GRX_P9 XDP_TMS R158 *51_NC Scan Chain STUFF -> R780, R783, R786
PCIE_MTX_GRX_C_N10 16 C597 0.1U PCIE_MTX_GRX_N10 PCIE_MTX_GRX_C_P10 16 C596 0.1U PCIE_MTX_GRX_P10 XDP_TDI_R R493 *51_NC (Default) NO STUFF -> R781, R785
PCIE_MTX_GRX_C_N11 16 C601 0.1U PCIE_MTX_GRX_N11 PCIE_MTX_GRX_C_P11 16 C599 0.1U PCIE_MTX_GRX_P11 XDP_PREQ# R157 *51_NC
PCIE_MTX_GRX_C_N12 16 C605 0.1U PCIE_MTX_GRX_N12 PCIE_MTX_GRX_C_P12 16 C602 0.1U PCIE_MTX_GRX_P12 CRB(V1.0) P11: XDP_TCLK R156 *51_NC
PCIE_MTX_GRX_C_N13 16 C612 0.1U PCIE_MTX_GRX_N13 PCIE_MTX_GRX_C_P13 16 C606 0.1U PCIE_MTX_GRX_P13 T17
is it necessery? CPU Only STUFF -> R780, R781
PCIE_MTX_GRX_C_N14 16 C614 0.1U PCIE_MTX_GRX_N14 PCIE_MTX_GRX_C_P14 16 C613 0.1U PCIE_MTX_GRX_P14 NO STUFF -> R783, R785, R786
PCIE_MTX_GRX_C_N15 16 C618 0.1U PCIE_MTX_GRX_N15 PCIE_MTX_GRX_C_P15 16 C616 0.1U PCIE_MTX_GRX_P15

GMCH Only STUFF -> R785, R786

NO STUFF -> R780, R781, R783
+1.1V_VTT
Processor Compensation Signals DDR3 Compensation Signals
Processor H_COMP0
Pullups H_COMP1
SM_RCOMP_2 DG(v1.0) table 27 TRST#
SC(V1.0)P22:
SC(1.0V),P17: SM_RCOMP_1 should be routed as a single
H_COMP2 daisy chain to all loads and
A
H_PROCHOT#D SM_RCOMP_0 terminated at the end of the trace. A
R100 R121 R122 use: pull to 68 ohm H_COMP3 51 Ω ± 5% pull down resistor.
49.9/F 49.9/F *68_NC if it isn'tt used: pull to 50 ohm CRB()V1.0)P11

Layout Note: Place

H_CATERR# R123 R72 R124 R125 R95 R89 R94

H_PROCHOT#_D
SC(1.0V),P17:
H_CATERR#
49.9/F 49.9/F 20/F 20/F 130/F 24.9/F 100/F
these resistors
near Processor QUANTA
H_CPURST# 49.9-Ω ±1% Pull-Up to the VTT rail
(+V1.1S_VTT) DG(V1.0),P83: Title
COMPUTER
DG(V1.0),P17: SM_RCOMP[0] 100-Ω ±1% pull-down to GND AUBURNDA 1/4
COMP[0.1] 49.9-Ω ±1% pull-down to GND SM_RCOMP[1] 24.9-Ω ±1% pull-down to GND
COMP[2.3] 20-Ω ±1% pull-down to GND Size Document Number Rev
SM_RCOMP[2] 130-Ω ±1% pull-down to GND FM9 1A

Date: Wednesday, March 04, 2009 Sheet 3 of 64

5 4 3 2 1
 5 4 3 2 1

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)

U34D
U34C

14 M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 14

SA_CK[0] AA6 M_A_CLK0 13 SB_CK#[0] W9 M_B_CLK0# 14
AA7 M_A_CLK0# 13 M_B_DQ0 B5 M3 M_B_CKE0 14
D SA_CK#[0] M_B_DQ1 SB_DQ[0] SB_CKE[0] D
13 M_A_DQ[63:0] SA_CKE[0] P7 M_A_CKE0 13 A5 SB_DQ[1]
M_A_DQ0 A10 M_B_DQ2 C3
M_A_DQ1 SA_DQ[0] M_B_DQ3 SB_DQ[2]
C10 SA_DQ[1] B3 SB_DQ[3] SB_CK[1] V7 M_B_CLK1 14
M_A_DQ2 C7 M_B_DQ4 E4 V6 M_B_CLK1# 14
M_A_DQ3 SA_DQ[2] M_B_DQ5 SB_DQ[4] SB_CK#[1]
A7 SA_DQ[3] SA_CK[1] Y6 M_A_CLK1 13 A6 SB_DQ[5] SB_CKE[1] M2 M_B_CKE1 14
M_A_DQ4 B10 Y5 M_A_CLK1# 13 M_B_DQ6 A4
M_A_DQ5 SA_DQ[4] SA_CK#[1] M_B_DQ7 SB_DQ[6]
D10 SA_DQ[5] SA_CKE[1] P6 M_A_CKE1 13 C4 SB_DQ[7]
M_A_DQ6 E10 M_B_DQ8 D1
M_A_DQ7 SA_DQ[6] M_B_DQ9 SB_DQ[8]
A8 SA_DQ[7] D2 SB_DQ[9]
M_A_DQ8 D8 M_B_DQ10 F2 AB8 M_B_CS0# 14
M_A_DQ9 SA_DQ[8] M_B_DQ11 SB_DQ[10] SB_CS#[0]
F10 SA_DQ[9] SA_CS#[0] AE2 M_A_CS0# 13 F1 SB_DQ[11] SB_CS#[1] AD6 M_B_CS1# 14
M_A_DQ10 E6 AE8 M_A_CS1# 13 M_B_DQ12 C2
M_A_DQ11 SA_DQ[10] SA_CS#[1] M_B_DQ13 SB_DQ[12]
F7 SA_DQ[11] F5 SB_DQ[13]
M_A_DQ12 E9 M_B_DQ14 F3
M_A_DQ13 SA_DQ[12] M_B_DQ15 SB_DQ[14]
B7 SA_DQ[13] G4 SB_DQ[15] SB_ODT[0] AC7 M_B_ODT0 14
M_A_DQ14 E7 AD8 M_A_ODT0 13 M_B_DQ16 H6 AD1 M_B_ODT1 14
M_A_DQ15 SA_DQ[14] SA_ODT[0] M_B_DQ17 SB_DQ[16] SB_ODT[1]
C6 SA_DQ[15] SA_ODT[1] AF9 M_A_ODT1 13 G2 SB_DQ[17]
M_A_DQ16 H10 M_B_DQ18 J6
M_A_DQ17 SA_DQ[16] M_B_DQ19 SB_DQ[18]
G8 SA_DQ[17] J3 SB_DQ[19]
M_A_DQ18 K7 M_B_DQ20 G1 M_B_DM[7:0] 14
M_A_DQ19 SA_DQ[18] M_B_DQ21 SB_DQ[20] M_B_DM0
J8 SA_DQ[19] G5 SB_DQ[21] SB_DM[0] D4
M_A_DQ20 G7 M_B_DQ22 J2 E1 M_B_DM1
M_A_DQ21 SA_DQ[20] M_B_DQ23 SB_DQ[22] SB_DM[1] M_B_DM2
G10 SA_DQ[21] M_A_DM[7:0] 13 J1 SB_DQ[23] SB_DM[2] H3
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ24 J5 K1 M_B_DM3
M_A_DQ23 SA_DQ[22] SA_DM[0] M_A_DM1 M_B_DQ25 SB_DQ[24] SB_DM[3] M_B_DM4
J10 SA_DQ[23] SA_DM[1] D7 K2 SB_DQ[25] SB_DM[4] AH1
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ26 L3 AL2 M_B_DM5
M_A_DQ25 SA_DQ[24] SA_DM[2] M_A_DM3 M_B_DQ27 SB_DQ[26] SB_DM[5] M_B_DM6
M6 SA_DQ[25] SA_DM[3] M7 M1 SB_DQ[27] SB_DM[6] AR4
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ28 K5 AT8 M_B_DM7
M_A_DQ27 SA_DQ[26] SA_DM[4] M_A_DM5 M_B_DQ29 SB_DQ[28] SB_DM[7]
L9 SA_DQ[27] SA_DM[5] AM7 K4 SB_DQ[29]
C M_A_DQ28 L6 AN10 M_A_DM6 M_B_DQ30 M4 C
M_A_DQ29 SA_DQ[28] SA_DM[6] M_A_DM7 M_B_DQ31 SB_DQ[30]
K8 SA_DQ[29] SA_DM[7] AN13 N5 SB_DQ[31]
M_A_DQ30 N8 M_B_DQ32 AF3
M_A_DQ31 SA_DQ[30] M_B_DQ33 SB_DQ[32]
P9 SA_DQ[31] AG1 SB_DQ[33] M_B_DQS#[7:0] 14
M_A_DQ32 AH5 M_B_DQ34 AJ3 D5 M_B_DQS#0
M_A_DQ33 SA_DQ[32] M_B_DQ35 SB_DQ[34] SB_DQS#[0] M_B_DQS#1
AF5 SA_DQ[33] M_A_DQS#[7:0] 13 AK1 SB_DQ[35] SB_DQS#[1] F4
M_A_DQ34 AK6 C9 M_A_DQS#0 M_B_DQ36 AG4 J4 M_B_DQS#2
SA_DQ[34] SA_DQS#[0] SB_DQ[36] SB_DQS#[2]
DDR SYSTEM MEMORY A

M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ37 AG3 L4 M_B_DQS#3

M_A_DQ36 SA_DQ[35] SA_DQS#[1] M_A_DQS#2 M_B_DQ38 SB_DQ[37] SB_DQS#[3] M_B_DQS#4
AF6 SA_DQ[36] SA_DQS#[2] J9 AJ4 SB_DQ[38] SB_DQS#[4] AH2
M_A_DQ37 M_A_DQS#3 M_B_DQ39 M_B_DQS#5

DDR SYSTEM MEMORY - B

AG5 SA_DQ[37] SA_DQS#[3] N9 AH4 SB_DQ[39] SB_DQS#[5] AL4
M_A_DQ38 AJ7 AH7 M_A_DQS#4 M_B_DQ40 AK3 AR5 M_B_DQS#6
M_A_DQ39 SA_DQ[38] SA_DQS#[4] M_A_DQS#5 M_B_DQ41 SB_DQ[40] SB_DQS#[6] M_B_DQS#7
AJ6 SA_DQ[39] SA_DQS#[5] AK9 AK4 SB_DQ[41] SB_DQS#[7] AR8
M_A_DQ40 AJ10 AP11 M_A_DQS#6 M_B_DQ42 AM6
M_A_DQ41 SA_DQ[40] SA_DQS#[6] M_A_DQS#7 M_B_DQ43 SB_DQ[42]
AJ9 SA_DQ[41] SA_DQS#[7] AT13 AN2 SB_DQ[43]
M_A_DQ42 AL10 M_B_DQ44 AK5
M_A_DQ43 SA_DQ[42] M_B_DQ45 SB_DQ[44]
AK12 SA_DQ[43] AK2 SB_DQ[45]
M_A_DQ44 AK8 M_B_DQ46 AM4
M_A_DQ45 SA_DQ[44] M_B_DQ47 SB_DQ[46]
AL7 SA_DQ[45] M_A_DQS[7:0] 13 AM3 SB_DQ[47] M_B_DQS[7:0] 14
M_A_DQ46 AK11 C8 M_A_DQS0 M_B_DQ48 AP3 C5 M_B_DQS0
M_A_DQ47 SA_DQ[46] SA_DQS[0] M_A_DQS1 M_B_DQ49 SB_DQ[48] SB_DQS[0] M_B_DQS1
AL8 SA_DQ[47] SA_DQS[1] F9 AN5 SB_DQ[49] SB_DQS[1] E3
M_A_DQ48 AN8 H9 M_A_DQS2 M_B_DQ50 AT4 H4 M_B_DQS2
M_A_DQ49 SA_DQ[48] SA_DQS[2] M_A_DQS3 M_B_DQ51 SB_DQ[50] SB_DQS[2] M_B_DQS3
AM10 SA_DQ[49] SA_DQS[3] M9 AN6 SB_DQ[51] SB_DQS[3] M5
M_A_DQ50 AR11 AH8 M_A_DQS4 M_B_DQ52 AN4 AG2 M_B_DQS4
M_A_DQ51 SA_DQ[50] SA_DQS[4] M_A_DQS5 M_B_DQ53 SB_DQ[52] SB_DQS[4] M_B_DQS5
AL11 SA_DQ[51] SA_DQS[5] AK10 AN3 SB_DQ[53] SB_DQS[5] AL5
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ54 AT5 AP5 M_B_DQS6
M_A_DQ53 SA_DQ[52] SA_DQS[6] M_A_DQS7 M_B_DQ55 SB_DQ[54] SB_DQS[6] M_B_DQS7
AN9 SA_DQ[53] SA_DQS[7] AR13 AT6 SB_DQ[55] SB_DQS[7] AR7
M_A_DQ54 AT11 M_B_DQ56 AN7
M_A_DQ55 SA_DQ[54] M_B_DQ57 SB_DQ[56]
AP12 SA_DQ[55] AP6 SB_DQ[57]
M_A_DQ56 AM12 M_B_DQ58 AP8
M_A_DQ57 SA_DQ[56] M_B_DQ59 SB_DQ[58]
B
AN12 SA_DQ[57] M_A_A[15:0] 13 AT9 SB_DQ[59] B
M_A_DQ58 AM13 Y3 M_A_A0 M_B_DQ60 AT7
M_A_DQ59 SA_DQ[58] SA_MA[0] M_A_A1 M_B_DQ61 SB_DQ[60]
AT14 SA_DQ[59] SA_MA[1] W1 AP9 SB_DQ[61]
M_A_DQ60 AT12 AA8 M_A_A2 M_B_DQ62 AR10 M_B_A[15:0] 14
M_A_DQ61 SA_DQ[60] SA_MA[2] M_A_A3 M_B_DQ63 SB_DQ[62] M_B_A0
AL13 SA_DQ[61] SA_MA[3] AA3 AT10 SB_DQ[63] SB_MA[0] U5
M_A_DQ62 AR14 V1 M_A_A4 V2 M_B_A1
M_A_DQ63 SA_DQ[62] SA_MA[4] M_A_A5 SB_MA[1] M_B_A2
AP14 SA_DQ[63] SA_MA[5] AA9 SB_MA[2] T5
V8 M_A_A6 V3 M_B_A3
SA_MA[6] M_A_A7 SB_MA[3] M_B_A4
SA_MA[7] T1 SB_MA[4] R1
Y9 M_A_A8 14 M_B_BS0 AB1 T8 M_B_A5
SA_MA[8] M_A_A9 SB_BS[0] SB_MA[5] M_B_A6
13 M_A_BS0 AC3 SA_BS[0] SA_MA[9] U6 14 M_B_BS1 W5 SB_BS[1] SB_MA[6] R2
13 M_A_BS1 AB2 AD4 M_A_A10 14 M_B_BS2 R7 R6 M_B_A7
SA_BS[1] SA_MA[10] M_A_A11 SB_BS[2] SB_MA[7] M_B_A8
13 M_A_BS2 U7 SA_BS[2] SA_MA[11] T2 SB_MA[8] R4
U3 M_A_A12 R5 M_B_A9
SA_MA[12] M_A_A13 SB_MA[9] M_B_A10
SA_MA[13] AG8 14 M_B_CAS# AC5 SB_CAS# SB_MA[10] AB5
T3 M_A_A14 14 M_B_RAS# Y7 P3 M_B_A11
SA_MA[14] M_A_A15 SB_RAS# SB_MA[11] M_B_A12
13 M_A_CAS# AE1 SA_CAS# SA_MA[15] V9 14 M_B_WE# AC6 SB_W E# SB_MA[12] R3
13 M_A_RAS# AB3 AF7 M_B_A13
SA_RAS# SB_MA[13] M_B_A14
13 M_A_WE# AE9 SA_W E# SB_MA[14] P5
N1 M_B_A15
SB_MA[15]

Clarksfield/Auburndale

A A
Channel A DQ[15,32,48,54], DM[5] Clarksfield/Auburndale
Requires minimum 12mils spacing
with all other signals, including data signals.
Channel B DQ[16,18,36,42,56,57,60,61,62]
QUANTA
Requires minimum 12mils spacing
with all other signals, including data signals. Title
COMPUTER
AUBURNDA 2/4

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 4 of 64

5 4 3 2 1
 5 4 3 2 1

U34F
CPU Core Power +1.1V_VTT AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)
+VCC_CORE

AG35 AH14 U34G

VCC1 VTT0_1
AG34 VCC2 VTT0_2 AH12
AG33 VCC3 VTT0_3 AH11 AT21 VAXG1
AG32 AH10 C628 C216 C228 C189 C541 C525 C515 C593 C592 AT19 AR22
VCC4 VTT0_4 10U 10U 10U 10U 10U 10U 10U *10U_NC *10U_NC VAXG2 VAXG_SENSE

SENSE
LINES
AG31 VCC5 VTT0_5 J14 AT18 VAXG3 VSSAXG_SENSE AT22
AG30 J13 AT16
D AG29
VCC6
VCC7
VTT0_6
VTT0_7 H14 AR21
VAXG4
VAXG5
4 D
AG28 VCC8 VTT0_8 H12 AR19 VAXG6
AG27 VCC9 VTT0_9 G14 AR18 VAXG7
AG26 VCC10 VTT0_10 G13 AR16 VAXG8 GFX_VID[0] AM22
AF35 VCC11 VTT0_11 G12 AP21 VAXG9 GFX_VID[1] AP22 GFX_VID[0..6],GFX_VR_EN,GFX_DPRSLPVR,GFX_IMON:
+1.1V_VTT

GRAPHICS VIDs
AF34 VCC12 VTT0_12 G11 AP19 VAXG10 GFX_VID[2] AN22 Could this be left unconnected when not in use?
AF33 VCC13 VTT0_13 F14 AP18 VAXG11 GFX_VID[3] AP23
AF32 VCC14 VTT0_14 F13 AP16 VAXG12 GFX_VID[4] AM23
AF31 VCC15 VTT0_15 F12 AN21 VAXG13 GFX_VID[5] AP24 GFX_VID[0..6],GFX_VR_EN,GFX_DPRSLPVR,GFX_IMON:(Intel feedback)

GRAPHICS
AF30 VCC16 VTT0_16 F11 AN19 VAXG14 GFX_VID[6] AN24 Yes, see DG rev1.5
AF29 E14 C540 C552 C590 AN18
VCC17 VTT0_17 22U 22U 22U VAXG15
AF28 VCC18 VTT0_18 E12 AN16 VAXG16
AF27 VCC19 VTT0_19 D14 AM21 VAXG17 GFX_VR_EN AR25
AF26 VCC20 VTT0_20 D13 AM19 VAXG18 GFX_DPRSLPVR AT25
AD35 D12 AM18 AM24 R145 *1K/F_NC

1.1V RAIL POWER

VCC21 VTT0_21 VAXG19 GFX_IMON
AD34 VCC22 VTT0_22 D11 AM16 VAXG20
AD33 VCC23 VTT0_23 C14 AL21 VAXG21
AD32 VCC24 VTT0_24 C13 AL19 VAXG22
AD31 C12 AL18 +1.5V_SUS
VCC25 VTT0_25 VAXG23
AD30 VCC26 VTT0_26 C11 AL16 VAXG24
AD29 VCC27 VTT0_27 B14 AK21 VAXG25 VDDQ1 AJ1
AD28 VCC28 VTT0_28 B12 AK19 VAXG26 VDDQ2 AF1
AD27 A14 AK18 AE7

- 1.5V RAILS
VCC29 VTT0_29 VAXG27 VDDQ3 C212 C197 C237 C243 C196
AD26 VCC30 VTT0_30 A13 AK16 VAXG28 VDDQ4 AE4
AC35 A12 AJ21 AC1 1U 1U 1U 1U 1U
VCC31 VTT0_31 VAXG29 VDDQ5
AC34 VCC32 VTT0_32 A11 AJ19 VAXG30 VDDQ6 AB7
AC33 VCC33 AJ18 VAXG31 VDDQ7 AB4
AC32 VCC34 AJ16 VAXG32 VDDQ8 Y1
AC31 +1.1V_VTT AH21 W7
VCC35 VAXG33 VDDQ9

POWER
AC30 VCC36 VTT0_33 AF10 AH19 VAXG34 VDDQ10 W4
AC29 AE10 AH18 U1 + C646 C253 C218 +VCC_CORE
VCC37 VTT0_34 VAXG35 VDDQ11 330U 22U 22U
AC28 VCC38 VTT0_35 AC10 AH16 VAXG36 VDDQ12 T7
CPU CORE SUPPLY

C AC27 AB10 T4 7343 C

VCC39 VTT0_36 +1.1V_VTT VDDQ13 2.5
AC26 VCC40 VTT0_37 Y10 VDDQ14 P1
AA35 W10 C591 C551 N7
VCC41 VTT0_38 22U 22U VDDQ15 C244 C517 C511 C512 C543 C523
AA34 VCC42 VTT0_39 U10 VDDQ16 N4

DDR3
22U 22U 22U 22U 22U 22U
AA33
AA32
VCC43 VTT0_40 T10
J12
3 J24
VDDQ17 L1
H1
VCC44 VTT0_41 VTT1_45 VDDQ18

FDI
AA31 VCC45 VTT0_42 J11 J23 VTT1_46
AA30 J16 H25 +1.1V_VTT
VCC46 VTT0_43 C633 C242 VTT1_47
AA29 VCC47 VTT0_44 J15
AA28 22U 22U
VCC48
AA27 VCC49 VTT0_59 P10
AA26 VTT0_43,VTT0_44: N10 C544 C202 C227 C208 C516
VCC50 VTT0_60 + C518 22U 22U 22U 22U 22U C624
Y35 VCC51 CRB(V1.0)P13 VTT0_61 L10
Y34 Why add 0ohm?? Is it trace width control?? K10 C209 C169 *330U_NC 22U
VCC52 VTT0_62 10U 10U 7343
Y33 VCC53
Y32 2.5
VCC54
Y31 VCC55
VTT0_43,VTT0_44:(Intel feedback)
Y30 VCC56 They are connected to hidden page for

1.1V
Y29 VCC57 intel validation purpose. VTT1_63 J22
Y28 K26 J20 C269 C220 C267 C241 C238 C621 C632 C627
VCC58 VTT1_48 VTT1_64 10U 10U 10U 10U 10U 10U 10U 10U
Y27 VCC59 J27 VTT1_49 VTT1_65 J18

PEG & DMI

Y26 J26 H21 C524 C603
VCC60 C617 C622 C514 C611 VTT1_50 VTT1_66 22U 22U
V35 VCC61 PSI# AN33 H_PSI# 51 J25 VTT1_51 VTT1_67 H20
V34 22U 22U 22U 22U H27 H19
POWER

VCC62 VTT1_52 VTT1_68

V33 VCC63 G28 VTT1_53
V32 AK35 VID0 G27 +1.8V_RUN
VCC64 VID[0] VID0 51 VTT1_54
V31 AK33 VID1 VID1 51 G26
VCC65 VID[1] VID2 VTT1_55 C252 C249 C221 C215 C211 C263 C264 C610
V30 VCC66 VID[2] AK34 VID2 51 F26 VTT1_56
V29 AL35 VID3 VID3 51 E26 L26 10U 10U 10U 10U 10U 10U 10U 10U
VCC67 VID[3] VTT1_57 VCCPLL1
CPU VIDS

1.8V
V28 AL33 VID4 VID4 51 E25 L27
VCC68 VID[4] VID5 VTT1_58 VCCPLL2
V27 VCC69 VID[5] AM33 VID5 51 VCCPLL3 M26
V26 AM35 VID6 VID6 51 C162 C170 C184 C195 C589
B VCC70 VID[6] DPRSLPVR 1U 1U 2.2U 4.7U/6.3V 22U B
U35 VCC71 PROC_DPRSLPVR AM34 DPRSLPVR 51
U34 VCC72
U33 VCC73
U32 VTT_SELECT: + C262 + C37
VCC74 *470U_NC *470U_NC
U31 VCC75 VTT_SELECT G15 H_VTTVID1 49 High level 1.05V for Auburndale
U30
U29
VCC76 Low level 1.1V for Clarksfield Clarksfield/Auburndale
VCC77
U28 VCC78
U27 VCC79
U26 +VCC_CORE
VCC80
R35 VCC81
R34 VCC82
R33 VCC_SENSE & VSS_SENSE:
VCC83 R446 SC(V1.0)P19 +1.1V_VTT
R32 VCC84 ISENSE AN35 I_MON 51
R31 100/F 100- ±1% pull-down to GND near processor
VCC85
R30 VCC86
R29 VCC87
R28 AJ34
SENSE LINES

VCC88 VCC_SENSE VCCSENSE 51

R27 VCC89 VSS_SENSE AJ35 VSSSENSE 51
R26 R451 R448 R454 R458 R460 R472 R462 R465 R469
VCC90 1K 1K 1K *1K_NC *1K_NC 1K *1K_NC 1K *1K_NC
P35 VCC91
P34 VCC92 VTT_SENSE B15 VTT_SENSE 49
P33 A15 TP_VSS_SENSE_VTT VID0
VCC93 VSS_SENSE_VTT T40 R447 VID1
P32 VCC94
P31 100/F VID2
VCC95 VID3
P30 VCC96
P29 VID4
VCC97 VSS_SENSE_VTT: VID5
P28 VCC98
P27 SC(V1.0)P20 PROC_DPRSLPVR: VID6
VCC99 Connect VSS_SENSE_VTT to GND SC(V1.0)P19: DPRSLPVR
P26 VCC100 or can be left floating. It is important to have the resistor stuffing options H_PSI#
Note: CRB has the VSS_SENSE_VTT floating. in the design for the Turbo functionality.
A The stuffing and no-stuffing of the resistors A
will depend on the POC configuration of AUB
and CFD Note: R452 R449 R455 R459 R461 R473 R463 R466 R470
CRB(V1.0)P67: For Validating IMVP VR R814 should be STUFF *1K_NC *1K_NC *1K_NC 1K 1K *1K_NC 1K *1K_NC 1K
uses 1K pull-up and pull-down resistors and R827 NO_STUFF

Clarksfield/Auburndale
CRB default setting is "1"
QUANTA
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER) Title
COMPUTER
AUBURNDA 3/4

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 5 of 64

5 4 3 2 1
 5 4 3 2 1

AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

U34H U34I U34E

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162 AP25 RSVD1
AR26 VSS5 VSS85 AE30 K6 VSS163 AL25 RSVD2 RSVD34 AH25
AR24 VSS6 VSS86 AE29 K3 VSS164 AL24 RSVD3 RSVD35 AK26
AR23 VSS7 VSS87 AE28 J32 VSS165 AL22 RSVD4
AR20 VSS8 VSS88 AE27 J30 VSS166 AJ33 RSVD5 RSVD36 AL26
AR17 VSS9 VSS89 AE26 J21 VSS167 AG9 RSVD6 RSVD_NCTF_37 AR2
D AR15 AE6 J19 M27 D
VSS10 VSS90 VSS168 RSVD7
AR12 VSS11 VSS91 AD10 H35 VSS169 L28 RSVD8 RSVD38 AJ26
AR9 VSS12 VSS92 AC8 H32 VSS170 +M_VREF_DQ_DIMM0 J17 SA_DIMM_VREF RSVD39 AJ27
AR6 VSS13 VSS93 AC4 H28 VSS171 +M_VREF_DQ_DIMM1 H17 SB_DIMM_VREF
AR3 VSS14 VSS94 AC2 H26 VSS172 G25 RSVD11
AP20 VSS15 VSS95 AB35 H24 VSS173 G17 RSVD12
AP17 VSS16 VSS96 AB34 H22 VSS174 E31 RSVD13 RSVD_NCTF_40 AP1
AP13 VSS17 VSS97 AB33 H18 VSS175 E30 RSVD14 RSVD_NCTF_41 AT2
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177 RSVD_NCTF_42 AT3
AP4 VSS20 VSS100 AB30 H11 VSS178 RSVD_NCTF_43 AR1
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182 RSVD45 AL28
AN20 AB6 G31 CFG0 AM30 AL29
VSS25 VSS105 VSS183 CFG[0] RSVD46
AN17 VSS26 VSS106 AA10 G20 VSS184 AM28 CFG[1] RSVD47 AP30
AM29 VSS27 VSS107 Y8 G9 VSS185 AP31 CFG[2] RSVD48 AP32
AM27 Y4 G6 CFG3 AL32 AL27
VSS28 VSS108 VSS186 CFG4 CFG[3] RSVD49
AM25 VSS29 VSS109 Y2 G3 VSS187 AL30 CFG[4] RSVD50 AT31
AM20 VSS30 VSS110 W 35 F30 VSS188 AM31 CFG[5] RSVD51 AT32
AM17 VSS31 VSS111 W 34 F27 VSS189 AN29 CFG[6] RSVD52 AP33
AM14 W 33 F25 CFG7 AM32 AR33
VSS32 VSS112 VSS190 CFG[7] RSVD53
AM11 VSS33 VSS113 W 32 F22 VSS191 AK32 CFG[8] RSVD_NCTF_54 AT33
AM8 W 31 F19 AK31 AT34

RESERVED
VSS34 VSS114 VSS192 CFG[9] RSVD_NCTF_55
AM5 VSS35 VSS115 W 30 F16 VSS193 AK28 CFG[10] RSVD_NCTF_56 AP35
AM2 VSS36 VSS116 W 29 E35 VSS194 AJ28 CFG[11] RSVD_NCTF_57 AR35
AL34 W 28 E32 AN30 AR32
C AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W 27
W 26
E29
E24
VSS195
VSS196
VSS197
VSS AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58
C

AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

AL17 VSS41 VSS121 V10 E18 VSS199 AJ30 CFG[16] RSVD_TP_60 F15
AL12 VSS42 VSS122 U8 E13 VSS200 AK30 CFG[17] KEY A2
AL9 VSS43 VSS123 U4 E11 VSS201 H16 RSVD_TP_86 RSVD62 D15
AL6 VSS44 VSS124 U2 E8 VSS202 RSVD63 C15
AL3 T35 E5 AJ15 RSVD64_R R98 0
VSS45 VSS125 VSS203 RSVD64 RSVD65_R R99 0
AK29 VSS46 VSS126 T34 E2 VSS204 VSS_NCTF1 AT35 RSVD65 AH15
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34 B19 RSVD15
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34 A19 RSVD16
AK17 T30 D9 B2

NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 R414 0 TP_RSVD17_R
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 A20 RSVD17
AJ23 T28 D3 A35 R415 0 TP_RSVD18_R B20
VSS52 VSS132 VSS210 VSS_NCTF7 RSVD18
AJ20 VSS53 VSS133 T27 C34 VSS211 RSVD_TP_66 AA5
AJ17 VSS54 VSS134 T26 C32 VSS212 U9 RSVD19 RSVD_TP_67 AA4
AJ14 VSS55 VSS135 T6 C29 VSS213 T9 RSVD20 RSVD_TP_68 R8
AJ11 VSS56 VSS136 R10 C28 VSS214 RSVD_TP_69 AD3
AJ8 VSS57 VSS137 P8 C24 VSS215 AC9 RSVD21 RSVD_TP_70 AD2
AJ5 VSS58 VSS138 P4 C22 VSS216 AB9 RSVD22 RSVD_TP_71 AA2
AJ2 VSS59 VSS139 P2 C20 VSS217 RSVD_TP_72 AA1
AH35 VSS60 VSS140 N35 C19 VSS218 RSVD_TP_73 R9
AH34 VSS61 VSS141 N34 C16 VSS219 RSVD_TP_74 AG7
AH33 VSS62 VSS142 N33 B31 VSS220 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
AH32 VSS63 VSS143 N32 B25 VSS221 A3 RSVD_NCTF_24
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223 RSVD_TP_76 V4
B AH29 VSS66 VSS146 N29 B17 VSS224 RSVD_TP_77 V5 B
AH28 VSS67 VSS147 N28 B13 VSS225 RSVD_TP_78 N2
AH27 VSS68 VSS148 N27 B11 VSS226 J29 RSVD26 RSVD_TP_79 AD5
AH26 VSS69 VSS149 N26 B8 VSS227 J28 RSVD27 RSVD_TP_80 AD7
AH20 VSS70 VSS150 N6 B6 VSS228 RSVD_TP_81 W3
AH17 VSS71 VSS151 M10 B4 VSS229 A34 RSVD_NCTF_28 RSVD_TP_82 W2
AH13 VSS72 VSS152 L35 A29 VSS230 A33 RSVD_NCTF_29 RSVD_TP_83 N3
AH9 VSS73 VSS153 L32 A27 VSS231 RSVD_TP_84 AE5
AH6 VSS74 VSS154 L29 A23 VSS232 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
AH3 VSS75 VSS155 L8 A9 VSS233 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34
AF4 VSS78 VSS158 K34 Can be left NC is Intel CRM
AF2 K33 R476
VSS79 VSS159 implementation; ESD/DG
AE35 VSS80 VSS160 K30 0
recommendation to GND
Clarksfield/Auburndale

Clarksfield/Auburndale Clarksfield/Auburndale

1 0
CFG4 Enabled; An external Display port
(Display Port Disabled; No Physical Display Port device is connected to the Embedded
A
The Clarkfield processor's PCI Express interface may CFG4 R155 *3.01K/F_NC Presence) attached to Embedded Diplay Port Display port
A

not meet PCI Express 2.0 jitter specifications. Intel CFG0 R154 *3.01K/F_NC CFG0
recommends placing a 3.01K +/- 5% pull down resistor to
VSS on CFG[7] pin for both rPGA and BGA components. CFG3 R101 3.01K/F (PCI-Epress Single PEG Bifurcation enabled
QUANTA
This pull down resistor should be removed when this
issue is fixed. CFG7 R153 *3.01K/F_NC
Configuration Select)
Title
COMPUTER
CFG3
Normal Operation Lane Numbers Reversed AUBURNDA 4/4
(PCI-Epress Static
PCIE LANE is Lane Numbers Reversed Lane Reversal) Size Document Number Rev
FM9 1A

Date: Wednesday, March 04, 2009 Sheet 6 of 64

5 4 3 2 1
 5 4 3 2 1

IBEX PEAK-M (DMI,FDI,GPIO)

U42C
IBEX PEAK-M (LVDS,DDI)
BA18
FDI_RXN0 DG(V1.0)P185:
3 DMI_RXN0 BC24 DMI0RXN FDI_RXN1 BH17
BJ22 BD16 If the LVDS interface is not implemented, U42D
3 DMI_RXN1 DMI1RXN FDI_RXN2
D 3 DMI_RXN2 AW20 DMI2RXN FDI_RXN3 BJ16 all signals associated with the interface can T48 L_BKLTEN SDVO_TVCLKINN BJ46 D
3 DMI_RXN3 BJ20 DMI3RXN FDI_RXN4 BA16 be left as No Connects. The supply pins T47 L_VDD_EN SDVO_TVCLKINP BG46
FDI_RXN5 BE14
BD24 BA14
VccTX_LVDS and VCCA_LVD can be Y48 BJ48
3 DMI_RXP0 DMI0RXP FDI_RXN6 connected to ground. L_BKLTCTL SDVO_STALLN
3 DMI_RXP1 BG22 DMI1RXP FDI_RXN7 BC12 SDVO_STALLP BG48
3 DMI_RXP2 BA20 DG(V1.1) P83:FDI_FSYNC[0], FDI_FSYNC[1], AB48
DMI2RXP L_DDC_CLK
3 DMI_RXP3 BG20 DMI3RXP FDI_RXP0 BB18 FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT Y45 L_DDC_DATA SDVO_INTN BF45
FDI_RXP1 BF17 signals on PCH side can be left as SDVO_INTP BH45
3 DMI_TXN0 BE22 DMI0TXN FDI_RXP2 BC16 no connect without any power AB46 L_CTRL_CLK
3 DMI_TXN1 BF21 DMI1TXN FDI_RXP3 BG16 V48 L_CTRL_DATA
BD20 AW16
or functional impact.
3 DMI_TXN2 DMI2TXN FDI_RXP4
3 DMI_TXN3 BE18 DMI3TXN FDI_RXP5 BD14 AP39 LVD_IBG SDVO_CTRLCLK T51

SDVO
FDI_RXP6 BB14 AP41 LVD_VBG SDVO_CTRLDATA T53
3 DMI_TXP0 BD22 BD12
DMI0TXP FDI_RXP7
3 DMI_TXP1 BH21 AT43
DMI1TXP LVD_VREFH

Display port B
3 DMI_TXP2 BC20 AT42 BG44
DMI2TXP LVD_VREFL DDPB_AUXN
3 DMI_TXP3 BD18 BJ14 BJ44
DMI3TXP FDI_INT DDPB_AUXP
AU38

DMI
FDI
DDPB_HPD

LVDS
BF13 AV53
FDI_FSYNC0 LVDSA_CLK#
BH25 DMI_ZCOMP AV51 LVDSA_CLK DDPB_0N BD42
BH13 BC42
R545 49.9/F DMI_ZCOMP FDI_FSYNC1 DDPB_0P
+1.05V_VCCIO BF25 DMI_IRCOMP BB47 LVDSA_DATA#0 DDPB_1N BJ42
BJ12 BA52 BG42

Digital Display Interface

FDI_LSYNC0 LVDSA_DATA#1 DDPB_1P
AY48 LVDSA_DATA#2 DDPB_2N BB40
CS(V1.0) P32 BG14 AV47 BA40
FDI_LSYNC1 LVDSA_DATA#3 DDPB_2P
PWROK and SYS_PWROK should be tied DDPB_3N AW38
together on the platform.MEPWROK can be connected BB48 BA38
LVDSA_DATA0 DDPB_3P
C to PCH_PWROK pin on PCH when Intel AMT BA50 C
LVDSA_DATA1
AY49
is not enabled. LVDSA_DATA2
AV48 Y49
LVDSA_DATA3 DDPC_CTRLCLK
AB49
DDPC_CTRLDATA

3,60 XDP_DBRESET# T6 SYS_RESET# WAKE# J12 PCIE_W AKE# 28,31,32,41 AP48 LVDSB_CLK#

Display port C
AP47 BE44
LVDSB_CLK DDPC_AUXN
DDPC_AUXP BD44
R302 0 SYS_PW ROK M6 Y1 CLKRUN# AY53 AV40
SYS_PWROK CLKRUN# / GPIO32 CLKRUN# 29 LVDSB_DATA#0 DDPC_HPD
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40

System Power Management

R581 0 PW ROK B17 AT53 BD40
29 PCH_PW RGD PWROK LVDSB_DATA#3 DDPC_0P
DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
R304 0 MEPW ROK K5 P8 RSV_LPCPD# T28 AT48 BD38
MEPWROK SUS_STAT# / GPIO61 LVDSB_DATA1 DDPC_2N
AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 BB36
LAN_RST# ICH_SUSCLK LVDSB_DATA3 DDPC_3N
A10 LAN_RST# SUSCLK / GPIO62 F3 T34 DDPC_3P BA36

D9 E4 SLP_S5#_R R307 0 AA52 U50

3 PM_DRAM_PW RGD DRAMPWROK SLP_S5# / GPIO63 SIO_SLP_S5# 29 CRT_BLUE DDPD_CTRLCLK
AB53 U52
CRT_GREEN DDPD_CTRLDATA
AD53
ICH_RSMRST# SLP_S4#_R R306 0 CRT_RED
29 ICH_RSMRST# C16 H7 SIO_SLP_S4# 13
RSMRST# SLP_S4#

Display port D
DDPD_AUXN BC46
V51 CRT_DDC_CLK DDPD_AUXP BD46
29 SUS_PW R_ACK M1 P12 SLP_S3#_R V53 AT38
SUS_PWR_DN_ACK / GPIO30 SLP_S3# SIO_SLP_S3# 29 CRT_DDC_DATA DDPD_HPD
B B
BJ40
SLP_M#_R DDPD_0N
29 SIO_PW RBTN# P5 PWRBTN# SLP_M# K8 T38 Y53 CRT_HSYNC DDPD_0P BG40
Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38

CRT
29 AC_PRESENT P7 N2 T56 BF37
ACPRESENT / GPIO31 TP23 DDPD_2N
AD48 BH37
DAC_IREF DDPD_2P
AB51 BE36
PM_BATLOW # CRT_IRTN DDPD_3N
A6 BJ10 PM_SYNC 3 BD36
MEPWROK BATLOW# / GPIO72 PMSYNCH R269 DDPD_3P
SC(V1.0)P32: 1K IbexPeak-M_R1P0
It can be connected to PCH_PWROK pin PM_RI# F14 F6 PM_SLP_LAN#_R T36
RI# SLP_LAN# / GPIO29
on PCH when Intel AMT is not enabled.
IbexPeak-M_R1P0
+3.3V_RUN

CLKRUN# R555 10K/F

+3.3V_SUS +3.3V_SUS 5 DG(V1.0)P189:
If the CRT interface is not implemented,
all signals associated with the interface can
PM_RI# R326 10K/F PM_BATLOW # R577 8.2K/F
PCH_PW RGD R582 10K/F
be left as No Connects. The pins
PCIE_W AKE# R325 1K CRT_IRTN Connect this signals to GND
ICH_RSMRST# R321 10K/F and DAC_IREF Connect to GND
PM_BATLOW#: via a 1.0 k ±0.5% pull-down resistor
A LAN_RST# R591 10K/F EDS(V1.0)P95: 15K~40K (+3.3V_SUS) A
CRB(V1.0)P25: 8.2K (+3.3V_ALW)
LAN_RST#
DG(V1.0) P311
PM_BATLOW#:(Intel feedback)
15K ~ 40K is a simulation result,
QUANTA
the expected value should be 20K
If integrated LAN is not used, recommend
to connect LAN_RST# to GND via an 8.2-kΩ PWROK
internal pull high in PCH.
8.2K is external pull high. Title
COMPUTER
to 10-kΩ pull-down resistor. SC(V1.0)P32: IBEX PEAK-M 2/6
EDS(V1.0)P64 8.2 kΩ to 10 kΩ pull-down resistor to GND.
must be grounded if Intel LAN is disabled. PWROK and SYS_PWROK should be tied together on the platform.
Size Document Number Rev
FM9 1A

Date: W ednesday, March 04, 2009 Sheet 7 of 64

5 4 3 2 1
 5 4 3 2 1

+RTC_CELL
D D

C751
R593 20K/F 18P/50V
IBEX PEAK-M (HDA,JTAG,SATA)

2
1
C749

1U Y5 R580
32.768KHZ 10M
C750

3
4
U42A
R583 20K/F 18P/50V
RTC_X1 B13 D33
RTCX1 FWH0 / LAD0 LPC_LAD0 29,32
C746 RTC_X2 D13 B33
RTCX2 FWH1 / LAD1 LPC_LAD1 29,32
Cap values depend on Xtal C32 LPC_LAD2 29,32
R589 1U FWH2 / LAD2
FWH3 / LAD3 A32 LPC_LAD3 29,32
1M RTC_RST# C14 RTCRST#
FWH4 / LFRAME# C34 LPC_LFRAME# 29,32
SRTC_RST# D17 SRTCRST#
A34

RTC

LPC
SM_INTRUDER# LDRQ0#
A16 INTRUDER# LDRQ1# / GPIO23 F34

+RTC_CELL R592 330K PCH_INVRMEN A14 AB9

INTVRMEN SERIRQ IRQ_SERIRQ 29

INTVRMEN(Internal Voltage Regulator Enable) :

This signal enables the internal 1.05 V regulators. ACZ_BIT_CLK A30 HDA_BCLK
This signal must be always pulled-up to VccRTC. SATA0RXN AK7 SATA_RX0- 35
C R587 33 ACZ_BIT_CLK ACZ_SYNC D29 AK6 C
39 ICH_AZ_CODEC_BITCLK HDA_SYNC SATA0RXP SATA_RX0+ 35
SATA0TXN AK11 SATA_TX0- 35 SATA HDD
SPKR P1 AK9
39 SPKR SPKR SATA0TXP SATA_TX0+ 35
C747 ACZ_RST# C30
*27P_NC HDA_RST#
Flash Descriptor Security Override SATA1RXN AH6 SATA_RX1- 35
SATA1RXP AH5 SATA_RX1+ 35
50 G30 AH9 SATA ODD
39 ICH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA1TXN SATA_TX1- 35
SATA1TXP AH8 SATA_TX1+ 35
Low = Enabled F30
R586 33 ACZ_SYNC HDA_SDIN1
39 ICH_AZ_CODEC_SYNC GPIO33 High = Disabled SATA2RXN AF11
E32 AF9 Distance between the PCH and

IHDA
R313 33 ACZ_RST# HDA_SDIN2 SATA2RXP
29,39 ICH_AZ_CODEC_RST# SATA2TXN AF7 cap on the "P" signal should be
F32 AF6 SATA port 2/3 are not support in HM55 .
R585 33 ACZ_SDOUT HDA_SDIN3 SATA2TXP identical distace between the
39 ICH_AZ_CODEC_SDOUT They are only in PM 55
SATA3RXN AH3 PCH and cap on the "N" signal
ACZ_SDOUT B29 AH1
Place all series terms close to PCH except for SDIN input HDA_SDO SATA3RXP
AF3 for the same pair.
R315 1 SATA3TXN
lines,which should be close to source.Placement of R773, R775, 2 *10K/F_NC GPIO33 SATA3TXP AF1
GPIO33 H32

SATA
R776 & R777 should equal distance to the T split trace point. HDA_DOCK_EN# / GPIO33
SATA4RXN AD9 SATA_RX4- 33
Basically, keep the same distance from T for all series 36 KB_LED_DET J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8 SATA_RX4+ 33
termination resistors. SATA4TXN AD6 SATA_TX4- 33 E-SATA
(Internal 20K/F pull high to +3.3V_RUN) AD5 SATA_TX4+ 33
SATA4TXP
T55 PCH_JTAG_TCK_BUF M3 AD3
JTAG_TCK SATA5RXN
Note : GPIO33 is a signal used for Flash SATA5RXP AD1
T57 PCH_JTAG_TMS K3 AB3
Descriptor Security Override/ME Debug JTAG_TMS SATA5TXN
SATA5TXP AB1
Mode.This signal should be only asserted T58 PCH_JTAG_TDI K1
B JTAG_TDI B
lowthrough an external pull-down in

JTAG
T59 PCH_JTAG_TDO J2 AF16
manufacturing or debug environments JTAG_TDO SATAICOMPO
ONLY. T60 PCH_JTAG_RST# J4 AF15 SATA_COMP R266 37.4/F
TRST# SATAICOMPI +1.05V_PCH

SPI_CLK BA2 R568 100K

30 SPI_CLK SPI_CLK
+3.3V_RUN
No Reboot strap. SPI_CS0# AV3
30 SPI_CS0# SPI_CS0#
Low = Default. T52 SPI_CS1# AY3 T3 SATA_ACT#
SPI_CS1# SATALED# SATA_ACT# 29
SPKR High = No Reboot.
+3.3V_RUN SPI_SI AY1 Y9 R2731 2 10K/F
30 SPI_SI SPI_MOSI SATA0GP / GPIO21 +3.3V_RUN

SPI
SPI_SO AV1 V1 R5561 2 10K/F
30 SPI_SO SPI_MISO SATA1GP / GPIO19
1 2 SPKR
R284 *1K_NC
IbexPeak-M_R1P0

JTAG
Test Pads are need to put on
the same side of mother board.
A A

QUANTA
Title
COMPUTER
IBEX PEAK-M 1/6

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 8 of 64

5 4 3 2 1
 5 4 3 2 1

IBEX PEAK-M (PCI,USB,NVRAM) IBEX PEAK-M (PCI-E,SMBUS,CLK)

Place TX DC blocking caps close PCH.
U42B
U42E
H40 AY9 BG30 B9 RSV_SMBALERT# T71
AD0 NV_CE#0 31 PCIE_RX1- PERN1 SMBALERT# / GPIO11
N34 BD1 31 PCIE_RX1+ BJ30
AD1 NV_CE#1 C721 0.1U PCIE_TXN1_C PERP1 ICH_SMBCLK
C44
AD2 NV_CE#2
AP15 MiniWWAN 31 PCIE_TX1- BF29
PETN1 SMBCLK
H14 ICH_SMBCLK 32,41,60
A38 BD8 C717 0.1U PCIE_TXP1_C BH29
AD3 NV_CE#3 31 PCIE_TX1+ PETP1
C36 C8 ICH_SMBDATA
AD4 SMBDATA ICH_SMBDATA 32,41,60
J34 AD5 NV_DQS0 AV9 32 PCIE_RX2- AW30 PERN2
A40 BG8 32 PCIE_RX2+ BA30
AD6 NV_DQS1 C374 0.1U PCIE_TXN2_C PERP2 RSV_ICH_CL_RST1# T30
D
D45
AD7 MiniWLAN 32 PCIE_TX2- BC30
PETN2 SML0ALERT# / GPIO60
J14
D
E36 AP7 C375 0.1U PCIE_TXP2_C BD30
AD8 NV_DQ0 / NV_IO0 32 PCIE_TX2+ PETP2
H48 AP6 C6 SMB_CLK_ME0
AD9 NV_DQ1 / NV_IO1 SML0CLK
E40 AT6 AU30

SMBus
AD10 NV_DQ2 / NV_IO2 PERN3 SMB_DATA_ME0
C40 AT9 AT30 G8
AD11 NV_DQ3 / NV_IO3 PERP3 SML0DATA
M48 AD12 NV_DQ4 / NV_IO4 BB1 AU32 PETN3
M45 AD13 NV_DQ5 / NV_IO5 AV6 AV32 PETP3
F53 BB3 M14 LPD_SPI_INTR# T31
AD14 NV_DQ6 / NV_IO6 SML1ALERT# / GPIO74
M40 BA4 28 PCIE_RX4- BA32
AD15 NV_DQ7 / NV_IO7 PERN4 SMB_CLK_ME1 SML0CLK/SML0DATA:
Express Card

NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4 28 PCIE_RX4+ BB32 PERP4 SML1CLK / GPIO58 E10
J36 BB6 C376 0.1U PCIE_TXN4_C BD32 DG(V1.1) P255: The 82577 SMBus
AD17 NV_DQ9 / NV_IO9 28 PCIE_TX4- PETN4 signals
K48 BD6 C377 0.1U PCIE_TXP4_C BE32 G12 SMB_DATA_ME1
AD18 NV_DQ10 / NV_IO10 28 PCIE_TX4+ PETP4 SML1DATA / GPIO75 (SMB_DATA and SMB_CLK) cannot be
F40 BB7

PCI-E*
AD19 NV_DQ11 / NV_IO11 connected to any other
C42 BC8 26 PCIE_RX5- BF33
AD20 NV_DQ12 / NV_IO12 PERN5 devices other than the PCH.
K46 BJ8 26 PCIE_RX5+ BH33 T13
AD21 NV_DQ13 / NV_IO13 PERP5 CL_CLK1

Controller
C396 0.1U PCIE_TXN5_C Connect the SMB_DATA and SMB_CLK
M51
AD22 NV_DQ14 / NV_IO14
BJ6 Card Reader 26 PCIE_TX5- BG32
PETN5 pins
J52 BG6 C389 0.1U PCIE_TXP5_C BJ32 T11
AD23 NV_DQ15 / NV_IO15 26 PCIE_TX5+ PETP5 CL_DATA1 to the PCH SML0DATA and SML0CLK
K51

Link
AD24 pins,
L34 AD25 NV_ALE BD3 NV_ALE 10 41 PCIE_RX6-/GLAN_RX- BA34 PERN6 CL_RST1# T9 respectively.
F42 AD26 NV_CLE AY6 NV_CLE 10 41 PCIE_RX6+/GLAN_RX+ AW34 PERP6
J40 Giga Bit LOM C379 0.1U PCIE_TXN6_C BC34
AD27 41 PCIE_TX6-/GLAN_TX- PETN6
G46 C378 0.1U PCIE_TXP6_C BD34
AD28 41 PCIE_TX6+/GLAN_TX+ PETP6
F44 AU2 H1 PEG_CLKREQ# T65
AD29 NV_RCOMP PEG_A_CLKRQ# / GPIO47
M47 AT34
AD30 PERN7

PCI
H36 AV7 AU34
AD31 NV_RB# PERP7
AU36 AD43 CLK_PCIE_VGA# 16
PETN7 CLKOUT_PEG_A_N
J50 AY8 AV36 AD45 CLK_PCIE_VGA 16
C/BE0# NV_WR#0_RE# PCI-E port 7/8 are not support in HM55 . PETP7 CLKOUT_PEG_A_P
G42 AY5
C/BE1# NV_WR#1_RE#
H47 They are only in PM 55 BG34 AN4 CLK_PCIE_3GPLL# 3
C/BE2# PERN8 CLKOUT_DMI_N

PEG
G34 C/BE3# NV_WE#_CK0 AV11 BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_PCIE_3GPLL 3
BF5 BG36
T35 PCI_PIRQA# NV_WE#_CK1 PETN8
G38 PIRQA# BJ36 PETP8
PCI_PIRQB# H51 AT1
PCI_PIRQC# PIRQB# CLKOUT_DP_N / CLKOUT_BCLK1_N
B37 PIRQC# USBP0N H18 ICH_USBP0- 33 Left Side pair Top CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
T62 PCI_PIRQD# A44 J18 AK48
PIRQD# USBP0P ICH_USBP0+ 33 CLKOUT_PCIE0N
A18 ICH_USBP1- 33 AK47
USBP1N Left Side pair bottom CLKOUT_PCIE0P

From CLK BUFFER

PCI_REQ0# F51 C18 AW24
C REQ0# USBP1P ICH_USBP1+ 33 CLKIN_DMI_N CLK_BUF_PCIE_3GPLL# 15 C
T61 REQ1# A46 N20 CLK_PEG0_REQ# P9 BA24
REQ1# / GPIO50 USBP2N ICH_USBP2- 34 PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_PCIE_3GPLL 15
T63 SB_WWAN_PCIE_RST# B45 P20 Right Side pair top (Cable)
REQ2# / GPIO52 USBP2P ICH_USBP2+ 34
USB_MCARD1_DET# M53 J20
32 USB_MCARD1_DET# REQ3# / GPIO54 USBP3N
L20 31 CLK_PCIE_MINI2# AM43 AP3 CLK_BUF_BCLK_N 15
PCI_GNT0# USBP3P CLKOUT_PCIE1N CLKIN_BCLK_N
F48 GNT0# USBP4N F20 ICH_USBP4- 32 MiniWWAN 31 CLK_PCIE_MINI2 AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_BUF_BCLK_P 15
T32 GNT#1 K45 G20 Mini Card (WLAN)
GNT1# / GPIO51 USBP4P ICH_USBP4+ 32
T37 GNT#2 F36 A20 CLK_PCIE_REQ1# R275 0 U4
GNT2# / GPIO53 USBP5N ICH_USBP5- 31 31 CLK_PCIE_REQ1# PCIECLKRQ1# / GPIO18
10 GNT3# H53 GNT3# / GPIO55 USBP5P C20 ICH_USBP5+ 31 Mini Card (WWAN) CLKIN_DOT_96N F18 CLK_BUF_DREFCLK# 15
USBP6N M22 CLKIN_DOT_96P E18 CLK_BUF_DREFCLK 15
T68 SB_WPAN_PCIE_RST# B41 N22 USB port 6/7 are not support in HM55 . AM47
SB_WLAN_PCIE_RST# PIRQE# / GPIO2 USBP6P CLKOUT_PCIE2N
T54 K53 B21 They are only in PM 55 AM48
PIRQG# PIRQF# / GPIO3 USBP7N CLKOUT_PCIE2P
T70 A36 D21 AH13 CLK_BUF_DREFSSCLK# 15
PCH_IRQH_GPIO5 PIRQG# / GPIO4 USBP7P CLK_PCIE_REQ2# R292 0 CLKIN_SATA_N / CKSSCD_N
35 PCH_IRQH_GPIO5 A48 PIRQH# / GPIO5 USBP8N H22 ICH_USBP8- 32 N4 PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P AH12 CLK_BUF_DREFSSCLK 15
USBP8P
J22 ICH_USBP8+ 32 Mini Card (WPAN)
USB

PCI_RST# K6 E22
PCIRST# USBP9N ICH_USBP9- 28
PCIRST#: T33 F22 Express Card AH42 P41
USBP9P ICH_USBP9+ 28 32 CLK_PCIE_MINI1# CLKOUT_PCIE3N REFCLK14IN CLK_ICH_14M 15
DG(V1.0) P277 PCI_SERR# E44 A22 MiniWLAN AH41
SERR# USBP10N 32 CLK_PCIE_MINI1 CLKOUT_PCIE3P
PCI_PERR# E50 C22 CLKIN_PCILOOPBACK:
Can be left unconnected. PERR# USBP10P PDG (V1.1): 22 ohm series resistor
G24 MINI1CLK_REQ# R323 0 A8 J42 CLK_PCI_FB
USBP11N ICH_USBP11- 40 32 MINI1CLK_REQ# PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK is recommend
PAR: H24 ICH_USBP11+ 40 Camera
PCI_IRDY# USBP11P 0214
SC(V1.0) P36 A42 L24 ICH_USBP12- 37
IRDY# USBP12N
Can be left unconnected H44
PAR USBP12P
M24 ICH_USBP12+ 37 Touch Screen Module 28 CLK_PCIE_EXPCARD# AM51
CLKOUT_PCIE4N XTAL25_IN
AH51
PCI_DEVSEL# F46 A24 Express Card AM53 AH53 DG(V1.1) P256: XTAL_OUT and XTAL_IN
if not using PCI. DEVSEL# USBP13N 28 CLK_PCIE_EXPCARD CLKOUT_PCIE4P XTAL25_OUT are the signal names for the PHY.
PCI_FRAME# C46 C24
FRAME# USBP13P CARD_CLK_REQ# R295 0 XCLK_RCOMP
28 CARD_CLK_REQ# M9 PCIECLKRQ4# / GPIO26 XCLK_RCOMP AF38 +1.05V_PCH
PCI_PLOCK# D49 Note : place these R259 90.9/F
PLOCK# USB_BIAS
USBRBIAS# B25 resistors near to PCIe
PCI_STOP# D41 R584 22.6/F AJ50 T45 CLK_FLEX0 T26
STOP# Slots 26 CLK_PCIE_CARD_READER# CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
PME: PCI_TRDY# C48 D25 AJ52
TRDY# USBRBIAS 26 CLK_PCIE_CARD_READER CLKOUT_PCIE5P
DG(V1.0) P277
PME# M7 Card Reader CLK_PCIE_REQ5# R308 0 H6 P43 CLK_FLEX1 T29

Clock Flex
Can be left unconnected. PME# 26 CLK_PCIE_REQ5# PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
T27 N16 OC0#
OC0# / GPIO59 OC0# 33
0214 PCI_PLTRST# D5 J16 OC1#
PLTRST# OC1# / GPIO40 OC1# 34
F16 OC2# AK53 T42 CLK_FLEX2 T25
OC2# / GPIO41 41 CLK_PCIE_LOM# CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
R566 22/F CLK_LPC_DEBUG_C N52 L16 OC3# AK51
32 CLK_LPC_DEBUG CLKOUT_PCI0 OC3# / GPIO42 41 CLK_PCIE_LOM CLKOUT_PEG_B_P
P53 E14 OC4# Giga Bit LOM
B R277 22/F CLK_PCI_8512_C CLKOUT_PCI1 OC4# / GPIO43 OC5# LOM_CLK_REQ# R276 0 CLK_FLEX3 T53 B
29 CLK_PCI_8512 P46 G16 41 LOM_CLK_REQ# P13 N50
CLK_PCI_FB R564 22/F CLK_PCI_FB_C CLKOUT_PCI2 OC5# / GPIO9 OC6# PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
P51 CLKOUT_PCI3 OC6# / GPIO10 F12
CLKOUT_PCI[0..4]: P48 T15 OC7# CLKOUTFLEX3: 0214
CLKOUT_PCI4 OC7# / GPIO14 IbexPeak-M_R1P0
22 ohm series resistor is recommend EDS(V1.0) :support 48MHz
(single & double load) on PDG v1.1 OC0#~OC7#: CLKOUT_PEG_A_P/N,CLKOUT_PEG_B_P/N, 33MHz and 14.31818MHz.
IbexPeak-M_R1P0 DG(V1.0)P214 CLKOUT_DMI_P/N,support GEN-1 and GEN-2
Pin Default Port Mapping
CLKOUTFLEX[0..3]:
+3.3V_SUS OC0# Port0,Port1
Reserve capacitor pads for PDG v1.1: 22 ohm series resistor is
OC1# Port2,Port3 PCIECLKRQ{0,3,4,5,6,7}# should have a
improving WWAN. recommend (PCI & non PCI routing,
RSV_SMBALERT# 10K/F R590 +3.3V_SUS 10K pull-up to +V3.3A.PCIECLKRQ{1,2}
RSV_ICH_CL_RST1# 10K/F R293 single & double load)
should have a 10K pull-up to +3.3S
ICH_SMBCLK 2.2K/F R320 R324 10K MINI1CLK_REQ#
ICH_SMBDATA 2.2K/F R322 +3.3V_RUN R288 10K CARD_CLK_REQ# +3.3V_SUS
SMB_CLK_ME0 2.2K/F R579 R309 10K CLK_PCIE_REQ5#
CLK_LPC_DEBUG 50 SMB_DATA_ME0 2.2K/F R310 PIRQG# R588 8.2K/F R287 10K CLK_PEG0_REQ#
C738 *27P_NC SMB_CLK_ME1 2.2K/F R600 SB_WPAN_PCIE_RST# R578 8.2K/F R278 10K LOM_CLK_REQ#
CLK_PCI_8512 50 SMB_DATA_ME1 2.2K/F R601 SB_WWAN_PCIE_RST# R576 8.2K/F
C437 *27P_NC LPD_SPI_INTR# 10K/F R281 SB_WLAN_PCIE_RST# R570 8.2K/F +3.3V_RUN

PEG_CLKREQ# 10K/F R573 R272 10K CLK_PCIE_REQ1#

R290 10K CLK_PCIE_REQ2# Q52

2
+3.3V_SUS 2N7002W-7-F
RP9
OC7# 6 5 SMB_CLK_ME1 1 3 SMBCLK1 29
OC5# 7 4 OC2#
OC4# 8 3 OC6#
OC3# 9 2 OC1#
OC0# R294 1K PCI_GNT0# +3.3V_SUS
Non-iAMT Add Buffers as needed for +3.3V_SUS
10 1
R291 1K GNT#1
Loading and fanout concerns. 10P8R-8.2K Q53

2
2N7002W-7-F

+3.3V_RUN SMB_DATA_ME1 1 3 SMBDAT1 29

RP10
+3.3V_SUS PCH_IRQH_GPIO5 6 5 Boot BIOS Strap
A C768 0.047U PCI_REQ0# 7 4 PCI_TRDY# A
PCI_PIRQB# 8 3 PCI_FRAME# PCI_GNT0# GNT#1 Boot BIOS Location
USB_MCARD1_DET# 9 2 REQ1#
+3.3V_RUN 10 1 PCI_PIRQD# 0 0 LPC
5

U43
10 2 10P8R-8.2K 0 1 Reserved (NAND)
4
PCI_PLTRST# 1
PLTRST# 3,16,26,28,29,31,32,41
+3.3V_RUN
1 0 PCI QUANTA
RP8 SPI
TC7SZ32FU(T5L,F,T)
PCI_STOP#
PCI_PIRQA#
6
7
5
4 PCI_SERR#
1 1
Title
COMPUTER
PCI_PIRQC# 8 3 PCI_PERR# IBEX PEAK-M 3/6
PCI_IRDY# 9 2 PCI_PLOCK#
+3.3V_RUN 10 1 PCI_DEVSEL# Size Document Number Rev
FM9 1A
10P8R-8.2K
Date: Wednesday, March 04, 2009 Sheet 9 of 64
5 4 3 2 1
 5 4 3 2 1

IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)

U42F +3.3V_SUS

S_GPIO Y3 AH45 TEST_WOOFER_EN R271 1K

BMBUSY# / GPIO0 CLKOUT_PCIE6N RSV_WOL_EN R331 10K/F
CLKOUT_PCIE6P AH46
29 SIO_EXT_SMI# SIO_EXT_SMI# C38 TP_PCH_GPIO28 R274 10K/F
TACH1 / GPIO1 GPIO45 R574 10K/F
29 SIO_EXT_SCI# SIO_EXT_SCI# D37 GPIO46 R575 10K/F
TACH2 / GPIO6 GPIO57 R329 10K/F
CLKOUT_PCIE7N AF48

MISC
29 SIO_EXT_WAKE# SIO_EXT_WAKE# J32 AF47 LAN_PHY_PWR_CTRL R603 10K/F
TACH3 / GPIO7 CLKOUT_PCIE7P
D RSV_WOL_EN F10 D
GPIO8

29,41 LAN_PCIE_PWR_CTRL R602 *0_NC LAN_PHY_PWR_CTRL K9 U2

LAN_PHY_PWR_CTRL / GPIO12 A20GATE SIO_A20GATE 29
TEST_WOOFER_EN T7 +3.3V_RUN
39 TEST_WOOFER_EN GPIO15
SATA4GP AA2 AM3 +1.1V_VTT SIO_EXT_SMI# R317 10K/F
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# 3
SIO_EXT_SCI# R316 10K/F
R319 0 PCIE_MCARD1_DET#_R F38 AM1 SIO_EXT_WAKE# R289 10K/F
32 PCIE_MCARD1_DET# TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK 3
PCIE_MCARD2_DET# R258 10K/F
PCIE_MCARD2_DET# Y7 BG10
31 PCIE_MCARD2_DET# SCLOCK / GPIO22 PECI H_PECI 3

GPIO
PCIE_MCARD1_DET#_R R318 10K/F
GPIO24 register not cleared by CF9h reset event. H10
GPIO24 RCIN#
T1 SIO_RCIN# 29
R234 WLAN_RADIO_DIS# R557 10K/F
56/F CRB_SV_DET R569 10K/F
GPIO27 reserve for internal VR. R255 *10K_NC GPIO27 AB12 BE10
GPIO27 PROCPWRGD H_PWRGOOD 3,60

CPU
SIO_RCIN# R565 10K/F
TP_PCH_GPIO28 V13 BD10 PCH_THRMTRIP#_R R235 54.9/F SIO_A20GATE R563 10K/F
GPIO28 THRMTRIP# H_THERM 3
SATA2GP R254 10K/F
USB_MCARD2_DET# M11 SATA5GP R264 10K/F
31 USB_MCARD2_DET# STP_PCI# / GPIO34
(Both these should be close to PCH) SATA3GP R268 10K/F
GPIO35 V6 SATA4GP R554 10K/F
SATACLKREQ# / GPIO35 USB_MCARD2_DET# R303 10K/F
SATA2GP AB7 BA22 CRIT_TEMP_REP# R262 10K/F
SATA2GP / GPIO36 TP1
SATA3GP AB13 AW22
SATA3GP / GPIO37 TP2
32 WLAN_RADIO_DIS# WLAN_RADIO_DIS# V3 BB22
SLOAD / GPIO38 TP3
R571 0 CRB_SV_DET P3 AY45
32 BT_RADIO_DIS# SDATAOUT0 / GPIO39 TP4
C GPIO45 H3 AY46 C
PCIECLKRQ6# / GPIO45 TP5
GPIO46 F1 AV43
PCIECLKRQ7# / GPIO46 TP6
R256 0 SV_SET_UP AB6 AV45
31 WWAN_RADIO_DIS# SDATAOUT1 / GPIO48 TP7
R263 0 SATA5GP AA4 AF13
29 CRIT_TEMP_REP# SATA5GP / GPIO49 TP8
GPIO57 F8 M18
GPIO57 TP9
N18
TP10
A4 AJ24
VSS_NCTF_1 TP11
A49
NCTF

VSS_NCTF_2 RSVD
A5 VSS_NCTF_3 TP12 AK41
A50
VSS_NCTF_4
DMI Termination Voltage
A52 AK42
VSS_NCTF_5 TP13
A53
VSS_NCTF_6 Set to Vcc when LOW
B2 M32
VSS_NCTF_7 TP14
B4 VSS_NCTF_8
NV_CLE
B52 N32 Set to Vcc/2 when HIGH +NVRAM_VCCQ
VSS_NCTF_9 TP15
B53
VSS_NCTF_10
BE1 M30
VSS_NCTF_11 TP16 R553 *1K_NC
BE53 VSS_NCTF_12 9 NV_ALE
BF1 VSS_NCTF_13 TP17 N30
BF53 R246 *1K_NC
VSS_NCTF_14 9 NV_CLE
BH1 H12
VSS_NCTF_15 TP18
BH2
VSS_NCTF_16
BH52
VSS_NCTF_17 TP19
AA23 Danbury Technology Enabled
BH53
VSS_NCTF_18
B BJ1
VSS_NCTF_19 NC_1
AB45 High = Enable B
BJ2 NV_ALE
VSS_NCTF_20
BJ4 AB38 Low = Disable
VSS_NCTF_21 NC_2
BJ49
VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
BJ50
VSS_NCTF_24
BJ52 AB41
VSS_NCTF_25 NC_4
BJ53 VSS_NCTF_26
D1 T39
VSS_NCTF_27 NC_5
D2
VSS_NCTF_28
D53
VSS_NCTF_29
E1 VSS_NCTF_30 INIT3_3V# P6
E53 VSS_NCTF_31
C10
TP24
IbexPeak-M_R1P0

+3.3V_RUN
6
R267 10K/F GPIO35
BMBUSY#:
If not used, require a weak pull-up (8.2- KΩ to 10 kΩ) to Vcc3_3.
R572 *1K/F_NC S_GPIO R270 10K/F CRB(V1.0)P28: it has 1K PU and 100 ohm on this net for validation purpose.
GNT3# 9
A SV_SET_UP R257 10K/F BMBUSY#:(Intel feedback) A

Follow CRB checklist, 1K is

for intel BIOS validation purpose.
A16 swap override Strap/Top-Block
Swap Override jumper
SV_SET_UP 1-X High = Strong (Default)
QUANTA
Low = A16 swap
override/Top-Block Title
COMPUTER
GNT3# Swap Override enabled IBEX PEAK-M 4/6
High = Default Size Document Number Rev
FM9 1A

Date: Wednesday, March 04, 2009 Sheet 10 of 64

5 4 3 2 1
 5 4 3 2 1

VCCCORE=1.524A max U42G POWER L66

IBEX PEAK-M (POWER) +1.05V_PCH AB24
AB26
VCCCORE[1] VCCADAC[1] AE50 +VCCA_DAC_1_2
HCB1608KF-181T15
+3.3V_RUN VCCADAC = 100mA max
VCCCORE[2]
AB28 VCCCORE[3] VCCADAC[2] AE52
C412 C424 AD26 C732 C731 C730
VCCCORE[4]

CRT
10U AD28 AF53
10 1U VCCCORE[5] VSSA_DAC[1] 0.01U 10U 0.1U
AF26 VCCCORE[6]

VCC CORE
805 AF28 AF51 6.3
VCCCORE[7] VSSA_DAC[2]
AF30
AF31
VCCCORE[8]
VCCCORE[9]
U42J POWER
AH26 VCCACLK = 100mA max
VCCCORE[10] L65 *10uH_NC +1.1V_LAN_VCCA_CLK VCCIO = 3.208A max
AH28 VCCCORE[11] +1.05V_PCH AP51 VCCACLK[1] VCCIO[5] V24 +1.05V_PCH
AH30 VCCCORE[12] VCCIO[6] V26
AH31 AH38 C726 C724 AP53 Y24 C433
D VCCCORE[13] VCCALVDS *10U_NC *1U_NC VCCACLK[2] VCCIO[7] 1U D
AJ30 VCCCORE[14] VCCIO[8] Y26
AJ31 AH39 VCCME = 1.998A max
VCCCORE[15] VSSA_LVDS VCCSUS3_3 = 0.163A max
+1.05V_PCH AF23 VCCLAN[1] VCCSUS3_3[1] V28 +3.3V_SUS
VCCSUS3_3[2] U28
VCCTX_LVDS[1] AP43 AF24 VCCLAN[2] VCCSUS3_3[3] U26
AP45 C415 U24 C451 C444
VCCTX_LVDS[2] 1U VCCSUS3_3[4]
AT46 P28

LVDS
VCCTX_LVDS[3] DCPSUSBYP VCCSUS3_3[5] 0.1U 0.1U
+1.05V_PCH AK24 VCCIO[24] VCCTX_LVDS[4] AT45 Y20 DCPSUSBYP VCCSUS3_3[6] P26
VCCAPLLEXP = 100mA max N28
C438 VCCSUS3_3[7]
VCCSUS3_3[8] N26
L64 *1uH_NC +1.05V_LAN_VCCAPLL_EXP BJ24 VCC3_3 = 0.357A max AD38 M28
+1.05V_PCH VCCAPLLEXP VCCME[1] VCCSUS3_3[9]
AB34 +3.3V_RUN 0.1U M26
VCCAPLLEXP: VCC3_3[2] VCCSUS3_3[10]
AD39 L28

USB
C718 C431 VCCME[2] VCCSUS3_3[11]
This pin can be left as no connect in AN20 VCCIO[25] VCC3_3[3] AB35 VCCSUS3_3[12] L26
On-Die VR enabled mode (default). *10U_NC AN22 AD41 J28

HVCMOS
VCCIO[26] 0.1U VCCME[3] VCCSUS3_3[13]
AN23 VCCIO[27] VCC3_3[4] AD35 VCCSUS3_3[14] J26
AN24 VCCIO[28] AF43 VCCME[4] VCCSUS3_3[15] H28
+1.05V_VCCIO AN26 H26
PJP20 VCCIO[29] VCCSUS3_3[16]
AN28 VCCIO[30] AF41 VCCME[5] VCCSUS3_3[17] G28
+1.05V_PCH 2 1 BJ26 VCCIO[31] VCCSUS3_3[18] G26
BJ28 VCCIO[32] AF42 VCCME[6] VCCSUS3_3[19] F28
C716 AT26 F26
POWER_JP 10U C715 C392 C391 C400 VCCIO[33] VCCSUS3_3[20]
AT28 VCCIO[34] V39 VCCME[7] VCCSUS3_3[21] E28

Clock and Miscellaneous

VCCIO = 3.208A max 10 1U 1U 1U 1U AU26 E26
805 VCCIO[35] VCCSUS3_3[22]
AU28 VCCIO[36] +1.05V_PCH V41 VCCME[8] VCCSUS3_3[23] C28
AV26 VCCVRM = 0.035A max C26
VCCIO[37] C436 C416 C434 VCCSUS3_3[24]
AV28 VCCIO[38] VCCVRM[2] AT24 +1.5VS_1.8VS V42 VCCME[9] VCCSUS3_3[25] B27
AW26 VCCIO[39] VCCSUS3_3[26] A28
AW28 VCCDMI = 0.061A max 22U 22U 1U Y39 A26
VCCIO[40] VCCME[10] VCCSUS3_3[27]

DMI
BA26 AT16 R232 0 +1.1V_VTT
VCCIO[41] VCCDMI[1]
BA28 VCCIO[42] Y41 VCCME[11] VCCSUS3_3[28] U23
BB26 AU16 R231 *0_NC +1.05V_PCH
C VCCIO[43] VCCDMI[2] VCCIO = 3.208A max C
BB28 VCCIO[44] Y42 VCCME[12] VCCIO[56] V23 +1.05V_PCH
BC26 C373
VCCIO[45]

PCI E*
BC28 1U F24 +V5REF_SUS R596 100
VCCIO[46] V5REF_SUS +5V_SUS
BD26 V5REF_SUS>1mA
VCCIO[47] C439 0.1U DCPRTC C756 D24 RB500V-40
BD28 VCCIO[48] V9 DCPRTC +3.3V_SUS
BE26 AM16 1U
VCCIO[49] VCCPNAND[1]
BE28 VCCIO[50] VCCPNAND[2] AK16
+3.3V_RUN BG26 AK20 VCCPNAND = 0.156A max K49 +V5REF R286 100 V5REF>1mA
VCCIO[51] VCCPNAND[3] V5REF +5V_RUN
BG28 AK19 AU24

PCI/GPIO/LPC
VCCIO[52] VCCPNAND[4] +NVRAM_VCCQ +1.5VS_1.8VS VCCVRM[3]
VCC3_3 = 0.357A max BH27 AK15 D16 RB500V-40 +3.3V_RUN
VCCIO[53] VCCPNAND[5] C410 VCCADPLLA = 0.072A max C446
VCCPNAND[6] AK13 VCC3_3[8] J38
AN30 AM12 BB51 1U
VCCIO[54] VCCPNAND[7] VCCADPLLA[1]

NAND / SPI
AN31 AM13 0.1U +1.1V_VCCADPLLA BB53 L38
C408 VCCIO[55] VCCPNAND[8] VCCADPLLB = 0.073A max VCCADPLLA[2] VCC3_3[9]
VCCPNAND[9] AM15
0.1U M36 +3.3V_RUN VCC3_3 = 0.357A max
+1.1V_VCCADPLLB VCC3_3[10]
AN35 VCC3_3[1] BD51 VCCADPLLB[1]
BD53 VCCADPLLB[2] VCC3_3[11] N36
VCCVRM = 0.035A max VCCIO = 3.208A max C445
VCCFDIPLL = 100mA max +1.5VS_1.8VS AT22 +1.05V_PCH AH23 P36 0.1U
VCCVRM[1] VCCIO[21] VCC3_3[12]
AJ35 VCCIO[22]
+1.05V_PCH L63 *1uH_NC +1.05V_VCCFDIPLL BJ18 AM8 VCCME3_3 = 0.085A max C422 C423 C426 AH35 U35
VCCFDIPLL VCCME3_3[1] VCCIO[23] VCC3_3[13]
VCCME3_3[2] AM9 +3.3V_RUN
FDI

+1.05V_PCH AM23 AP11 1U 1U 1U AF34

C720 VCCIO[1] VCCME3_3[3] C407 VCCIO[2]
VCCME3_3[4] AP9 VCC3_3[14] AD13
*10U_NC AH34
VCCIO = 3.208A max 0.1U VCCIO[3] C421
AF32 0.1U
IbexPeak-M_R1P0 VCCIO[4]
VCCSATAPLL[1] AK3
C442 0.1U DCPSST V12 AK1 +1.05V_VCCSATAPLL L35 *10uH_NC +1.05V_PCH
VCCME3_3: DCPSST VCCSATAPLL[2]
EDS(V1.0)P84:supply for the Intel Management Engine.This is a separate power plane C418 C413
that may or may not be powered in S3–S5 states. *1U_NC *10U_NC VCCIO = 3.208A max
B This plane must be on in S0 C443 0.1U DCPSUS Y22 B
and other times the Intel Management Engine is used. DCPSUS
VCCIO[9] AH22 +1.05V_PCH
VCCVRM = 0.035A max
+1.05V_PCH R228 *0_NC P18 AT20 +1.5VS_1.8VS C425
VCCSUS3_3 = 0.163A max VCCSUS3_3[29] VCCVRM[4] 1U
+1.5V_RUN R230 *0_NC +1.5VS_1.8VS +3.3V_SUS U19

SATA
VCCSUS3_3[30]

PCI/GPIO/LPC
VCCIO[10] AH19
R229 0 U20
C448 VCCSUS3_3[31]
+1.8V_RUN VCCIO[11] AD20
R243 0 +NVRAM_VCCQ 0.1U U22 VCCSUS3_3[32]
VCCIO[12] AF22
+3.3V_RUN R238 *0_NC
VCC3_3 = 0.357A max AD19
PCH EDS(V1.0) P84 VCCIO[13]
+3.3V_RUN V15 VCC3_3[5] VCCIO[14] AF20
+NVRAM_VCCQ: VCCIO[15] AF19
1.8 V supply for Dual Channel NAND interface. C430 V16 AH20
VCC3_3[6] VCCIO[16]
This power is supplied by core
0.1U Y16 AB19
well. If unused, this pin should VCC3_3[7] VCCIO[17]
VCCIO[18] AB20
be connected to Vcc3_3. AB22
V_CPU>1mA VCCIO[19]
VCCIO[20] AD22
+1.1V_VTT AT18 V_CPU_IO[1]
L36 10uH +1.1V_VCCADPLLA AA34 VCCME = 1.998A max

CPU
+1.05V_PCH VCCME[13] +1.05V_PCH
C394 C405 C404 Y34
VCCME[14]
AU18 V_CPU_IO[2] VCCME[15] Y35
+ C398 4.7U 0.1U 0.1U AA35
220U C397 VCCME[16]
3528 1U

RTC
+RTC_CELL A12 L30 0 R285 +3.3V_SUS VCCSUSHDA = 6mA max
VCCRTC VCCSUSHDA

HDA
C745 C741 C752
A IbexPeak-M_R1P0 C447 A
L32 10uH +1.1V_VCCADPLLB 1U 0.1U 0.1U 1U

VCCRTC = 2mA max

+ C388
220U C387
QUANTA
3528 1U

Title
COMPUTER
IBEX PEAK-M 5/6

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 11 of 64

5 4 3 2 1
 5 4 3 2 1

U42I
AY7 H49
IBEX PEAK-M (GND) B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260] H5
J24
VSS[161] VSS[261]
D B19 VSS[162] VSS[262] K11 D
B23 VSS[163] VSS[263] K43
B31 VSS[164] VSS[264] K47
B35 VSS[165] VSS[265] K7
B39 VSS[166] VSS[266] L14
B43 VSS[167] VSS[267] L18
B47 VSS[168] VSS[268] L2
B7 VSS[169] VSS[269] L22
BG12 VSS[170] VSS[270] L32
BB12 VSS[171] VSS[271] L36
U42H BB16 L40
VSS[172] VSS[272]
AB16 VSS[0] BB20 VSS[173] VSS[273] L52
BB24 VSS[174] VSS[274] M12
AA19 VSS[1] VSS[80] AK30 BB30 VSS[175] VSS[275] M16
AA20 VSS[2] VSS[81] AK31 BB34 VSS[176] VSS[276] M20
AA22 VSS[3] VSS[82] AK32 BB38 VSS[177] VSS[277] N38
AM19 VSS[4] VSS[83] AK34 BB42 VSS[178] VSS[278] M34
AA24 VSS[5] VSS[84] AK35 BB49 VSS[179] VSS[279] M38
AA26 VSS[6] VSS[85] AK38 BB5 VSS[180] VSS[280] M42
AA28 VSS[7] VSS[86] AK43 BC10 VSS[181] VSS[281] M46
AA30 VSS[8] VSS[87] AK46 BC14 VSS[182] VSS[282] M49
AA31 VSS[9] VSS[88] AK49 BC18 VSS[183] VSS[283] M5
AA32 VSS[10] VSS[89] AK5 BC2 VSS[184] VSS[284] M8
AB11 VSS[11] VSS[90] AK8 BC22 VSS[185] VSS[285] N24
AB15 VSS[12] VSS[91] AL2 BC32 VSS[186] VSS[286] P11
AB23 VSS[13] VSS[92] AL52 BC36 VSS[187] VSS[287] AD15
AB30 VSS[14] VSS[93] AM11 BC40 VSS[188] VSS[288] P22
AB31 VSS[15] VSS[94] BB44 BC44 VSS[189] VSS[289] P30
AB32 VSS[16] VSS[95] AD24 BC52 VSS[190] VSS[290] P32
AB39 VSS[17] VSS[96] AM20 BH9 VSS[191] VSS[291] P34
AB43 VSS[18] VSS[97] AM22 BD48 VSS[192] VSS[292] P42
AB47 VSS[19] VSS[98] AM24 BD49 VSS[193] VSS[293] P45
C C
AB5 VSS[20] VSS[99] AM26 BD5 VSS[194] VSS[294] P47
AB8 VSS[21] VSS[100] AM28 BE12 VSS[195] VSS[295] R2
AC2 VSS[22] VSS[101] BA42 BE16 VSS[196] VSS[296] R52
AC52 VSS[23] VSS[102] AM30 BE20 VSS[197] VSS[297] T12
AD11 VSS[24] VSS[103] AM31 BE24 VSS[198] VSS[298] T41
AD12 VSS[25] VSS[104] AM32 BE30 VSS[199] VSS[299] T46
AD16 VSS[26] VSS[105] AM34 BE34 VSS[200] VSS[300] T49
AD23 VSS[27] VSS[106] AM35 BE38 VSS[201] VSS[301] T5
AD30 VSS[28] VSS[107] AM38 BE42 VSS[202] VSS[302] T8
AD31 VSS[29] VSS[108] AM39 BE46 VSS[203] VSS[303] U30
AD32 VSS[30] VSS[109] AM42 BE48 VSS[204] VSS[304] U31
AD34 VSS[31] VSS[110] AU20 BE50 VSS[205] VSS[305] U32
AU22 VSS[32] VSS[111] AM46 BE6 VSS[206] VSS[306] U34
AD42 VSS[33] VSS[112] AV22 BE8 VSS[207] VSS[307] P38
AD46 VSS[34] VSS[113] AM49 BF3 VSS[208] VSS[308] V11
AD49 VSS[35] VSS[114] AM7 BF49 VSS[209] VSS[309] P16
AD7 VSS[36] VSS[115] AA50 BF51 VSS[210] VSS[310] V19
AE2 VSS[37] VSS[116] BB10 BG18 VSS[211] VSS[311] V20
AE4 VSS[38] VSS[117] AN32 BG24 VSS[212] VSS[312] V22
AF12 VSS[39] VSS[118] AN50 BG4 VSS[213] VSS[313] V30
Y13 VSS[40] VSS[119] AN52 BG50 VSS[214] VSS[314] V31
AH49 VSS[41] VSS[120] AP12 BH11 VSS[215] VSS[315] V32
AU4 VSS[42] VSS[121] AP42 BH15 VSS[216] VSS[316] V34
AF35 VSS[43] VSS[122] AP46 BH19 VSS[217] VSS[317] V35
AP13 VSS[44] VSS[123] AP49 BH23 VSS[218] VSS[318] V38
AN34 VSS[45] VSS[124] AP5 BH31 VSS[219] VSS[319] V43
AF45 VSS[46] VSS[125] AP8 BH35 VSS[220] VSS[320] V45
AF46 VSS[47] VSS[126] AR2 BH39 VSS[221] VSS[321] V46
AF49 VSS[48] VSS[127] AR52 BH43 VSS[222] VSS[322] V47
AF5 VSS[49] VSS[128] AT11 BH47 VSS[223] VSS[323] V49
AF8 VSS[50] VSS[129] BA12 BH7 VSS[224] VSS[324] V5
B AG2 AH48 C12 V7 B
VSS[51] VSS[130] VSS[225] VSS[325]
AG52 VSS[52] VSS[131] AT32 C50 VSS[226] VSS[326] V8
AH11 VSS[53] VSS[132] AT36 D51 VSS[227] VSS[327] W2
AH15 VSS[54] VSS[133] AT41 E12 VSS[228] VSS[328] W52
AH16 VSS[55] VSS[134] AT47 E16 VSS[229] VSS[329] Y11
AH24 VSS[56] VSS[135] AT7 E20 VSS[230] VSS[330] Y12
AH32 VSS[57] VSS[136] AV12 E24 VSS[231] VSS[331] Y15
AV18 VSS[58] VSS[137] AV16 E30 VSS[232] VSS[332] Y19
AH43 VSS[59] VSS[138] AV20 E34 VSS[233] VSS[333] Y23
AH47 VSS[60] VSS[139] AV24 E38 VSS[234] VSS[334] Y28
AH7 VSS[61] VSS[140] AV30 E42 VSS[235] VSS[335] Y30
AJ19 VSS[62] VSS[141] AV34 E46 VSS[236] VSS[336] Y31
AJ2 VSS[63] VSS[142] AV38 E48 VSS[237] VSS[337] Y32
AJ20 VSS[64] VSS[143] AV42 E6 VSS[238] VSS[338] Y38
AJ22 VSS[65] VSS[144] AV46 E8 VSS[239] VSS[339] Y43
AJ23 VSS[66] VSS[145] AV49 F49 VSS[240] VSS[340] Y46
AJ26 VSS[67] VSS[146] AV5 F5 VSS[241] VSS[341] P49
AJ28 VSS[68] VSS[147] AV8 G10 VSS[242] VSS[342] Y5
AJ32 VSS[69] VSS[148] AW14 G14 VSS[243] VSS[343] Y6
AJ34 VSS[70] VSS[149] AW18 G18 VSS[244] VSS[344] Y8
AT5 VSS[71] VSS[150] AW2 G2 VSS[245] VSS[345] P24
AJ4 VSS[72] VSS[151] BF9 G22 VSS[246] VSS[346] T43
AK12 VSS[73] VSS[152] AW32 G32 VSS[247] VSS[347] AD51
AM41 VSS[74] VSS[153] AW36 G36 VSS[248] VSS[348] AT8
AN19 VSS[75] VSS[154] AW40 G40 VSS[249] VSS[349] AD47
AK26 VSS[76] VSS[155] AW52 G44 VSS[250] VSS[350] Y47
AK22 VSS[77] VSS[156] AY11 G52 VSS[251] VSS[351] AT12
AK23 VSS[78] VSS[157] AY43 AF39 VSS[252] VSS[352] AM6
AK28 VSS[79] VSS[158] AY47 H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
IbexPeak-M_R1P0 H30 AK45
VSS[255] VSS[355]
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

QUANTA
IbexPeak-M_R1P0

Title
COMPUTER
IBEX PEAK-M 6/6

Size Document Number Rev

FM9 1A

Date: W ednesday, March 04, 2009 Sheet 12 of 64

5 4 3 2 1
 5 4 3 2 1

4 M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
98
97
96
95
92
JDIM1A

A0
A1
A2
A3
DQ0
DQ1
DQ2
DQ3
5
7
15
17
4
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ[63:0] 4
+1.5V_SUS

75
76
81
82
87
JDIM1B

VDD1
VDD2
VDD3
VDD4
VSS16
VSS17
VSS18
VSS19
44
48
49
54
55
11
M_A_A5 A4 DQ4 M_A_DQ5 VDD5 VSS20 +3.3V_RUN
91 A5 DQ5 6 88 VDD6 VSS21 60
M_A_A6 90 16 M_A_DQ6 93 61
M_A_A7 A6 DQ6 M_A_DQ7 VDD7 VSS22
86 A7 DQ7 18 94 VDD8 VSS23 65
D M_A_A8 89 21 M_A_DQ8 99 66 R510 *10K/F_NC PM_EXTTS#0 D
M_A_A9 A8 DQ8 M_A_DQ9 VDD9 VSS24
85 A9 DQ9 23 100 VDD10 VSS25 71
M_A_A10 107 33 M_A_DQ10 105 72

PC2100 DDR3 SDRAM SO-DIMM

M_A_A11 A10/AP DQ10 M_A_DQ11 VDD11 VSS26
84 A11 DQ11 35 106 VDD12 VSS27 127
M_A_A12 83 22 M_A_DQ12 111 128
M_A_A13 A12/BC# DQ12 M_A_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_A_A14 80 34 M_A_DQ14 117 134
M_A_A15 A14 DQ14 M_A_DQ15 VDD15 VSS30
78 36 118 138

PC2100 DDR3 SDRAM SO-DIMM

A15 DQ15 M_A_DQ16 VDD16 VSS31
DQ16 39 123 VDD17 VSS32 139
109 41 M_A_DQ17 124 144
4 M_A_BS0 BA0 DQ17 VDD18 VSS33 Intel is requesting that customers implement
108 51 M_A_DQ18 145
4 M_A_BS1 BA1 DQ18 VSS34 all methods (M1 and M2 and M3
79 53 M_A_DQ19 199 150
4 M_A_BS2 BA2 DQ19 +3.3V_RUN VDDSPD VSS35 described below) to generate and control
114 40 M_A_DQ20 151
4 M_A_CS0# S0# DQ20 VSS36 Reference voltage for Data/Strobe inputs
121 42 M_A_DQ21 77 155
4 M_A_CS1# S1# DQ21 NC1 VSS37 (VREFDQ) on Clarksfield based platforms.
101 50 M_A_DQ22 122 156
4 M_A_CLK0 CK0 DQ22 NC2 VSS38 for fine tuning of the VREFDQ levels to
103 52 M_A_DQ23 125 161
4 M_A_CLK0# CK0# DQ23 NCTEST VSS39 optimize the voltage and timing margins.
102 57 M_A_DQ24 162
4 M_A_CLK1 CK1 DQ24 VSS40
104 59 M_A_DQ25 PM_EXTTS#0 198 167 M1:Fixed voltage resistor divider or
4 M_A_CLK1# CK1# DQ25 3 PM_EXTTS#0 EVENT# VSS41
73 67 M_A_DQ26 30 168 DDR Voltage Regulator drives the Vref
4 M_A_CKE0 CKE0 DQ26 3,14 DDR3_DRAMRST# RESET# VSS42
74 69 M_A_DQ27 172 M2:A set of Digital potentiometers
4 M_A_CKE1 CKE1 DQ27 VSS43
115 56 M_A_DQ28 173 and op amps are added on the motherboard (one pair
4 M_A_CAS# CAS# DQ28 VSS44
110 58 M_A_DQ29 1 178 for each channel). This circuit is controlled by
4 M_A_RAS# RAS# DQ29 +SMDDR_VREF_DQ0 VREF_DQ VSS45
113 68 M_A_DQ30 126 179 SMBUS (SMB_CLK & SMB_DATA) on PCH.
4 M_A_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R177 10K/F_4 DIMM0_SA0 197 70 M_A_DQ31 184 M3:Intel investigating future processor
R178 10K/F_4 DIMM0_SA1 SA0 DQ31 M_A_DQ32 VSS47 VREF_DQ generation to replace M1 and M2. This
201 SA1 DQ32 129 VSS48 185
EC_SMBCLK0 202 131 M_A_DQ33 2 189 would require routing processor signal balls
14,15,38 EC_SMBCLK0 SCL DQ33 VSS1 VSS49 J17 and H17 to SO-DIMM connectors
EC_SMBDAT0 200 141 M_A_DQ34 3 190
14,15,38 EC_SMBDAT0 SDA DQ34 VSS2 VSS50

(204P)
M_A_DQ35 directly.
C DQ35 143 8 VSS3 VSS51 195 C
116 130 M_A_DQ36 9 196
4 M_A_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 M_A_DQ37 13
4 M_A_ODT1 ODT1 DQ37 VSS5
140 M_A_DQ38 14
4 M_A_DM[7:0] DQ38 VSS6
M_A_DM0 11 142 M_A_DQ39 19
M_A_DM1 DM0 DQ39 M_A_DQ40 VSS7
28 DM1 DQ40 147 20 VSS8
M_A_DM2
M_A_DM3
46
63
DM2
DM3
(204P) DQ41
DQ42
149
157
M_A_DQ41
M_A_DQ42
25
26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
M_A_DM4 136 159 M_A_DQ43 31 204
M_A_DM5 DM4 DQ43 M_A_DQ44 VSS11 VTT2 +5V_ALW
153 DM5 DQ44 146 32 VSS12
M_A_DM6 170 148 M_A_DQ45 37 G1
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS13 G1
187 DM7 DQ46 158 38 VSS14 G2 G2
160 M_A_DQ47 43
4 M_A_DQS[7:0] DQ47 VSS15
M_A_DQS0 12 163 M_A_DQ48 R213
M_A_DQS1 DQS0 DQ48 M_A_DQ49
29 DQS1 DQ49 165 100K
M_A_DQS2 47 175 M_A_DQ50 AS0A626-UARN-7F
M_A_DQS3 DQS2 DQ50 M_A_DQ51
64 DQS3 DQ51 177
M_A_DQS4 137 164 M_A_DQ52
DQS4 DQ52 PP_S4GT 14
M_A_DQS5 154 166 M_A_DQ53
DQS5 DQ53

3
M_A_DQS6 171 174 M_A_DQ54
M_A_DQS7 DQS6 DQ54 M_A_DQ55
4 M_A_DQS#[7:0] 188 DQS7 DQ55 176 7 SIO_SLP_S4# 2
M_A_DQS#0 10 181 M_A_DQ56 R214
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57 2N7002W-7-F 1M
27 183

1
M_A_DQS#2 DQS#1 DQ57 M_A_DQ58 Q41
45 DQS#2 DQ58 191
M_A_DQS#3 62 193 M_A_DQ59
M_A_DQS#4 DQS#3 DQ59 M_A_DQ60 +1.5V_SUS +3.3V_SUS
135 DQS#4 DQ60 180
M_A_DQS#5 152 182 M_A_DQ61 +3.3V_SUS
M_A_DQS#6 DQS#5 DQ61 M_A_DQ62
B 169 DQS#6 DQ62 192 B
M_A_DQS#7 186 194 M_A_DQ63
DQS#7 DQ63 C348
C349 R188 1U
AS0A626-UARN-7F 1U U18 12.1K/F603
603 10 +SMDDR_VREF_DQ0

5
10 1 6 U20
VCC RH OPA343NA/3K
RW 5 3 +
EC_SMBCLK0 3 1 R206 2.2 R204 *0_NC
14,15,38 EC_SMBCLK0 SCL
EC_SMBDAT0 4 2 4 -
14,15,38 EC_SMBDAT0 SDA GND R187 C358
12.1K/F *1U_NC R207

2
ISL90727WIE627Z-TK 603 10
10
+1.5V_SUS
Place these Caps near So-Dimm1. +SMDDR_VREF_DIMM

3
C619 C583 C623 C600 C171 C274 C273
10U 10U 10U 0.1U 0.1U 2.2U/6.3V/06032.2U/6.3V/0603 PP_S4GT 2N7002W-7-F
2
Q34
C229 + C615 C278

1
10U 330U
7343 0.1U
2.5
C190 C239 C607 C250 C251 C270
10U 10U 0.1U 0.1U 0.1U 0.1U
R22 0 +SMDDR_VREF_DIMM
C27 470P
A
+3.3V_RUN +DDR_VTTREF A
+0.75V_DDR_VTT
R26 *10K/F_NC
R20 *10K/F_NC
R25 0 R24
+1.5V_SUS
*0_NC +M_VREF_DQ_DIMM0
QUANTA
C323 C327 C339 C333 C340 C334 C354 C346 C344

2.2U/6.3V/06030.1U 1U 1U 1U 1U
10U
10
10U
10
10U
10
+SMDDR_VREF_DQ0
Title
COMPUTER
805 805 805 DDR3 DIMM-0

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 13 of 64

5 4 3 2 1
 5 4 3 2 1

4 M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
98
97
96
95
92
JDIM2A

A0
A1
A2
A3
DQ0
DQ1
DQ2
DQ3
5
7
15
17
4
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ[63:0] 4
+1.5V_SUS

75
76
81
82
87
JDIM2B

VDD1
VDD2
VDD3
VDD4
VSS16
VSS17
VSS18
VSS19
44
48
49
54
55
12
M_B_A5 A4 DQ4 M_B_DQ5 VDD5 VSS20
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
M_B_A7 A6 DQ6 M_B_DQ7 VDD7 VSS22
86 A7 DQ7 18 94 VDD8 VSS23 65
D M_B_A8 89 21 M_B_DQ8 99 66 D
M_B_A9 A8 DQ8 M_B_DQ9 VDD9 VSS24
85 A9 DQ9 23 100 VDD10 VSS25 71
M_B_A10 107 33 M_B_DQ10 105 72

PC2100 DDR3 SDRAM SO-DIMM

M_B_A11 A10/AP DQ10 M_B_DQ11 VDD11 VSS26
84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ12 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ14 117 134
M_B_A15 A14 DQ14 M_B_DQ15 VDD15 VSS30
78 36 118 138

PC2100 DDR3 SDRAM SO-DIMM

A15 DQ15 M_B_DQ16 VDD16 VSS31
DQ16 39 123 VDD17 VSS32 139
109 41 M_B_DQ17 124 144
4 M_B_BS0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ18 145
4 M_B_BS1 BA1 DQ18 VSS34
79 53 M_B_DQ19 199 150
4 M_B_BS2 BA2 DQ19 +3.3V_RUN VDDSPD VSS35
114 40 M_B_DQ20 151
4 M_B_CS0# S0# DQ20 VSS36
121 42 M_B_DQ21 77 155 +3.3V_RUN
4 M_B_CS1# S1# DQ21 NC1 VSS37
101 50 M_B_DQ22 122 156
4 M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ23 125 161
4 M_B_CLK0# CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ24 162 R175 PM_EXTTS#1
4 M_B_CLK1 CK1 DQ24 VSS40
104 59 M_B_DQ25 PM_EXTTS#1 198 167 *10K/F_NC
4 M_B_CLK1# CK1# DQ25 3 PM_EXTTS#1 EVENT# VSS41
73 67 M_B_DQ26 30 168
4 M_B_CKE0 CKE0 DQ26 3,13 DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ27 172
4 M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ28 173
4 M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ29 1 178
4 M_B_RAS# RAS# DQ29 +SMDDR_VREF_DQ1 VREF_DQ VSS45
113 68 M_B_DQ30 126 179
4 M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R161 10K/F_4 DIMM1_SA0 197 70 M_B_DQ31 184
R160 10K/F_4 DIMM1_SA1 SA0 DQ31 M_B_DQ32 VSS47
201 SA1 DQ32 129 VSS48 185
EC_SMBCLK0 202 131 M_B_DQ33 2 189
13,15,38 EC_SMBCLK0 SCL DQ33 VSS1 VSS49
EC_SMBDAT0 200 141 M_B_DQ34 3 190
+3.3V_RUN 13,15,38 EC_SMBDAT0 SDA DQ34 VSS2 VSS50

(204P)
C 143 M_B_DQ35 8 195 C
DQ35 M_B_DQ36 VSS3 VSS51
4 M_B_ODT0 116 ODT0 DQ36 130 9 VSS4 VSS52 196
120 132 M_B_DQ37 13
4 M_B_ODT1 ODT1 DQ37 VSS5
140 M_B_DQ38 14
4 M_B_DM[7:0] DQ38 VSS6
M_B_DM0 11 142 M_B_DQ39 19
M_B_DM1 DM0 DQ39 M_B_DQ40 VSS7
28 DM1 DQ40 147 20 VSS8
M_B_DM2
M_B_DM3
46
63
DM2
DM3
(204P) DQ41
DQ42
149
157
M_B_DQ41
M_B_DQ42
25
26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 31 204
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 170 148 M_B_DQ45 37 G1
M_B_DM7 DM6 DQ45 M_B_DQ46 VSS13 G1
187 DM7 DQ46 158 38 VSS14 G2 G2
160 M_B_DQ47 43
4 M_B_DQS[7:0] DQ47 VSS15
M_B_DQS0 12 163 M_B_DQ48
M_B_DQS1 DQS0 DQ48 M_B_DQ49
29 DQS1 DQ49 165
M_B_DQS2 47 175 M_B_DQ50 AS0A626-U2RN-7F
M_B_DQS3 DQS2 DQ50 M_B_DQ51
64 DQS3 DQ51 177
M_B_DQS4 137 164 M_B_DQ52
M_B_DQS5 DQS4 DQ52 M_B_DQ53
154 DQS5 DQ53 166
M_B_DQS6 171 174 M_B_DQ54
M_B_DQS7 DQS6 DQ54 M_B_DQ55
4 M_B_DQS#[7:0] 188 DQS7 DQ55 176
M_B_DQS#0 10 181 M_B_DQ56
M_B_DQS#1 DQS#0 DQ56 M_B_DQ57
27 DQS#1 DQ57 183
M_B_DQS#2 45 191 M_B_DQ58 +1.5V_SUS +3.3V_SUS
M_B_DQS#3 DQS#2 DQ58 M_B_DQ59 +3.3V_SUS
62 DQS#3 DQ59 193
M_B_DQS#4 135 180 M_B_DQ60
M_B_DQS#5 DQS#4 DQ60 M_B_DQ61
152 DQS#5 DQ61 182
B M_B_DQS#6 169 192 M_B_DQ62 C350 B
M_B_DQS#7 DQS#6 DQ62 M_B_DQ63 C351 R190 1U
186 DQS#7 DQ63 194
1U U19 12.1K/F603 +SMDDR_VREF_DQ1
603 10

5
AS0A626-U2RN-7F 10 1 6 U21
VCC RH OPA343NA/3K
RW 5 3 +
EC_SMBCLK0 3 1 R205 2.2 R202 *0_NC
13,15,38 EC_SMBCLK0 SCL
EC_SMBDAT0 4 2 4 -
13,15,38 EC_SMBDAT0 SDA GND R189 C357
12.1K/F *1U_NC R208

2
ISL90728WIE627Z-TK 603 10
10

3
+1.5V_SUS 2N7002W-7-F
2
Place these Caps near So-Dimm2. +SMDDR_VREF_DIMM
13 PP_S4GT Q36
C240 C246 C143 C210 C213 C276 C275

1
10U 10U 10U 0.1U 0.1U 2.2U/6.3V/06032.2U/6.3V/0603

C247 + C565 C272

10U 330U
7343 0.1U
2.5
C236 C223 C217 C203 C219 C271
10U 10U 0.1U 0.1U 0.1U 0.1U

A A
+3.3V_RUN +0.75V_DDR_VTT
R27 0 R28 *0_NC
+SMDDR_VREF_DIMM +M_VREF_DQ_DIMM1

+SMDDR_VREF_DQ1
QUANTA
C324 C330 C336 C326 C325 C341 C318 C347 C317

2.2U/6.3V/06030.1U 1U 1U 1U 1U
10U
10
10U
10
10U
10 Title
COMPUTER
805 805 805 DDR3 DIMM-1

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 14 of 64

5 4 3 2 1
 5 4 3 2 1

D D

Realtek: 0.1uFx6pcs, 22uFx1pcs Place within 0.5" of CLKGEN

+3.3V_RUN IDT: 0.1uFx5pcs, 10uFx1pcs
U27
L40 BLM21PG600SN1D
40mil +3.3V_CLK_VDD 1
805 VDD_USB CLK_BUF_BCLK_P
5 VDD_LCD CPU-0 23 CLK_BUF_BCLK_P 9
17 22 CLK_BUF_BCLK_N
VDD_SRC CPU-0# CLK_BUF_BCLK_N 9
C472 C469 C461 C465 C453 C460 +VDDIO_CLK 24 VDD_CPU
29 20
10U 0.1U 0.1U 0.1U 0.1U 0.1U 15
18
VDD_REF
VDD_SRC_IO
VDD_CPU_IO
CK505 CPU-1
CPU-1# 19

9 VSS_SATA
QFN32 DOT96T_LPR 3 CLK_BUF_DREFCLK
CLK_BUF_DREFCLK 9
0.1uF near the every power pin. 2 4 CLK_BUF_DREFCLK#
VSS_USB DOT96C_LPR CLK_BUF_DREFCLK# 9
8 VSS_LCD
12 13 CLK_BUF_PCIE_3GPLL
VSS_SRC SRC-1 CLK_BUF_PCIE_3GPLL 9
21 14 CLK_BUF_PCIE_3GPLL#
VSS_CPU SRC-1# CLK_BUF_PCIE_3GPLL# 9
26
8 VSS_REF
SATA
SATA#
10
11
CLK_BUF_DREFSSCLK
CLK_BUF_DREFSSCLK#
CLK_BUF_DREFSSCLK 9
CLK_BUF_DREFSSCLK# 9
C
+3.3V_RUN C
R335 10K 16 6 CLK_VGA_27M_R R314 33
CPU_STOP# 27MHz_nonSS CLK_VGA_27M 17
25 7 CLK_VGA_27M_SS_R R327 33
42 CK_PWRGD_R CK_PWRGD/PD#_3.3 27MHz_SS CLK_VGA_27M_SS 17
CLK_ICH_14M R299 33 CPU_SEL 30
9 CLK_ICH_14M REF_0/CPU_SEL

Place the 33 ohm XTAL_OUT 27

XTAL_IN XOUT
resistors close to the CK 505 28 XIN
EC_SMBDAT0 31 33
13,14,38 EC_SMBDAT0 SDATA GND
EC_SMBCLK0 32
13,14,38 EC_SMBCLK0 SCLK

SLG8SP585VTR
Realtek: 0.1uFx3pcs, 22uFx1pcs
IDT: 0.1uFx2pcs, 10uFx1pcs

+3.3V_RUN +VDDIO_CLK

Add capacitor pads for improving WWAN.

L41 BLM21PG600SN1D
R346 *0_NC 40mil
C441
Y3 805
B CLK_ICH_14M XTAL_IN 1 2 XTAL_OUT +1.05V_PCH C478 C475 C467 B

14.318MHZ 10U 0.1U 0.1U

*27P_NC

2
C455 R353 0
50 C454 33P
33P HP: 10u x2pcs

1
50 50

SLG,IDT: +1.05V Place each 0.1uF cap as close as

possible to each VDD IO pin. Place
Realtek: +3.3V the 10uF caps on the VDD_IO plane.

+VDDIO_CLK:
SLG date sheet (V0.2) P15: Min 1.05V,Max3.465V.
Realtek date sheet(V1.2) P11: Min 1.05V,Max 3.3V.
7 +3.3V_RUN IDT date sheet(V0.7) P10: Min 0.9975V,Max 3.465V.
CPU_SEL:
2

PIN 30 CPU_0 CPU_1 SLG date sheet (V0.2) P15:

R300
*4.7K_NC
High Voltage: Min 0.7V, Max 1.5V.
0(default) 133MHz 133MHz Low Voltage: Min Vss-0.3V, Max 0.35V.
Realtek date sheet(V1.2) P11:
1

A CPU_SEL A
High Voltage: Min 0.7V, Max 1.5V.
1(0.7V-1.5V) 100MHz 100MHz
QUANTA
2

Low Voltage: Min Vss-0.3V, Max 0.35V.

R301 IDT date sheet(V0.7) P10:
C452
4.7K
*10P/50V_NC
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V. Title
COMPUTER
1

EMI Capacitor Clock Generator

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 15 of 64

5 4 3 2 1
 5 4 3 2 1

U32A
PART 1 OF 10
3 PCIE_MTX_GRX_P[0..15] 3 PCIE_MRX_GTX_P[0..15]
3 PCIE_MTX_GRX_N[0..15] 3 PCIE_MRX_GTX_N[0..15]

PCIE_MTX_GRX_P0 AF30 AH30 PCIE_MRX_GTX_C_P0

PCIE_MTX_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_MRX_GTX_C_N0 PCIE_MRX_GTX_P0 0.1U PCIE_MRX_GTX_C_P0
AE31 PCIE_RX0N PCIE_TX0N AG31 2 1 C87 16

PCIE_MRX_GTX_P1 0.1U 2 1 C94 16 PCIE_MRX_GTX_C_P1

D PCIE_MTX_GRX_P1 AE29 AG29 PCIE_MRX_GTX_C_P1 D
PCIE_MTX_GRX_N1 PCIE_RX1P PCIE_TX1P PCIE_MRX_GTX_C_N1 PCIE_MRX_GTX_P2 0.1U PCIE_MRX_GTX_C_P2
AD28 PCIE_RX1N PCIE_TX1N AF28 2 1 C92 16

PCIE_MRX_GTX_P3 0.1U 2 1 C88 16 PCIE_MRX_GTX_C_P3

PCIE_MTX_GRX_P2 AD30 AF27 PCIE_MRX_GTX_C_P2
PCIE_MTX_GRX_N2 PCIE_RX2P PCIE_TX2P PCIE_MRX_GTX_C_N2 PCIE_MRX_GTX_P4 0.1U PCIE_MRX_GTX_C_P4
AC31 PCIE_RX2N PCIE_TX2N AF26 2 1 C100 16

PCIE_MRX_GTX_P5 0.1U 2 1 C103 16 PCIE_MRX_GTX_C_P5

PCIE_MTX_GRX_P3 AC29 AD27 PCIE_MRX_GTX_C_P3
PCIE_MTX_GRX_N3 PCIE_RX3P PCIE_TX3P PCIE_MRX_GTX_C_N3 PCIE_MRX_GTX_P6 0.1U PCIE_MRX_GTX_C_P6
AB28 PCIE_RX3N PCIE_TX3N AD26 2 1 C108 16

PCI-EXPRESS INTERFACE
PCIE_MRX_GTX_P7 0.1U 2 1 C115 16 PCIE_MRX_GTX_C_P7
PCIE_MTX_GRX_P4 AB30 AC25 PCIE_MRX_GTX_C_P4
PCIE_MTX_GRX_N4 PCIE_RX4P PCIE_TX4P PCIE_MRX_GTX_C_N4 PCIE_MRX_GTX_P8 0.1U PCIE_MRX_GTX_C_P8
AA31 PCIE_RX4N PCIE_TX4N AB25 2 1 C131 16
PCIE_MRX_GTX_P9 0.1U 2 1 C148 16 PCIE_MRX_GTX_C_P9
PCIE_MTX_GRX_P5 AA29 Y23 PCIE_MRX_GTX_C_P5
PCIE_MTX_GRX_N5 PCIE_RX5P PCIE_TX5P PCIE_MRX_GTX_C_N5 PCIE_MRX_GTX_P10 0.1U PCIE_MRX_GTX_C_P10
Y28 PCIE_RX5N PCIE_TX5N Y24 2 1 C136 16
PCIE_MRX_GTX_P11 0.1U 2 1 C167 16 PCIE_MRX_GTX_C_P11
PCIE_MTX_GRX_P6 Y30 AB27 PCIE_MRX_GTX_C_P6
PCIE_MTX_GRX_N6 PCIE_RX6P PCIE_TX6P PCIE_MRX_GTX_C_N6 PCIE_MRX_GTX_P12 0.1U PCIE_MRX_GTX_C_P12
W 31 PCIE_RX6N PCIE_TX6N AB26 2 1 C140 16
PCIE_MRX_GTX_P13 0.1U 2 1 C180 16 PCIE_MRX_GTX_C_P13
PCIE_MTX_GRX_P7 W 29 Y27 PCIE_MRX_GTX_C_P7
C
PCIE_MTX_GRX_N7 PCIE_RX7P PCIE_TX7P PCIE_MRX_GTX_C_N7 PCIE_MRX_GTX_P14 0.1U PCIE_MRX_GTX_C_P14 C
V28 PCIE_RX7N PCIE_TX7N Y26 2 1 C150 16
PCIE_MRX_GTX_P15 0.1U 2 1 C168 16 PCIE_MRX_GTX_C_P15
PCIE_MTX_GRX_P8 V30 W 24 PCIE_MRX_GTX_C_P8
PCIE_MTX_GRX_N8 PCIE_RX8P PCIE_TX8P PCIE_MRX_GTX_C_N8
U31 PCIE_RX8N PCIE_TX8N W 23

PCIE_MRX_GTX_N0 0.1U 2 1 C90 16 PCIE_MRX_GTX_C_N0

PCIE_MTX_GRX_P9 U29 V27 PCIE_MRX_GTX_C_P9
PCIE_MTX_GRX_N9 PCIE_RX9P PCIE_TX9P PCIE_MRX_GTX_C_N9 PCIE_MRX_GTX_N1 0.1U PCIE_MRX_GTX_C_N1
T28 PCIE_RX9N PCIE_TX9N U26 2 1 C96 16

PCIE_MRX_GTX_N2 0.1U 2 1 C95 16 PCIE_MRX_GTX_C_N2

PCIE_MTX_GRX_P10 T30 U24 PCIE_MRX_GTX_C_P10
PCIE_MTX_GRX_N10 PCIE_RX10P PCIE_TX10P PCIE_MRX_GTX_C_N10 PCIE_MRX_GTX_N3 0.1U PCIE_MRX_GTX_C_N3
R31 PCIE_RX10N PCIE_TX10N U23 2 1 C91 16

PCIE_MRX_GTX_N4 0.1U 2 1 C105 16 PCIE_MRX_GTX_C_N4

PCIE_MTX_GRX_P11 R29 T26 PCIE_MRX_GTX_C_P11
PCIE_MTX_GRX_N11 PCIE_RX11P PCIE_TX11P PCIE_MRX_GTX_C_N11 PCIE_MRX_GTX_N5 0.1U PCIE_MRX_GTX_C_N5
P28 PCIE_RX11N PCIE_TX11N T27 2 1 C107 16
PCIE_MRX_GTX_N6 0.1U 2 1 C114 16 PCIE_MRX_GTX_C_N6
PCIE_MTX_GRX_P12 P30 T24 PCIE_MRX_GTX_C_P12
PCIE_MTX_GRX_N12 PCIE_RX12P PCIE_TX12P PCIE_MRX_GTX_C_N12 PCIE_MRX_GTX_N7 0.1U PCIE_MRX_GTX_C_N7
N31 PCIE_RX12N PCIE_TX12N T23 2 1 C128 16
PCIE_MRX_GTX_N8 0.1U 2 1 C118 16 PCIE_MRX_GTX_C_N8
PCIE_MTX_GRX_P13 N29 P27 PCIE_MRX_GTX_C_P13
PCIE_MTX_GRX_N13 PCIE_RX13P PCIE_TX13P PCIE_MRX_GTX_C_N13 PCIE_MRX_GTX_N9 0.1U PCIE_MRX_GTX_C_N9
B M28 PCIE_RX13N PCIE_TX13N P26 2 1 C159 16 B

PCIE_MRX_GTX_N10 0.1U 2 1 C142 16 PCIE_MRX_GTX_C_N10

PCIE_MTX_GRX_P14 M30 P24 PCIE_MRX_GTX_C_P14
PCIE_MTX_GRX_N14 PCIE_RX14P PCIE_TX14P PCIE_MRX_GTX_C_N14 PCIE_MRX_GTX_N11 0.1U PCIE_MRX_GTX_C_N11
L31 PCIE_RX14N PCIE_TX14N P23 2 1 C181 16
PCIE_MRX_GTX_N12 0.1U 2 1 C147 16 PCIE_MRX_GTX_C_N12
PCIE_MTX_GRX_P15 L29 M27 PCIE_MRX_GTX_C_P15
PCIE_MTX_GRX_N15 PCIE_RX15P PCIE_TX15P PCIE_MRX_GTX_C_N15 (1.1V) PCIE_MRX_GTX_N13 0.1U PCIE_MRX_GTX_C_N13
K30 PCIE_RX15N PCIE_TX15N N26 2 1 C166 16

100 MHz (+/-300 ppm) input frequency, 0-0.7 V single-ended swing. +PCIE_VDDC PCIE_MRX_GTX_N14 0.1U 2 1 C160 16 PCIE_MRX_GTX_C_N14
clock must be provided less than 400ns
after CLKREQ# is asserted PCIE_MRX_GTX_N15 0.1U 2 1 C182 16 PCIE_MRX_GTX_C_N15

AK30 AA22 PCIE_CALRN 2.0K R62

9 CLK_PCIE_VGA PCIE_REFCLKP PCIE_CALRN
9 CLK_PCIE_VGA# AK32 PCIE_REFCLKN
Y22 PCIE_CALRP 1.27K R51
PCIE_CALRP

AL27 PERSTB
3,9,26,28,29,31,32,41 PLTRST#

M92-S2/M92-XT
A A

QUANTA
Title
COMPUTER
M92-S2 XT AJ072800T04 100-CG1675(216-0728004)
VGA-M92-XT (PCIe)
M92-S2 AJ072800T03 100-CG1643(216-0728003)
Size Document Number Rev
FM9 1A

Date: Wednesday, March 04, 2009 Sheet 16 of 64

5 4 3 2 1
 5 4 3 2 1

MEMORY APERTURE SIZE SELECT

R32 0 603
MEMORY CFG3 CFG2 CFG1 CFG0 Q10
SIZE GPIO9 GPIO13 GPIO12 GPIO11
*SI2303BDS-T1-E3_NC U32B VGA_BLU
PART 2 OF 10 VGA_GRN
128MB 0 0 0 +3.3V_DELAY 3 1 +3.3V_RUN VGA_RED
DIS only

1
For Park S3: DVP PORT DAC1
256MB 0 0 1 R35 R431 1 2 *0_NC U1 AM26 R398 R399 R400 Layout Note:
Install All components in this Box

2
DVPCLK R 150/F 150/F 150/F
*100K_NC AK26 Place 150 ohm
L86,C960,C905,C898,L84, RB
AC7
C959,C891,C890,R142, DVPCNTL_0 termination resistors
64MB 0 1 0 Y2

2
DVPCNTL_1 close to ATI CHIP.
R143,R144,R145 U5 AL25
DVPCNTL_2 G
AJ25
R423 1 GB
D 512MB 1 0 0 2 *0_NC AA1 D
DVPCNTL_MVP_0
DPC_VDD18#1 and DPC_VDD18#2 are for Y4
DVPCNTL_MVP_1
AH24
Future ASIC B
AG25

3
+3.3V_DELAY R34 *75K/F_NC BB
For M92-S2: DO NOT Install any Component
2 Q9 Y7
R436 1 2 10K RAM_CFG0
19,29,50 GFX_ON
*2N7002W-7-F_NC
in this Box. V2
DVPDATA_0
AH26 +3.3V_DELAY
R435 1 DVPDATA_1 HSYNC
2 *10K_NC RAM_CFG1 C38 C47 Y8 AJ27

1
R437 1 DVPDATA_2 VSYNC
2 *10K_NC RAM_CFG2 *0.1U_NC *0.1U_NC V4
25 +1.8V_RUN_GFX DVPDATA_3 +1.8V_RUN_GFX
AB7
603 10 R427 1 DVPDATA_4
2 *0_NC W1
L52 *BLM15BD121SN1D_NC +DPC_VDD18 DVPDATA_5 AVDD=70mA max
AB8 AG24
OPTIONAL RC NETWORK DVPDATA_6 AVDD
W3
TO FINE TUNE DVPDATA_7 C101 R425 R424
AB9
POWER SEQUENCING C545 DVPDATA_8 *0.1U_NC 10K 10K
W5
*1U_NC DVPDATA_9
AC6
DVPDATA_10 HPD1
W6
DVPDATA_11
AD7
+PCIE_VDDC DVPDATA_12
GPIO Straps DESCRIPTION OF DEFAULT SETTINGS FM9 AA3 AE22

3
DVPDATA_13 AVSSQ
setting AC8
table L23 *BLM15BD121SN1D_NC AA5
DVPDATA_14
2
DVPDATA_15 +1.8V_RUN_GFX
GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable) AE8
R421 1 DVPDATA_16
GPIO0 0: 50% Tx output swing for mobile mode 0 2 *0_NC AA6 Q60

1
C111 DVPDATA_17 MMST3904-7-F
1: full Tx output swing (Default setting for Desktop) AE9 AE23

3
*1U_NC DVPDATA_18 VDD1DI VDD1DI=45mA max
AB4
RAM_TYPE_CFG0 DVPDATA_19
GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable) AD9
RAM_TYPE_CFG1 DVPDATA_20
GPIO1 0: Tx de-emphasis disabled for mobile mode 0 AB2
DVPDATA_21
2 HDMI_DET 24
1: Tx de-emphasis enabled (Default setting for Desktop) RAM_TYPE_CFG2 AC10 C112

1
+DPC_VDD18 R407 1 DVPDATA_22 *0.1U_NC
2 *0_NC AC5
DVPDATA_23 Q59 R420
GPIO(2) - BIF_GEN2_EN (5.0 GT/s Enable)

1
GPIO2 0 : Default. (Driver Controlled Gen2) 0 AD23 DTC114TUAT106 100K
VSS1DI
1 : Strap Controlled Gen2
As M82 design, for GPIO use

2
R408 *0_reserve
GPIO3 ATI reserved configuration straps. 0 OSC_SPREAD 1 2 I/O
C C
GPIO4 GPIO0 U6 AD22 RSET R49 499R
ATI reserved configuration straps. 0 GPIO1 GPIO_0 RSET
U10
R416 *0_NC GPIO2 GPIO_1
GPIO_5_AC_BATT T10
CLK_VGA_27M_SSIN_R GPIO3 GPIO_2
GPIO5 0 : Battery saving mode = 0.0 V 0 15 CLK_VGA_27M_SS 1 2 U8
GPIO_3_SMBDATA
1 : AC (Performance mode) = 3.3 V GPIO4 U7

1
GPIO5 GPIO_4_SMBCLK DAC2
T9
R409 GPIO_5_AC_BATT VGA_RED
0 T8 AM12 VGA_RED 25
GPIO6 ATI Internal use only
*10K_NC
50 GFX_CORE_CNTRL2
T7
GPIO_6_TACH R2
AK12
29 PANEL_BKEN GPIO_7_BLON R2B
R45 0 HDMI_HD_EN P10
R417 100/F GPIO_8_ROMSO
15 CLK_VGA_27M 1 2 T45 PAD P4

2
GPIO_9_ROMSI VGA_GRN
T46 PAD P2 AL11 VGA_GRN 25
+3.3V_DELAY R410 120/F RAM_CFG0 GPIO_10_ROMSCK G2
N6 AJ11
RAM_CFG1 GPIO_11 G2B
N5
R430 *10K_NC GPIO0 RAM_CFG2 GPIO_12
1 2 N3
R426 *10K_NC GPIO1 OSC_OUT GPIO_13 VGA_BLU
1 2 1 2 XTALIN 21 T42 PAD Y9 AK10 VGA_BLU 25
R61 *10K_NC GPIO2 R404 *182R_reserve GPIO_14_HPD2 B2
1 2 50 GFX_CORE_CNTRL0 N1 AL9

2
R429 *10K_NC GPIO3 CLK_VGA_27M_SSIN_R GPIO_15_PWRCNTL_0 B2B
1 2 M4
R428 *10K_NC GPIO4 R406 R46 *221/F_reserve R433 1 *0_NC 2 GPIO_16_SSIN
1 2 19 THERMAL_INT# R6
R68 *10K_NC GPIO5 GPIO_17_THERMAL_INT
1 2 *1M_reserve T8 PAD W10
Y4 TEMP_FAIL GPIO_18_HPD3 VGAHSYNC
M2 AL13 VGAHSYNC 25
GPIO_19_CTF H2SYNC VGAVSYNC
1 2 1 2 XTALOUT 21 50 GFX_CORE_CNTRL1 P8 AJ13 VGAVSYNC 25

1
R392 *0_reserve GPIO_20_PWRCNTL_1 V2SYNC
18 BB_ENA P7
R55 10K HDMI_HD_EN GPIO_21_BB_EN
1 2 *27MHZ_reserve T10 PAD N8
R438 *10K_NC TEMP_FAIL GFX_CLKREQ# GPIO_22_ROMCSB
1 2 N7
R432 10K GFX_CLKREQ# R439 2 GPIO_23_CLKREQB
1 2 1 1K L6
R384 10K VGAVSYNC JTAG_TRSTB
1 2 T49 PAD L5 AH12
R383 10K VGAHSYNC R394 *1M_reserve JTAG_TDI C
1 2 T48 PAD L3
1

JTAG_TCK
T47 PAD L1 AM10
C535 C534 JTAG_TMS Y
T13 PAD K4
R403 1 JTAG_TDO
2 *10K_NC VGAVSYNC *12P/50V_reserve *12P/50V_reserve AJ9
2

R402 1 VGAHSYNC COMP

2 *10K_NC
R440 1 2 10K TEMP_FAIL 50 50 +3.3V_DELAY

AB13 AE20 +A2VDD L49 BLM15BD121SN1D

T5 PAD GENERICA A2VDD
B
T44 PAD W8 A2VDD=65mA max B
GENERICB
T41 PAD W9
GENERICC
T43 PAD W7
+3.3V_RUN GENERICD C548 C537 C530 C521
Spread Spectrum T2 PAD AD10
GENERICE_HPD4 0.01U 0.1U 1U 4.7U/6.3V
If U4, the discrete spread spectrum chip
HPD1 AC14 +1.8V_RUN_GFX
is not used, then pop R48 in order to +1.8V_RUN_GFX HPD1
pull-down BXTALOUT for EMI reasons. AE17 +A2VDDQ L48 BLM15BD121SN1D
R390 R391 A2VDDQ A2VDDQ=1mA max
2 1
*10K_reserve *10K_reserve R382 499/F VREFG AC16
R393 *10K_reserve VREFG
U31 C528 C522
1 2
OSC_OUT 1 8 R396 249/F 0.1U 1U
XIN/CLKIN XOUT
2 7 +3VL L54 +3.3V_RUN AE19
R411 *0_reserve VSS VDD *BLM11A05S_reserve C527 0.1U A2VSSQ
1 2 3 6 C531 C542 RESERVED
1

SO PD# *10U_reserve *0.1U_reserve

OSC_SPREAD 4 5 805 N10 Keep A2VSSQ away from noisy ground.
SSCLK REFCLK T9 PAD NC_PWRGOOD
10 10
2

AB22 +1.8V_RUN_GFX
*P1819GF-08SR_reserve T7 PAD RSVD#8
T6 PAD AC22
RSVD#9 +VDD2DI L51 BLM15BD121SN1D
AD19
VDD2DI VDD2DI=40mA max
S0

-1.75% (DOWN) 0 L9 C547 C536 C529

T14 PAD NC#1 0.1U
N9 0.01U 1U
T11 PAD NC#2
+1.8V_RUN_GFX AB16 AC19
T3 PAD RSVD#3 VSS2DI
24 ENVDD 1 2 AB12
R395 0 RSVD#2
24 BIA_PWM AB11
R56 1 RSVD#1
2 10K RAM_TYPE_CFG0 Place very close to ASIC balls.
R422 1 2 *10K_NC RAM_TYPE_CFG1 R50
A A
R419 1 2 *10K_NC RAM_TYPE_CFG2 10K R42 1K
1 2 AF24 AG13 R2SET R401 715
TESTEN R2SET

M92-S2/M92-XT

Memory Straps
RAM_TYPE
_CFG2
RAM_TYPE
_CFG1
RAM_TYPE Quanta PN
_CFG0
Quanta PN
Vendor PN 31 level PN QUANTA
(QuantaBuy) (WinBuy)
800MHz
AKD5LGGT502 K4W1G1646E-HC12 Title
COMPUTER
512MB(64M*16) Samsung 0 0 1
VGA-M92-XT (PCIe)
800MHz
0 1 0 AKD5LZGTW00 H5TQ1G63BFR-12C Size Document Number Rev
512MB(64M*16) Hynix FM9 1A

Date: Wednesday, March 04, 2009 Sheet 17 of 64

5 4 3 2 1
 5 4 3 2 1

+1.5V_RUN
layout note: close to VDDR1#[1:17] VDDR1#[1..17]=2A max
(PCIE_VDDC 1.0~1.1V +/- 5%@ 2A )
L12 BLM18PG121SN1D (1.1V)
C173 C207 C204 C191 C192 C198 C188 C205 C193 +1.1V_GFX_PCIE +PCIE_VDDC
0.01U 0.01U 0.01U 0.01U 0.01U 0.1U 0.1U 0.1U 0.1U

1
C40 C68 C54
10U 1U 0.1U
603 402

2
6.3 6.3 16
+1.8V_RUN_GFX
C201 C185 C199 C179 C200 C186 PCIE_VDDR#[1..8]=500mA max

1
1U 1U 1U 1U 1U 0.1U C41 C45 C79
10U 1U 0.1U
603 402

2
6.3 6.3 16
D C99 C119 C135 C132 C102 D
1U 0.1U 1U 0.01U 10U
U32D
+1.5V_RUN PART 4 OF 10
+1.5V_RUN

C254 C255 C158

H13
H16
VDDR1#1 POWER AB23 (1.1V)
10U 10U 10U VDDR1#2 PCIE_VDDR#1
H19 VDDR1#3 PCIE_VDDR#2 AC23
J10 AD24 +PCIE_VDDC
VDDR1#4 PCIE_VDDR#3 PCIE_VDDC#[1..12]=2A max
J23 AE24
VDDR1#5 PCIE_VDDR#4
J24 AE25
VDDR1#6 PCIE_VDDR#5
J9 AE26
VDDR1#7 PCIE_VDDR#6
K10 AF25
VDDR1#8 PCIE_VDDR#7
K23 AG26
VDDR1#9 PCIE_VDDR#8 C85 C73 C59 C176 C50 C86 C177 C42
K24 VDDR1#10
K9 1U 1U 1U 1U 1U 1U 1U 10U
VDDR1#11
L11 VDDR1#12
L12 VDDR1#13
L13 VDDR1#14
L20 L23
VDDR1#15 PCIE_VDDC#1
L21 L24
VDDR1#16 PCIE_VDDC#2
L22 L25
+1.8V_RUN_GFX VDDR1#17 PCIE_VDDC#3 U32E
L26
VDD_CT#[1..4]=110mA max PCIE_VDDC#4 PART 5 OF 10
M22
PCIE_VDDC#5
N22
L17 +VDD_CT PCIE_VDDC#6
AA20 N23
VDD_CT#1 PCIE_VDDC#7
BLM15BD121SN1D
AA21
AB20
VDD_CT#2 PCIE_VDDC#8
N24
R22 AA27
GND F18
C46 C49 C58 C72 C83 VDD_CT#3 PCIE_VDDC#9 PCIE_VSS#1 GND#33
AB21 T22 AB24 F2
10U 0.1U 1U 1U 0.1U VDD_CT#4 PCIE_VDDC#10 PCIE_VSS#2 GND#34
PCIE_VDDC#11 U22 AB32 PCIE_VSS#3 GND#35 F20
PCIE_VDDC#12 V22 AC24 PCIE_VSS#4 GND#36 F22
(0.9~1.2V) AC26 PCIE_VSS#5 GND#37 F24
AC27 F26
+3.3V_DELAY VDDR3#[1..4]=50mA max +VCC_GFX_CORE PCIE_VSS#6 GND#38
AD25 F6
PCIE_VSS#7 GND#39
AD32 F8
VDDC#[2..3]=120mA max PCIE_VSS#8 GND#40
AA17 AA15 AE27 G10
VDDR3#1 VDDC#1 PCIE_VSS#9 GND#41
C AA18 M11 +BBP AF32 G27 C
VDDR3#2 VDDC#2 PCIE_VSS#10 GND#42
AB17 M12 AG27 G31
C113 C556 C577 C125 VDDR3#3 VDDC#3 PCIE_VSS#11 GND#43
AB18 N15 AH32 G8
1U 1U 0.1U 0.1U VDDR3#4 VDDC#4 PCIE_VSS#12 GND#44
VDDC#5 N17 K28 PCIE_VSS#13 GND#45 H14
R13 C172 C163 K32 H17
R53 2 VDDC#6 PCIE_VSS#14 GND#46
1*150/F_NC VDDC#7 R16 0.1U 1U L27 PCIE_VSS#15 GND#47 H2
AA11 VDDR4#1 VDDC#8 R18 M32 PCIE_VSS#16 GND#48 H20
+1.8V_RUN_GFX 1 R57 02 AA12 R21 N25 H6
VDDR4#2 VDDC#9 PCIE_VSS#17 GND#49
1 R54 02 Y11 T12 N27 J27
For M92-S2: Install R147,R148,R149 VDDR4#3 VDDC#10 PCIE_VSS#18 GND#50
VDDR4#[1..4] & VDDR5#[1..4]=340mA max Y12 T15 P25 J31
Use R150 0R to VDDR4 VDDR4#4 VDDC#11 PCIE_VSS#19 GND#51
T17 P32 K11
VDDC#12 PCIE_VSS#20 GND#52
M93-S3 and Park: Remove R147,R148,R149 T20 R27 K2
VDDC#13 PCIE_VSS#21 GND#53
Use R45 150 Ohms Pull Down U13 T25 K22
C137 C130 C146 C120 VDDC#14 PCIE_VSS#22 GND#54
1 R66 02 U11 U16 T32 K6
1U 0.1U 1U 0.1U VDDR5#1 VDDC#15 PCIE_VSS#23 GND#55
U12 U18 U25 M6
VDDR5#2 VDDC#16 PCIE_VSS#24 GND#56
1 R64 02 V11 U21 U27 N11
+1.5V_RUN VDDR5#3 VDDC#17 PCIE_VSS#25 GND#57
V12 V15 V32 N12
VDDR5#4 VDDC#18 PCIE_VSS#26 GND#58
V17 W25 N13
VDDC#19 PCIE_VSS#27 GND#59
V20 W26 N16
VDDC#20 PCIE_VSS#28 GND#60
V21 W27 N18
L56 BLM15BD121SN1D +VDDRH1 VDDC#21 PCIE_VSS#29 GND#61
L17 Y13 Y25 N21
VDDRHA VDDC#22 PCIE_VSS#30 GND#62
Y16 Y32 P6
VDDC#23 PCIE_VSS#31 GND#63
Y18 P9
C609 C608 VDDC#24 GND#64
VDDC#25 Y21 GND#65 R12
1U 1U R15
GND#66
A3 GND#1 GND#67 R17
L16
VSSRHA
DDCI=2A max A30
GND#2 GND#68
R20
AA13 T13
+VDDCI GND#3 GND#69
M13 AA16 T16
VDDCI#1 GND#4 GND#70
M15 AB10 T18
VDDCI#2 GND#5 GND#71
VDDCI#3
M16 (0.9~1.2V) AB15
GND#6 GND#72
T21
M17 AB6 T6
VDDCI#4 GND#7 GND#73
M18 AC9 U15
VDDCI#5 GND#8 GND#74
M20 AD6 U17
VDDCI#6 GND#9 GND#75
M21 AD8 U20
VDDCI#7 GND#10 GND#76
N20 AE7 U3
VDDCI#8 GND#11 GND#77
AG12 GND#12 GND#78 U9
B AH10 GND#13 GND#79 V13 B
AH28 V16
GND#14 GND#80
B10 V18
GND#15 GND#81
B12 V6
GND#16 GND#82
B14 Y10
M92-S2/M92-XT GND#17 GND#83
B16 Y15
+BBP GND#18 GND#84
B18 Y17
GND#19 GND#85
(0.9~1.2V) B20 Y20
GND#20 GND#86
3 1 +VCC_GFX_CORE B22 Y6
GND#21 GND#87
B24 T11
Q18 Q20 GND#22 GND#88
B26 R11
2N7002W-7-F GND#23 GND#89
3 1 +1.8V_RUN_GFX B6
2

GND#24
(0.9~1.2V) B8 GND#25
1

C1 GND#26
C152 SI2301BDS-T-GE3 +VCC_GFX_CORE C32
2

1U GND#27
E28
2

GND#28
402 1 2
layout note: close to VDDC#[1:25] F10
F12
GND#29
A32
+5V_RUN GND#30 VSS_MECH#1
6.3 R63 100K F14 AM1
GND#31 VSS_MECH#2
F16 AM32
GND#32 VSS_MECH#3
3

2 Q19 C178 C141 C122 C133 C154

17 BB_ENA
2N7002W-7-F 1U 1U 1U 1U 1U M92-S2/M92-XT
1

R67
10K

(0.9~1.2V)
C153 C110 C109 C121 C145 C124 C139 C134 +VCC_GFX_CORE
1U 1U 1U 1U 1U 1U 1U 1U (0.9~1.2V)
+VDDCI L25
BLM18EG221SN1D
(0.9~1.2V)
C157 C156 C165 C155 C161
+VCC_GFX_CORE 0.1U 0.1U 1U 1U 10U
A A

C138 C116 C117

10U 10U 10U

QUANTA
Title
COMPUTER
VGA-M92-XT (PCIe)

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 18 of 64

5 4 3 2 1
 5 4 3 2 1

MEMORY INTERFACE

U32C
D PART 3 OF 10 D

MDA0 K27 K17 MAA0

MDA1 DQA_0 MAA_0 MAA1
MDA2
J29
H30
DQA_1 MEMORY MAA_1 J20
H23 MAA2
MDA3 DQA_2 MAA_2 MAA3
MDA4
H32
G29
DQA_3 INTERFACE MAA_3 G23
G24 MAA4
MDA5 DQA_4 MAA_4 MAA5
F28 DQA_5 MAA_5 H24
MDA6 F32 J19 MAA6
MDA7 DQA_6 MAA_6 MAA7
F30 DQA_7 MAA_7 K19
MDA8 C30 J14 MAA8
MDA9 DQA_8 MAA_8 MAA9 +3.3V_ADM1032A
F27 DQA_9 MAA_9 K14
MDA10 A28 J11 MAA10
MDA11 DQA_10 MAA_10 MAA11
C28 DQA_11 MAA_11 J13
MDA12 E27 J16 A_BA0 +3.3V_ADM1032A
MDA13 DQA_12 MAA_BA0 A_BA1
G26 DQA_13 MAA_BA1 L15
MDA14 D26 H11 MAA12
DQA_14 MAA_12

2
MDA15 F25 G11 A_BA2
MDA16 DQA_15 MAA_BA2 Q15
A25 DQA_16 THERMAL MONITOR

1
MDA17 C25 3 1
DQA_17 29 SMBCLK2
MDA18 E25
MDA19 DQA_18 DQMA#0 R43 R44
D24 DQA_19 DQMA_0 E32
MDA20 E23 E30 DQMA#1 2N7002W-7-F 4.7K 4.7K
MDA21 DQA_20 DQMA_1 DQMA#2
F23 A21

2
MDA22 DQA_21 DQMA_2 DQMA#3 +3.3V_ADM1032A
D22 DQA_22 DQMA_3 C21 U4
MDA23 F21 E13 DQMA#4
DQA_23 DQMA_4 VGA_THERMDP 21

2
MDA24 E21 D12 DQMA#5 8 1
DQA_24 DQMA_5 SCLK VDD

1
QSA#[7..0] MDA25 D20 E3 DQMA#6 Q16
20 QSA#[7..0] DQA_25 DQMA_6
MDA26 F19 F4 DQMA#7 3 1 7 2 C80
QSA[7..0] DQA_26 DQMA_7 29 SMBDAT2 SDATA D+
20 QSA[7..0] MDA27 A19 2N7002W-7-F 2200P

2
MDA28 DQA_27 THERMAL_INT# 50
D18 DQA_28 6 ALERT# D- 3 VGA_THERMDN 21
C DQMA#[7..0] MDA29 F17 17 THERMAL_INT# C
20 DQMA#[7..0] DQA_29
MDA30 A17 H28 QSA0 5 4 MB_THERM# MB_THERM# 46
MDA[63..0] MDA31 DQA_30 QSA_0 QSA1 GND THERM#
C17 DQA_31 QSA_1 C27
20 MDA[63..0] MDA32 E17 A23 QSA2
DQA_32 QSA_2 ADM1032ARMZ-1
MAA[12..0] MDA33 D16 E19 QSA3

WRITE STROBE READ STROBE

20 MAA[12..0] DQA_33 QSA_3
MDA34 F15 E15 QSA4
DQA_34 QSA_4

1
MDA35 A15 D10 QSA5 C48
A_BA[2..0] MDA36 DQA_35 QSA_5 QSA6 0.1U
20 A_BA[2..0] D14 DQA_36 QSA_6 D6
MDA37 F13 G5 QSA7 MB_THERM# R38 2 1 10K +3.3V_ADM1032A

2
MDA38 DQA_37 QSA_7 16
A13 DQA_38
MDA39 C13 THERMAL_INT# R41 2 1 10K
MDA40 DQA_39
E11 DQA_40
MDA41 A11 H27 QSA#0
MDA42 DQA_41 QSA_0B QSA#1
C11 DQA_42 QSA_1B A27
MDA43 F11 C23 QSA#2
MDA44 DQA_43 QSA_2B QSA#3
A9 DQA_44 QSA_3B C19
MDA45 C9 C15 QSA#4
MDA46 DQA_45 QSA_4B QSA#5
F9 DQA_46 QSA_5B E9
MDA47 D8 C5 QSA#6
MDA48 DQA_47 QSA_6B QSA#7 Q12
E7 DQA_48 QSA_7B H4
MDA49 A7 SI2303BDS-T1-E3
MDA50 DQA_49
C7 DQA_50
MDA51 F7 L18 ODTA0 20 +3.3V_ADM1032A 3 1 +3.3V_SUS
MDA52 DQA_51 ODTA0
A5 DQA_52 ODTA1 K16 ODTA1 20
MDA53 E5 DQA_53

1
MDA54 C3

2
MDA55 DQA_54 R40
E1 DQA_55 CLKA0 H26 CLKA0 20
DIVIDER RESISTORS DDR3 MDA56 G7 G9 CLKA1 20 100K
MDA57 DQA_56 CLKA1
G6 DQA_57
MDA58 G1

2
MDA59 DQA_58
MVREF TO 1.5V 100R MDA60
G3 DQA_59 CLKA0B H25 CLKA0# 20
J6 DQA_60 CLKA1B H9 CLKA1# 20
B MDA61 J1 B
DQA_61

3
MVREF TO GND 100R MDA62 J3
MDA63 DQA_62 Q13
J5 DQA_63 RASA0B G22 RASA0# 20 17,29,50 GFX_ON 2
RASA1B G17 RASA1# 20 2N7002W-7-F

1
+1.5V_RUN

CASA0B G19 CASA0# 20

CASA1B G16 CASA1# 20
R453
100R H22 CSA0_0# 20
CSA0B_0
CSA0B_1 J22
MVREFD_A K26 MVREFDA
J26 MVREFSA
CSA1B_0 G13 CSA1_0# 20
R444 C634 C636 K13
100R 0.1U 0.01U CSA1B_1
+1.5V_RUN
CKEA0 K20 CKEA0 20
CLKTESTA K8 J17 +1.5V_RUN
CLKTESTA CKEA1 CKEA1 20
CLKTESTB L7
R450 CLKTESTB
100R MEMTEST J8 G25 WEA0# 20
MEM_CALRP1 WEA0B
WEA1B H10 WEA1# 20
MVREFS_A R75 R74 R79
4.7K 4.7K 243R R506
4.7K
R445 C637 C635 +1.5V_RUN G20
100R 0.1U 0.01U NC_MAA_13
G14 NC_MAA_14
R80 243R K7
R87 243R NC_MEM_CALRN1
K25 NC_MEM_CALRP0 DRAM_RST L10 DRAM_RST# 20
R86 243R J25
A NC_MEM_CALRN0 A
M92-S2/M92-XT
2

C175 R76
1U 4.7K
QUANTA
1

20 MAA13

Title
COMPUTER
VGA-M92-XT (PCIe)
Reserve for Park-S3 Size Document Number Rev
FM9 1A

Date: Wednesday, March 04, 2009 Sheet 19 of 64

5 4 3 2 1
 5 4 3 2 1

MDA[63..0]
19 MDA[63..0]

MAA[12..0]
19 MAA[12..0]
QSA[7..0]
19 QSA[7..0]
QSA#[7..0]
19 QSA#[7..0]
DQMA#[7..0]
19 DQMA#[7..0]

19 DRAM_RST#
DRAM_RST# DDR3
A_BA[2..0]
19 A_BA[2..0]
U11 U36 U10 U35
D D
VREFC_U47 M8 E3 MDA4 VREFC_U48 M8 E3 MDA8 VREFC_U49 M8 E3 MDA45 VREFC_U50 M8 E3 MDA63
VREFD_U47 VREFCA DQL0 MDA3 VREFD_U48 VREFCA DQL0 MDA14 VREFD_U49 VREFCA DQL0 MDA42 VREFD_U50 VREFCA DQL0 MDA58
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 MDA7 VREFDQ DQL1 MDA11 VREFDQ DQL1 MDA47 VREFDQ DQL1 MDA56
F2 F2 F2 F2
MAA0 DQL2 MDA1 MAA0 DQL2 MDA9 MAA0 DQL2 MDA40 MAA0 DQL2 MDA59
N3 F8 N3 F8 N3 F8 N3 F8
MAA1 A0 DQL3 MDA6 MAA1 A0 DQL3 MDA10 MAA1 A0 DQL3 MDA44 MAA1 A0 DQL3 MDA60
P7 H3 P7 H3 P7 H3 P7 H3
MAA2 A1 DQL4 MDA2 MAA2 A1 DQL4 MDA15 MAA2 A1 DQL4 MDA43 MAA2 A1 DQL4 MDA62
P3 H8 P3 H8 P3 H8 P3 H8
MAA3 A2 DQL5 MDA5 MAA3 A2 DQL5 MDA12 MAA3 A2 DQL5 MDA46 MAA3 A2 DQL5 MDA57
N2 G2 N2 G2 N2 G2 N2 G2
MAA4 A3 DQL6 MDA0 MAA4 A3 DQL6 MDA13 MAA4 A3 DQL6 MDA41 MAA4 A3 DQL6 MDA61
P8 H7 P8 H7 P8 H7 P8 H7
MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7
P2 P2 P2 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
R8 R8 R8 R8
MAA7 A6 MDA18 MAA7 A6 MDA29 MAA7 A6 MDA33 MAA7 A6 MDA52
R2 D7 R2 D7 R2 D7 R2 D7
MAA8 A7 DQU0 MDA22 MAA8 A7 DQU0 MDA27 MAA8 A7 DQU0 MDA38 MAA8 A7 DQU0 MDA50
T8 C3 T8 C3 T8 C3 T8 C3
MAA9 A8 DQU1 MDA17 MAA9 A8 DQU1 MDA31 MAA9 A8 DQU1 MDA35 MAA9 A8 DQU1 MDA55
R3 C8 R3 C8 R3 C8 R3 C8
MAA10 A9 DQU2 MDA21 MAA10 A9 DQU2 MDA24 MAA10 A9 DQU2 MDA34 MAA10 A9 DQU2 MDA49
L7 C2 L7 C2 L7 C2 L7 C2
MAA11 A10/AP DQU3 MDA19 MAA11 A10/AP DQU3 MDA28 MAA11 A10/AP DQU3 MDA36 MAA11 A10/AP DQU3 MDA54
R7 A7 R7 A7 R7 A7 R7 A7
MAA12 A11 DQU4 MDA23 MAA12 A11 DQU4 MDA26 MAA12 A11 DQU4 MDA37 MAA12 A11 DQU4 MDA51
N7 A2 N7 A2 N7 A2 N7 A2
MAA13 A12/BC DQU5 MDA16 MAA13 A12/BC DQU5 MDA30 MAA13 A12/BC DQU5 MDA32 MAA13 A12/BC DQU5 MDA53
19 MAA13 T3 B8 19 MAA13 T3 B8 19 MAA13 T3 B8 19 MAA13 T3 B8
A13 DQU6 MDA20 A13 DQU6 MDA25 A13 DQU6 MDA39 A13 DQU6 MDA48
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V_RUN A15 +1.5V_RUN A15 +1.5V_RUN A15 +1.5V_RUN
Reserve for Park-S3 Reserve for Park-S3 Reserve for Park-S3 Reserve for Park-S3
A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2
A_BA1 BA0 VDD#B2 A_BA1 BA0 VDD#B2 A_BA1 BA0 VDD#B2 A_BA1 BA0 VDD#B2
N8 D9 N8 D9 N8 D9 N8 D9
A_BA2 BA1 VDD#D9 A_BA2 BA1 VDD#D9 A_BA2 BA1 VDD#D9 A_BA2 BA1 VDD#D9
M3 G7 M3 G7 M3 G7 M3 G7
BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 VDD#K2 VDD#K2 VDD#K2
K8 K8 K8 K8
VDD#K8 VDD#K8 VDD#K8 VDD#K8
N1 N1 N1 N1
CLKA0 VDD#N1 CLKA0 VDD#N1 CLKA1 VDD#N1 CLKA1 VDD#N1
19 CLKA0 J7 N9 19 CLKA0 J7 N9 19 CLKA1 J7 N9 19 CLKA1 J7 N9
CLKA0# CK VDD#N9 CLKA0# CK VDD#N9 CLKA1# CK VDD#N9 CLKA1# CK VDD#N9
19 CLKA0# K7 R1 19 CLKA0# K7 R1 19 CLKA1# K7 R1 19 CLKA1# K7 R1
CKEA0 CK VDD#R1 CKEA0 CK VDD#R1 CKEA1 CK VDD#R1 CKEA1 CK VDD#R1
19 CKEA0 K9 R9 19 CKEA0 K9 R9 19 CKEA1 K9 R9 19 CKEA1 K9 R9
CKE VDD#R9 +1.5V_RUN CKE VDD#R9 +1.5V_RUN CKE VDD#R9 +1.5V_RUN CKE VDD#R9 +1.5V_RUN

ODTA0 K1 A1 ODTA0 K1 A1 ODTA1 K1 A1 ODTA1 K1 A1

19 ODTA0 ODT VDDQ#A1 19 ODTA0 ODT VDDQ#A1 19 ODTA1 ODT VDDQ#A1 19 ODTA1 ODT VDDQ#A1
CSA0_0# L2 A8 CSA0_0# L2 A8 CSA1_0# L2 A8 CSA1_0# L2 A8
19 CSA0_0# CS VDDQ#A8 19 CSA0_0# CS VDDQ#A8 19 CSA1_0# CS VDDQ#A8 19 CSA1_0# CS VDDQ#A8
RASA0# J3 C1 RASA0# J3 C1 RASA1# J3 C1 RASA1# J3 C1
19 RASA0# RAS VDDQ#C1 19 RASA0# RAS VDDQ#C1 19 RASA1# RAS VDDQ#C1 19 RASA1# RAS VDDQ#C1
CASA0# K3 C9 CASA0# K3 C9 CASA1# K3 C9 CASA1# K3 C9
19 CASA0# CAS VDDQ#C9 19 CASA0# CAS VDDQ#C9 19 CASA1# CAS VDDQ#C9 19 CASA1# CAS VDDQ#C9
WEA0# L3 D2 WEA0# L3 D2 WEA1# L3 D2 WEA1# L3 D2
19 WEA0# WE VDDQ#D2 19 WEA0# WE VDDQ#D2 19 WEA1# WE VDDQ#D2 19 WEA1# WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
QSA0 VDDQ#F1 QSA1 VDDQ#F1 QSA5 VDDQ#F1 QSA7 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
QSA2 DQSL VDDQ#H2 QSA3 DQSL VDDQ#H2 QSA4 DQSL VDDQ#H2 QSA6 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
C DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 C

DQMA#0 E7 A9 DQMA#1 E7 A9 DQMA#5 E7 A9 DQMA#7 E7 A9

DQMA#2 DML VSS#A9 DQMA#3 DML VSS#A9 DQMA#4 DML VSS#A9 DQMA#6 DML VSS#A9
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
QSA#0 VSS#G8 QSA#1 VSS#G8 QSA#5 VSS#G8 QSA#7 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
QSA#2 DQSL VSS#J2 QSA#3 DQSL VSS#J2 QSA#4 DQSL VSS#J2 QSA#6 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
VSS#M9 VSS#M9 VSS#M9 VSS#M9
P1 P1 P1 P1
DRAM_RST# T2 VSS#P1 DRAM_RST# T2 VSS#P1 DRAM_RST# VSS#P1 DRAM_RST# VSS#P1
P9 P9 T2 P9 T2 P9
RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VSS#T1 VSS#T1 VSS#T1 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

Should be 240 R484 B1 Should be 240 B1 Should be 240 B1 Should be 240 B1

VSSQ#B1 R483 VSSQ#B1 R138 VSSQ#B1 R486 VSSQ#B1
Ohms +-1% 243/F B9 Ohms +-1% B9 Ohms +-1% B9 Ohms +-1% B9
VSSQ#B9 240/F VSSQ#B9 240/F VSSQ#B9 240/F VSSQ#B9
D1 D1 D1 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
D8 D8 D8 D8
VSSQ#D8 VSSQ#D8 VSSQ#D8 VSSQ#D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12

+1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN

1

1
R139 R479 R504 R481 R503 R116 R162 R115
B B
4.99K/F 4.99K/F 4.99K/F 4.99K/F 4.99K/F 4.99K/F 4.99K/F 4.99K/F
2

2
VREFC_U47 VREFD_U47 VREFC_U48 VREFD_U48 VREFC_U49 VREFD_U49 VREFC_U50 VREFD_U50
Placement has to be close to VRAM
1

1
1

1
CLKA0 R464 56/F R119 C302 R475 C651 R508 C689 R480 C656 R507 C688 R111 C294 R143 C310 R112 C292
4.99K/F 0.1U 4.99K/F 0.1U 4.99K/F 0.1U 4.99K/F 0.1U 4.99K/F 0.1U 4.99K/F 0.1U 4.99K/F 0.1U 4.99K/F 0.1U
10 10 10 10 10 10 10 10
2

2
C653 0.01U
2

2
25
CLKA0# R468 56/F

CLKA1 R118 56/F

C309 0.01U

25
CLKA1# R120 56/F
close to U47 close to U48 close to U49 close to U50
+1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN
1

1
C287 C277 C301 C629 C640 C650 C281 C268 C280 C652 C657 C642
1U 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U
2

2
6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3

+1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN

1

2
C256 C312 C290 C639 C630 C683 C259 C641 C258 C284 C645 C638 C691 C692 C631 C660
A 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U 10U 10U 10U 10U A
603 603 603 603
2

1
6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3

+1.5V_RUN +1.5V_RUN +1.5V_RUN

QUANTA
2

C311 C295 C286 C283 C671 C685 C647 C643 C319 C320 C321 C322
10U 10U 10U 10U 10U 10U 10U 10U 10U 10U 10U 10U
603 603 603 603 603 603 603 603 603 603 603 603
COMPUTER
1

6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3
Title
VGA-M92-S (VRAM)

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 20 of 64

5 4 3 2 1
 5 4 3 2 1

U32J
Part 10 of 10

XTAL / PLL DPLL_PVDD=120mA max +1.8V_RUN_GFX

H7 AF14 +DPLL_PVDD L47

D T15 PAD NC_SPV18 DPLL_PVDD D
BLM15BD121SN1D

C546 C533 C526 C520

0.01U 0.1U 10U 10U

J7 SPVSS
AE14
DPLL_PVSS
SPV10=120mA max (1.1V)
(0.9~1.2V)
L26 +SPV10 H8 +PCIE_VDDC
+VCC_GFX_CORE SPV10
BLM15BD121SN1D DPLL_VDDC=150mA max
C233 C232 C234 C235 AD14 +DPLL_VDDC L19
1U 1U 0.1U 0.01U DPLL_VDDC BLM15BD121SN1D
C82 C74 C65 C51
0.01U 0.1U 1U 10U

+1.8V_RUN_GFX
PCIE_PVDD=40mA max
AM28 AM30 +PCIE_PVDD L50
17 XTALIN XTALIN PCIE_PVDD BLM15BD121SN1D
C532 C550 C539 C519
1U 0.01U 0.1U 10U
17 XTALOUT AK28 XTALOUT

NC_MPV18 L8 PAD T12

C M92-S2/M92-XT C

U32H
Part 8 of 10

I2C / DDC / AUX

AD2
AUX1P +3.3V_DELAY
25 G_CLK_DDC2 AC1
DDC6CLK AUX1N
AD4
LVDS
CRT 25 G_DAT_DDC2 AC3
DDC6DATA
AE6 LCD_DDCCLK
LCD_DDCCLK 24

TMDP / DAC1
DDC1CLK LCD_DDCDAT LCD_DDCDAT R385 2
DDC1DATA AE5 LCD_DDCDAT 24 1 2.2K
LCD_DDCCLK R405 2 1 2.2K

AD13
AUX2P
AD11
AUX2N

DDC2CLK AC11
AC13
HDMI_SCL 24 HDMI
DDC2DATA HDMI_SDA 24

AE16
DDCCLK_AUX5P

LVTMDP / DAC2
B B
DDCDATA_AUX5N AD16

R1 AD20
SCL NC_DDCCLK_AUX7P
R3 AC20
SDA NC_DDCDATA_AUX7N

M92-S2/M92-XT

U32I
Part 9 of 10

+1.8V_RUN_GFX
TSVDD=20mA max TSS FDO
L53 +TSVDD AD17 R5
BLM15BD121SN1D TSVDD TS_FDO

C538 C549 T4
0.1U DPLUS VGA_THERMDP 19
1U
GND AC17
TSVSS
DMINUS T2 VGA_THERMDN 19
A A

M92-S2/M92-XT

QUANTA
Title
COMPUTER
VGA-M92-XT (PCIe)

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 21 of 64

5 4 3 2 1
 5 4 3 2 1

TMDP(HDMI) INTERFACE LVDS INTERFACE

U32F
PART 6 OF 10

D U32G D
+DPA_PVDD AG8
DPA AK3 Part 7 of 10
DPA_PVDD TX2P_DPA0P
TX2M_DPA0N AK1

AH3 +DPF_PVDD AG19

DPF RSVD#6 AK24
AJ23
TX1P_DPA1P NC_DPF_PVDD RSVD#4
TX1M_DPA1N AH1
AG7 DPA_PVSS T2X5P_DPF0P AL23 LCD_B2+ 24
TX0P_DPA2P AG3 T2X5M_DPF0N AK22 LCD_B2- 24
TX0M_DPA2N AG5
AF20 NC_DPF_PVSS T2X4P_DPF1P AH22 LCD_B1+ 24
+DPA_VDD18 AF11 AF2 AJ21
NC_DPA_VDD18#2 TXCAP_DPA3P T2X4M_DPF1N LCD_B1- 24
AE11 NC_DPA_VDD18#1 TXCAM_DPA3N AF4
T2X3P_DPF2P AL21 LCD_B0+ 24
AH5 +DPF_VDD18 AG17 AK20
DPA_VSSR#5 DPF_VDD18#2 T2X3M_DPF2N LCD_B0- 24
DPA_VSSR#3 AG1 AF16 DPF_VDD18#1
DPA_VSSR#4 AG6 T2XCFP_DPF3P AH20 LCD_BCLK+ 24
DPA_VSSR#2 AE3 T2XCFM_DPF3N AJ19 LCD_BCLK- 24
+DPA_VDD10 AF6 AE1
DPA_VDD10#1 DPA_VSSR#1
AF7 DPA_VDD10#2 DPF_VSSR#4 AM22
DPF_VSSR#5 AM24
DPF_VSSR#2 AG23
+DPF_VDD10 AG22 AF23
DPF_VDD10#2 DPF_VSSR#1
DPB TX5P_DPB0P AK8
AL7
HDMI_TX2+ 24 AF22 DPF_VDD10#1 DPF_VSSR#3 AM20
C TX5M_DPB0N HDMI_TX2- 24 C

TX4P_DPB1P AJ7 HDMI_TX1+ 24

+DPA_PVDD AG10 DPB_PVDD TX4M_DPB1N AH6 HDMI_TX1- 24 DPE RSVD#7 AL19
AK18
RSVD#5
TX3P_DPB2P AK6 HDMI_TX0+ 24
TX3M_DPB2N AM5 HDMI_TX0- 24 T2X2P_DPE0P AH18 LCD_A2+ 24
T2X2M_DPE0N AJ17 LCD_A2- 24
AG11 DPB_PVSS TXCBP_DPB3P AK5 HDMI_CLK+ 24
AM3 HDMI_CLK- 24 +DPF_PVDD AG18 AL17
TXCBM_DPB3N DPE_PVDD T2X1P_DPE1P LCD_A1+ 24
T2X1M_DPE1N AK16 LCD_A1- 24
DPB_VSSR#5 AM8
DPB_VSSR#2 AG9 T2X0P_DPE2P AH16 LCD_A0+ 24
DPB_VSSR#1 AF10 T2X0M_DPE2N AJ15 LCD_A0- 24
+DPA_VDD18 AE13 AM6 AF19
NC_DPB_VDD18#1 DPB_VSSR#4 DPE_PVSS
AF13 NC_DPB_VDD18#2 DPB_VSSR#3 AH8 T2XCEP_DPE3P AL15 LCD_ACLK+ 24
T2XCEM_DPE3N AK14 LCD_ACLK- 24
+DPF_VDD18 AG16 AM14
DPE_VDD18#2 DPE_VSSR#3
CALIBRATION AG15 DPE_VDD18#1 DPE_VSSR#2 AH14
AG14
+DPA_VDD10 DPE_VSSR#1
AF8 DPB_VDD10#1 DPAB_CALR AE10 DPAB_CALR 150R R397
DPE_VSSR#4 AM16
AF9 DPB_VDD10#2 DPE_VSSR#5 AM18

B M92-S2/M92-XT B

+DPF_VDD10 AG21
CALIBRATION
DPE_VDD10#2
AG20 DPE_VDD10#1 DPEF_CALR AF17 DPEF_CALR 150R R48

+1.8V_RUN_GFX for HDMI interface use M92-S2/M92-XT

DPB_PVDD=20mA max
+1.8V_RUN_GFX
L14 +DPA_PVDD
for LVDS interface use DPB_PVDD=20mA max
BLM15BD121SN1D
C44 C57 C71 L16 +DPF_PVDD
4.7U/6.3V 1U 0.1U BLM15BD121SN1D
C53 C66 C75
4.7U/6.3V 1U 0.1U
+1.8V_RUN_GFX

NC_DPB_VDD18#[1..2]=400mA max +1.8V_RUN_GFX

L18 +DPA_VDD18 NC_DPB_VDD18#[1..2]=400mA max

BLM15BD121SN1D
(1.1V) C81 C55 C70 L15 +DPF_VDD18
4.7U/6.3V 1U 0.1U BLM15BD121SN1D
+PCIE_VDDC (1.1V) C52 C67 C78
4.7U/6.3V 1U 0.1U
A DPB_VDD10#[1..2]=200mA max +PCIE_VDDC A
L22
BLM18PG300SN1D
+DPA_VDD10
DPE_VDD10#[1..2]=170mA max
QUANTA
L20 +DPF_VDD10
C98
4.7U/6.3V 1U
C104 C97
0.1U
BLM18PG300SN1D
Title
COMPUTER
C60 C76 C84 VGA-M92-XT (PCIe)
4.7U/6.3V 1U 0.1U
Size Document Number Rev
FM9 1A

Date: Wednesday, March 04, 2009 Sheet 22 of 64

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

QUANTA
Title
COMPUTER
VGA-M82-S (PCIe)

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 23 of 64

5 4 3 2 1
 5 4 3 2 1

J1
44 LCD_BCLK-
+15V_ALW +3.3V_RUN +LCDVCC 44 LCD_BCLK+
43 43
Q54 42 +LCDVCC +3.3V_RUN
FDC655BN 42 LCD_B2-
41 41 LCD_B2- 22
6 40 LCD_B2+
40 LCD_B2+ 22

2
5 4 39 39
R369 2 38 LCD_B1-
38 LCD_B1- 22

1
330K 1 37 LCD_B1+
37 LCD_B1+ 22

2
36 C11 C10 C9
36

2
R367 35 LCD_B0- 0.1U 0.047U 0.1U
LCD_B0- 22

2
47 C501 C500 35 LCD_B0+
34 34 LCD_B0+ 22
LCDVCC_ON 805 22U 0.01U 33 16 10 16

1
1206 33 LCD_ACLK-
32

1
32

1
D D
10 25 31 LCD_ACLK+
31

2
30 30
R368 C503 29 LCD_A2-
29 LCD_A2- 22
*100K_NC 0.01U 28 LCD_A2+
LCD_A2+ 22

1
28
27

2
25 27 LCD_A1-
26 26 LCD_A1- 22
25 LCD_A1+
25 LCD_A1+ 22
+3.3V_SUS 24
24

3
23 LCD_A0-
23 LCD_A0- 22
2 2 22 LCD_A0+
22 LCD_A0+ 22
Q55 21
21

1
Q56 2N7002W-7-F 20 LCD_DDCCLK
LCD_DDCCLK 21

1
R7 2N7002W-7-F 20 LCD_DDCDAT
19 19 LCD_DDCDAT 21
47K 18
18
17 17 +3.3V_RUN
Support the new imbeded 16

2
16
15
diagnostics. 15
14
+LCDVCC
Adress : A9H --Contrast
D1 14
13 LCD_TST 29
13 AAH --Backlight

3
17 ENVDD 1 12 12
11 11 +GFX_PWR_SRC
3 EN_LCDVCC 2 Q1 10
DDTC124EUA-7-F 10
9 9
29 LCDVCC_TST_EN 2 8 8
7

1
BAT54C T/R 7
6 6 LCD_CONTRAST 29
5 5
4 4 INVERTER_CBL_DET# 29
3 3 LCD_BAK# 29
C 2 ATI_PWM C
2
1 1 LCD_CBL_DET# 29
+3.3V_RUN
FI-TD44SB-LE
1

+3.3V_RUN Shunt capacitors on LVDS for improving WWAN.

R607
*10K_NC
5

U45 LCD_B0- C13 1 2 *3.3P_NC 50 LCD_B0+

2 LCD_B1- C5 1 2 *3.3P_NC 50 LCD_B1+
17 BIA_PWM
2

4 ATI_PWM LCD_B2- C4 1 2 *3.3P_NC 50 LCD_B2+

1 LCD_A0- C3 1 2 *3.3P_NC 50 LCD_A0+
29 PWM_VADJ EXC24CG240U EXC24CG240U
LCD_A1- C7 1 2 *3.3P_NC 50 LCD_A1+
*TC7SZ32FU(T5L,F,T)_NC LCD_A2- C2 1 2 *3.3P_NC 50 LCD_A2+ HDMI_TX2+_R 4 3 HDMI_TX2+_C HDMI_TX0+_R 2 1 HDMI_TX0+_C
R608 1 2 0 HDMI_TX2-_R 1 2 HDMI_TX2-_C HDMI_TX0-_R 3 4 HDMI_TX0-_C

R609 1 2 *0_NC L7 L8
LCD_ACLK-
LCD_ACLK- 22
R16 *0_NC R18 *0_NC
2

1 2 1 2
+PWR_SRC +GFX_PWR_SRC R2 2 C1 R17 *0_NC R19 *0_NC
*0_NC 1 2 1 2
40mil *3.3P_NC
1

40mil 6
1

4 5 LCD_ACLK+
LCD_ACLK+ 22 EXC24CG240U EXC24CG240U
2 50
1 HDMI_TX1+_R 1 2 HDMI_TX1+_C HDMI_CLK+_R 1 2 HDMI_CLK+_C
1

HDMI_TX1-_R 4 3 HDMI_TX1-_C HDMI_CLK-_R 4 3 HDMI_CLK-_C

2

Q4 C6 C12 LCD_BCLK-
LCD_BCLK- 22
3

R11 C14 FDC658AP 0.1U 0.1U L6 L5

2

B B
100K 0.1U 603 603
1

603 25 25 R1 C8 R15 *0_NC R13 *0_NC

2

25 *0_NC *3.3P_NC 1 2 1 2
1

R14 *0_NC R12 *0_NC

1
2

LCD_BCLK+ 1 2 1 2
LCD_BCLK+ 22
R9 50
100K

+3.3V_DELAY
HDMI
3 1

CN3 R377 2 1 499/F HDMI_TX2+_R

R372 0 20 R378 2 1 499/F HDMI_TX2-_R
Q2 HDMI_TX2+_C SHELL1
44,47,48,49,52 RUN_ON 2 +5V_RUN 19 D2+ GND 22
2N7002W-7-F 603 18 R376 2 1 499/F HDMI_TX1+_R
HDMI_TX2-_C D2 Shield R375
17 2 1 499/F HDMI_TX1-_R
1

D2-
1

HDMI_TX1+_C 16 D1+ R379

15 D1 Shield 2 1 499/F HDMI_TX0+_R
1

1
R10 R8 HDMI_TX1-_C 14 R380 2 1 499/F HDMI_TX0-_R
4.7K 4.7K HDMI_TX0+_C D1-
13 D0+
R371 R370 12 R374 2 1 499/F HDMI_CLK+_R
2

Q5 FDV301N 2.2K 2.2K HDMI_TX0-_C D0 Shield R373

11 D0- 2 1 499/F HDMI_CLK-_R
HDMI_CLK+_C 10
2

CK+

3
1 3 HDMI_CLK 9
21 HDMI_SCL CK Shield
HDMI_CLK-_C 8 +5V_RUN 2
CK- Q6
7 CE Remote
6 2N7002W-7-F
2

1
C21 0.1U HDMI_TX2+_R NC
22 HDMI_TX2+ +3.3V_DELAY 5 DDC CLK
4 DDC DATA
2

C22 0.1U HDMI_TX2-_R 3

22 HDMI_TX2- GND
A C20 0.1U HDMI_TX1+_R 2 A
22 HDMI_TX1+ +5V
1 3 HDMI_DAT 17 HDMI_DET 1 23
21 HDMI_SDA HP DETGND
C19 0.1U HDMI_TX1-_R 21
22 HDMI_TX1- SHELL2
C23 0.1U HDMI_TX0+_R
22

22
HDMI_TX0+

HDMI_TX0-
C24 0.1U HDMI_TX0-_R
Q3 FDV301N
+5V_RUN
LTS_ABA-HDM-018-K06 QUANTA
22 HDMI_CLK+
C18

C17
0.1U

0.1U
HDMI_CLK+_R

HDMI_CLK-_R Title
COMPUTER
22 HDMI_CLK-
C504 LCD CONN & CK-SSCD
*0.1U_NC
Size Document Number Rev
FM9 1A

Date: Wednesday, March 04, 2009 Sheet 24 of 64

5 4 3 2 1
 A B C D E

4 4

+3.3V_RUN +5V_RUN

2
D2

2
SDM10K45-7-F

1
Layout Note:
Setting R,G,B treac
D4 D5 D6
impedance to 50 ohm.

3
*DA204U_NC *DA204U_NC *DA204U_NC
+5V_CRT_REF
L21 BLM18BB750SN1D RED
17 VGA_RED
603
PAD T4 M_SEN#_R

L13 BLM18BB750SN1D GREEN

17 VGA_GRN
603 JVGA1
6
11
L11 BLM18BB750SN1D BLUE 1
17 VGA_BLU
603 7
2

3 1 12 3

1
R30 R36 R39 C34 C39 C56 C36 C43 C77 2
150/F 150/F 150/F 22P 22P 22P 10P/50V 10P/50V 10P/50V 8
13
2

2
50 50 50 50 50 50 3
1

9
14
PAD T1 M_ID2# 4
10
+3.3V_DELAY +5V_CRT_REF 15
5
+5V_CRT_REF
SUY_ 070549FR015S512ZR

3
1

3
1
2
RP2 C25 RP1
2.2KX2 0.01U 2.2KX2
Q58

1
BSS138-7-F 25

4
2

4
2
+5V_RUN 1 3 G_DAT_DDC2_C
21 G_DAT_DDC2
R21 1K
2 1

2
+3.3V_RUN
5

2
U2

2 4 HSYNC 1 3 G_CLK_DDC2_C
17 VGAHSYNC 21 G_CLK_DDC2

1
2 2
74AHCT1G125GW Q57
BSS138-7-F C32 C33
C29 0.1U *10P/50V_NC *10P/50V_NC

2
2 1
50 50
L10 BLM11A05S
JVGA_HS
5

16 603
U1
L9 BLM11A05S
2 4 VSYNC JVGA_VS
17 VGAVSYNC
603

1
74AHCT1G125GW
C26 C31 C30 C28
10P/50V 10P/50V 10P/50V 10P/50V
2

2
50 50 50 50

Place near JVGA1

connector < 200 mil

1 1

QUANTA
Title
COMPUTER
CRT&TV CONN

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 25 of 64

A B C D E
 A B C D E

1 1

MFIO Pin Assignment Table

MFIO SD8 MS8 XD

Place close U23 00 WP BS D7
SD_WP#/MS_BS/XD_DATA7 28 01 D1 - D6
SD_DATA1/XD_DATA6 28
SD_DATA0/MS_DATA1/XD_DATA5 28 02 D0 D1 D5
SD_DATA7/XD_DATA4 28 03 D7 - D4
SDATA_6/MS_DATA5/XD_DATA3 28
R605 0
SD_CLK/MS_DAT0/XD_DATA2 28 04 D6 D5 D3
XD_DATA1 28 05 CLK D0 D2
SD_DATA5/MS_DATA4/XD_DATA0 28
SD_CMD/MS_DATA2/XD_WP# 28
C771 06 - - D1
*22p_NC
SD_DATA4/MS_DATA6/XD_WE# 28 07 D5 D4 D0
SD_DATA3/MS_DATA3/XD_ALE 28 50
SD_DATA2/XD_CLE 28 08 CMD D2 WP#
XD_CE# 28 09 D4 D6 WE#
MS_DATA7/XD_RE# 28
R606 0
MS_CLK/XD_R/B# 28 10 D3 D3 ALE
SD_CD#/XD_CD0# 28 11 D2 - CLE
MS_INS#/XD_CD1# 28
C772 12 - - CE#
*22p_NC
13 - D7 RE#

25
26
27
28
29
30
31
32
33
34
35
38
39
40
41
50

4
5
U23 +3.3V_R5U230 14 - CLK R/B#

MFIO00
MFIO01
MFIO02
MFIO03
MFIO04
MFIO05
MFIO06
MFIO07
MFIO08
MFIO09
MFIO10
MFIO11
MFIO12
MFIO13
MFIO14

MFCD0N
MFCD1N
2 1 1394_XI 44 11
2 C390 10P/50V
50 1394_XO XI VCC_3V1 2
43 XO VCC_3V0 37

1
Y2 C381 C385
24.576MHZ
30PPM 0.1U 0.1U

2
16p
2 1
C403 10P/50V
50 12
PCIE_VOUT1
PCIE_VOUT0 42

2
13 C401 C383 C382 +3.3V_RUN +3.3V_R5U230
9 CLK_PCIE_CARD_READER REFCLKP
14 10U R236 0
9 CLK_PCIE_CARD_READER# REFCLKN
18 0.1U 0.1U 603 1 2

1
C409 0.1U TXP PCIE_VIN1 6.3 805
9 PCIE_RX5+ 19 23
C414 0.1U TXN TXP PCIE_VIN0
9 PCIE_RX5- 20
TXN C420 C402
9 PCIE_TX5+ 15
RXP 0.1U 0.1U
9 PCIE_TX5- 17
RXN +3.3V_R5U230
3,9,16,28,29,31,32,41 PLTRST# 9 PERSTN
RXC 16
RXC
22 2
RREF CPO AVCC_3V
24
RREF C419 C384
2

+MF_VCC
C427 C417 R265 0.1U 1U
0.022U 1500P 5.1K/F
36
MF_VOUT
1

3 3
TPB0N 45 49
28 TPB0N TPB0P TPBN0 GND0
28 TPB0P 46 21
TPA0N TPBP0 AGND0
28 TPA0N 47 TPAN0
TPA0P 48
28 TPA0P TPAP0
1

UDIO0
UDIO1
UDIO2
UDIO3
TPBIAS0

TEST
3
6
7
8

10
R250 R252 R241 R242 R5U230
56.2/F 56.2/F 56.2/F 56.2/F

9 CLK_PCIE_REQ5#

R251 C393 C386 +3.3V_R5U230 R2402 1 47K

5.11K/F 270P 0.33U
25

4 4

QUANTA
Title
COMPUTER
5 IN 1 CONTROLLER

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 26 of 64

A B C D E
 A B C D E

1 1

2 2

3 3

4 4

QUANTA
Title
COMPUTER
IEEE 1394

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 27 of 64

A B C D E
 1 2 3 4 5 6 7 8

Express Card/CARD READER

J7
SD_DATA7/XD_DATA4 25
A 26 SD_DATA7/XD_DATA4 A
26 SD_DATA1/XD_DATA6
SD_DATA1/XD_DATA6 26
SD_DATA5/MS_DATA4/XD_DATA0 24
26 SD_DATA5/MS_DATA4/XD_DATA0
27 SDATA_6/MS_DATA5/XD_DATA3
SDATA_6/MS_DATA5/XD_DATA3 26
SD_WP#/MS_BS/XD_DATA7 23
26 SD_WP#/MS_BS/XD_DATA7
28 SD_DATA0/MS_DATA1/XD_DATA5
SD_DATA0/MS_DATA1/XD_DATA5 26
XD_DATA1 22
26 XD_DATA1
29 SD_CLK/MS_DAT0/XD_DATA2
SD_CLK/MS_DAT0/XD_DATA2 26
21
30 SD_DATA3/MS_DATA3/XD_ALE
SD_DATA3/MS_DATA3/XD_ALE 26
XD_CE# 20
26 XD_CE#
31
19
32 SD_CMD/MS_DATA2/XD_WP#
SD_CMD/MS_DATA2/XD_WP# 26
WLAN_SMBDATA 18
31,32,35 WLAN_SMBDATA
33 SD_DATA4/MS_DATA6/XD_WE#
SD_DATA4/MS_DATA6/XD_WE# 26
WLAN_SMBCLK 17
31,32,35 WLAN_SMBCLK
34 SD_DATA2/XD_CLE
SD_DATA2/XD_CLE 26
16
35 MS_DATA7/XD_RE#
MS_DATA7/XD_RE# 26
MS_INS#/XD_CD1# 15
26 MS_INS#/XD_CD1#
36
SD_CD#/XD_CD0# 14
26 SD_CD#/XD_CD0#
37 PCIE_WAKE#
PCIE_WAKE# 7,31,32,41
13
38 CARD_CLK_REQ#
CARD_CLK_REQ# 9
12
39 EXPRCRD_PWREN# PAD T64
MS_CLK/XD_R/B# 11
26 MS_CLK/XD_R/B#
40
B +MF_VCC 10 B
41 PLTRST#
PLTRST# 3,9,16,26,29,31,32,41
9
42
8
43
+1.5V_RUN 7
44 +1.5V_RUN
6
45
5
46 1394 CONNECTOR
+3.3V_RUN 4
47 +3.3V_RUN
3 AS CLOSE AS POSSIBLE TO 1394 CONNECTOR.
48
2
49
+3.3V_SUS 1 *DLW21HN121SQ2L_NC
50 +3.3V_SUS
4 4 3 3
1 1 2 2
88242-5001
L60 CN5
FOX_UV31413-WRJOL-7H

R522 0 TPB0- 1
26 TPB0N 1

1
R525 0 TPB0+ 2
C 26 TPB0P 2 C
R533 0 TPA0- 3
26 TPA0N 3
R532 0 TPA0+ 4
26 TPA0P 4

5
6
5
6
4 4 3 3
1 1 2 2
J9
L62
1
2 *DLW21HN121SQ2L_NC
9 ICH_USBP9- ICH_USBP9- 3
9 ICH_USBP9+ ICH_USBP9+ 4
5
PCIE_TX4- 6 *TPA0P/TPA0N,TPB0P/TPB0N pair trace : As close as possible.
9 PCIE_TX4- PCIE_TX4+
9 PCIE_TX4+ 7 *TPA0P/TPA0N,TPB0P/TPB0N pair trace : Same length electrically.
8
PCIE_RX4- 9
9 PCIE_RX4-
PCIE_RX4+ 10
9 PCIE_RX4+
11
CLK_PCIE_EXPCARD# 12
9 CLK_PCIE_EXPCARD# CLK_PCIE_EXPCARD
9 CLK_PCIE_EXPCARD 13
14

ACS_88513-144N

D D

QUANTA
Title
COMPUTER
ExpressCard/SmartCard

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 28 of 64

1 2 3 4 5 6 7 8
 5 4 3 2 1

U22 +RTC_CELL
36 KSO[0..16]
R534 0
3 1 2 +3.3V_ALW
36 KSI[0..7] ITE8502E VBAT1
VCC 11 +3.3V_RUN
SMBDAT0 4 3 RP4
LQFP-128L

2
57 26 +3.3V_ALW SMBCLK0 2 1 2.2KX2
51 IMVP_PWRGD KSO17/GPC5 VSTBY1
KSO16 56 50 C710
KSO15 KSO16/GPC3 VSTBY2 0.1U SMBDAT1
55 92 4 3 RP5

1
KSO14 KSO15 VSTBY3 SMBCLK1
54 KSO14 VSTBY4 114 2 1 10KX2
+3.3V_ALW KSO13 53 121 16
KSO12 KSO13 VSTBY5 SMBDAT2
52 KSO12/SLCT VSTBY6 127 4 3 RP6
KSO11 51 SMBCLK2 2 1 2.2KX2
KSO10 KSO11/ERR
46 KSO10/PE
KSO9 45 USBP1_SIDE_EN# R198 2 1 10K
KSO9/BUSY
2

2
D D
KSO8 44 66 HWPG
KSO8/ACK ADC0/GPI0 HWPG 42
C342 C368 C713 C364 C316 KSO7 43 67
KSO7/PD7 ADC1/GPI1 IMVP6_PROCHOT# 51
10U 0.1U 0.1U 0.1U 0.1U KSO6 42 68 PCH_PWRGD R526 1 2 1K
SUS_PWR_ACK 7
1

1
603 KSO5 KSO6/PD6 ADC2/GPI2 LCD_CBL_DET# SUS_ON R536 2
41 KSO5/PD5 KEYBOARD ADC3/GPI3 69 LCD_CBL_DET# 24 1 100K
6.3 16 16 16 16 KSO4 40 70 INVERTER_CBL_DET# HWPG R180 100K
KSO4/PD4 ADC4/GPI4 INVERTER_CBL_DET# 24
KSO3 39 71 IMVP_VR_ON R215 *100K_NC
KSO3/PD3 ADC5/GPI5 PBAT_PRES# 53
KSO2 38 72
KSO2/PD2 ADC6/GPI6 IINP 45 +3.3V_RUN
Place these caps close to ITE8502. KSO1 37 ADC/DAC 73 SIO_SLP_S5#
KSO1/PD1 ADC7/GPI7 SIO_SLP_S5# 7
KSO0 36 KSO0/PD0 LCD_CBL_DET# R192 10K
DAC0/GPJ0 76 CRIT_TEMP_REP# 10 2 1
KSI7 65 77 INVERTER_CBL_DET# R194 2 1 10K
KSI7 DAC1/GPJ1 SIO_EXT_WAKE# 10
KSI6 64 78 USBP1_SIDE_EN# IRQ_SERIRQ R529 1 2 10K/F
KSI6 DAC2/GPJ2 USBP1_SIDE_EN# 33
KSI5 63 79 R200 1 2 0 LCD_BAK# R524 2 1 *10K_NC
KSI5 DAC3/GPJ3 LAN_PCIE_PWR_CTRL 10,41
KSI4 62 80
KSI4 DAC4/GPJ4 ICH_RSMRST# 7
KSI3 61 81 1 2
KSI3/SLIN DAC5/GPJ5 SIO_PWRBTN# 7 +3.3V_SUS
KSI2 60 D9 SDMK0340L-7-F
KSI1 KSI2/INT
59 KSI1/AFD
KSI0 58 SUS_PWR_ACK R183 10K
KSI0/STB AC_PRESENT R530 10K
PW M0/GPA0 24 BREATH_LED# 37
PW M1/GPA1 25 BAT2_LED# 37
R521 1 2 0 22 28
3,9,16,26,28,31,32,41 PLTRST# LPCRST/W UI4/GPD2 PW M2/GPA2 FAN1_PWM 38
9 CLK_PCI_8512 13 LPCCLK PW M3/GPA3 29 PWM_VADJ 24
8,32 LPC_LFRAME# 6 LFRAME PW M4/GPA4 30 BAT1_LED# 37
8,32 LPC_LAD0 10 LAD0 PW M5/GPA5 31 KB_BACKLITE_EN 36
9 PWM 32 +3.3V_RUN
8,32 LPC_LAD1 LAD1 PW M6/GPA6 USBP0_BUS_SW_CB 33
8,32 LPC_LAD2 8 LAD2 PW M7/GPA7 34 BEEP 39
8,32 LPC_LAD3 7 LAD3
47 R528 ICH_AZ_CODEC_RST0#
TACH0/GPD6 FAN1_TACH 38
7 CLKRUN# 93 CLKRUN/GPH0/ID0 TACH1/GPD7 48 PANEL_BKEN 17 100K
C SERIRQ IRQ_SERIRQ 5 LPC C
8 IRQ_SERIRQ SERIRQ

3
SC(V1.0)P38: D10 2 SDMK0340L-7-F
1 15 120 Q66
8.2-k pull-up to +V3.3S 10 SIO_EXT_SMI# ECSMI/GPD4 TMRI0/W UI2/GPC4 LID_SW# 36
D8 2 SDMK0340L-7-F
1 23 124 2 2N7002W-7-F
10 SIO_EXT_SCI# ECSCI/GPD3 TMRI1/W UI3/GPC6 SIO_SLP_S3# 7 R531

3
CRB uses a 10-k pull-up to +V3.3S. D12 2 SDMK0340L-7-F
1 126
10 SIO_A20GATE GA20/GPB5

1
17 8,39 ICH_AZ_CODEC_RST# 1 2 2

1
24 LCD_TST LPCPD/W UI6/GPE6 C706
D21 2 SDMK0340L-7-F
1 4 108 LCD_CONTRAST1 390K *0.1U_NC
10 SIO_RCIN#

2
WRST# KBRST/GPB6 RXD/GPB0 Q67 10
14 W RST TXD/GPB1 109 PAD T24
LCD_BAK# 16 119 MMST3904-7-F
24 LCD_BAK# PW UREQ/GPC7 GPC0
IR/UART CTX0/GPB2 123 RUN_ON_1 42
39 NB_MUTE# 19 L80HLAT/GPE0 CRX1/GPH1/ID1 94 HDDC_EN 35
ICH_AZ_CODEC_RST0# R519 0 20 95 IMVP_VR_ON
L80LLAT/W UI7/GPE7 CTX1/GPH2/ID2 IMVP_VR_ON 51

SMBCLK0
Board ID Straps
Charge and BAT 38,45,53 SMBCLK0 110 SMCLK0/GPB3
SMBDAT0 SUS_ON +3.3V_ALW
38,45,53 SMBDAT0 111 SMDAT0/GPB4 FLFRAME/GPG2/LF 100 SUS_ON 47,52 Discrete
FLRST/GPG0/TM 106 KB_DET# 36
SMBCLK1 115 104
CLK, LCD and Thermal 9 SMBCLK1
SMBDAT1 SMCLK1/GPC1 FLAD3/GPG6
9 SMBDAT1 116 SMDAT1/GPC2 SMBUS LPC/FWH
FLASH FLAD2/SO 103 EC_FLASH_SPI_DO 30
SMBCLK2 117 102
G_Thermal 19 SMBCLK2 SMCLK2/GPF6 FLAD1/SI EC_FLASH_SPI_DIN 30

1
SMBDAT2 118 101
19 SMBDAT2 SMDAT2/GPF7 FLAD0/SCE EC_FLASH_SPI_CS# 30
and Media button FLCLK 105 EC_FLASH_SPI_CLK 30
R217 R226 R223 R222
10K *10K_NC *10K_NC *10K_NC

T22 PAD 85

2
USB_CHG_DET#_R PS2CLK0/GPF0 PCH_PWRGD
37 USB_CHG_DET#_R 86 PS2DAT0/GPF1 EGAD/GPE1 82 PCH_PWRGD 7
EGPC 83 USB_BACK_EN#
EGCS/GPE2 ALW_ON 37,46
87 84 BID1
53 PS_ID PS2CLK1/GPF2 EGCLK/GPE3 GFX_ON 17,19,50
88 PS/2 CHIPSET_ID1
B T23 PAD PS2DAT1/GPF3 B
USBP0_SIDE_EN#
36 CLK_TP_SIO 89 PS2CLK2/GPF4

2
90 96 USBP0_SIDE_EN#
36 DAT_TP_SIO PS2DAT2/GPF5 GPH3/ID3 USBP0_SIDE_EN# 33
97 USB_BACK_EN#
GPH4/ID4 USB_BACK_EN# 34
GPIO 98 BID1 R216 R225 R224 R221
+3.3V_ALW GPH5/ID5 CHIPSET_ID1 *10K_NC 10K 10K 10K
GPH6/ID6 99
ITE8512_XTAL1 128 107 MODC_EN 35

1
CK32K GPG1/ID7
2

ITE8512_XTAL2 2 CK32KE
R527 1 18 UMA
VSS1 RI1/W UI0/GPD0 SATA_ACT# 8
D22 100K ITE8512IX_JX 12 21
VSS2 RI2/W UI1/GPD1 ACAV_IN 37,45
1 2 WRST# 27 35
38,46 THERM_STP# PCB_BEEP_EN 39
1 1

VSS3 W UI5/GPE5
49 VSS4
SDMK0340L-7-F C707 91 112 AC_PRESENT 7 VGA_IDENTIFY
1U VSS5 RING/PW RFAIL/LPCRST/GPB7
113 VSS6
603 +3.3V_ALW 122 125 SYS_PWR_SW# 37
2

10 L59 BLM11A05S VSS7 PW RSW /GPE4

BID0
74 AVCC GINT/GPD5 33 LCDVCC_TST_EN 24
603 75 CHIPSET_ID1 BID1 USB_BACK_EN# FM9B(UMA) FM9 (Dis)
AVSS
2

C705 0 0 0 SSI (X00) SSI (X00)

0.1U ITE8502E 0 0 1 PT (X01) PT (X01)
32KHz Clock. L61 lqfp128-16x16-4-nb1 0 1 0 ST (X02) ST (X02)
1

16 0 1 1 QT (A00) QT (A00)
ITE8512_XTAL2 603 1 0 0 (A01) (A01)
BLM11A05S 1 0 1

A CLK_PCI_8512 ITE8512IX_JX A
W1 +3.3V_RUN
4 1 ITE8512_XTAL1
R203
QUANTA
2

3 2 10 C361
0.1U R227
C714 32.768KHZ C712 *10K_NC
COMPUTER
1

18P/50V 18P/50V 16
1

50 50 R219 *0_NC Title

1

C352 LCD_CONTRAST1 1 2 Ultra I/O Controller ECE5028

LCD_CONTRAST 24
2.2P
2

Size Document Number Rev

50 FM9 1A

Date: Wednesday, March 04, 2009 Sheet 29 of 64

5 4 3 2 1
 5 4 3 2 1

For EC 16Mbit (2M Byte), SPI/ RTC BATTERY

+3.3V_ALW +3.3V_ALW
32Mbit (4M Byte), SPI +RTC_CELL +3.3V_ALW +PWR_SRC

1
R540

1
10K
R542 U29
U39 10K 1 2 3 1

2
D23 OUT IN
29 EC_FLASH_SPI_CS# 1 CE# VDD 8 4 5/3#
R541 1 2 15 EC_FLASH_SPI_CLK_R 6 SDMK0340L-7-F
29 EC_FLASH_SPI_CLK

2
SCK

1
D D
R537 1 2 15 EC_FLASH_SPI_DIN_R 5 C491 2 GND C484
29 EC_FLASH_SPI_DIN
R543 1 SI SHDN 5
29 EC_FLASH_SPI_DO 2 15 EC_FLASH_SPI_DO_R 2
SO HOLD# 7 2.2U/6.3V/0603 *1U_NC
603 *MAX1615EUK-T+_NC 805

2
2
C711 3 4 6.3 25
22P W P# VSS C371
SST25VF016B-50-4C-S2AF 0.1U

1
50 BT1
16 1 2 +RTC_1 1 2 +RTC 2
D25 R597 1K 1
SDMK0340L-7-F

2
C753 AAA-BAT-019-K01 RTC-BATTERY
1U
603

1
10

For PCH 16Mbit (2M Byte), SPI/

32Mbit (4M Byte), SPI

+3.3V_RUN +3.3V_RUN

C C

R550
10K
R544
U40 10K +3.3V_RUN
iTPM ENABLE/DISABLE
SPI_CS0# R548 15 SPI_CS0#_R 1 8
8 SPI_CS0# CE# VDD
SPI_CLK R551 15 SPI_CLK_R 6
8 SPI_CLK SCK
SPI_SI R547 15 SPI_SI_R 5 R552 *1K_NC SPI_SI
8 SPI_SI SI
SPI_SO R549 15 SPI_SO_R 2 7
8 SPI_SO SO HOLD#
C723 3 4
22P W P# VSS C719 TPM Function R712
SST25VF016B-50-4C-S2AF 0.1U
50 Enable Mount
10
Disable NC
(Default)

B B

A A

QUANTA
Title
COMPUTER
Ultra I/O Controller ECE5028

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 30 of 64

5 4 3 2 1
 1 2 3 4 5 6 7 8

A A

B B

MiniCard WWAN connector

+3.3V_RUN +3.3V_RUN +1.5V_RUN

J13

7,28,32,41 PCIE_WAKE# 1 W AKE# 3.3V_1 2

T74 PAD 3 RESERVED_1 GND0 4
T73 PAD 5 RESERVED_2 1.5V_1 6
CLK_PCIE_REQ1# 7 8 UIM_PWR
9 CLK_PCIE_REQ1# CLKREQ# UIM_PW R
9 10 UIM_DATA
GND1 UIM_DATA UIM_CLK
9 CLK_PCIE_MINI2#
11 REFCLK- UIM_CLK 12
13 14 UIM_RESET
9 CLK_PCIE_MINI2 REFCLK+ UIM_RESET UIM_VPP
15 GND2 UIM_VPP 16
L42
C C
USBP5 D+ 1 2 ICH_USBP5+ 9
17 18 USBP5 D- 4 3 ICH_USBP5- 9
UIM_C8 GND3
19 UIM_C4 W _DISABLE# 20 WWAN_RADIO_DIS# 10
21 22 *PLW3216S900SQ2T1_NC
GND4 PERST# PLTRST# 3,9,16,26,28,29,32,41
9 PCIE_RX1- 23 PERn0 3.3VAUX1 24 +3.3V_RUN Layout Note:
9 PCIE_RX1+ 25 PERp0 GND5 26 R359 and R358
27 GND6 1.5V_2 28 1 2 close to choke
29 GND7 SMB_CLK 30 WLAN_SMBCLK 28,32,35 R344 0
PCI-Express TX and RX 31 32 as possible to
9 PCIE_TX1- PETn0 SMB_DATA WLAN_SMBDATA 28,32,35 minimize stubs.
direct to connector 9 PCIE_TX1+ 33 PETp0 GND8 34 1 2
35 36 USBP5 D- R345 0
GND9 USB_D- USBP5 D+
10 PCIE_MCARD2_DET# 37 RESERVED_3 USB_D+ 38
39 RESERVED_4 GND10 40 USB_MCARD2_DET# 10
41 RESERVED_5 LED_W W AN# 42 PAD T72
43 RESERVED_6 LED_W LAN# 44
45 RESERVED_7 LED_W PAN# 46
47 RESERVED_8 1.5V_3 48 +1.5V_RUN +3.3V_RUN Place caps close to connector.
49 RESERVED_9 GND11 50
51 RESERVED_10 3.3V_2 52

1
1

1
LTS_AAA-PCI-092-K01 C487 C759 C760 C758 C755 C754 + C494 + C493
0.047U 33P 33P 0.047U 33P 0.047U 100U *330U_NC
7343

2
10 50 50 10 50 10 6.3 6.3

ESD3
JSIM1 UIM_RESET UIM_VPP UIM_PWR
1 1 6 6
UIM_PWR 5 6 2 5 UIM_PWR
VCC GND UIM_CLK 2 5 UIM_DATA
D 3 3 4 4 D
UIM_RESET 3 4 UIM_VPP
RST VPP
2

C505 C509 C506 C508 C507

UIM_CLK 1 2 UIM_DATA 33P 33P IP4220CZ6 33P 33P 1U
CLK DATA 603 QUANTA
1

50 50 50 50 10

TYC_1747314-1
Title
COMPUTER
MINI-PCI

Place as close as possible to JSIM1 connector Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 31 of 64

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

MiniCard WLAN connector

+3.3V_RUN +3.3V_RUN +1.5V_RUN

J12 It is for debug only L37

it is can remove at QT. USBP4 D- 1 2 ICH_USBP4- 9
1 2 USBP4 D+ 4 3 ICH_USBP4+ 9
A 7,28,31,41 PCIE_WAKE# W AKE# 3.3V_1 A
COEX2_WLAN_ACTIVE 3 4
COEX1_BT_ACTIVE_MINI RESERVED_1 GND0 *PLW3216S900SQ2T1_NC
5 RESERVED_2 1.5V_1 6
MINI1CLK_REQ# MINI1CLK_REQ# 7 8 R562 1 2 0 1206
9 MINI1CLK_REQ# CLKREQ# UIM_PW R LPC_LFRAME# 8,29
9 10 R561 1 2 0
GND1 UIM_DATA LPC_LAD3 8,29
1

11 12 R560 1 2 0 1 2
9 CLK_PCIE_MINI1# REFCLK- UIM_CLK LPC_LAD2 8,29
C740 13 14 R559 1 2 0 R283 0
9 CLK_PCIE_MINI1 REFCLK+ UIM_RESET LPC_LAD1 8,29
220P 15 16 R558 1 2 0
LPC_LAD0 8,29
2

GND2 UIM_VPP
It is for debug only 1 2
50 it is can remove at QT. R282 0

R312 1 2 0 17 18
3,9,16,26,28,29,31,41 PLTRST# R311 1 UIM_C8 GND3
9 CLK_LPC_DEBUG 2 0 CLK_LPC_DEBUG_R 19 UIM_C4 W _DISABLE# 20 WLAN_RADIO_OFF#
21 GND4 PERST# 22 PLTRST# 3,9,16,26,28,29,31,41
9 PCIE_RX2- 23 PERn0 3.3VAUX1 24 +3.3V_RUN
9 PCIE_RX2+ 25 PERp0 GND5 26
27 GND6 1.5V_2 28
29 30 WLAN_SMBCLK_C 1R280 02 WLAN_SMBCLK
GND7 SMB_CLK WLAN_SMBDATA_C WLAN_SMBDATA
PCI-Express TX and RX 9 PCIE_TX2-
31 PETn0 SMB_DATA 32 1 2
direct to connector 33 34 R279 0 +3.3V_RUN
9 PCIE_TX2+ PETp0 GND8 USBP4 D-
35 GND9 USB_D- 36
37 38 USBP4 D+
10 PCIE_MCARD1_DET# RESERVED_3 USB_D+
39 RESERVED_4 GND10 40 USB_MCARD1_DET# 9

4
2
41 RESERVED_5 LED_W W AN# 42
43 RESERVED_6 LED_W LAN# 44
45 46 RP7
T67 PAD RESERVED_7 LED_W PAN# 2.2KX2
Non-iAMT T69 PAD 47
49
RESERVED_8 1.5V_3 48
50 Q48
T66 PAD RESERVED_9 GND11

2
51 52 2N7002W-7-F

3
1
RESERVED_10 3.3V_2
B WLAN_SMBCLK 1 3 ICH_SMBCLK 9,41,60 B
28,31,35 WLAN_SMBCLK
LTS_AAA-PCI-092-K01

1 2
Suport for WoW R297 *0_NC
+1.5V_RUN +3.3V_RUN Place caps close to connector.
WLAN_RADIO_OFF# 2 1 +3.3V_RUN
WLAN_RADIO_DIS# 10
D17 Q49

2
SDMK0340L-7-F 2N7002W-7-F
1

2
+ C432
1 2 Prevent backdrive when C733 C736 C735 C737 C734 C742 C748 *330U/6.3V_NC WLAN_SMBDATA 1 3
28,31,35 WLAN_SMBDATA ICH_SMBDATA 9,41,60
R298 *0_NC 0.047U 0.047U 0.1U 0.047U 0.1U 0.047U 4.7U 7343
WoW is enabled.
2

2
805 6.3
10 10 16 10 16 10 10

1 2
R296 *0_NC

C C
+3.3V_RUN

C490 0.1U Support Dell BT365 (Little Stone) module

2 1
Bluetooth BTB Conn
L43
USBP8 D- 1 2 ICH_USBP8- 9
J8 USBP8 D+ 4 3 ICH_USBP8+ 9
COEX1_BT_ACTIVE_MINI 2 1
COEX1_BT_ACTIVE BT_DET# PAD T39
*PLW3216S900SQ2T1_NC
4 3 COEX2_WLAN_ACTIVE 1206
3.3V COEX2_W LAN_ACTIVE
USBP8 D+ 6 5 1 2
USB+ NC R348 0
USBP8 D- 8 7
USB- HW _RADIO_DIS# BT_RADIO_DIS# 10
1 2
10 9 R349 0
GND BT_ACTIVE
1

C489 12 11
GND NC
2

0.1U 14 13
GND NC
2

C495
R361 C496 100P
2

1-2041112-4 10K 33P

2

H23
H-TC232BC138D122P2
1

H-TC232BC138D122P2

D D
1

QUANTA
Title
COMPUTER
MDC CONN.

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 32 of 64

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

Side External USBX2

PN is old, Because New Part can't ready before SST build.
External USB PORT hookup reference. Your design may
need more or less external ports and may be mapped
differently
+USB_SIDE_PWR_CHARGE 1 9
USBP0 D- VBUS GND ESATA_TX4+_C C659 0.01U/16V ESATA_TX4+_R
2 D- A+ 10
DLW21HN900SQ2L USBP0 D+ 3 11 ESATA_TX4-_C C655 0.01U/16V ESATA_TX4-_R
ICH_USBP0+_R USBP0 D+ D+ A-
1 2 4 GND GND 12

1
ICH_USBP0-_R 4 3 USBP0 D- C282 13 ESATA_RX4-_C C658 0.01U/16V ESATA_RX4-_R
150P C279 B- ESATA_RX4+_C C654 0.01U/16V ESATA_RX4+_R
A B+ 14 A
L57 1206 25 0.1U 5 15

2
NPO USBP1 D- VBUS GND USB_CHG_DET#
6 D- DET# 16 USB_CHG_DET# 37
10 USBP1 D+ 7 17
D+ Shield
1 2 8 GND Shield 18
R456 *0_NC +USB_SIDE_PWR 19
Shiled
Shield 20
1 2

1
R457 *0_NC JUSB1
C266 C265 APPLING
150P 0.1U

2
DLW21HN900SQ2L 25
ICH_USBP1+ 1 2 USBP1 D+ NPO 10
9 ICH_USBP1+
ICH_USBP1- 4 3 USBP1 D- Please put those on the same side of MB PCB
9 ICH_USBP1-
L58 1206
USBx2 & ESATA COMBO & PWR CHARGE
1 2
R467 *0_NC

1 2
USB BUS SW CB EN# Function
R471 *0_NC +USB_SIDE_PWR_CHARGE +5V_ALW
C261 0.1U X H Disconnect
1 2
Platforms should put in PADS for the USB chokes if they L L COM_=NC_

2
have the room. Chokes should be NOPOP. H L COM_=NO_
R96 R92 U7
75K_F 43.2K_F
B 9 VCC
B
3 ICH_USBP0+_R

1
RES_DIV_D+ COM1 ICH_USBP0-_R
1 NC1 COM2 5
RES_DIV_D- 7
Place ESD diodes as close as USB connector. NC2

2
9 ICH_USBP0+ 2 NO1
R91 6 8 USB_CHG_DET#_C 1 2 USB_CHG_DET#
9 ICH_USBP0- NO2 EN
ESD2 49.9K_F R93 R85 0

2
USBP0 D- 1 6 USBP1 D+ 49.9K_F 10 4
1 6 29 USBP0_BUS_SW_CB CB GND
2 5 +USB_SIDE_PWR R88

1
USBP0 D+ 2 5 USBP1 D-
3 3 4 4 *0_NC
MAX4983EEVB+
*SRV05-4.TCT_NC

1
(5V)-43.2K-(D-)-49.9K-GND (about 2.68V)
(5V)-75.0K-(D+)-49.9K-GND (about 2.00V)
Place one 150uF cap by each
USB connector.
+5V_SUS

U8 Each channel is 1A E-SATA Re-driver Please put those on the same side of MB PCB
2 1 +3.3V_RUN Note: Boost:5dB, Standard SATA:0dB
IN GND
EN D0 D1 CH : 0 CH : 1
3 7 +USB_SIDE_PWR
29 USBP1_SIDE_EN# EN1# OUT1
8 OC0# 0 X X Standby Standby
OC1# OC0# 9
C289 C288 C663 +3.3V_RUN
1

4 6 +USB_SIDE_PWR 1U 0.1U/ 10V 0.01U 1 0 0 Standard SATA Standard SATA

C
C644 C649 EN2# OUT2 25 C
OC2# 5
*10U_NC 0.1U 1 1 0 Boost Standard SATA
2

805
10 10 TPS2062AD + C648 1 0 1 Standard SATA Boost
150U
1 1 1 Boost Boost

20

10

16

24

25

26
6
6.3 U12

VCC

VCC

VCC

VCC

GND

GND

GND
8 SATA_TX4+ C304 0.01U/16V ESATA_TX4+_L 1 15 ESATA_TX4+_R
+5V_ALW RX_0P TX_0P
C300 0.01U/16V ESATA_TX4-_L 2 14 ESATA_TX4-_R
U6 +USB_SIDE_PWR_CHARGE 8 SATA_TX4- RX_0N TX_0N
2 1 C296 0.01U/16V ESATA_RX4-_L 4 12 ESATA_RX4-_R
IN GND 8 SATA_RX4- TX_1N RX_1N +3.3V_RUN
8 SATA_RX4+ C293 0.01U/16V ESATA_RX4+_L 5 11 ESATA_RX4+_R
+USB_SIDE_PWR_CHARGE TX_1P RX_1P
29 USBP0_SIDE_EN# 3 EN1# OUT1 7
8 OC0# ESATA_BUS_SW_EN 7 9 R107 *4.7K_NC
OC1# EN D0

GND

GND

GND

GND

GND

GND

GND

GND
1

4 6 +USB_SIDE_PWR_CHARGE 8 R108 *4.7K_NC

C260 C245 EN2# OUT2 D1
OC2# 5
*10U_NC 0.1U SN75LVCP412
2

17

19

18

13

21

22

23

2
805 +3.3V_RUN
10 10 TPS2062AD + C625 R103 R104
150U 0 0
1

6.3
R84

1
Need to add control pin to control PUSB charge 100K

D D
2

ESATA_BUS_SW_EN
3

Support USBP1 charge function.

JUSB1 need to add USB_CHG_DET# pin wire to EC GPIO to detect USB device.
USB_CHG_DET# 2 Q21
2N7002W-7-F
QUANTA
COMPUTER
1

Title
SERIAL PORT & USB

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 33 of 64

1 2 3 4 5 6 7 8
 5 4 3 2 1

D D

LN1 1206
ICH_USBP2- 4 3 USBP2 D-
9 ICH_USBP2-
ICH_USBP2+ 1 2 USBP2 D+
9 ICH_USBP2+
DLW21HN900SQ2L

R106 *0_NC
1 2

R105 *0_NC
1 2

Place one 150uF cap by each

C C
USB connector.
+5V_SUS
U33 Each channel is 1A
2 IN GND 1

3 7 +USB_BACK_PWR
29 USB_BACK_EN# EN1# OUT1
OC1# 8 OC1# 9
4 6 +USB_BACK_PWR
EN2# OUT2

1
OC2# 5
C564 C578
*10U_NC 0.1U

2
805 TPS2062AD + C626
10 16 150U
6.3

J6
Place ESD diodes as close as USB connector. +USB_BACK_PWR 1 1

1
B B
USBP2 D+ 2
ESD1 C257 C248 USBP2 D- 2
3 3
USBP2 D- 1 6 150P 0.1U 4

2
1 6 +USB_BACK_PWR 25 4
2 2 5 5
USBP2 D+ 3 4 NPO 16 1775295-4
3 4
*SRV05-4.TCT_NC

A A

QUANTA
Title
COMPUTER
Right USB

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 34 of 64

5 4 3 2 1
 1 2 3 4 5 6 7 8

CON4
SATA Connector. DG: Place TX cap close to connector ODD Connector
GND1 1
RXP 2 SATA_TXP0_C C725 0.01U/16V SATA_TX0+ 8 CN4
DG: Place TX cap close to connector
3 SATA_TXN0_C C727 0.01U/16V SATA_TX0- 8
RXN S1
GND2 4 GND1 1
5 SATA_RXN0_C C728 0.01U/16V 2 SATA_TXP1_C C709 0.01U/16V SATA_TX1+ 8
TXN SATA_RX0- 8 TXP
6 SATA_RXP0_C C729 0.01U/16V 14 3 SATA_TXN1_C C708 0.01U/16V SATA_TX1- 8
TXP SATA_RX0+ 8 14 TXN
GND3 7 GND2 4
5 SATA_RXN1_C C704 0.01U/16V
RXN SATA_RX1- 8
6 SATA_RXP1_C C703 0.01U/16V
RXP SATA_RX1+ 8
A 3.3V_0 8 +3.3V_RUN GND3 7 A
9 S7
3.3V_1 P1
3.3V_2 10 DP 8
GND4 11 +5V 9
GND5 12 +5V 10 +5V_MOD
GND6 13 15 15 MD 11
5V_0 14 +5V_HDD GND 12
5V_1 15 GND 13
16 P6
5V_2 48325-1106
GND7 17
RSVD 18
GND8 19
12V_0 20
12V_1 21
12V_2 22

67492-1441

+3.3V_RUN Place caps close to connector.

Place caps close to connector.
+5V_MOD

C739 C459 C449 C456 C457

*10U/10V/0805_NC *1U/10V/0603_NC *0.1U/16V_NC *0.1U/16V_NC *1000P_NC C666 C672 C676 C682 C679

B *10U/10V/0805_NC 1U/10V/0603 0.1U/16V 0.1U/16V 1000P B

Place caps close to connector.

+5V_HDD

C468 C466 C470 C471 C476 C473

10U 1U/10V/0603 0.1U/16V 0.1U/16V 0.1U/16V 1000P

+5V_RUN +5V_MOD +5V_RUN

+5V_RUN +5V_HDD +5V_RUN Q64

*SI4800BDY-T1-E3_NC
Q50 8 3 R173 0
*FDC655BN_NC 7 2 1 2
6 R334 0 +3.3V_ALW 6 1 805
5 4 1 2 5

1
2 805 C335
1

1 *10U_NC

4
2

1
805 R184

2
C480 R340 R523 10 *100K_NC
3

+3.3V_ALW +15V_ALW *4.7U_NC *100K_NC *100K_NC R520

1

2
603 +15V_ALW 2 1 MOD_EN_5V
2

6.3 *100K_NC

2
1

6
C C
R343
R360 2 1 HDD_EN_5V 2
*100K_NC Q65B
*100K_NC
*2N7002DW-7-F_NC

1
6

3
2

1
2 29 MODC_EN 5
Q51B Q65A C345

1
*2N7002DW-7-F_NC *2N7002DW-7-F_NC *0.1U_NC
1

2
3

603
R518
1

5 25
29 HDDC_EN *100K_NC
Q51A C488
1

*2N7002DW-7-F_NC *0.1U_NC
4

2
603
R356 25
*100K_NC
2

3-axis Fall Sensor (HDD data protector)

+3.3V_RUN U13

1 VDD_IO SCL 14 WLAN_SMBCLK 28,31,32

1

D C307 C306 2 13 D
GND1 SDA WLAN_SMBDATA 28,31,32
10U 0.1U/10V
603 3 12
2

6.3 Reserved1 SDO

4 GND2 Reserved2 11 QUANTA
5

6
GND3 GND4 10

9 Title
COMPUTER
VDD INT2 SATA (HDD&CD_ROM)
DE351DL is ST vender for DELL Part Number 7 8 R117 0
Vender PN: LIS302DLTR CS INT1 PCH_IRQH_GPIO5 9
Size Document Number Rev
Quanta PN: AL000302A00 FM9 1A
DE351DLTR
Date: Wednesday, March 04, 2009 Sheet 35 of 64
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

KEYBOARD CONNECTOR
+5V_RUN +3.3V_ALW R47 1 2 10K
+3.3V_ALW +3.3V_ALW
JKB1
Touch Pad

GND1
29 KB_DET# 1

2
KSI7
2

1
3
R195 KSI6
RP3 100K KSI4 3
KSI2 4
4.7KX2 KSI5 5

1
KSI1 6
A
JP1 KSI3 7 A
29 KSO[0..16]

2
4
KSI0 8
29 LID_SW# 9
1 KSO5
1 29 KSI[0..7] 10
L28 1 2 BLM18AG601SN1D TP_CLK 2 KSO4
29 CLK_TP_SIO 2 11
603 3 KSO7
L29 1 3 12
29 DAT_TP_SIO 2 BLM18AG601SN1D TP_DATA 4 4
KSO6
13
603 5 KSO8
5 KSO3 14
+5V_RUN 6 6 15
KSO1
88513-064N KSO2 16
17
1

1
C355 C360 KSO0
10P/50V 10P/50V C363 C353 C359 C362 C343 C356 KSO12 18
10P/50V 10P/50V 0.1U 0.047U 0.047U 0.1U KSO16 19
2

2
50 50 KSO15 20
50 50 16 10 10 16 KSO13 21
KSO14 22
KSO9 23
KSO11 24
KSO10 25
26
27
28

GND2
29
30
FH28-60(30)SB-1SH(86)

B B

CP2 *100PX4_NC CP1 *100PX4_NC

C89 *100P_NC KSI7 8 7 KSO12 8 7 KSO14
50 6 5 KSO16 6 5 KSO9
4 3 KSO15 4 3 KSO11
2 1 KSO13 2 1 KSO10

1206 50 1206 50

CP4 *100PX4_NC CP3 *100PX4_NC

8 7 KSO4 8 7 KSO3
6 5 KSO7 6 5 KSO1
4 3 KSO6 4 3 KSO2
2 1 KSO8 2 1 KSO0

1206 50 1206 50

CP6 *100PX4_NC CP5 *100PX4_NC

8 7 KSI6 8 7 KSI1
6 5 KSI4 6 5 KSI3
4 3 KSI2 4 3 KSI0
2 1 KSI5 2 1 KSO5
C C
1206 50 1206 50

100P CAPS CLOSE TO JKB1

Key board illumination

+KB_LED power trace width >10 mil +KB_LED

J5 +KB_LED
R60 100K 1
+5V_RUN +KB_LED 1
8 KB_LED_DET 1 2 2 2
1206L050YR 3 3

1
1 2 LED_PWM 4
FS1 1206 4 C129
R52 88513-044N 0.1U

2
200K
16

2
Q17
SI2304BDS-T1-E3

D LED_PWM 3 1 D

2
QUANTA
Title
COMPUTER
29 KB_BACKLITE_EN
TOUCH PAD, BULE TOOTH & FIR

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 36 of 64

1 2 3 4 5 6 7 8
 A B C D E

Touch Screen Module Note:

1. VBUS IND:VBUS indication should be supplied
to single the DuoSense to connect
According to the USB 2.0 specification.
A GND voltage from the host should indicate
+3.3V_RUN a connection.

J2
2. Maximum cable resistance on VCC, GND should be
150m ohm.
Power button Cable
1 3. FPC cable should support 12MHz USB singles.
USBP12 D- A tri-state should indicate no connection.
USBP12 D+ 2 J4
4 3 4
4 1 1
BREATH_PWRLED 2
5 POWER_ SW_IN0# 2
3 3
4 4
87212-05G0
1775295-4

Need check the connector footprint and symble.

9 ICH_USBP12+ 1
4
L1
2
3
USBP12 D+
USBP12 D- +3.3V_ALW
3VALW ON POWER LOGIC
9 ICH_USBP12-
*PLW3216S900SQ2T1_NC
+3.3V_ALW

2
1206
1 2 R209
R5 0 100K

1 2 D11

2
R3 0 +5V_ALW2
R233
33 USB_CHG_DET# USB_CHG_DET#_R 29
100K
BAS316

1
Battery status.

2
R237 R239
D13
3 100K 100K 3

+5V_ALW SYS_PWR_SW# 29
+3.3V_ALW +3.3V_ALW

1
BAS316

1
1

02/12 C372
1

R29 0.1U

2
100K POWER_ SW_IN0# 16
3.3V_ALW_ON 46
2

47K
2

1 3 2 Q8
29 BAT1_LED#
10K D14

3
Q7 DDTA114YUA-7-F
2N7002W-7-F 2 Q43
2N7002W-7-F
3

1
BAS316

1
BAT1_LED
D15
R23 2 1 220 RBAT1_LED 53 C380
*0.1U_NC

2
10
BAS316

3
2 Q44
29,46 ALW_ON
+3.3V_ALW 2N7002W-7-F

1
3
2 Q42
29,45 ACAV_IN
1

2
2N7002W-7-F 2

1
47K
2 Q11
29 BAT2_LED#
10K
DDTA114YUA-7-F
3

BAT2_LED
R37 2 1 68 RBAT2_LED 53

+3.3V_ALW

BREATH_LED# C69 *100P_NC 50

1

2
POWER_ SW_IN0# C35 *100P_NC 50
+3.3V_SUS +5V_SUS +5V_SUS *DA204U_NC
D3
3

R33 POWER_ SW_IN0#

100K
2

R31 100
1 1 3 2 4 BR_LED 1 2 BREATH_PWRLED 1
29 BREATH_LED#
Q14 U3
2N7002W-7-F TC7SZ04FU(T5L,F,T)
QUANTA
3

Title
COMPUTER
SWITCH, KEYBOARD & LED&Touch Screen Module

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 37 of 64

A B C D E
 1 2 3 4 5 6 7 8

A A

+3.3V_RUN
D18
*SSM34PT_NC
1 2
+5V_RUN
J11

2
+5V_RUN 4 4

2
FAN1_PWM 3 R109 R102 Q23
29 FAN1_PWM 3
2 2 1 3 SMBCLK0 29,45,53
2

1 1 *DA204U_NC
C510 C513
2.2U 0.1U MLX_53398-0471 D19 2N7002W-7-F +3.3V_RUN
1

805 10K 10K

3
16 16

2
EC_SMBCLK0
13,14,15 EC_SMBCLK0
FAN1_PWM Q62
+5V_RUN R381 4.7K EC_SMBDAT0 1 3
FAN1_TACH 29 13,14,15 EC_SMBDAT0 SMBDAT0 29,45,53
2N7002W-7-F

B B

Place under CPU 10/20mils

REM_DIODE1_P
+3.3V_RUN
U9
3

1
C620 C291 1 8 EC_SMBCLK0
Q61 *2200P_NC 2200P VDD SCL
2
MMST3904-7-F 2 7 EC_SMBDAT0
2

2
DP SDA
1

50 REM_DIODE1_N 50 3 6 THERM_ALERT#
DN ALERT#
4 SYS_SHDN# GND 5

1.Place C160 close to EMC1422 EMC1422-1-ACZL-TR

2.Place C518 to be close to Q51
1
Total capacitance between D+/D- is 2200pF(max)
C285
if use 2200pF for C160, then C518 should be dummy 0.1U SYS_SHDN#
THERM_STP# 29,46
2

10
+3.3V_RUN

1
C C
R113
1M

3
Q25
OTP 85 degree C
2

2 2N7002W-7-F

1
3

1 +3.3V_RUN R110 1 2 10K/F THERM_ALERT#

2 C303
0.1U R114 1 2 6.8K/F SYS_SHDN#
2

Q24
1

2N7002W-7-F 10

D D

QUANTA
Title
COMPUTER
FAN & THERMAL

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 38 of 64

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+5V_SPK_AMP LIN- RIN- HP2_OUT_L HP2_OUT_R J3

AUD_SPK_R1 R389 2 1 0 603 1
1

1
C680 C695 C687 C684 +5V_SPK_AMP AUD_SPK_R2 R387 2 1 0 603 2
2

2
*47P_NC *47P_NC 220P 220P AUD_SPK_L1 R386 2 1 0 603 3
R515 R514 AUD_SPK_L2 R388 0 603 3
2 1 4

2
100K *100K_NC 50 50 50 50 4
R159 1775295-4

2
100K

1
AUD_AMP_GAIN1 C64 C63 C62 C61
AUD_AMP_GAIN2 Check it is ok at ST, 100P 100P 100P 100P
GAIN1 GAIN2 GAIN

1
R140 *0_NC if it is ok then remove it.

2
0 0 6dB REGEN AUD_AMP_MUTE# 50 50 50 50

1
R512 R511
A A
*100K_NC 100K 0 1 10dB C308
0.068UF

2
1 0 15.6dB 16

1
R509 1 2 *0_NC 1 1 21.6dB

R336 4.99K/F +3.3V_RUN

2 1
VDD +5V_SPK_AMP
INTERNAL SPEAKER AMP +3.3V_RUN

1
+5V_SPK_AMP C435

1
C483 0.1U/10V 0.1U C440

1
C661 C665 C670 U14 U24 0.1U
1 2

2
1U 1U 0.1U 16 TC7SZ08FU(T5L,F,T)

2
C477

5
C479 0.015U U28A 603 603 AUD_FRONT_L C690 1 2 0.068U 1206 50 LIN- 3 6 AUD_SPK_L1 16

2
SPKR_INL+ OUTL+

5
AUD_FRONT_L_1 3 MAX4492AUD+ 10 10 16 Layout Note: AUD_FRONT_R C698 1 2 0.068U 1206 50 RIN- 2 7 AUD_SPK_L2 NB_MUTE# 1
VDD
AUD_FRONT_L 2.2U 1206 25 SPKR_INR+ OUTL- AMP_HP1_SHUD_L#
1 Place close 4 1
2 AUD_HP2_L0 C668 2 1 AUD_HP2_L0_R 1 R502 2 2.2K HP2_OUT_L 27 20 AUD_SPK_R1 HP1_JD 2 4
0.1U/16V R339
VSS
U18 pin 23. AUD_HP2_R0 C667 2 1 AUD_HP2_R0_R 1 R501 2 2.2K HP2_OUT_R 26
HP_INL
HP_INR
TPA6040A4 OUTR+
OUTR-
19 AUD_SPK_R2 EAPD# 2
AMP_HP1_SHUD# 40
BUFFER_VIAS 1 2 2.2U 1206 25 U25
QFN 32PIN

11

3
40 BUFFER_VIAS
C328 1 2 1U 603 10 24 16 TC7SZ08FU(T5L,F,T)

3
BIAS HPL AUD_HP2_L1 40
14K/F AUD_SPK_ENABLE# 23 15
SPKR_EN# HPR AUD_HP2_R1 40
Layout Note: AMP_HP2_EN 22
R193 +VDDA AUD_AMP_MUTE# HP_EN REGEN R492 1 +VDDA
25 4 2 0
Close to U18 Pin 34 5.1K/F AUD_AMP_GAIN1 31
MUTE# SPKR_INL-
1 SET R500 1 2 0 AUD_PC_BEEP
SENSEB +3.3V_RUN AUD_AMP_GAIN2 GAIN1 SPKR_INR-
1 2 32
GAIN2
29
VOUT
17 +5V_SPK_AMP
HPVDD

1
C332 9 30 VDD +5V_SPK_AMP C696 C697
R513 1 CPVDD VDD
B 2 *0_NC R186 R179 1000P 8 1U 1U B
PVDD_8

1
20K/F 39.2K/F C305 C299 C298 1 2 1U 10 18 603 603

2
50 10U 1U 805 16 C1P PVDD_18 10 10
12

1
805 603 C1N C674 C673 C664
11 28 Layout Note:

3 2

3 2

2
R350 4.99K/F 10 10 CPGND GND_28 1U 10U 0.1U
5
2 1 14
PGND_5
21 603 805 Place close U18.

2
PVSS PGND_21 10 10 16
40 HP2_JD 2 2 MIC1_JD 40 13
CPVSS

2
+5V_SPK_AMP
Q33 Q30 C297

1
2N7002W-7-F 2N7002W-7-F 1U TPA6040A4

1
C486
4

C485 0.015U U28B 805 Layout Note: +3.3V_RUN

AUD_FRONT_R_1 5 MAX4492AUD+ 16
VDD
7 AUD_FRONT_R Place close to +3.3V_RUN

1
6 pin 18. C331

1
0.1U/16V R341
VSS
0.1U U17 C315
+3.3V_RUN
FB_60ohm+-25%_100MHz +VDDA
BUFFER_VIAS 1 2 R142 +VDDA TC7SZ08FU(T5L,F,T) 0.1U
11

2
5.1K/F _3A_0.05ohm DC 10
AZALIA (HD) CODEC

2
5
14K/F SENSEA 1 2 DVDD 10

5
NB_MUTE# 1

1
C694 C699 C681 C702 C675 4 AMP_HP2_EN_L 1
U16
1

1
C662 1U 1U 0.1U 1U 0.1U HP2_JD 2 4 AMP_HP2_EN
R478 1000P 10 10 10 16 EAPD# 2

2
39.2K/F 603 603 16 1 25 603 U15

3
50 DVDD_CORE AVDD TC7SZ08FU(T5L,F,T)
9 38

3
DVDD_CORE AVDD
2 1 40
3 2

DVDD

2
Depop R479,C699 R516
*100K_NC 13 SENSEA
2
for using 92HD73C C701 SENSE_A
34 SENSEB

1
HP1_JD 40 SENSE_B +VDDA +5V_SPK_AMP +5V_RUN
*1000P_NC 50
Q26 ICH_AZ_CODEC_BITCLK 6 R170 *2.2K_NC
1

C 8 ICH_AZ_CODEC_BITCLK HDA_BITCLK C
2N7002W-7-F R165 1 2 33 AZ_CODEC_SDIN0 8 SET 2 1
8 ICH_AZ_CODEC_SDIN0 HDA_SDI BLM21PG600SN1D
Layout Note: 5 39 L27
8 ICH_AZ_CODEC_SDOUT HDA_SDO PORT_A_L AUD_HP1_L 40
Close to U19 Pin 13 8 ICH_AZ_CODEC_SYNC 10 41 AUD_HP1_R 40

1
HDA_SYNC PORT_A_R C314 R168
8,29 ICH_AZ_CODEC_RST# 11
HDA_RST# NC/VREFOUT_A
37 FB_60ohm+-25%_100MHz
0.068UF *0_NC C337 C338
21 1U 10U _3A_0.05ohm DC

2
PORT_B_L 16 603 805
AUD_SPK PORT_B_R
22 Layout Note:
EAPD# NB_MUTE# TEST_WOOFER_EN SUB_MUTE# ICH_AZ_CODEC_BITCLK R505 *22_NC C686 *1P_NC 28 10 10
_ENABLE# VREFOUT_B Place close to
0 0 0 H L PORT_C_L
23 pin 8.
24
+5V_SPK_AMP PORT_C_R
0 0 1 H L VREFOUT_C
29
18
NC/CD_L AUD_FRONT_L_1 +VDDA C669
0 1 0 H L 19
NC/CD_GND PORT_D_L
35 AUD_FRONT_L_1 40 Close to U19
20 36 AUD_FRONT_R_1 0.1U
NC/CD_R PORT_D_R AUD_FRONT_R_1 40
0 1 1 H L Depop R477,R478,R484,R473 32 25
VREFOUT_D
Pop R476,R480,R483,R475 2 1
2

1 0 0 H L R191 R185 R201 for using 92HD73C PORT_E_L

14 AUD_MIC_L 40
15 AUD_MIC_R 40
PORT_E_R

5
1 0 1 H (Disable SPK) H (Test Woofer) 100K 100K 100K R476,R483 close to U19, Let DVDD width be 10-mils 31
GPIO4/VREFOUT_E AUD_MIC1_VREFO 40
C678 1U R487 10K 1 BEEP 29
1 1 0 L (Test SPK) L (Disable Woofer) 16 AUD_HP2_L0 AUD_PC_BEEP 1 2BEEP2 2 1 BEEP1 4
1

AUD_SPK_ENABLE# PORT_F_L AUD_HP2_R0 603 10

WOOFER_EN 40 17 2 SPKR 8

1
PORT_F_R
1 1 1 L H GPIO3/VREFOUT_F
30
R488 603

3
3

+3.3V_RUN 43 2.2K U37

AUD_SPK_ENABLE# DMIC_CLK PORT_G_L 74LVC1G86GW
29 NB_MUTE# 2 2 TEST_WOOFER_EN 10 40 DMIC_CLK 2 44
DVDD DMIC0/VOL_UP/GPIO1 PORT_G_R
3

2
1

Q32 Q37 DMIC1/VOL_DN/GPIO2

45
1

2N7002W-7-F 2N7002W-7-F R517 PORT_H_L

D 46 D
*10K_NC PORT_H_R
3

Q63
3

2 EAPD# 47
29 PCB_BEEP_EN
QUANTA
2

EAPD# EAPD# DMIC_CLK/GPIO0/SPDIF_IN

2 48 12
SPDIF_OUT_0 PC_BEEP
33
1

CAP2
2N7002W-7-F Q31 27
COMPUTER
1

2N7002W-7-F DMIC_DATA VREFFILT

40 DMIC_DATA 4
DVSS1

1
7 26 Title
DVSS2 AVSS1 C693 C329 Azelia CODEC
42
AVSS2 10U 1U

2
92HD73C 805 603 Size Document Number Rev
10 10 FM9 1A

Date: Wednesday, March 04, 2009 Sheet 39 of 64

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

Headphone Jack Array Microphone & Camera

JCAMERA1
Stereo MIC Jack USBP11 D+
USBP11 D-
1
1
2 2 50
+CAM_VCC 3 3 C429 1 2 220P
39 DMIC_CLK L4 0 603 DMIC_CLK_L 4 4
5 5 39 AUD_HP1_L
C406 2 1 2.2U AUD_HP1_L_R 1 R261 2 2.2K AUD_HP1_L0
C365 1U +3.3V_RUN L3 0 603 DMIC_DATA_L 6 6 1206 25
39 DMIC_DATA
39 AUD_MIC1_VREFO 2 1 7
7
603 10 1 2 39 AUD_HP1_R
C411 2 1 2.2U AUD_HP1_R_R 1 R260 2 2.2K AUD_HP1_R0
R245 100K 1206 25
L22.L24,L29,L30,L31,L32 87212-0700l-7p-l C428 1 2 220P

2
DMIC_DATA 50
R220 R218 FB_600ohm+-25%_100MHz MIC1_JD 39

1
4.7K 4.7K _200mA_0.6ohm DC +3.3V_RUN L46 603 U26
C15 BLM11A05S AUD_HP1_L0 13 9 AUD_HP1_L2
CON2 *33P_NC AUD_HP1_R0 INL OUTL AUD_HP1_R2
15 11

2
INR OUTR
A
2 1770882-4 50 +5V_RUN L44 603
NC1 4 A
C366 1 2 2.2U AUD_MIC_L1 L30 1 2 BLM18BD601SN1D AUD_MIC_L2 4 *BLM11A05S_NC 6
39 AUD_MIC_L NC2
1206 25 603 3 14 8
39 AMP_HP1_SHUD# SHDNR NC3
C367 1 2 2.2U AUD_MIC_R1 L31 1 2 BLM18BD601SN1D AUD_MIC_R2 1 L45 603 +CAM_VCC 18 12
39 AUD_MIC_R
1206 25 603 6
JACK 2 (MIC) DMIC_CLK
+3.6V_CAMERA
*BLM11A05S_NC SHDNL NC4
16
C502 C463 1 NC5
5 2 2.2U 1 C1P NC6 20

1
+3.3V_RUN 10U 1206 16 3 10
C1N SVDD +3.3V_RUN
C369 C370 C16 10 19
PVDD

2
220P 220P 1 2 *33P_NC Y5V 5 2

GND
GND
GND
GND
GND
2

2
R567 100K 50 805 PVSS PGND C458
7 SVSS SGND 17
50 50 1U

1
2
L2 C464 MAX4411ETP+ 805

21
22
23
24
25
HP2_JD 39
1 2 USBP11 D- 2.2U 25
9 ICH_USBP11-
4 3 USBP11 D+ 1206

1
9 ICH_USBP11+
16
CON3 *PLW3216S900SQ2T1_NC
2 1770882-4
L33 1 2 BLM18BD601SN1D AUD_HP2_L2 4
39 AUD_HP2_L1
603 3
JACK 1 1
1206
2
L34 1 2 BLM18BD601SN1D AUD_HP2_R2 R6 0
39 AUD_HP2_R1
603
1
6
(HP2)
2

5 1 2

1
R249 R244 +5V_RUN R4 0 +3.6V_CAMERA
*20K_NC *20K_NC C395 C399 U30
2 220P 220P 1 5

2
IN OUT
1

50 50 +3.3V_RUN 3 EN R366
1 2 C497 2 GND NC/FB 4 *100K/F_NC C498 C499
R328 100K *1U_NC *20P/50V_NC
*4.7U_NC
603 *TPS73601DBVR_NC 50 603
10 6.3
HP1_JD 39

CON5 R363
2 1770882-4 *49.9K/F_NC
AUD_HP1_L2 L38 1 2 BLM18BD601SN1D AUD_HP1_L3 4
603 3
B AUD_HP1_R2 L39 1 2 BLM18BD601SN1D AUD_HP1_R3 1
JACK 3 (HP1) B
603 6
5
2

R330 R305 C450 C462

*20K_NC *20K_NC 220P 220P
2

50 50
1

C C

Gur_0808: 0 ohm removal,

INTERNAL SUBWOOFER AMP L67 BLM18PG121SN1D
1U/10V
C765 CC0603 U44
delete R304, R309
CN2
AUD_MONO_OUT AUD_SUB_IN+ 1 2 SUB_IN+ 2 11 SUB_OUT+ 1
IN+ OUT+ 1
120ohm, 2A 1 2 SUB_IN- 3 MAX9759 10 SUB_OUT- 2
+5V_SPK_AMP IN- OUT- 2
SYNC Condition C769 C764 1U/10V
TQFN 16PIN
MLX_53261-0271
VDD Spread-spectrum mode with fS = 1200kHz ±70kHz. 100P CC0603 1
VDD
2

1
50 C492 C766 C767
R355 GND Fixed-frequency mode with fS = 1100kHz. NPO R351 100K 0.1U 3300P 3300P
100K +5V_SPK_AMP 1 2 5 4

2
SHDN# GND +5V_SPK_AMP
FLOAT Fixed-frequency mode with fS = 1500kHz. SUB_MUTE#
+5V_SPK_AMP 1 2 8
1

SYNC R604 100K MUTE#

Clocked Fixed-frequency mode with fS = external clock frequency. PVDD
9
3

1
C762
2

2 0.1U
39 WOOFER_EN
R352 SYNC 7 6

2
SYNC PGND

1
*100K_NC Q68 13 C763
1

2N7002W-7-F SYNC_OUT 10U

AUD_SUB_GAIN1 16 12 CC0805
1

2
G1 PVDD

1
AUD_SUB_GAIN2 15 C770
G2 0.1U
17 Exposed Paddle PGND 14 2

MAX9759ETE+
+5V_SPK_AMP
2

R332 +5V_SPK_AMP
100K
GAIN1 GAIN2 GAIN
0 0 24dB
2

+5V_SPK_AMP
1

BUFFER_VIAS +5V_SPK_AMP R357 R358

D
BUFFER_VIAS 39
BUFFER_VIAS
0 1 18dB D
100K 100K
2

BUFFER_VIAS U28C U28D 1 0 12dB

2

R333 C474 C743 0.47U/6.3V R594 10K/F MAX4492AUD+ 12 MAX4492AUD+

1

VDD
100K 1 2 1 2 10 R347 C482 C481 14 AUD_MONO_OUT AUD_SUB_GAIN1 1 1 6dB
39 AUD_FRONT_L_1 R598 VDD
AUD_SUB_GAIN2
2.2U/10V 8 1 2 13
1

VSS
CC0805 1 2 1 2 1 2 9
1

39 AUD_FRONT_R_1 VSS
1

10K/F 0.068U/16V 0.068U/16V

11

C744 0.47U/6.3V R595 10K/F R354 R359

QUANTA
11

10K/F R342 *100K_NC *100K_NC

1

C757 20K/F
C761 0.015U R337 100K/F
COMPUTER
2

0.068U/16V 1 2
2

Title
R599 4.99K/F R338 14K/F AUDIO CONN
2 1 1 2
Size Document Number Rev
FM9 1A

Date: Wednesday, March 04, 2009 Sheet 40 of 64

1 2 3 4 5 6 7 8
 5 4 3 2 1

0-ohm resister Place Close to Pin10,13,30,36,39

+1.2V_LAN reserved for EMI +3.3V_LAN +3.3V_LAN +3.3V_SUS
+1.2V_LAN
R83 0 R434 0
D D
R418 0
603 603 C569 C570 C561 C574 C582 C187 C571 C572

2
C231 C230 C586 C598 C174 C573 C224 C149 10U 0.1U *0.1U_NC *0.1U_NC 0.1U 0.1U 0.1U 0.1U 603

1
1U 1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 603 10 10 10 10 16 10 10
10 10 10 10 10 10 10 10 6.3 X7R X7R X7R X7R Y5V X7R X7R

1
X5R X5R X7R X7R X7R X7R X7R X7R

2
Place Close 603 603
to Pin19
Place Close Place Close
Place Close to Pin44,45 <200mil to Pin1,29,37,40
to Pin4 Width >40mil

+1.2V_LAN
+3.3V_LAN +3.3V_LAN

Realtek feedback:
L118: R58 2.49K
4.7uH power choke, +1.2V_LAN
tolerance <20%, 耐耐耐

LAN_XTALO
>600mA, efficiency >75% L24

LAN_XTALI
4.7uH_680mA
C123
C106 0.1U
22U 10
Place Close 805 X7R +1.2V_LAN
6.3 +3.3V_LAN
U5

48
47
46
45
44
43
42
41
40
39
38
37
to Pin48 <200mil
Width >60mil

VCTRL12A/SROUT12

CKTAL2
CKTAL1
NC/AVDD33
NC/LV_PLL
LED0
VDD33
GND

VCTR12DVDDSR
NC/VDDSR
RSET

NC/ENSWREG
C
RJ-45 Connector C
+3.3V_LAN
1 36
TRD0+ AVDD33 DVDD12 R70 3.6K
2 35
TRD0- MDIP0 LED1/EESK EEDI CON1 2006123-4
3 34 1 2
MDIN0 LED2/EEDI
+1.2V_LAN 4 33
TRD1+ NC/FB12 LED3/EEDO
5 32
TRD1- MDIP1 EECS
6 31
MDIN1 GND
TRD2+
7
GND RTL8111DL DVDD12
30 +1.2V_LAN
RJ45-TX3-
8 29 +3.3V_LAN 8
TRD2- NC/MDIP2 VDD33 ISOLATE# RJ45-TX3+ 8
9 28 7
NC/MDIN2 ISOLATEB R77 0 RJ45-TX1- 7
10 27 PLTRST# 3,9,16,26,28,29,31,32 6
R59 0 TRD3+ DVDD12/AVDD12 PERSTB RJ45-TX2- 6
11 26 PCIE_WAKE# 7,28,31,32 5
LAN_XTALO TRD3- NC/MDIP3 LANWAKEB RJ45-TX2+ 5
12 25 LOM_CLK_REQ# 9 4
NC/MDIN3 CLKREQB 4

NC/SMDATA
RJ45-TX1+ 3

REFCLK_N
3

REFCLK_P

NC/SMCLK
Y1 RJ45-TX0- 2
2

DVDD12

EVDD12
LAN_XTALI 2 1 RJ45-TX0+ 1
1

HSON
EGND
HSOP
ISOLATEB

HSIN
HSIP
GND
25MHz Datasheet(V1.4)P5:
Used to isolate the RTL8111DL
from the PCI-E bus.RTL8111DL will not drive
13
14
15
16
17
18
19
20
21
22
23
24
C127 C126 +3.3V_RUN its PCI-E outputs(excluding LANWAKEB) O G
27P 27P and will not sample its PCI-E input
50 50 as long as the isolate pin is asserted.

CHSGND1
CHSGND2
NPO NPO Realtek feed back:
+1.2V_LAN 進進S3,S4,S5要
R441
1K/F 拉low 離離S3,S4,S5要拉high for WOL support

9 PCIE_TX6+/GLAN_TX+ 1R81 02
ICH_SMBDATA 9,32,60
1 2 ICH_SMBCLK 9,32,60 R442 100/F
9 PCIE_TX6-/GLAN_TX-

9
10
R82 0 ISOLATE#
LAN_PCIE_PWR_CTRL 10,29
9 CLK_PCIE_LOM
9 CLK_PCIE_LOM#
2 1

C225 0.1U LAN_PCIETXDP R443 D20 *RB501V-40_NC

9 PCIE_RX6+/GLAN_RX+
C226 0.1U LAN_PCIETXDN 15K/F
9 PCIE_RX6-/GLAN_RX-
B B

L55
24 TXCT0 TRD3+ C214 6.8P 50
TDCT MCT0 TRD3- C222 6.8P 50
1
R65 75/F TXCT0 TCT0 RJ45-TX0+ TRD2+ C194 6.8P 50
23
R69 75/F TXCT1 TRD0+ TX0+ TRD2- C206 6.8P 50
2
R73 75/F TXCT2 TD0+ RJ45-TX0- TRD1+ C164 6.8P 50
22
R78 75/F TXCT3 TRD0- TX0- TRD1- C183 6.8P 50
3
TD0- TXCT1 TRD0+ C144 6.8P 50
21
TDCT MCT1 TRD0- C151 6.8P 50
4
C93 TCT1 RJ45-TX1+
20
1000P TRD1+ TX1+
5
3KV TD1+ RJ45-TX1-
19
1808 TRD1- TX1-
6
TD1- TXCT2
18
TDCT MCT2
7
TDCT TCT2 RJ45-TX2+
17
TDCT TRD2+ TX2+
8
TDCT TD2+ RJ45-TX2-
16
TDCT TRD2- TX2-
9
TD2- TXCT3
15
TDCT MCT3
10
C567 C604 C581 C594 TCT3 RJ45-TX3+
LAYOUT NOTE: TX3+
14
0.01U 0.01U 0.01U 0.01U TRD3+ 11
CAP CLOSE TO TRANSFORMER TD3+
13 RJ45-TX3-
25 25 25 25 one cap for each pin TRD3- TX3-
12
TD3-
Reserved for EMI. LFE9249-R

A A

QUANTA
Title
COMPUTER
LAN

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 41 of 64

5 4 3 2 1
 1 2 3 4 5 6 7 8

+3.3V_SUS
A A

C722
0.1U

5
51 VR_PWRGD_CLKEN# 2 4 R546 0
CK_PWRGD_R 15
U41
TC7SZ04FU(T5L,F,T)

3
B B

+3.3V_SUS

R176 0
49 1.1V_VTT_PWRGD
+3.3V_ALW
R167
100K
R172 0
48 1.05V_PWRGD
U38
74AHCT1G08GW

5
R169 0 HWPG
50 GFX_PCIE_PWRGD HWPG 29
47 1.5V_DDR_PWRGD 2
4 RUN_ON 24,44,47,48,49,52
29 RUN_ON_1 1
R166 0
50 GFX_CORE_PWRGD
+3.3V_RUN

3
R182 0
44 1.8V_RUN_PWRGD
R196
2K/F R535 *0_NC
R174 0
C 44 1.8V_RUN_GFX_PWRGD D7 C
H_VTTPWRGD
H_VTTPWRGD 3
R538 *10K_NC RUN_ON
RB500V-40
VTTPWRGOOD
R197 SC(V1.0)P18: R539 *10K_NC RUN_ON_1
1K/F VTT_1.1 VR power good signal
to processor. Signal voltage level
is 1.1 V.

D D

QUANTA
Title
COMPUTER
System Reset Circuit

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 42 of 64

1 2 3 4 5 6 7 8
 1 2 3 4 5

A A

B B

C C

D D

QUANTA
Title
COMPUTER
Battery Selector

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 43 of 64

1 2 3 4 5
 5 4 3 2 1

PQ10
FDS6298
POWER_JP 9
PJP3
8 3
+3.3V_ALW 1 2 7
6
2
1
+1.8V_RUN_GFX
5 TDC : 1.05A
D D
PC42 PC43

4
10U 0.1U PJP4 POWER_JP

1 2 +1.8V_RUN_GFX
PR174
*100K/0402_NC
+3.3V_SUS
PU11 RT9024PE PC173
4 100P PR176 PC47
42 1.8V_RUN_GFX_PWRGD PGD DRV 5 R1 49.9K/F 22U/6.3V/0805

1 EN
24,42,47,48,49,52 RUN_ON 3
PR173 FB

GND
+5V_ALW 0 6 VCC

2
PC170 PC171 PR175
Vout =0.8(1+R1/R2)
0.1U 1U/10V/0603
R2 39K/F =1.8V

C
+1.8V_RUN_GFX for VGA 1.8V C
+1.8V_RUN for CPU and PCH 1.8V

+3.3V_SUS
1

PR110
*100K_NC
+1.8V_RUN
TDC : 0.74A
2

PU6 RT9018B
42 1.8V_RUN_PWRGD 1 POK 8 PJP7 POWER_JP
GND
2 VEN ADJ 7
24,42,47,48,49,52 RUN_ON PR109 0 3 VIN 6 1 2
VO +1.8V_RUN
4 VPP NC 5

1
9

POWER_JP PR108 PR105 0 603

PJP6
*100K_NC +5V_ALW PR106 PC83
9
2

1 2 49.9K/F 10U
+3.3V_ALW R1

2
805
PC85 PC84 PC86 PC82 10
B
1U 0.1U 0.1U 0.1U B
805 25 25 25 Vout =0.8(1+R1/R2)
1

PR107
10 603 603 603 39K/F
R2
=1.8V

A A

Title
+1.8V_RUN_GFX (RT9024PE) & +1.8V_RUN(RT9018B)

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 44 of 64

5 4 3 2 1
 A B C D E

Continuous current : 13A

Continuous current : 13A Rds(on) : 18mohm
Rds(on) : 18mohm
PQ25 PQ23
SI4835DDY-T1-E3 SI4835DDY-T1-E3
+PWR_SRC
8 1 PR146 0.01/F 1 8
+DC_IN_SS 7 2 2 1 2 7
+DC_IN_SS
6 3 3 6
5 2512 5

3
1 1

4
+DC_IN_SS

PR71 10K PR73 100K PR144

470K

3
2

PQ9

1
2N7002W-7-F

+DC_IN_SS

CSSN
CSSP
LDO

2
PD8 FL1 FL2
SDM10K45-7-F
PR83 PC40 PC162 PC163 PC38 HI1206T161R-10(160,6A) HI1206T161R-10(160,6A)
365K/F 1U 2200P 0.1U *10U_NC PC164

1
805 603 1206 10U

28

27

1
1
25 PR80 0 603 50 25 25 1206
PR84 25

CSSP
GND

CSSN
LDO 49.9K/F 22 PC41 1U
DCIN LDO
603 10
8731_ACIN 2 25 BST PC46
ACIN BST

5
6
7
8
2 PR78 PC55 0.01U PR75 0.1U 2
10K/F 25 33/F 603 PQ34
PR76 603
21 25 4 SI4800BDY-T1-E3
LDO PC52 1U
29,37 ACAV_IN 13 ACOK
26 PC34 PL1 PR149
VCC FL3
0 +3.3V_ALW 11 603 10 3300P 5.8UH+-30%5.5A SIL104R-5R8B 0.01/F 2512

1
2
3
VDD DHI CHG_CS
DHI 24 1 2 2 1 1 2 +VCHGR 53
PR77 10*10.1

5
6
7
8
15.8K/F PC48 0.1U 23 LX PR79 1 HI1206T161R-10(160,6A)

3
603 25 LX 603 PR170 PC27 PC22
10 20 DLO 4 2.2 3300P 2200P
29,38,53 SMBCLK0 SCL DLO
9 805 PC24 PC19
29,38,53 SMBDAT0 SDA
14 19 50 1000P 50 0.1U PC26 PC147 PC148
PR85 BATSEL PGND
SMBUS Address 12 603 10U 10U *10U_NC

1
2
3
8731_IINP 8 18 PC166 50 25 1206 1206 1206
29 IINP IINP CSIP

12H
Adress :
PQ39 1000P 25 25 25
17 SI4800BDY-T1-E3
0 CSIN 50
6
CCV
PR82 CSIP
PR72 +VCHGR
4.7K 5
CCI FBSA
15 Max Charging current
100 CSIN
setting 4.7A
4
CCS
GND
PC53 16 PC44
DAC

PC57 FBSB 220P

3 REF
0.1U

Charger circuit
0.01U

PR81 PC60 PC56 MAX8731A 50 Control IC: MAX8731AETI+

7

12

8.45K/F 0.01U 0.01U 8731REF PU4

16 25 25 H/S MOSFET: SI4800(Vishay), Qg=13nC, Rds(on)=30mohm, PD:1.3W
25 PC59 PC58 L/S MOSFET: SI4800(Vishay), Qg=13nC, Rds(on)=30mohm, PD:1.3W
3 1U 0.1U Inductor: 5.8UH +-30% 5.5A SIL104R-5R8B(Delta), DCR=24mohm 3
603 PR74 Output Cap: 2*10U 25V(+-10%,X6S,1206)
10 16

Short Jump
GNDA_CHG

4 4

QUANTA
Title
COMPUTER
Charger (MAX8731)

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 45 of 64

A B C D E
 5 4 3 2 1

+3.3V_ALW
Control IC: TPS51427A
PJP26 PR181 H/S MOSFET: FDS8878(Fairchild), Qg=14nC, Rds(on)=17mohm, PD:2.5W
1 2 ISL6237_ONLOD L/S MOSFET: FDS6680AS(Fairchild), Qg=16nC, Rds(on)=10.5mohm, PD:2.5W
+DC1_PWR_SRC PR182 0 Inductor: 3.3UH +-20% 12.3A FDVE1040-H-3R3M=P3(TOKO), DCR=10.1mohm
POWER_JP PD9 390K Output Cap: 1*150U 6.3V(20%,ESR15,7343,H=1.9),ripple current 2700mA
PR180
1 2 150K/F
603
D PJP25 *UDZSTE-175.6B_NC D

+PWR_SRC 1 2
+5V_ALW2 PR123 +5V_VCC1
POWER_JP *10/0603_NC
PC110 PC193 PC194 PC109
*10U_NC 10U PC195 PC111 PC192 PC108 10U *10U_NC
1206 1206 PC99 1206 1206
+5V_ALW 25 25
0.1U
25
2200P
50 4.7U
0.1U
25
2200P
50 25 25 +3.3V_ALW
Fs=400K 603 10 603 Fs=300K
1206
TDC : 5.83A PC104
TDC : 8.23A
OCP : 8.33A PC101 0.1U OCP : 11.77A

ISL6237_ONLOD
PR121
PC100 *0_NC PC102
0.1U 1U
25 603
1U/25V 10 +3.3V_ALW
603 PR122

5
6
7
8
+5V_ALW 50
603 PQ48

1
4 FDS8878
PJP24
*0_NC POWER_JP

42
1

8
7
6
5
4
3
2
1

1
2
3
8
7
6
5
PJP23 41 PL9

PAD
LDOREFIN
LDO
VIN
RTC
ONLDO
VCC
TON
REF

2
POWER_JP PAD FDVE1040-H-3R3M=P3
PQ47 40 PAD
SI4800BDY-T1-E3 4 +5V_DH 39 +3.3V_LX +3.3V_ALWP
PAD
38
2

+5V_ALWP PAD PR126 200K/F

C 9 BYP REFIN2 32 C
PL10 3 10 31
2
1
3.3uH/SIL1045R-3R3A/8A/21mOhm OUT1 ILIM2 PR178
11 FB1 OUT2 30
+5V_ALWP +5V_LX 12 PU8 29 PR128 2.2/F
ILIM1 SKIP#

5
6
7
8
PR127 237K/F POK1 13 TPS51427A 28 POK2 0 + PC189
PGOOD1 PGOOD2 *0603_NC
+5V_EN1 14 27 +3.3V_EN2 PC186 150U
PR125 PR179 ON1 ON2 +3.3V_DH 0.1U
15 DH1 DH2 26 4 6.3
*0_NC 2.2/F 16 25 603
LX1 LX2 7343
8
7
6
5

+ PC185 37 PC182 25
*0603_NC PAD
150U PC184 36 PQ45 *2200P_NC

1
2
3
PAD

AGND
PGND
7343 0.1U +5V_DL PC105

BST1

BST2
4 50

VDD
PAD
PAD
PAD

DL1

DL2
6.3 603 PC183 PC106 FDS6680AS

NC
0.1U
25 *2200P_NC 25 0.1U
PR124 25
3
2
1

35
34
33

17
18
19
20
21
22
23
24
0 50 603
PQ46 603
SI4812BDY-T1-E3 PR131 603 1
PR133 +3.3V_DL
1 603

+5V_ALW2 PR132

+3.3V_ALWP +3.3V_ALWP
PC107 Short Jump
+5V_ALW 1U
Control IC: TPS51427A 603
10
H/S MOSFET: SI4800BDY-T1-E3(Vishay), Qg=13nC, Rds(on)=30mohm, PD:1.3W PR129 PR130
L/S MOSFET: SI4812BDY-T1-E3(Vishay), Qg=13nC, Rds(on)=21mohm, PD:1.4W 100K 100K
Inductor: 3.3UH +-30% 9A SIL1045R-3R3(Delta), DCR=21mohm
Output Cap: 1*150U 6.3V(20%,ESR15,7343,H=1.9),ripple current 2700mA BAT54S-7-F
B B
+5V_ALWP 1 POK2
PC188 3V_ALW_PWRGD
PD11 3 POK1
PC187 5V_ALW_PWRGD
2 0.1U
+15V_ALW 25 PC190
PQ43 0.1U 603 0.1U
50 1
DDTA114YUA-7-F 25
603
PD12 603
3
Ton GND VREF2 or Float 5V
3 1 +15V_ALWP 2
47K
10K

BAT54S-7-F
+5V_ALW2 Channel1 Fs 400 kHz 400 kHz 200 kHz
PC191
2

0.1U
PR189 +3.3V_RUN
25
3

*39K/F_NC 603
Channel2 Fs
2 PQ44 500 kHz 300 kHz 300 kHz
2N7002W-7-F
2

PQ42
1

2N7002W-7-F
3 1 MB_THERM# 19
PR184 0

A +3.3V_EN2 PR186 0 A
PR187 0 PM_THRMTRIP# 3

PR183 200K PD10 BAS316

PR188 0 THERM_STP# 29,38
QUANTA
29,37 ALW_ON
+5V_EN1
PR190 0 3.3V_ALW_ON 37
Title
COMPUTER
3.3V_ALW / 5V_ALW(TPS51427A)

PR185 *0_NC Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 46 of 64

5 4 3 2 1
 5 4 3 2 1

D D

+1.5V_SUS
Fs=400K
TDC : 14.25A
+1.5V_SUS PJP19 POWER_JP OCP : 20.37A
+DC2_PWR_SRC
+0.75V_DDR_VTT 2 1 +PWR_SRC

25
PC66 PC67
TDC : 0.7A 10U 10U 1 24 PC63

GND
VTTGND VTT

2
805 805 10U PQ41
PJP5 POWER_JP 10 10 805 PC178 PC179 PC180 PC62

5
6
7
8
2 1 VTT 2 23 10 FDS6298 2200P 0.1U 10U *10U_NC
+0.75V_DDR_VTT

1
VTTSNS VLDOIN PJP18 POWER_JP
50 25 1206 1206
PR86 PC64 4
DDR_VBST 0 603 25 25
3 22 2 1 0.1U 2 1
GND VBST 603 25 603

1
2
3
4 21 +1.5V_DH
MODE DRVH PJP17 POWER_JP
PL7

+DDR_VTTREF PR93 0 5 20 +1.5V_LX +1.5V_SUS_P 2 1

VTTREF LL +1.5V_SUS
0.88uH_MPC1040LR88
1

DDR_V5IN 6 19 +1.5V_DL PR177

PC70 COMP DRVL
2.2/F

5
6
7
8
9

1
0.033U PC71 *0603_NC
2

7 18 PC174 + PC176 + PC175

603 NC PGND
1 2 4 0.1U 220U/2.5V/ESR15

2
25

220U/2.5V/ESR15
C 25 C
*0.1U_NC 8 17 PQ40 PC177
50 603 VDDQSNS CS_GND FDMS7672 603
*2200P_NC

1
2
3
PR89 12.4K/F 50
DDR_V5IN PR96 *0_NC 9 16 DDR_CS 1 2
VDDQSET CS

24,42,44,48,49,52 RUN_ON 0 PR94 S3_1.5V 10 15 DDR_V5IN

S3 V5IN
PR91
PR90
29,52 SUS_ON 0 PR95 S5_1.5V 11 14 DDR_V5FILT
S5 V5FILT +5V_ALW
PR92 5.1 603 0
12
NC PU5 PGOOD
13 2 1 +3.3V_ALW
PC72 100K PC69 PC68
*0.1U_NC TPS51116REGR 1.5V_DDR_PWRGD 42 1U/10V/0603 1U/10V/0603
25
603

50
+1.5V_SUS
PC73 PR97 Control IC: TPS51116REGR
49.9K/F
*18P/50V_NC H/S MOSFET: FDS6298(Fairchild), Qg=14nC, Rds(on)=12mohm, PD:3W
L/S MOSFET: FDMS7672(Fairchild), Qg=19nC, Rds(on)=6.9mohm, PD:2.5W
Inductor: 0.88UH +-20% 24A MPC1040LR88C(Tokin), DCR=2.3mohm
PR98
Output Cap: 2*220U 2.5V(20%,ESR15,7343,H1.9),ripple current 2700mA
49.9K/F
B B

VDDQ and VTT discharge control VDDQ output voltage selection Outputs Management by S3, S5 control

MODE pin Discharge mode VDDQSET VDDQ(V) VTTREF and VTT NOTE State S3 S5 VDDQ VTTREF VTT

V5IN No discharge GND 2.5V VDDQSNS/2 DDR S0 HI HI On On On

VDDQ Tracking discharge V5IN 1.8V VDDQSNS/2 DDR2 S3 LO HI On On Off (Hi-Z)

A A
S4/GND Non-tracking discharge FB Resistors Adjusting VDDQSNS/2 1.5V < VVDDQ < 3V S4/S5 LO LO On (discharge) Off (discharge) Off (discharge)

Title
DDR3 +1.5V_SUS(TPS51116)

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 47 of 64

5 4 3 2 1
 5 4 3 2 1

D D

+PWR_SRC
PJP8
+1.05V_PWR_SRC 1 2

POWER_JP

PC92 PC91 PC96 PC95

*10U_NC 10U 0.1U 2200P
1206 1206
25 25
25 50 +1.05V_PCH
603
Fs=300K
+5V_ALW
TDC : 4.91A +1.05V_PCH
OCP : 7.02A

5
6
7
8
C PQ19 C

1
PC89 4 SI4800BDY-T1-E3
1U/10V/0603 PJP22 PJP21
POWER_JP POWER_JP
PU7 PR117 0 0.1U/50V/0603 PC90

1
2
3
PR114 7 10

2
100K/F V5IN VBST
603
2 9 +1.05V_DH PL8
TRIP DRVH 1.5UH30%10A(SIL104R-1R5B)
3 8 +1.05V_LX 1 2 +1.05V_P
42,44,47,49,52 RUN_ON EN SW
0 +1.05V_VFB 4 1
PR113 VFB PGOOD 1.05V_PWRGD 42
5 RF DRVL 6

5
6
7
8
PC88 11 PR119
GND +1.05V_DL *2.2/F/0603_NC PR112 PC97
4
*0.1U_NC TPS51218DSCR 11K/F + PC94

220U/2.5V/ESR15
PC87 0.1U
PR116 *1500P_NC 25

1
2
3
470K/F PQ20 50 603
PR115 PR118 SI4812BDY-T1-E3 PC98 +1.05V_VFB
*100K_NC *422K/F_NC *2200p/50V_NC

PR111
22.1K/F

+3.3V_SUS

B B

Frequency setting

pin5 resister 470kΩ 200kΩ 100kΩ 47kΩ

+1.05V_PCH
Control IC: TPS51218DSCR
Frequency 300kHz 350kHz 390kHz 450kHz H/S MOSFET: SI4800BDY-T1-E3(Vishay), Qg=13nC, Rds(on)=30mohm, PD:1.3W
L/S MOSFET: SI4812BDY-T1-E3(Vishay), Qg=13nC, Rds(on)=21mohm, PD:1.4W
Inductor: 1.5UH +-30% 10A SIL104R-1R5B(Delta), DCR=8.1mohm
Output Cap: 1*220U 2.5V(20%,ESR15,7343,H1.9),ripple current 2700mA

A A

Title
+1.05V_PCH(TPS51218)

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 48 of 64

5 4 3 2 1
 5 4 3 2 1

D D

+PWR_SRC
PJP11
+1.1V_VTT_PWR_SRC 1 2

POWER_JP

PC158 PC36 PC35 PC157

10U *10U_NC 0.1U 2200P
1206 1206
25 25
25 50 +1.1V_VTT
603
Fs=300K
+5V_ALW
TDC : 12.64A +1.1V_VTT
OCP : 18.06A
PQ32

5
6
7
8
FDS6298

1
PC160 4
1U/10V/0603 PJP15 PJP14
POWER_JP POWER_JP
PU10 PR168 0 0.1U/50V/0603 PC161

1
2
3
C PR158 7 10 C

2
90.9K/F V5IN VBST
603
2 9 +1.1V_VTT_DH
TRIP DRVH PL2
3 8 +1.1V_VTT_LX +1.1V_VTT_P
44,47,48,52 RUN_ON EN SW 0.88uH_MPC1040LR88
0 +1.1V_VTT_VFB 4 1 1.1V_VTT_PWRGD 42
PR159 VFB PGOOD
5 CCM DRVL 6

5
6
7
8
9
PC149 11 PR171
GND +1.1V_VTT_DL *2.2/F/0603_NC PR156 + PC37 + PC159
4
*0.1U_NC TPS51218DSCR 10K/F PC169
PQ38 PC152

330U/2V/E9/7343

330U/2V/E9/7343
0.1U
PR166 FDMS7672 *1500P_NC 50

1
2
3
470K/F 50 603
PR165 PR167 PC167 +1.1V_VTT_VFB
*100K_NC *422K/F_NC *2200p/50V_NC
PR153
20K/F
VFB=0.7V

+3.3V_SUS
PR154
0

PR157

B B

137K/F
PR172

3
*0_NC
+3.3V_SUS
PR155
Frequency setting
2 PQ33
BSS138-7-F
pin5 resister 470kΩ 200kΩ 100kΩ 47kΩ 100K
PR160 VTT_SENSE 5
*10K_NC

1
3
Frequency 300kHz 350kHz 390kHz 450kHz PR163
10K
5 H_VTTVID1 2 PQ35
BSS138-7-F

PR164 PC155 +1.1V_VTT

100K 0.01U Control IC: TPS51218DSCR
1

H_VTTVID1: H/S MOSFET: FDS6298(Fairchild), Qg=14nC, Rds(on)=12mohm, PD:3W

High level 1.05V for Auburndale 25
L/S MOSFET: FDMS7672(Fairchild), Qg=19nC, Rds(on)=6.9mohm, PD:2.5W
Low level 1.1V for Clarksfield Inductor: 0.88UH +-20% 24A MPC1040LR88C(Tokin), DCR=2.3mohm
Output Cap: 2*330U 2V(+10/-35%,7343,ESR=9),ripple current 3000mA

A A

Title
+1.1V_VTT(TPS51218)

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 49 of 64

5 4 3 2 1
 5 4 3 2 1

+PWR_SRC

+5V_ALW +GPU_PWR_SRC 2 1

PJP12
+3.3V_SUS PR150 POWER_JP

1
D 0 D
603 PC30 PC154 PC150 PC28
2200P 0.1U 10U *10U_NC

2
PC140 1U/10V/0603 603 1206 1206

5
6
7
8
2 7 8792TON 1 2 50 50 25 25
PR143 VDD TON PR151 200K/F
*100K_NC PC124 1U/10V/0603 5 8792DH 4 PQ36
8792VCC DH FDS6298 +VCC_GFX_CORE
13 VCC PR152 1 603 PC141 0.22U

2
6 8792BST 1 2 1 2 PJP13

1
2
3
42 GFX_CORE_PWRGD 8792PGD BST 805 50 POWER_JP
14 PGOOD
PR148 0 8792EN 1 PU9 PL6 2 1
17,19,29 GFX_ON EN 8792LX
LX 4
PR142 *0_NC MAX8792ETD+T 0.75U +-20% 14.5A(FDVE0630-R75M=P3)
8792SKIP# 12 2 1 +VCC_GFX_CORE_P 2 1
SKIP# 8792DL
DL 3

1
PC137
8792REFIN 10 PR169 PJP16
REFIN

5
6
7
8
9
0.1U PC45 PC172 POWER_JP
FB 8 *2.2_NC
+VCC_GFX_CORE

1
+ +
805

220U/2.5V/ESR15

220U/2.5V/ESR15
PC168
REF-2V 4 Fs=300K

2
8792REF 11 9 8792ILIM 0.1U

2
REF ILIM
PQ37
FDMS7672
10 TDC : 8.13A

EP

1
2
3
PR141 PR145
PC165 OCP : 11.62A
*1500P_NC

15
1
60.4K/F 50

1
PR139
PC128 5.23K/F Short Jump
+3.3V_SUS 1000P

2
50 Place near GND pin15
2

C C
PR36 PR41
3

1
10K 267K/F
PR43 PR140
10K 100K/F
1

2 1 CNTRL0 2 PQ6
BSS138-7-F

2
1

PC12
3

PR40 0.01U PR33

1

100K 49.9K/F
2

25
17 GFX_CORE_CNTRL0 2 PQ5 +VCC_GFX_CORE
2

BSS138-7-F GFX_CORE_CNTRL0 GFX_CORE_CNTRL1 GFX_CORE_CNTRL2 +VCC_GFX_CORE Control IC: MAX8792ETD+T

PR48 H/S MOSFET: FDS6298(Fairchild), Qg=14nC, Rds(on)=12mohm, PD:3W
LOW LOW LOW 0.9 L/S MOSFET: FDMS7672(Fairchild), Qg=19nC, Rds(on)=6.9mohm, PD:2.5W
20K
1

HIGH LOW LOW 1.0V Inductor: 0.75UH +-20% 14.5A FDVE0630-R75M=P3(TOKO), DCR=6.2mohm
8792REFIN_1

Output Cap: 2*220U 2.5V(20%,ESR15,7343,H1.9),ripple current 2700mA

HIGH HIGH LOW 1.1V
+3.3V_SUS
HIGH HIGH HIGH 1.2V
2

PR39
10K
PR38
3

20.5K/F
1

PR31 PR30
10K PQ2 20K/F
2 1 CNTRL1 2
BSS138-7-F +3.3V_SUS
1
3

B PR32 PC11 B
100K 0.01U
1

1
2

17 GFX_CORE_CNTRL1 2 PQ4 25 PR54

2

BSS138-7-F *100K_NC
+1.1V_GFX_PCIE

2
PR47
TDC : 1.41A
1

20K PU3 RT9018B

1 POK 8 PJP2 POWER_JP
8792REFIN_2

42 GFX_PCIE_PWRGD GND
2 VEN ADJ 7
17,19,29 GFX_ON PR50 0 3 VIN 6 1 2
VO +1.1V_GFX_PCIE
4 VPP NC 5

1
9
POWER_JP PR49 PR58 0 603
PJP1
*100K_NC +5V_ALW PR60 PC39

9
2
49.9K/F 10U
+1.5V_SUS 1 2 R1

2
+3.3V_SUS 805
PC18 PC23 PC20 PC29 10
1U 0.1U 0.1U 0.1U
805 25 25 25 Vout =0.8(1+R1/R2)
1
2

PR61
PR16 10 603 603 603 133K/F
R2 =1.5V
10K
PR35
3

5.11K/F
1

PR17
10K PQ3
2 1 CNTRL1 2
BSS138-7-F
1

PR34
3

PR18 PC6 21K/F

100K 0.01U
1
2

17 GFX_CORE_CNTRL2 2 PQ1 25
2

BSS138-7-F
A A
PR14
20K
1

Title
VGA power (MAX8792 & RT9018B)

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 50 of 64

5 4 3 2 1
 5 4 3 2 1

+PWR_SRC +CPU_PWR_SRC
PJP9

PC123 PC133 PC130 PC122

+ + + + PJP10

*100U/25V_NC

*100U/25V_NC

*100U/25V_NC

*100U/25V_NC
+5V_SUS

PR136
10/0603
PQ31
PC146 PC25 PC21 PC142

5
6
7
8
9
NTMFS4943N 2200P/50V 0.1U/50V/0603 10U/25V/1206 10U/25V/1206
PC114 PC9
D
2.2U/6.3V/0603 2.2U/6.3V/0603 4
+VCC_CORE D

TDC:38A

26
7
PR2 PR3
133K/F 9.1K/F Max current: 51A

VCC

VDD

1
2
3
6 28 UG1
TIME DH1
PR28 PL5 0.36uH_30A_ETQP4LR36WFC
1/0603 PH1 2 1 +VCC_CORE
5 30
ILIM BST1

3
PQ30 PQ49 PC33
PC10 *NTMFS4935N_NC *1500P/50V_NC
PR13 0.22U/25V/0603 NTMFS4935N

5
6
7
8
9

5
6
7
8
9
200K/F 29
LX1 PR64
+CPU_PWR_SRC 16
TON PC51 + PC61 + PC181
4 4 1.8K/F
PR53 0.1U/50V/0603 330U 330U
27 LG1 *2.2_NC PR67 PR70 2 2
DL1 3.4K/F 10K/NTC/0603
805

1
2
3

1
2
3
7343 7343
32 PC121
5 VID0 D0
33 *1000P_NC
5 VID1 D1
5 VID2 34
D2
5 VID3 35
D3 CSP1
5 VID4 36 39
D4 CSP1
5 VID5 37
D5 PR11
5 VID6 38
PR7 D6
2.2/0603
0 PC4
29 IMVP_VR_ON 13 0.22U/25V/0603
SHDN CSN1
40
CSN1
+CPU_PWR_SRC
PR9
499/F *1000P_NC
14 PC119
5 DPRSLPVR DPRSLPVR
C PQ27 C
23
DH2

5
6
7
8
9
NTMFS4943N PC139 PC16 PC14 PC132
PR27 2200P/50V 0.1U/50V/0603 10U/25V/1206 10U/25V/1206
PR12 1/0603 UG2 4
0 21
BST2
5 H_PSI# 15
+3.3V_RUN PSI

1
2
3
10K PC8
PR20 18 22 0.22U/25V/0603
29 IMVP_PWRGD PWRGD LX2 PL4 0.36uH_30A_ETQP4LR36WFC
PH2 2 1 +VCC_CORE
PR10 24 PQ29

3
13K/F DL2
PQ50
3 NTMFS4935N *NTMFS4935N_NC PC32
+5V_RUN THRM

5
6
7
8
9
PC115 *1500P/50V_NC

5
6
7
8
9
+3.3V_RUN *1000P_NC
LG2 4 PR63
PR8 4 PR52 1.8K/F PC50 + PC54
PR44 *NTC_100K_NC 12 CSP2 *2.2_NC 0.1U/50V/0603 330U
499/F CSP2 PR66 PR69
805 2

1
2
3
PR4 3.4K/F 10K/NTC/0603

1
2
3
PR37 7343
2.2/0603
0
29 IMVP6_PROCHOT# 25 PC1
VRHOT 0.22U/25V/0603 CSN2
11
PR5 CSN2
1K/F PC113 PR88
5 I_MON 4 1000P *10_NC
IMON *1000P_NC
PC116
PC3 10
GNDS VSSSENSE 5
0.1U PR6
14.7K/F 10
VSSSENSE PC118 PR137
PR135 *1000P_NC PR138
B 10 B
4.99K/F
PR15 9
FBAC VCCSENSE 5
1.91K/F
+3.3V_ALW
+VCC_CORE +CPU_PWR_SRC
17 1000P *10_NC
CLKEN PC120 PR87
42 VR_PWRGD_CLKEN# 8
FB

PR21
1K +5V_ALW PQ26
+3.3V_RUN 20
PWM3
5
6
7
8
9
PR19 NTMFS4943N PC138 PC15 PC13 PC131
1/0603 2200P/50V 0.1U/50V/0603 10U/25V/1206 10U/25V/1206
4
31 PC7
PGD_IN
19 1U/10V/0603
DRVSKP PU2 PC5
1
2
3

5 1 0.22U/25V/0603
VDD BST
17030_PWM3 2 8 UG3
PR29 17030_SKIP# PWM DH PL3 0.36uH_30A_ETQP4LR36WFC
6
SKIP PH3
100K 7 2 1 +VCC_CORE
PC112 LX
3
*1000P_NC GND LG3
9 4 PQ28

3
PAD DL
MAX8791GTA+ NTMFS4935N PC31
5
6
7
8
9

2 *1500P/50V_NC
CSP3
+5V_SUS 4 PR62
PR1 PR51 1.8K/F PC49 + PC65
PU1 MAX17036GTL+ 2.2/0603 *2.2_NC 0.1U/50V/0603 330U
805 PR65 PR68 2
1
2
3

PC2 3.4K/F 10K/NTC/0603

PR326 7343
0.22U/25V/0603
*0_NC

A 1 A
CSN3
EP

CSP3
41

*1000P_NC CSN3
PR134 PC117

Short Jump PR334

*0_NC

AGND_VCORE
Title
CPU core (MAX17036)

Size Document Number Rev

FM9 <RevCode>

Date: Wednesday, March 04, 2009 Sheet 51 of 64

5 4 3 2 1
 1 2 3 4 5

+5V_RUN +3.3V_SUS
+5V_ALW +15V_ALW +3.3V_ALW PQ15 +3.3V_SUS
+5V_ALW +15V_ALW +5V_ALW PQ14 +5V_RUN TDC : 2.67A SI4800BDY-T1-E3 TDC : 0.46A
SI4800BDY-T1-E3
8 3
8 3 7 2
7 2 PR104 PR103 6 1
PR102 6 1 100K 100K 5
PR101 100K 5
100K PC79

4
PC76 SUS_3.3V_ENABLE 0.1U

4
RUN_ENABLE_5V 0.1U 603

3
A A
603 25

3
25 SUS_ON_3.3V# 5
RUN_ON# 5 PQ18A

6
2N7002DW-7-F

4
6
29,47 SUS_ON 2

4
2 PQ16A PC77 PQ18B PC80
24,42,44,47,48,49 RUN_ON
2N7002DW-7-F 4700P 2N7002DW-7-F 4700P

1
1 25 25
PQ16B
2N7002DW-7-F

+5V_SUS
+15V_ALW +5V_ALW PQ17 +5V_SUS
SI4800BDY-T1-E3 TDC : 2.1A
8 3
7 2
6 1
+15V_ALW +1.5V_SUS +1.5V_RUN +1.5V_RUN PR100 5
PQ11
FDS6298 TDC : 3.74A 100K
PC81

4
8 3 0.1U
7 2 SUS_ENABLE_5V 603
PR99 6 1 25

3
100K 5
SUS_ON_3.3V# 2
PC75 PC78

4
RUN_ENABLE_1.5V 0.1U PQ13 4700P

1
B 603 2N7002W-7-F 25 B
3

25
RUN_ON# RUN_ON# 2

PQ12
1

2N7002W-7-F PC74
0.047U
25

+3.3V_RUN
+15V_ALW +3.3V_ALW PQ22 +3.3V_RUN
FDS8880_NL TDC : 5.93A
8 3
7 2
6 1
PR120 5
100K
PC93
4

0.1U
C C
RUN_ENABLE_3.3V 603
25
3

RUN_ON# 2
PC103
PQ21 4700P
1

2N7002W-7-F 25

Reserve discharge path

+5V_RUN +3.3V_RUN +1.8V_RUN +1.5V_RUN +0.75V_DDR_VTT +1.8V_RUN_GFX +1.5V_SUS +5V_SUS +3.3V_SUS

R141 R253 R212 R199 R90 R211 R248 R210

R247 *10_NC *1K_NC *1K_NC *1K_NC *1K_NC *30/F_NC *1K_NC *1K_NC
47
3

3
D D
RUN_ON# 2 2 2 2 2 2 SUS_ON_3.3V# 2 2 2
Q46
Q27 Q47 Q39 Q35 Q22 Q40 Q45 Q38
QUANTA
1

1
2N7002W-7-F *2N7002W-7-F_NC *2N7002W-7-F_NC *2N7002W-7-F_NC *2N7002W-7-F_NC *2N7002W-7-F_NC *2N7002W-7-F_NC *2N7002W-7-F_NC *2N7002W-7-F_NC

Title
COMPUTER
RUN / SUS POWER SW

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 52 of 64

1 2 3 4 5
 A B C D E

+3.3V_ALW

2
PC135 1 2 2200P 50

PC134 1 2 1000P 50 +3.3V_ALW

PD4 PD3 PD2 PD1

3
1 1
PC136 *DA204U_NC *DA204U_NC *DA204U_NC *DA204U_NC
1 2 0.1U 25
+VCHGR 45

2
603
PR23
JBAT1 10K
BATT1+ 1 SMBUS Address 16
2 PR26 100
Adress : 16H

1
BATT2+
SMB_CLK 3 1 2 SMBCLK0 29,38,45
SMB_DAT 4 1 2 SMBDAT0 29,38,45
5 PR25 100 PR24 100
BATT_PRES#
SYSPRES# 6 1 2 PBAT_PRES# 29
BATT_VOLT 7 1 2 PBAT_ALARM#
8 PR22 100
BATT1-
BATT2- 9

200045MR009H579ZL

+5V_ALW2

+3.3V_ALW

1
PD7
DA204U PR57
2.2K

3
2 2
PQ8

2
2N7002W-7-F
PR56 100
DB_PSID PR45 0 DOCK_PSID 3 1 1 2 PS_ID 29
603

2
J10 PR42 +5V_ALW2 +5V_ALW2

1
100K/F
8 PC17
BAT2_LED RBAT2_LED 37

2
7 RBAT1_LED 37 100P

2
BAT1_LED

2
LED_DET 6 50
5 DB_PSID PD5 PR55
PSID

3
4 GND *BAS316_NC 10K PD6
GND *DA204U_NC
GND 3 2
2

3
DC +DCIN_JACK
1 1 2 PS_ID_DISABLE#

1
DC

1
PQ7
+DCIN_JACK PR46 MMST3904-7-F PR59 *100_NC
87438-0843 15K/F
2

PC153

2
PC151 PC145 PC156 100P
1

2200P 1000P 0.1U 50

50 50 25
603
Change Value per GG updated

3 3

EMI requirement on 0812

PQ24
+DC_IN SI4835DDY-T1-E3 +DC_IN_SS
+DCIN_JACK FL4
BLM41PG600SN1L 1 8
+DCIN_JACK 2 7
3 6

1
5
1

1
PC143 PC144 PR162
0.1U 0.47U 240K PC127 PR147 PC125 PC126 PC129

4
603 805 0.01U 10K/F 0.1U 0.1U 10U
2

2
25 25 603 603 603 1206

2
25 25 25 25

2
PRV1
2

*VZ0603M260APT_NC PR161
47K
1

4 4

QUANTA
Title
COMPUTER
DCIN,BATT CONNECTOR

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 53 of 64

A B C D E
 1 2 3 4 5 6 7 8

FOR CPU use

TH1 TH2
H16 H9 H17 H10 H-TC118BC197D63P2 H-TC118BC197D63P2
*H-C276D177P2_NC *H-C276D177P2_NC *H-C276D177P2_NC *H-C276D177P2_NC
H-C276D157P2 H-C276D157P2 H-C276D157P2 H-C276D177P2

1
A A
1

1
For MiniCard nut use.
on 31' header

H3 H1 H24 H14 H13 H11

*H-TC315BC394D79P2_NC *H-TC315BC394D126P2_NC *H-TC315BC394D126P2_NC *H-TC315BC335D126P2_NC *H-C256D154P2_NC *H-C256D154P2_NC
H-TC315BC394D79P2 H-TC315BC394D126P2 H-TC315BC394D126P2 h-tc315bc295d126p2 H-C256D154P2 H-C256D154P2
1

1
For GPU nut use.

B B

H6 H27 H26 H19

*o-o177x472d177x472n_NC *H-TC315BC394D126P2_NC *H-TC315BC394D126P2_NC *h-fm8b-1_NC
o-o177x472d177x472n H-TC315BC394D126P2 H-TC315BC394D126P2 h-fm8b-1

H22 H20
*H-C256D154P2_NC *H-C256D154P2_NC
H-C256D154P2 H-C256D154P2
1

1
For PCH nut use.

H21 H15 H8 H2 PV1 PV2

*H-TC315BC394D126P2_NC *H-TC315BC394D126P2_NC *H-TC315BC394D126P2_NC *h-TC256BC315D110P2_NC
H-TC315BC394D126P2 H-TC315BC394D126P2 H-TC315BC394D126P2 h-TC256BC315D110P2 *PAD138X98XH_NC *PAD138X98XH_NC

GND

GND
1

C C

1
H5
*h-tc256bc315d126p2_NC
h-tc315bc394d126p2
1

H7 H4 H12 H25 H18

D *H-C228D228N_NC *H-C228D228N_NC *H-C197D197N_NC *H-C394D394N_NC *H-TC256BC315D126P2_NC D
H-C228D228N H-C228D228N H-C197D197N H-C394D394N H-TC256BC315D126P2

QUANTA
1

Title
COMPUTER
SCREW PAD

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 54 of 64

1 2 3 4 5 6 7 8
 5 4 3 2 1

Reserved for EMI.

D D

C C

B B

A A

QUANTA
Title
COMPUTER
EMI CAP

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 55 of 64

5 4 3 2 1
 1 2 3 4 5 6 7 8

+3.3V_SUS

A +3.3V_RUN A

2.2K 2.2K
2.2K 2.2K
+3.3V_RUN
H14 ICH_SMBCLK WLAN_SMBCLK 30
7002 MINICARD-WLAN
C8 ICH_SMBDATA WLAN_SMBDATA 32 /WWAN
7002
+3.3V_RUN 7
8 EXPRESS CARD

13
14 Fall Sensor

51
53 XDP

24
+3.3V_SUS
23 LAN
PCH
2.2K 2.2K
B B

G6 SMB_CLK_ME0
G8 SMB_DATA_ME0

+3.3V_SUS
+3.3V_ALW

10K 10K
2.2K 2.2K
+3.3V_SUS
E10 SMB_CLK_ME1 SMBCLK1 115
7002
G12 SMB_DATA_ME1 SMBDAT1 116 EC
7002
+3.3V_SUS
202
+3.3V_ALW
200 SO-DIMM
+3.3V_RUN
32
10K 10K 31 CLOCK
2.2K 2.2K
+3.3V_RUN
C 110 SMBCLK0 8 C
7002
111 7
THERMAL(EMC1422)
SMBDAT0
7002
+3.3V_RUN
9
10 CHARGER

100
4
3 BATTERY
+3.3V_ALW
SIO 100
+3.3V_SUS
ITE8502
10K 10K 2.2K 2.2K

+3.3V_SUS
115 SMBCLK1 SMB_CLK_ME1 115
7002
116 SMBDAT1 SMB_DATA_ME1 116 PCH
7002
+3.3V_ALW +3.3V_SUS

+3.3V_ALW
+3.3V_ADM1032A
D D

4.7K 4.7K
2.2K 2.2K
+3.3V_ADM1032A
117 SMBCLK2 8
7002
118 SMBDAT2 7 VGA THERMAL
7002
+3.3V_ADM1032A QUANTA
Title
COMPUTER
SMBUS BLOCK

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 56 of 64

1 2 3 4 5 6 7 8
 5 4 3 2 1

VCC
REM_DIODE1_P
(OPT) (REMOTE - 1)
REM_DIODE1_N
SMBus EC Fan PWM FAN
D
CPU Fan SIG. connector D

H_THERMTRIP#
EMC1422-1-ACZL-TR
THERM_STP# THERM_ALERT#

3/5V DC/DC
3/5V EN

C
VGA_THERMDP C
D+
D- VGA_THERMDN SMBus
GPU
ADM1032ARMZ-1
ALERT#
For Discrete Only
MB_THERM#

B B

A A

QUANTA
Title
COMPUTER
Thermal Map

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 57 of 64

5 4 3 2 1
 5 4 3 2 1

VER : 1A

Adapter
D D

PWR_SRC
Charger
MAX8731AETI+

Battery
TI TI TI TI MAXIM MAXIM
TPS51427A TPS51116REGR LDO TPS51218DSCR TPS51218DSCR MAX8792ETD+T MAX17036GTL+

IMVP_VR_ON
+5V_ALW2 ALW_ON SUS_ON RUN_ON
+1.5V_SUS
+15V_ALW +3.3V_ALW +5V_ALW +1.5V_SUS +VCC_CORE
+0.75V_DDR_VTT

C C

RUN_ON RUN_ON
GFX_ON

+1.05V_PCH +1.1V_VTT
+VCC_GFX_CORE

Fairchild Fairchild Fairchild Fairchild Fairchild Richtek

FDS8880 SI4800BDY SI4800BDY SI4800BDY FDS6298 RT9018B
RUN_ON SUS_ON RUN_ON SUS_ON RUN_ON GFX_ON

+3.3V_RUN +3.3V_SUS +5V_RUN +5V_SUS +1.5V_RUN +1.1V_GFX_PCIE

B B

Richtek Richtek
RT9024PE RT9018B
RUN_ON RUN_ON

+1.8V_RUN_GFX +1.8V_RUN

A A

QUANTA
Title
COMPUTER
Schematic Block Diagram1

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 58 of 64

5 4 3 2 1
 5 4 3 2 1

(1) AC : DC_IN -> DC_IN_SS -> +PWR_SRC

FM9 Power Design Block Diagram 2009/02/25 (2)
Bat : +VCHGR -> +PWR_SRC,+5V_ALW2,
SYS_PWR_SW#
+5V_VCC1 (from +5V_ALW2) (3) 3.3V_ALW_ON, ALW_ON
(1) (1) (1) (4) +3.3V_ALW, +5V_ALW, +15V_ALW
+DC_IN +DC_IN_SS +PWR_SRC +5V_ALW2 (5) SUS_ON
Power Jack LDO (1)
SYSTEM POWER (6) +5V_SUS, +3.3V_SUS, +1.5V_SUS, 1.5V_DDR_PWRGD
+3.3V_ALW
Adapter input +3.3V_ALW_ON(From (4) (7) ICH_RSMRST#
SI4835 SI4835 3VALW ON POWER LOGIC) +5V_ALW +5V_ALW +15V_ALW (8) SIO_PWRBTN#
(3) (4) (4)
Diode & Cap (4)
ALW_ON(For +5V_ALW and
TPS51427A VR (9) SIO_SLP_S5#, SIO_SLP_S4#, SIO_SLP_S3#
D D
Page 46
Charger (3) +15V_ALW turn on) (10) GFX_ON
Page 46 (11) +VCC_GFX_CORE, +1.1V_GFX_PCIE and PWRGD
ISL88731 (12) RUN_ON_1(RUN_ON)
Page 45 3V_ALW_PWRGD (13) +0.75V_DDR_VTT
+5V_ALW 5V_ALW_PWRGD (14) +5V_RUN, +3.3V_RUN, +3.3V_DELAY,
+1.8V_RUN_GFX, +1.5V_RUN, +1.1V_VTT,
+VCHGR (1) +1.5V_SUS +1.05V_PCH ad PWRGD
(1) VRAM DDR3 POWER (6)
+PWR_SRC (5) SUS_ON VR 1.5V_DDR_PWRGD (16) IMVP_VR_ON
Battery (6)
TPS51116 (17) +VCC_CORE, IMVP_PWRGD
(12) RUN_ON (18) RESET_OUT#
SI4835 +0.75V_DDR_VTT
Page 47 LDO (13) (19) ICH_PWRGD
(20) PM_DRAM_PWRGD
(21) CLK_CPU_BCLK(PCH to CPU)
+5V_ALW (22) H_PWRGOOD
(4) +5V_ALW SI4800 +5V_SUS (23) PLTRST#(PCI_PLTRST#)
(6)
PCH CORE POWER +1.05V_PCH
Page 52
(12) RUN_ON TPS51218 VR 1.05V_PWRGD (14)
(5) SUS_ON
Page 48
C C

(4) +3.3V_ALW SI4800 +3.3V_SUS

(6)
+5V_SUS +5V_ALW (4)
Page 52
+VCC_GFX_CORE
(5) SUS_ON GFX CORE POWER GFX PCIE POWER +1.1V_GFX_PCIE
VR (11)
GFX_CORE_PWRGD (11)
(10) GFX_ON (10) GFX_ON RT9018B VR GFX_PCIE_PWRGD

(4) +5V_ALW +5V_RUN

MAX8792ETD Page 50
SI4800 (14)
Page 52 (4) +5V_ALW
Page 50
+5V_ALW (4)
(12) RUN_ON

GFX POWER +1.8V_RUN_GFX

(4) +3.3V_ALW FDS8880 +3.3V_RUN (12) RUN_ON RT9024PE VR 1.8V_RUN_GFX_PWRGD (14)

(14)
Page 52 Page 44

(12) RUN_ON
+5V_SUS +3.3V_SUS +5V_ALW (4)

+3.3V_DELAY
(14) +3.3V_RUN SI2303 (14) CPU CORE POWER CPU Memory Control +1.1V_VTT
B
+VCC_CORE & I/O Power B

Page 17 (16) IMVP_VR_ON (12) RUN_ON VR 1.1V_VTT_PWRGD (14)

ISL6262A VR
TPS51218
IMVP_PWRGD
(10) GFX_ON TWO PHASE (17) Page 49
SOLUTION VR_PWRGD_CLKEN#
Reset Circuit
Page 42 (17)
Page 51 +5V_ALW (4)
+1.5V_RUN (17) VR_PWRGD_CLKEN# CK_PWRGD_R
(6) +1.5V_SUS FDS6298 (14) Inverter
CPU VCCPLL
Page 52
(17) (6) 1.5V_DDR_PWRGD
CLK GEN (12) RUN_ON RT9018B VR RUN_ON (12)
(12) RUN_ON CK_PWRGD_R AND Gate
(12) RUN_ON_1
Page 44
Page 15
1.1V_VTT_PWRGD
+1.8V_RUN (14)
(2) 1.05V_PWRGD HWPG (15)
1.8V_RUN_PWRGD (14) (14)
SYS_PWR_SW# 3.3V_ALW_ON
(3) (19) SIO_SLP_S4# (9) (11) GFX_PCIE_PWRGD
ALW_ON To control DIMM VREF (15)
(3) ICH_PWRGD
SUS_ON (11) GFX_CORE_PWRGD H_VTTPWRGD
EC (5) PM_DRAM_PWRGD (20) Wire AND
PCH
IT8512 SIO_PWRBTN# (8) 1.8V_RUN_PWRGD
CLK_CPU_BCLK (21) (14)
ICH_RSMRST# (7) CPU (14) 1.8V_RUN_GFX_PWRGD
H_PWRGOOD (22)
Page 7~12 (19)
A SIO_SLP_S5# (9) (17) IMVP_PWRGD A
PLTRST#(PCI_PLTRST#) Page 3~6 ICH_PWRGD
(23) AND Gate
SIO_SLP_S3# (9) (18) RESET_OUT#

Page 29 (15) H_VTTPWRGD

(15) HWPG
RUN_ON_1
(12)
QUANTA
IMVP_VR_ON
Title
COMPUTER
(16)
(17) IMVP_PWRGD Power Block Diagram
RESET_OUT#
(18) Size Document Number Rev
FM9 1A

Date: Wednesday, March 04, 2009 Sheet 59 of 64

5 4 3 2 1
 1 2 3 4 5 6 7 8

CN1

1 GND0 GND1 2
3 XDP_PREQ# 3 OBSFN_A0 OBSFN_C0 4
3 XDP_PRDY# 5 OBSFN_A1 OBSFN_C1 6
7 GND2 GND3 8
3 XDP_OBS0 9 OBSDATA_A0 OBSDATA_C0 10
A
3 XDP_OBS1 11 OBSDATA_A1 OBSDATA_C1 12 A
13 GND4 GND5 14
3 XDP_OBS2 15 OBSDATA_A2 OBSDATA_C2 16
3 XDP_OBS3 17 OBSDATA_A3 OBSDATA_C3 18
19 GND6 GND7 20
21 OBSFN_B0 OBSFN_D0 22
23 24 +3.3V_RUN
OBSFN_B1 OBSFN_D1
25 GND8 GND9 26
3 XDP_OBS4 27 OBSDATA_B0 OBSDATA_D0 28
3 XDP_OBS5 29 OBSDATA_B1 OBSDATA_D1 30
31 GND10 GND11 32
33 34 R490
3 XDP_OBS6 OBSDATA_B2 OBSDATA_D2
3 XDP_OBS7 35 OBSDATA_B3 OBSDATA_D3 36
37 38 +1.1V_VTT
+1.1V_VTT R152 1K H_CPUPWRGD_XDP GND12 GND13 BCLK_ITP_R 1K/F
3,10 H_PWRGOOD 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40
HOOK1 41 42 BCLK_ITP#_R
T20 PAD HOOK1 ITPCLK#/HOOK5
43 VCC_OBS_AB VCC_OBS_CD 44
R181 0 PCIE_CLK_XDP_P 45 46 XDP_RST#_R R489 1K
3 H_PWRGD_XDP HOOK2 RESET#/HOOK6 H_CPURST# 3
C700 TP_PCIE_CLK_XDP_N 47 48
T21 PAD HOOK3 DBR#/HOOK7 XDP_DBRESET# 3,7
*0.1U_NC 49 50 C677
GND14 GND15 *0.1U_NC
9,32,41 ICH_SMBDATA 51 SDA TDO 52 XDP_TDO 3
9,32,41 ICH_SMBCLK 53 SCL TRSTN 54 XDP_TRST# 3
55 56 51
TCK1 TDI XDP_TDI 3
57 58 R491
3 XDP_TCLK TCK0 TMS XDP_TMS 3
B
59 GND16 GND17 60 B
BCLK_ITP_R R150 0
BCLK_ITP 3
BCLK_ITP#_R R151 0
BCLK_ITP# 3
Samtec BSH-030-01

C C

D D

QUANTA
Title
COMPUTER
SMBUS BLOCK

Size Document Number Rev

FM9 1A

Date: Wednesday, March 04, 2009 Sheet 60 of 64

1 2 3 4 5 6 7 8