MODULE 2

BASICS OF ASSEMBLY LANGUAGE PROGRAMMING

1. OPCODE and MNEMONIC
Microprocessors recognize and operate in binary numbers.

Word

The number of bits the microprocessor recognizes and processes at a time is called a word.

Byte

A group of eight bits is called a Byte.

Nibble

A group of four bits is called a Nibble.

Instruction

To communicate with a microprocessor, we must give instructions in machine language (binary language). Each
combination of bit patterns that have given a specific meaning is called an instruction. (operation code/
opcode)
It instructs the microprocessor to perform a specific function.

Mnemonic

Since it is difficult to write instructions in binary (or hexadecimal), computer manufacturers have created
English-like words to represent the binary instructions. Symbolic code for representing an instruction is called
a mnemonic.

Assembler

Programs written using these words(mnemonic) are called assembly language programs. Programs written in
assembly language is translated into machine language using a program called an assembler.

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2. Instruction format of 8085
The entire group of instructions that a microprocessor is called the instruction set of that microprocessor. The
instruction set determines what functions the microprocessor can perform.

The 8085 instructions are classified into five functional categories

• Data transfer group.

• Arithmetic group.
• Logical group.
• Branching group.
• Machine control group.

Data transfer instructions

Data transfer instructions copies data from a source to a destination without modifying the contents of the
source. MOV, MVI, OUT and IN are the data transfer instructions available in the 8085 Microprocessor.

Data transfer instructions copies data from a source to a destination without modifying the contents of the
source.

They perform the following six operations:

• Load an 8-bit number in a register.

• Copy from register to register.
• Copy between I/O and accumulator.
• Load 16-bit number in a register pair.
• Copy between register and memory.
• Copy between registers and stack memory.

The complete list of data transfer instructions in 8085 is described in the following table.

MNEMONIC DESCRIPTION EXAMPLE

2-byte instruction.
MVI A, 57H
MVI R, 8-bit Loads the 8 bits of the second byte into the register specified.

1-byte instruction.
MOV B, C
MOV Rd, Rs Copies data from source register Rs to destination register Rd.

Copy the data byte into register from the memory specified by the
MOV B, C
MOV R, M address in HL register.

Copy the data byte from register into the memory specified by the
MOV B, C
MOV M, R address in HL register.

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 MNEMONIC DESCRIPTION EXAMPLE

2-byte instruction.
OUT 8-bit (port Sends the contents of the accumulator to the output port specified OUT 35
address) in the second byte.

2-byte instruction.
IN 8-bit (port Accepts data from the input port specified in the second byte, and IN 15
address) loads into the accumulator.

LXI B,
Load 16-bit number in a register pair
LXI Rp, 16-bit 2050H

Copy the data byte into A from the memory specified by 16-bit
LDA 1050H
LDA 16-bit address

Copy the data byte from A into the memory specified by 16-bit
STA 2070H
STA 16-bit address

Copy the data byte into A from the memory specified by the address
LDAX B
LDAX Rp in the register pair

Copy the data byte from A into the memory specified by the address
STAX D
STAX Rp in the register pair

Arithmetic instructions

Arithmetic instructions perform various arithmetic operations such as addition, subtraction, increment, and
decrement. ADD, ADI, SUB, SUI, INR and DCR are the arithmetic instructions available in the 8085
Microprocessor.

Arithmetic instructions perform various arithmetic operations such as addition, subtraction, increment, and
decrement.

Commonly used arithmetic operations are:

• Add
• Subtract
• Increment
• Decrement

The complete list of arithmetic instructions in 8085 is described in the following table.

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 MNEMONIC DESCRIPTION EXAMPLE

1-byte instruction
ADD R ADD B
Adds the contents of register R to the contents of the accumulator.

2-byte instruction
ADI 8-bit ADI 57H
Adds the second byte to the contents of the accumulator.

ADD M Adds the content of memory to A; the address of memory is in HL register. ADD M

1-byte instruction
SUB R SUB B
Subtracts the contents of register R from the contents of the accumulator.

2-byte instruction
SUI 8-bit SUI 34H
Subtract the second byte from the contents of the accumulator.

SUB M Subtracts the content of memory from A; the address of memory is in HL register. SUB M

1-byte instruction
INR R Increases the contents of register R by 1 INR D
Caution: All flags except the CY are affected.

INR M Increments the content of memory the address of which is in HL register. INR M

1-byte instruction
DCR R Decreases the contents of register R by 1 DCR B
Caution: All flags except the CY are affected

DCR M Decrements the content of memory the address of which is in HL register. DCR M

INX Rp Increments the content of the register pair. INX H

DCX Rp Decrements the content of the register pair. DCX B

All instructions except INR and DCR,

• Assume that the accumulator is one of the operands.

• Modifies all the flags according to the data conditions of the result.
• Place the result in the accumulator.
• Do not affect the contents of the operand register.

The INR and DCR instructions affect the contents of the specified register and all flags except the CY flag.

Logical instructions

A microprocessor can perform all the logic functions of the hard-wired logic through its instruction set. All logic
operations are performed in relation to the contents of the accumulator. ANA, ANI, ORA, ORI, XRA, XRI, and
CMA are the logical instructions available in the 8085 Microprocessor.

A microprocessor can perform all the logic functions of the hard-wired logic through its instruction set. These
instructions include:

• AND

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• OR
• Exclusive-OR
• Compare
• Rotate Bits

All logic operations are performed in relation to the contents of the accumulator. The complete list of logical
instructions in 8085 is described in the following table.

MNEMONIC DESCRIPTION EXAMPLE

This is a 1-byte instruction.

ANA R Logically ANDs the contents of the register R with the contents of the accumulator. ANA B
8085: CY is reset and AC is set

This is a 2-byte instruction.

ANI 8-bit Logically ANDs the second byte with the contents of the accumulator. ANI 2FH
8085: CY is reset and AC is set.

ANA M Logically AND the contents of the memory with the contents of A. ANA M

This is a 1-byte instruction.

ORA R ORA B
Logically ORS the contents of the register R with the contents of the accumulator

This is a 2-byte instruction.

ORI 8-bit ORI 37H
Logically ORS the second byte with the contents of the accumulator.

ORA M Logically OR the contents of the memory with the contents of A. ORA M

This is a I-byte instruction.

XRA R XRA B
Exclusive-ORs the contents of register R with the contents of the accumulator.

This is a 2-byte instruction.

XRI 8-bit XRI 6AH
Exclusive-ORs the second byte with the contents of the accumulator.

XRA M Exclusive OR the contents of the memory with the contents of A. XRA M

Compare the contents of register with the contents of A for less than, or equal to,
CMP R CMP B
or greater than.

Compare 8-bit data with the contents of register with the contents of A for less
CPI 8-bit CPI 4FH
than, or equal to, or greater than.

This is an I-byte instruction that complements the contents of the accumulator

CMA CMA
No flags are affected

RLC Rotate Accumulator left by one position.

RRC Rotate Accumulator right by one position.

RAL Rotate Accumulator left by one position through carry flag.

RAR Rotate Accumulator right by one position through carry flag.

The logic instructions:

• Assume implicitly that the accumulator is one of the operands.

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• Reset (clear) the CY flag. The instruction CMA is an exception; it has no effect on any flags.
• Modify the Z, P, and S flags based on the result’s data conditions.
• Store the result into the accumulator.
• Do not change the operand register’s contents.

Branching instructions

Branch instructions allow the microprocessor to change the sequence of the program, either unconditionally or
under certain conditions. JMP, JC, JNC, JZ, JNZ, JP, JM, JPE, JPO, CALL, RET and RST are the branching
instructions available in the 8085 microprocessor.

Branch instructions allow the microprocessor to change the sequence of the program, either unconditionally or
under certain conditions.

Branch instructions are classified into the following three categories.

• Jump instructions.
• Call and return instructions.
• Restart instructions.

Jump instructions are classified into two categories: Unconditional and conditional jump instructions.

Unconditional Jump Instructions

Unconditional jump instructions allow the programmer to set up continuous loops.

OPCODE OPERAND DESCRIPTION

JMP 16-bit address Jump to the specified location unconditionally.

Conditional Jump Instructions

Conditional jump instructions allow the microprocessor to make decisions based on certain conditions indicated
by various flags. They check the flag condition and decide to change or not change the sequence of the
program.

The flags used by conditional jump instructions are:

• Carry flag.
• Zero flag.
• Sign flag.
• Parity flag.

The complete list of conditional jump instructions in 8085 is described in the following table.

OPCODE OPERAND DESCRIPTION

JMP 16-bit address Jump to the specified location unconditionally.

JC 16-bit address Jump On Carry (if result generates carry and CY = 1)

JNC 16-bit address Jump On No Carry (CY = 0)

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 OPCODE OPERAND DESCRIPTION

JZ 16-bit address Jump On Zero (if result is zero and Z = 1)

JNZ 16-bit address Jump On No Zero (Z = 0)

JP 16-bit address Jump On Plus (if D7 = O, and S = 0)

JM 16-bit address Jump On Minus (if D7 = 1, and S = 1)

JPE 16-bit address Jump On Even Parity (P = 1)

JPO 16-bit address Jump On Odd Parity (P = 0)

Call and Return Instructions

The Call and Return instructions in 8085 are associated with the subroutine technique.

When the CALL instruction is executed, the 8085 stores the contents of the Program Counter on the top of the
stack and transfers the program to the location of the subroutine. The Return instruction inserts the element
from the top of the stack two the Program Counter.

These instructions are described in the following table.

OPCODE OPERAND DESCRIPTION

CALL 16-bit address Jumps unconditionally to the memory location specified by the address.

RET Return to the calling program after completing the subroutine sequence.

Restart Instruction

The Restart instruction in 8085 is associated with the interrupt technique. They are executed the same way as
Call instruction.

OPCODE OPERAND DESCRIPTION

RST 0-7 Reset the programming sequence.

Machine control instructions

Machine control instructions affect the operations of the processor. HLT and NOP are the machine control
instructions in the 8085 microprocessor.

These instructions affect the operation of the microprocessor. Halt and No operation are the two-program
control or machine control instructions.

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 OPCODE DESCRIPTION

Halt
1-byte instruction.
HLT The processor stops executing and enters waiting state.
The address bus and data bus are placed in high impedance state.
Register contents are not affected.

No Operation
1-byte instruction.
NOP
No operation is performed.
Generally used to increase processing time or substitute in place of an instruction.

3. Addressing modes of 8085

The way in which the operand of an instruction is specified is referred to as addressing modes. The addressing
mode specifies how the address field of the instruction is to be interpreted before the operand is actually
executed.

The 8085 microprocessor has 5 types of addressing modes.

Immediate Addressing Mode

In immediate addressing mode, the source operand is always data.

Example: MVI B 37H (Copy 37H immediately into register B)

Direct Addressing Mode

In direct addressing mode, the memory location where the data to be operated is directly specified as the
operand.

Example: LDA 2030 (Load operand in memory location 2030 to Accumulator)

Register Addressing Mode

In register addressing mode, the register in which the data to be operated is directly specified as the operand.

Example: MOV B (Copies data in register B into Accumulator)

Register Indirect Mode

In register indirect addressing mode, the memory location where the data to be operated is indirectly specified
by a register pair.

Example: MOV A, M (Move the contents of the memory location pointed by the H-L pair to the
Accumulator)

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Implied/Implicit Addressing Mode

In implied/ implicit addressing mode, the operand is hidden and the data to be operated is available implicitly in
the instruction.

Example: CMA (Complement Accumulator)

4. Instruction cycle and timing diagram

The timing diagram is a graphical representation of the process in steps with respect to time. It represents the
step by step working of each instruction and its execution. The execution time of instructions is represented in
T-states.

Machine Cycle– The time required to access the memory or input/output device is called the machine cycle.

T-states– The portion of an operation carried out in one clock period is called a T-state. A t-state is defined as
the time elapsed between the falling edge of one clock pulse and the falling edge of the next clock pulse.

Instruction Cycle

The time required to complete the execution of an instruction is called an instruction cycle. It may consist of
one or more machine cycles. The first of these is always the opcode fetch cycle. The following steps should be
performed to execute an instruction.

1. Fetch – The address stored in the program counter (PC) is used to fetch the next instruction, which is then
stored in the instruction register.
2. Decode – The encoded instruction from the instruction register is interpreted by the decoder.
3. Reading effective address – The address specified in the instruction is read from main memory, and the
required data is fetched. The effective address is determined by whether direct or indirect addressing is
used.
4. Execute – Consists of memory read (MR), memory write (MW), input output read (IOR) and input output
write (IOW).

The fetch cycle takes 4 t-states and the execution cycle takes 3 t-states. A typical instruction cycle and the
machine cycles within it is shown in the figure.

Typical Instruction Cycle

Opcode Fetch Machine Cycle

Every instruction’s first machine cycle is an opcode fetch machine cycle, during which the 8085 microprocessor
determines the type of instruction to be executed. During this machine cycle, the processor puts the contents

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of the programme counter to the address lines and reads the instruction’s opcode through the read process.
The following figures show the timing diagram for the opcode fetch machine cycle.

Timing Diagram of 8085 Opcode Fetch Machine Cycle

The number of states in the opcode fetch machine cycle may vary from 4T states to 6T states as per the
instruction. The following is a detailed step-by-step explanation of the opcode fetch cycle.

State T1

• Places the contents of PC on the address bus.

• The higher order bits(PCH) is placed on the A15-A8 lines.
• The lower order bts(PCL) is placed on the AD7-AD0 lines.
• ALE signal goes high in the beginning to indicate that AD7-AD0 contains lower address bits.
• ̅ specifies whether it is a memory or I/O operation.
The status signals IO / 𝑀
• The S1 status signal specifies whether it is read/write operation.
• In opcode fetch machine cycles status signals are: IO / 𝑀 ̅ =0, S1=1, S0=1.

State T2

• The lower order address disappears from the AD7-AD0 lines.

• The ̅̅̅̅
𝑅𝐷 signal is set to 0 to enable the addressed memory location.
• The contents of addressed memory location is placed on the databus (AD7-AD0).

State T3

• The opcode is loaded into the instruction register from the databus.
• The ̅̅̅̅
𝑅𝐷 is raised to 1 which disables the memory device.

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State T4

• Decodes the opcode.

• One byte instructions that operate on 8bit data are executed in T4.

Memory Read Machine Cycle

During the memory read machine cycle, the contents of a memory location are read. This machine cycle is
made up of three T states. The first three T states are almost the same as the first three T states of the Opcode
Fetch Machine Cycle. The following figures show the timing diagram for the memory read machine cycle.

Timing Diagram of 8085 Memory Read Machine Cycle

The number of states in the opcode fetch machine cycle may vary from 4T states to 6T states as per the
instruction. The following is a detailed step-by-step explanation of the memory read machine cycle.

State T1

• Higher address bits have been loaded into A8-A15.

• Lower address bits have been loaded into AD0-AD7.
• In the beginning, the ALE signal is high, indicating that AD0-AD7 includes lower address bits.
• ̅ goes low since it is a memory operation.
IO / 𝑀
• S1 and S0 become 1 and 0, signifying a Memory Read Machine Cycle.
• By the end of the first T state, ALE goes low. Lower address bits should be latched by this time.

State T2 and T3

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• ̅̅̅̅
𝑅𝐷 goes low, indicating that the read process takes place.
• Data is read from memory and placed onto the data bus AD0-AD7.
• The data is loaded into the data bus at the start of the T2 state and remains in place until the end of the
T3 state.
• ̅̅̅̅
𝑅𝐷 gets high at the end of the T3 state, signifying the end of the read operation.

Memory Write Machine Cycle

Contents are written to a memory location/stack during a memory write machine cycle. This machine cycle is
made up of three T states. The following figures show the timing diagram for the memory write machine cycle.

Timing Diagram of 8085 Memory Write Machine Cycle

The following is a detailed step-by-step explanation of the memory write machine cycle.

State T1

• Higher address bits have been loaded into A8-A15.

• Lower address bits have been loaded into AD0-AD7.
• In the beginning, the ALE signal is high, indicating that AD0-AD7 includes lower address bits.
• ̅ goes low since it is a memory operation.
IO / 𝑀
• S1 and S0 become 0 and 1, signifying a Memory Write Machine Cycle.
• By the end of the first T state, ALE goes low. Lower address bits should be latched by this time.

State T2 and T3

• ̅̅̅̅̅ goes low, indicating that the write process has begun.
𝑊𝑅

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• Data to be written is loaded onto the data bus at the start of the T2 state and remains on the data bus until
the end of the T3 state.
• WR goes high at the end of the T3 state, signifying the end of the write operation.

5. Simple Programs for 8085 Microprocessor

8085 program to store a 8 bit data in memory

MVI A, 24H
STA 1423H
HLT

1. MVI A, 24H – store 24H in the accumulator.

2. STA 1423H – copy the contents of accumulator to memory loaction 1423H.
3. HLT – stop the execution.

8085 program to add two 8 bit data numbers

LXI H, 1500H
MOV A, M
INX H
ADD M
INX H
MOV M, A
HLT

1. LXI H, 1500H – store the address of first number (1500 H) in HL register pair.
2. MOV A, M – copy the contents of memory loaction to accumulator.
3. INX H – increments the contents of HL register pair. HL now points to 1501H.
4. ADD M – Add first operator in the accumulator with the second operator in memory location 1501H.
5. INX H – HL now points to 1502H.
6. MOV M, A – store result in accumulator at location 1502H.
7. HLT – stop the execution.

Example

1st operand (1500) - 1A

2nd operand (1501) - B7
Result (1502) - 1A + B7 = D1

8085 program to subtract two 8 bit data numbers

LXI H, 1500H
MOV A, M

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INX H
SUB M
INX H
MOV M, A
HLT

8085 program to find 1s compliment of a number

LDA 1500H
CMA
STA 1501H
HLT

8085 program to find 2s compliment of a number

LDA 1500 H
CMA
ADI, 01 H
STA 1501 H
HLT

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