ADVANCED DIGITAL SYSTEM DESIGN

Data Types

Dr. Dipali Borakhade

Assistant professor
St. Vincent Pallotti college
of engineering and
technology , Nagpur
 Data Types
q The data used in the hardware system is of several types to match the need for
describing the hardware.
q The data used in the hardware system is of several types to match the need for
describing the hardware.
q VHDL is a type oriented language. Many operations cannot be executed without
choosing the right type of data types for the operands. There are 5 major data types.
q It is also possible to have user defined data types and subtypes.
The values of the scalar object types are numeric. It is sub divided into 8 types.
q Bit type: the only value used is 0 or 1.
q Boolean type: the only value used is true(1) or false(0).
q Integer type: all integer values are used. “range” is used to define a shorter range of
q Integer. “natural” is used when all values are positive.
q Real type: this type accepts fractions.
q Character type: this type includes characters that can be used to print a message.
This is done by “report” command.
q Physical type: this type has values that can be measured in units. Ex time.
q User defined: the user can define a type using “type” followed by identifier.
q Severity type: this type can take one of the four values note, warning, error, failure.
•Integer •Real
•Minimum range for any •Minimum range for any
implementation as defined by standard: implementation as defined by standard:
-2,147,483,647 to 2,147,483,647 -1.0E38 to 1.0E38
v It is used to represent physical quantities such as distance , current , time and so on.
v The smallest unit representable is one base unit and largest is determined by the
range specified in physical type declaration

TYPE time IS RANGE 0 to 1E18

Type resistance IS Range 0 to 1000000 UNITS
Units FS; -- femtosecond
PS = 1000 FS; -- picosecond
Ohm ; -- Ω NS = 1000 PS; -- nanosecond
US = 1000 NS; -- microsecond
Kohm = 1000 ohm ; -- 1 K Ω MS = 1000 US; --millisecond
Mohm = 100 0Kohm ; -- 1MΩ SEC = 1000 MS; -- second
MIN = 60 SEC; -- minute
End units ; END UNITS;
Example
VARIABLE X : distance;
VARIABLE Y : time;
X := 5 A + 14 inch – 45 mil;
Y := 3 ns + 5 min;
q An enumerated data types is very powerful tool for abstract modelling.
q All of the values in enumerated data types are user defined.
q User can define exact values required for specific application.
q Values can be identifier or single character literals
q The order in which values appear defined their ordering.
q When using relational operators , the left value is always greater than the value
that appears to the right. Position numbers are associated with them
q type Fourval is ( ‘X’ , ‘0’, ‘1’ , ‘Z’);
q type opcodes is (add, sub, jump, call);
q Type color is (red ,yellow, blue, green, orange);
q Type MICRO_OP is ( LOAD, STORE, ADD, SUB, MUL, DIV);
ARCHITECTURE test_enum OF test IS
TYPE binary IS ( ON, OFF );
Variable a;
BEGIN
PROCESS
VARIABLE a: binary; --types are user defined.
BEGIN
a := ON; -- OK
... more statements ...
a := OFF; -- OK
... more statements ...
END PROCESS;
END test_enum;
v The predefined enumerated data types of VHDL v bit values: '0', '1'
language are CHARACTER, BIT, BOOLEAN, v boolean values: TRUE, FALSE
SEVERITY LEVEL, FILE_OPEN_STATUS. v integer values: -(231) to +(231 - 1) {SUN Limit}
v The values belonging to type CHARACTER consist v natural values: 0 to integer'high (subtype of integer)
of 191 character literals and always written in v positive values: 1 to integer'high (subtype of integer)
between the quotes (‘ ‘) v character values: ASCII characters (eg. 'A')
v time values include units (eg. 10ns, 20us)
v The composite data type is a collection of values.
v There are two classes of composite types: arrays containing elements of the same
type, and records containing elements of different types.
v This represents the collection of TYPE my_word IS ARRAY (0 to 31) of BIT;
values of single type. TYPE regs IS ARRAY (7 downto 0) of std_logic;
v This type is defined by using the pre TYPE rom IS ARRAY (0 to 125) of regs;
defined word “array”. TYPE reg_type IS ARRAY (15 DOWNTO 0) OF BIT;
v Arrays can be multi dimensional
(similar to arrays in C). VARIABLE X : reg_type;
v Elements of array can be accessed VARIABLE Y : BIT;

by specifying the index values into Y := X(4); -- Y gets value of element at index 4
array.
v It is Used to group elements of possibly different types into a single VHDL object.
v In VHDL, records help the designer organize data that belongs together.
v This data type can be composed of same or different data types (similar to
structures in C).
v It is possible to make arrays of records
type t_rec1 is record -- Declare a record with two fields
f1 : std_logic;
f2 : std_logic_vector(7 downto 0);
end record t_rec1;

constant ABC : t_rec1;

-- Declare a constant: declare the value of each field
-- Recommended: use name binding
constant XYZ : t_rec1 := ('1', (others => '1') );
-- Not recommended: positional binding for record constants
v The values belonging to access are pointers to objects of other types(similar to
pointers in C).
v Application of access types is restricted to variables: only variables can be of an access
value. Also, only variables can be designated by an access value.

-- declaration of record type Person:

type Person is record
address : ADRESS_TYPE;
age : DATE;
end record Person;
-- declaration of access type Person_Access:
type Person_Access is access Person;
Declare a type for creating file handles.
The file type is used to define objects representing files in the host environment.
The value of a file object is the sequence of values contained in the physical file.
The type mark in the file declaration defines the subtype of the values contained in the file

type identifier is file of type_mark ;

type my_text is file of string ;
type word_file is file of word ;
file output : my_text; file_open(output, "my.txt", write_mode);
write(output, "some text"&lf);
file_close(output);