+

A Top-Level View of Computer

Function and Interconnection
+ Data
Sequence of
arithmetic
and logic
functions
Results

(a) Programming in hardware

Instruction Instruction
codes interpreter

Control
signals

General-purpose
Data arithmetic Results
and logic
functions

(b) Programming in software

Figure 3.1 Hardware and Software Approaches

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 Software
• A sequence of codes or instructions
• Part of the hardware interprets each instruction and
generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware

Major components:
• CPU
• Instruction interpreter
• Module of general-purpose arithmetic and logic
functions
• I/O Components
+ • Input module
• Contains basic components for accepting data and
instructions and converting them into an internal
form of signals usable by the system
• Output module
• Means of reporting results
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 • Specifies the address • Contains the data to
in memory for the be written into
next read or write memory or receives
the data read from
memory

• Specifies a particular • Used for the

+ I/O device exchange of data
between an I/O
module and the CPU

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 CPU Main Memory
0
System 1
2
PC MAR Bus
Instruction
Instruction
Instruction
IR MBR

I/O AR
Data
E xecution
Data
unit I/O BR Data
Data

I/O Module n–2

n–1

PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register

Figure 3.2 Computer Components: Top-L evel View

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 Fetch Cycle E xecute Cycle

Fetch Next E xecute

START HALT
Instruction Instruction

Figure 3.3 Basic Instruction Cycle

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+

n At the beginning of each instruction cycle the processor

fetches an instruction from memory

n The program counter (PC) holds the address of the

instruction to be fetched next

n The processor increments the PC after each instruction

fetch so that it will fetch the next instruction in sequence

n The fetched instruction is loaded into the instruction

register (IR)

n The processor interprets the instruction and performs the

required action

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 • Data transferred from • Data transferred to or
processor to memory from a peripheral
or from memory to device by
processor transferring between
the processor and an
I/O module

• An instruction may • The processor may

specify that the perform some
sequence of arithmetic or logic
execution be altered operation on data

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 0 3 4 15
Opcode Address

(a) Instruction format

0 1 15
S Magnitude

(b) Integer format

Program Counter (PC) = Address of instruction

Instruction Register (IR) = Instruction being executed
Accumulator (AC) = Temporary storage

(c) Internal CPU registers

0001 = Load AC from Memory

0010 = Store AC to Memory
0101 = Add to AC from Memory

(d) Partial list of opcodes

Figure 3.4 C haracteristics of a Hypothetical Machine

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 Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 0 PC 300 1 9 4 0 3 0 1 PC
301 5 9 4 1 AC 301 5 9 4 1 0 0 0 3 AC
302 2 9 4 1 1 9 4 0 IR 302 2 9 4 1 1 9 4 0 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 2
Step 1 Step 2
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0 2 PC
301 5 9 4 1 0 0 0 3 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 5 9 4 1 IR 302 2 9 4 1 5 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3 3+2=5
941 0 0 0 2 941 0 0 0 2
Step 3 Step 4
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 3 PC
301 5 9 4 1 0 0 0 5 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 2 9 4 1 IR 302 2 9 4 1 2 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 5
Step 5 Step 6

Figure 3.5 E xample of Program E xecution

(contents of memory and registers in hexadecimal)
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+

n I/O module can exchange data directly with the processor

n Processor can read data from or write data to an I/O module

n Processor identifies a specific device that is controlled by a
particular I/O module
n I/O instructions rather than memory referencing instructions

n In some cases it is desirable to allow I/O exchanges to occur

directly with memory
n The processor grants to an I/O module the authority to read from
or write to memory so that the I/O memory transfer can occur
without tying up the processor
n The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
n This operation is known as direct memory access (DMA)

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 Read Memory
Write
N Words
Address 0 Data

Data N– 1

Read I/O Module Internal

Write Data

E xternal
Address M Ports Data

Internal
Data Interrupt
Signals
E xternal
Data

Instructions Address

Control
Data CPU Signals

Interrupt Data
Signals

Figure 3.15 Computer Modules

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 The interconnection structure must support the
following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

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 A communication pathway Signals transmitted by any one
connecting two or more device are available for
devices reception by all other devices
•Key characteristic is that it is a shared attached to the bus
transmission medium •If two devices transmit during the same
time period their signals will overlap and
become garbled

Typically consists of multiple

Computer systems contain a
communication lines
number of different buses that
•Each line is capable of transmitting signals provide pathways between
representing binary 1 and binary 0
components at various levels
of the computer system
hierarchy

System bus
•A bus that connects major computer The most common computer
components (processor, memory, I/O)
interconnection structures are
based on the use of one or
more system buses

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 n Data lines that provide a path for moving data among system
modules

n May consist of 32, 64, 128, or more separate lines

n The number of lines is referred to as the width of the data bus

n The number of lines determines how many bits can be

transferred at a time

n The width of the data bus

is a key factor in
determining overall
system performance

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+ Address Bus Control Bus

n Used to designate the source or

destination of the data on the n Used to control the access and the
data bus use of the data and address lines
n If the processor wishes to
read a word of data from n Because the data and address lines
are shared by all components there
memory it puts the address of
must be a means of controlling their
the desired word on the
use
address lines
n Control signals transmit both
n Width determines the maximum command and timing information
possible memory capacity of the among system modules
system
n Timing signals indicate the validity
n Also used to address I/O ports of data and address information
n The higher order bits are
used to select a particular n Command signals specify operations
module on the bus and the to be performed
lower order bits select a
memory location or I/O port
within the module
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 CPU Memory Memory I/O I/O

Control lines

Address lines Bus

Data lines

Figure 3.16 Bus Interconnection Scheme

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+
Instruction Set
n The repertoire of instructions of a computer
n Different computers have different
instruction sets
n But with many aspects in common
n Early computers had very simple
instruction sets
n Simplified implementation
n Many modern computers also have simple
instruction sets
n All
have a common goal: to find a language that
makes it easy to build the hardware
+ Instruction Set Architecture, ISA
+
Memory Addressing
+
Byte-Order (“Endianness”)
+
Little or Big Endian ?
+
Addressing Mode ?

n Where can operands/results be located?

n Recall
that we have two types of storage in
computer :

n registersand memory
n A single operand can come from either a register
or a memory location
n Addressing modes offer various ways of specifying
the specific location
+ Addressing Modes Visualization (1)
+ Addressing Modes Visualization (2)