TELKOMNIKA Telecommunication Computing Electronics and Control

Vol. 22, No. 1, February 2024, pp. 190~201

ISSN: 1693-6930, DOI: 10.12928/TELKOMNIKA.v22i1.25707  190

Proposing a new method for calculating DC sources in an

extended multilevel converter

Afzal Keivanlou Shahrestanaki1, Rahim Ildarabadi1, Mahmoud Zadehbagheri2, Tole Sutikno3,4

1
Department of Electrical Engineering, Hakim Sabzevari University, Sabzevar, Iran
2
Department of Electrical Engineering, Yasuj Branch, Islamic Azad University, Yasuj, Iran
3
Master Program of Electrical Engineering, Faculty of Industrial Technology, Universitas Ahmad Dahlan, Yogyakarta, Indonesia
4
Embedded System and Power Electronics Research Group, Yogyakarta, Indonesia

Article Info ABSTRACT

Article history: In this paper, we propose a method for calculating the DC source amplitude
in an extended multilevel inverter (MLI) structure so that the maximum
Received Sep 9, 2023 number of levels and the output voltage waveform are as close as possible to
Revised Dec 6, 2023 the sinusoidal wave with minimum total harmonic distortion (THD). For the
Accepted Dec 15, 2023 developed structure, three algorithms are suggested to determine the amounts
of DC voltage resources. The first important point about choosing the right
amounts for the DC resources is that the number of levels should be as large
Keywords: as possible, and the second important point is that the intervals between the
levels should be the same throughout the waveform. By observing these two
Cascaded points, the output voltage waveform can be as near as possible to the
H-bridge sinusoidal wave that we want. In this study, we used iteration-based methods
Multilevel inverter to find suitable values for DC sources. Simulation results are offered to
Power electronics confirm the capability of the extended multilevel converter. After we solved
Switches the problem through calculation and analysis, a code was written in MATLAB
Topology with the aim that this time the code will tell us for what values of DC sources
we will have the largest number of levels and as we expected, the output of
the MATLAB code confirmed the correctness of the calculations.
This is an open access article under the CC BY-SA license.

Corresponding Author:
Rahim Ildarabadi
Department of Electrical Engineering, Hakim Sabzevari University
Sabzevar, Iran
Email: [email protected]

NOMENCLATUR

𝐼(𝑡): Instantaneous current 𝑁𝐿 : Number of voltage levels

𝑛𝑝 : Number of voltage levels 𝑉𝐴𝐵 (𝑡): Instantaneous output voltage (line-to-line)
𝑉𝐴𝑁 (𝑡): Voltage of phase-to-neutral 𝑁𝑐 : Number of capacitors (each arm)
𝐼𝑐 : Current of conduction (through the switches) 𝑉𝑑𝑐: DC voltage source (isolated)
𝑁𝑙𝑒𝑣𝑒𝑙 : Number of levels (output voltage 𝑁𝑠𝑡𝑒𝑝 : Number of steps
waveform) 𝑇𝑠−𝑜𝑓𝑓 : Time switch (turn off)
𝑁𝑠𝑤𝑖𝑡𝑐ℎ : Number of switches 𝑇𝑡𝑜𝑡𝑎𝑙 : Time total (switch is on)
𝑇𝑠−𝑜𝑛 : Time switch (turn on) 𝑉𝐵𝑙𝑜𝑐𝑘 : Blocking voltage (switch)
𝑉(𝑡): Instantaneous voltage 𝑉𝑐 : Voltage of conduction (through the switches)
𝐴𝑘 : Switching angle Ө𝑜 : Phase-shifted sinusoidal modulator
𝑑(𝑡): Instantaneous duty cycle 𝑉𝑛 (𝑡): Instantaneous voltage (switch of the nth inverter
𝑉𝑢𝑐 : Upper arm instantaneous capacitor voltage leg)
𝑀: Index of modulation 𝑓𝑜 : Frequency modulator

Journal homepage: http://telkomnika.uad.ac.id

TELKOMNIKA Telecommun Comput El Control  191

𝑊𝑜 : Angular frequency modulation 𝑉𝑜𝑓 : Voltage magnitude of fundamental component

𝑉𝐿𝐶 : Lower arm capacitor voltage 𝑉𝑜𝑖 : Voltage magnitude of harmonic components

1. INTRODUCTION
For the first time, David Prince published an article titled “Inverter” in General Electric Review in
1925. In that article, he listed almost all the parts needed in inverters [1]. Currently, inverters have become an
integral part of many electrical appliances, from household appliances such as refrigerators and washing
machines to advanced industrial and military equipment. From another viewpoint, inverters are used in all
stages from producing electricity in power plants and transmission lines to the customer end. In simple terms,
an inverter is a device that converts DC voltage to AC voltage with the desired frequency and amplitude [2]–[4].
There are different types of inverters depending on the type of application as well as the type of circuit topology.
One of the most widely used inverters is multilevel inverters (MLIs), which have been widely studied today.
The most important challenge for this type of inverter is to increase the number of output voltage levels to bring
the output voltage waveform closer to the sine wave, as well as to reduce the number of components and voltage
sources used in them, provided that reducing the components does not reduce the quality of the output waveform,
and we see that many papers have been published in recent years with the phrase “reduced device count” and
similar phrases in the title of the paper [5]–[8]. Today, MLIs are used in a variety of industrial applications.
Such as renewable energy (RE) and flexible AC transmission system (FACTS) devices. Multilevel converters
have many benefits, such as improving the output voltage, reducing the total harmonic distortion (THD) and
reducing the stress on the switches compared to typical two-level converters [9].
MLIs have several different topologies, such as H-bridges, neutral point clamps (NPCs), and flying
capacitors (FCs). They can also be used to drive induction motors. One of the most popular topologies for
induction motor drives is the NPC type introduced in [10], in which the voltage of capacitors is unbalanced and
requires balancing methods [11]. FC topology was introduced in the 1990s by Lavieville et al. [12]. A cascaded
H-bridge (CHB) multilevel converter was introduced in [13]. It is a suitable topology for FACTS devices such as
STATCOM. The disadvantages that can be considered are the level of reliability due to the use of a high number
of parts [14] and the high variety in the magnitude of DC voltage sources in CHB inverters [15]. The most
common configurations for CHB topology are binary and binary; if each voltage source is twice the previous
source, the configuration will be binary, and if it is three times, the configuration will be trinary [16], [17].
A new structure of high-level multilevel converter is presented in [18]. The problem focuses on
minimizing the number of power MOSFETs for a given number of levels. Different combinations of topologies
are presented and the corresponding mathematical relations are obtained. This paper offers optimized curves
to obtain the relationship between the minimum number of power semiconductors required for a given number
of levels. For example, a CHB converter with three batteries can produce 15 voltage levels in binary and 27
voltage levels in trinary configurations. Therefore, choosing the value of DC sources in multilevel inverters
can be one of the most challenging steps for design and researchers may propose several methods for selecting
the amplitude of dc sources for each presented topology [19], [20].
PV system converters usually include two section: A DC to DC converter and a PWM inverter. This
cascade structure has drawbacks such as reduced efficiency and problems in maximum power point tracking [21].
Introduces a single phase 9-level hybrid inverter (H9LI). An innovative method has been used to balance the
voltage of the capacitors in this inverter.
An optimized topology of a 3-phase MLI is presented, in which the parts of level production and
sequence generation are separated from each other and become modular [22]. The advantage of this modular
structure is that to produce more voltage levels in this inverter, we have to increase the number of components
only in the level production part because in this structure, DC sources are shared equally between each phase,
and the “asymmetry of the phases” problem is solved [23]. A new method for generating more voltage levels
by stacking or connecting multilevel converters that have a spatial vector structure is proposed, one of the
advantages of which is the number of DC sources needed less than other structures [24]. A limitation of MLIs
is the limitation in switching frequency due to the increase in heat loss, especially at high powers. On the other
hand, the smaller the switching frequency, the more harmonics in the output waveform of the inverter, and this
is not to our liking [25], [26].
A method was introduced to remove harmonics in the output waveform at low switching frequencies [27].
However, the main idea of this manuscript is obtained from [17], where the author provided a new extended
multilevel topology that can be extended in both horizontal and cascade extension modes. After introducing
the topology, the main problem is how to choose the value of each DC source for generating maximum voltage
levels at the output.
Alishah et al. [17], two methods for calculating the value of DC sources in both horizontal and cascade
modes are extended, but the reason for using those methods is not mentioned. In this paper, we will show why

Proposing a new method for calculating DC sources in an extended … (Afzal Keivanlou Shahrestanaki)
192  ISSN: 1693-6930

the method is presented by [17] in the case of horizontal expansion. In subsection 2.1, the basic unit topology
presented by [17] is introduced, and the magnitude of DC sources in the primary unit for creating the maximum
voltage levels is calculated in subsection 2.2. Then, the submultilevel topology is introduced in subsection 2.3,
and again, the magnitude of DC sources in the submultilevel topology for creating the maximum voltage levels
is calculated in subsection 2.4. Finally, in section 3, according to the described process, a MATLAB code was
introduced. This code can calculate the best values for DC sources, and its most important feature is that it can
be used for any other CHB-based topology [18], [28]. A method for removing the DC component of the output
current of transformerless inverters is proposed [19]. The use of two separate paths for two half-cycles of the
flow in order to minimize circulating currents has also been suggested in [29].
A new topology for multi-level inverter circuit with series connection is introduced, which is used to
connect distributed generation sources to the grid without the need for transformers [1]. Usually, the design of
such circuits is based on the ability to inject current and power into the network, minimizing output current
harmonics and some physical limitations such as isolating distributed generation sources from the network. In
addition to injecting the maximum possible active power, the circuit proposed in this article can also
compensate some harmonics of the load current indicator as an active filter. Basic multi-level modules based
on switched capacitors are presented for cascade applications, which use series and parallel methods for
automatic capacitor voltage balancing [30].
In this paper, a method for calculating the DC source amplitude in an extended multilevel converter
topology was presented. The topology consists of a basic module that can be extended to produce more voltage
levels. In previous articles, the authors introduced methods to calculate the range of resources, but they did not
provide a reason for introducing these methods.
In this research, at the beginning, all the possible modes were extracted to produce voltage at the
output. Then, they were sorted from large to small based on the proposed algorithm. Finally, the values of the
DC sources were calculated in such a way as to create the maximum number of voltage levels with the same
intervals, which leads to a reduction in THD and a smaller number of parts. After we solved the problem
through calculations and analysis, a code was written in MATLAB with the aim that this time the code will tell
us for what values of DC sources we will have the highest number of levels.
As we expected, the output of the MATLAB code confirmed the correctness of the calculations. This
MATLAB code can be used for any other topology in such a way that first, the voltages that can be generated
at the output of the circuit are parametrically extracted and fed to the MATLAB code. The most important
application of the newly proposed structure is in the drive of electric motors used to remove harmonics using
switching and optimization algorithms such as particle swarm optimization (PSO) and Bee. Additionally, direct
torque control is another application of the proposed structure in induction motors, which provides less torque
ripple.
Additionally, the proposed topology is used in power system applications such as high voltage direct
current (HVDC), reactive power compensation, voltage drop compensation, and photovoltaic systems. To
show the advantages and capabilities of the proposed structure in this paper, the proposed algorithms are
compared with the algorithms and topologies of other papers. As shown in Table 1, these comparisons are
studied from the point of view of the number of insulated-gate bipolar transistors (IGBTs), cost, number of
voltage levels, number of capacitors and power diodes, and number of impedance sources.

Table 1. Comparison of the number of sources, IGBTs, and cost comparison

Number of Number of Number of Number of Number of Total cost
References Algorithm
sources IGBTs voltage levels capacitors power diodes (USD)
[5] First, second third 6 18 125 4 0 81.5
[11] Symmetrical 8 20 17 5 8 111.95
[14] First, second 3 10 13 0 0 66.75
[15] First, second, 10 20 11 3 0 80.63
third (PWM)
[31] asymmetric 2 9 13 4 0 63.33
[19] CHB-MLI 5 20 11 0 1 75.03
[20] First, second third 2 8 11 3 14 141
[24] First, second, 7 16 63 0 19 126.5
third, fourth
[17] First, second 4 10 39 2 1 −
This paper First, second, 4 10 17 0 0 −
third

TELKOMNIKA Telecommun Comput El Control, Vol. 22, No. 1, February 2024: 190-201
TELKOMNIKA Telecommun Comput El Control  193

2. INTRODUCING THE TOPOLOGY

2.1. Introducing the basic unit topology
The basic circuit of the topology is shown in Figure 1. This topology consists of two bidirectional
switches, six unidirectional switches and four DC voltage sources. Each unidirectional switch includes an
antiparallel diode and an IGBT. The type of bidirectional switches is a common emitter and consists of two
IGBTs and two antiparallel diodes and requires only one gate pulse [5], [30]. The two sources have the same
amplitude V1, and the other two sources have the same amplitude 𝑉̅ 1. As mentioned, this circuit is a basic
circuit that has the ability to produce 17 voltage levels, and the way they produce levels is given in Table 2. To
produce more levels, the basic unit can be extended to a submultilevel circuit, as shown in Figure 2.

Figure 1. Basic unit circuit for new extended multilevel Figure 2. Proposed submultilevel topology
converter topology

Table 2. Switching states for the basic unit for extended multilevel converter topology
State ON switches 𝑉𝑜𝑢𝑡
1 T1 , Sx , T1 0
T2 , Sy , T2
2 S1 , T2 , Sy V1
3 S1 , T1 , Sx −V1
4 S1 , T2 , Sy V1
5 S1 , T1 , Sx −V1
6 T1 , T2 , Sy 2V1
7 T1 , T2 , Sx −2V1
8 T1 , T2 , Sy 2V1
9 T1 , T2 , Sx −2V1
10 S1 , S1 , Sy V1 + V1
11 S1 , S1 , Sx −(V1 + V1 )
12 T1 , S1 , Sy 2V1 + V1
13 T2 , S1 , Sx −(2V1 + V1 )
14 S1 , T1 , Sy V1 + 2V1
15 S1 , T2 , Sx −(V1 + 2V1 )
16 T1 , T1 , Sy 2V1 + 2V1
17 T2 , T2 , Sx −(2V1 + 2V1 )

2.2. Determining the DC sources amplitude for the basic unit

To determine the amplitude of DC voltage sources at each level, Alishah et al. [17] proposed two
methods, first and second. The procedure is the same in both methods, but the number of levels in the second
method is greater than that in the first method, so we only investigate the second method. In this method, the
relationships are as (1) and (2) [20], [32].

𝑉1 = 𝑉𝑑𝑐 (1)

𝑉1 = 3 𝑉𝑑𝑐 (2)

Proposing a new method for calculating DC sources in an extended … (Afzal Keivanlou Shahrestanaki)
194  ISSN: 1693-6930

The problem that can be introduced in both methods and the author did not answer to it is that what is
the basis of the mentioned relations for calculating the amplitude of DC voltage sources? why the value of V
should be 3 times of the value of 𝑉̅ ? why not, for example, 4 or 5 times? this is a question that the author has
not answered and we will answer to it in this manuscript. As mentioned earlier, all the voltage levels that can
be generated using the basic unit shown in Figure 1 are listed in Table 2. There are no other levels because the
absolute value of the largest voltage that can be generated is 2𝑉̅1 + 2𝑉1 and the smallest voltage level after
zero is 𝑉̅1 Additionally, to generate all voltage levels, the spacing between the two levels must be 𝑉̅1 because
it is the smallest unit of voltage that can be generated by the circuit. If all voltage levels become calculated for
various values of 𝑉1 as an integer coefficient of 𝑉̅1 just for positive polarity (the negative is similar) from Table
2, we would have:
𝑡ℎ𝑒𝑙𝑒𝑣𝑒𝑙𝑠𝑎𝑟𝑒
𝐼𝑓: 𝑉1 = 𝑉1 → 0, 𝑉1 , 𝑉1 , 2𝑉1 , 2𝑉1 , 2𝑉1 , 3𝑉1 , 3𝑉1 , 4𝑉1 (3)
𝑡ℎ𝑒𝑙𝑒𝑣𝑒𝑙𝑠𝑎𝑟𝑒
𝐼𝑓: 𝑉1 = 2𝑉1 → 0, 𝑉1 , 2𝑉1 , 2𝑉1 , 3𝑉1 , 4𝑉1 , 4𝑉1 , 5𝑉1 , 6𝑉1 (4)
𝑡ℎ𝑒𝑙𝑒𝑣𝑒𝑙𝑠𝑎𝑟𝑒
𝐼𝑓: 𝑉1 = 3𝑉1 → 0, 𝑉1 , 2𝑉1 , 3𝑉1 , 4𝑉1 , 5𝑉1 , 6𝑉1 , 7𝑉1 , 8𝑉1 (5)
𝑡ℎ𝑒𝑙𝑒𝑣𝑒𝑙𝑠𝑎𝑟𝑒
𝐼𝑓: 𝑉1 = 4𝑉1 → 0, 𝑉1 , 2𝑉1 , 4𝑉1 , 5𝑉1 , 6𝑉1 , 8𝑉1 , 9𝑉1 , 10𝑉1 (6)
𝑡ℎ𝑒𝑙𝑒𝑣𝑒𝑙𝑠𝑎𝑟𝑒
𝐼𝑓: 𝑉1 = 5𝑉1 → 0, 𝑉1 , 2𝑉1 , 5𝑉1 , 6𝑉1 , 7𝑉1 , 10𝑉1 , 11𝑉1 , 12𝑉1 (7)

It is clear from (5) that for 𝑉1 = 3𝑉1 , all values are unique, so all 17 voltage levels can be achieved. For
𝑉1 = 4𝑉1 and higher coefficients, some levels are lost [33].

2.3. Proposed sub-multilevel converter

To produce more voltage levels, the basic unit can be extended in a way (shown in Figure 2)
Alishah et al. [17] named it “Submultilevel”. The topology consists of several legs. Each leg has two dc sources
with the same magnitude. However, the magnitude of 𝑑𝑐 sources in each leg differ from other legs. To calculate
the value of DC sources in each leg, the author proposed a method as (8) and (9):

𝑉𝑗 = 10𝑗−1 𝑉𝑑𝑐 𝑓𝑜𝑟𝑗 = 1,2, … , 𝑛 (8)

𝑉𝑗 = 3 × 10𝑗−1 𝑉𝑑𝑐 𝑓𝑜𝑟𝑗 = 1,2, … , 𝑛 (9)

In this method, the number of voltage levels is equal to:

𝑁𝑙𝑒𝑣𝑒𝑙𝑠,𝑆 = 16 × 10𝑛−1 + 1 (10)

Where 𝑛 is half the number of legs. Again, the author has not provided any proof for the mentioned
relationships, and we will prove them. First, we have listed all possible states where at least one voltage source
and 𝑉𝑜 can be placed in a closed circuit such that no source is short circuited [34]. These modes are extracted
for the circuit shown in Figure 3. To do this, first you need to write down all the combinations that can be made
by all the voltage sources. In other words, we need to list all the combinations where 1, 2, 3,…,7 or 8 sources
can be selected from among the eight voltage sources. The total number of combinations is 255. Then, we have
to check in which cases a closed circuit is created with at least one voltage source; the total number of cases is
98. The next step is to define the sign of the sources relative to the output voltage [35], [36]. These items are
extracted and listed in Table 3. Only positive modes are listed, and negative modes are similar because if we
look at Figure 3, we can see that the circuit is divided into two halves by the dotted red line and that these two
halves are the same. If we want to create a positive voltage at the output, the sources specified in Table 3 should
be placed in a closed circuit by the 𝑆𝑦 key, and if we want to create a negative voltage, the corresponding
sources with the same values in the other half of the circuit should be placed in a closed circuit by the 𝑆𝑥 key.
To extract all possible states for creating voltage at the output, we replaced the source names with the values
shown in Figure 4.

TELKOMNIKA Telecommun Comput El Control, Vol. 22, No. 1, February 2024: 190-201
TELKOMNIKA Telecommun Comput El Control  195

Figure 3. Submillilevel topology with n=2 Figure 4. Figure 3 with new source names

Table 3. Possible combinations for creating positive 𝑉𝑂 in the circuit shown in Figure 4
State 𝑉𝑜𝑢𝑡 State 𝑉𝑜𝑢𝑡 State 𝑉𝑜𝑢𝑡
1 A1+A2 34 -A1-A2-B2+C1+C2+D2 67 -A2-B1+C2+D1+D2
2 A1+C2 35 -A1-A2+C1+C2+D1+D2 68 A2-B1-B2+C1+D1+D2
3 A1+A2+B2 36 A1-B1-B2+C2+D1+D2 69 -A2-B1-B2+C2+D1+D2
4 A1+A2+D2 37 -A1-B1+C1+C2+D1+D2 70 B1+B2
5 A1+B2+C2 38 -A1-A2-B1+C1+C2+D1+D2 71 B1+D2
6 -A1+C1+C2 39 -A1-B1-B2+C1+C2+D1+D2 72 B1+B2+C2
7 A1+C2+D2 40 -A1-A2-B1-B2+C1+C2+D1+D2 73 B1+C2+D2
8 A1+A2+B1+B2 41 A2 74 -B1+D1+D2
9 A1+A2+B1+D2 42 A2+B2 75 B1+B2+C1+C2
10 A1+A2+B2+D1 43 A2+C1 76 -B1-B2+D1+D2
11 A1+A2-B2+D2 44 -A2+C2 77 B1+C1+C2+d2
12 -A1-A2+C1+C2 45 A2+D2 78 -B1+C2+D1+D2
13 A1+A2+D1+D2 46 A+B1+B2 79 -B1-B2+C2+D1+D2
14 A1+B1+B2+C2 47 A2+B1+D2 80 -B1+C1+C2+D1+D2
15 A1+B1+C2+D2 48 A2+B2+C1 81 -B1-B2+C1+C2+D1+D2
16 -A1+B2+C1+C2 49 -A2+B2+C2 82 B2
17 A1+B2+C2+D1 50 A2+B2+D1 83 B2+C2
18 A1-B2+C2+D2 51 A2-B2+D2 84 B2+D1
19 -A1+C1+C2+D2 52 A2+C1+D2 85 -B2+D2
20 A1+C2+D1+D2 53 -A2+C2+D2 86 B2+C1+C2
21 A1+A2-B1+D1+D2 54 A2+D1+D2 87 B2+C2+D1
22 -A1-A2+B2+C1+C2 55 A2+B1+B2+C1 88 -B2+C2+D2
23 -A1-A2+C1+C2+D2 56 -A2+B1+B2+C2 89 B2+C1+C2+D1
24 -A1+B1+B2+C1+C2 57 A2+B1+C1+D2 90 -B2+C1+C2+D2
25 -A1+B1+C1+C2+D2 58 -A2+B1+C2+D2 91 C1+C2
26 A1-B1+C2+D1+D2 59 A2-B1+D1+D2 92 C1+C2+D2
27 -A1+B2+C1+C2+D1 60 A2+B2+C1+D1 93 C1+C2+D1+D2
28 -A1-B2+C1+C2+D2 61 -A2+B2+C2+D1 94 C2
29 -A1+C1+C2+D1+D2 62 -A2-B2+C2+D2 95 C2+D2
30 -A1-A2+B1+B2+C1+C2 63 A2+C1+D1+D2 96 C2+D1+D2
31 -B1-B2+A1+A2+D1+D2 64 -A2+C2+D1+D2 97 D1+D2
32 -A1-A2+B1+C1+C2+D2 65 A2-B1-B2+D1+D2 98 D2
33 -A1-A2+B2+C1+C2+D1 66 A2-B1+C1+D1+D2

2.4. Determining the values of DC sources in the sub-multilevel topology

After we have extracted all the possible states to create the voltage at the output, we should discuss
the determination of the source values. Given that:

𝑎1 = 𝑎2 = 𝑎 𝑏1 = 𝑏2 = 𝑏 𝑐1 = 𝑐2 = 𝑐 𝑑1 = 𝑑2 = 𝑑 (11)

𝑎<𝑏<𝑐<𝑑 (12)

𝑏 = 3𝑎 (13)

Proposing a new method for calculating DC sources in an extended … (Afzal Keivanlou Shahrestanaki)
196  ISSN: 1693-6930

Replacing ralations 11 in Table 3 results in Table 4. Now, it is time to sort the contents of Table 4
from large to small. The flowchart shown in Figure 4 is proposed by this paper. Based on the proposed
procedure, we are sure that the largest 𝑉𝑂 that can be produced by the circuit is 2c + 2d. The largest 𝑉𝑂 before
2𝑐 + 2𝑑 must be −𝑎 + 2𝑐 + 2𝑑 because the interval between each two consecutive levels must equal to the
amount of the smallest DC source. (i.e., 𝑎). Now, we have to check whether this voltage level −𝑎 + 2𝑐 + 2𝑑
exists in Table 4, and the answer is YES. Likewise, the largest 𝑉𝑂 before −𝑎 + 2𝑐 + 2𝑑 must be −2a + 2c + 2d,
which exists in Table 4, and the next 𝑉𝑂 must be −3𝑎 + 2𝑐 + 2𝑑, which does not exist in Table 4; however,
instead, there is −𝑏 + 2𝑐 + 2𝑑, and from (13), we have (𝑏 = 3𝑎). If we continue like this, we would have
Table 5. The next relation after −2𝑎 − 2𝑏 + 2𝑐 + 2𝑑 should be −3𝑎 − 2𝑏 + 2𝑐 + 2𝑑 or −𝑏 − 2𝑏 + 2𝑐 + 2𝑑,
and none of them exist in Table 4. We must search for the largest voltage level among the remaining 𝑉𝑂 ’s and
that’s 𝑎 + 𝑐 + 2𝑑 because assuming that relationship 12 is established (𝑐 > 𝑎), all the other voltages are smaller
than 𝑎 + 𝑐 + 2𝑑. Next, 𝑉𝑂 after −a − 2b + c + 2d should be −2𝑎 − 2𝑏 + 𝑐 + 2𝑑 or 𝑎 − 𝑏 − 2𝑏 + 𝑐 + 2𝑑,
and none of them exist in Table 4. We must search for the largest 𝑉𝑂 among the remaining 2𝑎 + 2𝑑 in Table 3
because of the following assumption:

𝑑 > 𝑎 + 2𝑐 (14)

Table 4. Table 3 values after replacing (11)

State 𝑉𝑂 State VO State 𝑉𝑂
1 2A 34 -2A-B+2c+D 67 -A-b+C+2d
2 A+c 35 -2A+2c+2D 68 A-2b+C+2d
3 2A+b 36 A-2B+c+2D 69 -A-2b+C+2d
4 2A+d 37 -A-B+2c+2D 70 2B
5 A+B+C 38 -2A-B+2c+2D 71 B+D
6 -A+2c 39 -A-2B+2c+2D 72 2B+c
7 A+C+D 40 -2A-2b+2c+2D 73 B+c+D
8 2A+2b 41 A 74 -B+2D
9 2A+B+d 42 A+B 75 2B+2c
10 2A+b+d 43 A+C 76 -2B+2D
11 2A-b+d 44 -A+C 77 B+2c+D
12 -2A+2c 45 A+d 78 -B+c+2D
13 2A+2d 46 A+2B 79 -2B+c+2d
14 A+2B+c 47 A+B+d 80 -B+2c+2d
15 A+B+C+D 48 A+B+c 81 -2B+2c+2D
16 -A+b+2C 49 -A+B+c 82 B
17 A+b+C+D 50 A+b+d 83 b+c
18 A-b+c+D 51 A-b+d 84 b+d
19 -A+2c+D 52 A+c+d 85 -b+d
20 A+c+2D 53 -A+c+d 86 b+2c
21 2A-b+2D 54 A+2d 87 b+c+d
22 -2a+b+2C 55 A+2b+C 88 -b+c+d
23 -2A+2c+D 56 -A+2b+C 89 B+2c+D
24 -A+2b+2c 57 A+b+C+D 90 -B+2c+D
25 -A+B+2c+d 58 -A+b+C+D 91 2c
26 A-B+c+2d 59 A-b+2D 92 2c+D
27 -A+B+2c+D 60 A+b+C+D 93 2c+2D
28 -A-B+2c+D 61 -A+b+C+D 94 C
29 -A+2C+2d 62 -A-b+C+D 95 c+D
30 -2A+2B+2c 63 A+C+2D 96 c+2D
31 -2B+2a+2D 64 -A+C+2D 97 2D
32 -2A+b+2c+D 65 A-2B+2D 98 D
33 -2A+b+2c+D 66 A-B+c+2D

Figure 5 shows the proposed algorithm for sorting the values of Table 4 from large to small. All the other
voltages are smaller than 2𝑎 + 2𝑑. Finally, the next voltage level after −2𝑏 + 2𝑑 should be −𝑎 − 2𝑏 + 2𝑑 or
2𝑎 − 𝑏 − 2𝑏 + 𝑐 + 2𝑑, and none of them exist in Table 4. We must search for the largest voltage among the
remaining 𝑉𝑂 s in Table 4, which is 𝑏 + 2𝑐 + 𝑑. From the 10th and 26th rows of Table 5, we have:

−9𝑎 + 2𝑐 + 2𝑑 = 𝑎 + 𝑐 + 2𝑑 → 𝑐 = 10𝑎 (15)

𝑐=10𝑎
−7𝑎 + 2𝑑 = 𝑏 + 2𝑐 + 𝑑 → 𝑑 = 30𝑎 (16)

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TELKOMNIKA Telecommun Comput El Control  197

Table 5. Values of Table 4 in order from large to small

State 𝑉𝑂 values after subtracting “𝑎” in order from largest to smallest The equivalent expression in the Table 3
1 2C+2D 2C+2D
2 -A+2c+2D -a+2c+2D
3 -2A+2c+2D -2A+2c+2D
4 -3A+2c+2D -b+2c+2D
5 -4A+2c+2D -A-b+2c+2D
6 -5A+2c+2D -2A-b+2c+2D
7 -6A+2c+2D -2b+2c+2D
8 -7A+2c+2D -A-2b+2c+2D
9 -8A+2c+2D -2A-2b+2c+2D
10 -9A+2c+2D A+c+2D
11 C+2D c+2D
12 -A+c+2D -A+c+2D
13 -2A+c+2D A-b+c+2D
14 -3A+c+2D -b+c+2D
15 -4A+c+2D -A-b+c+2D
16 -5A+c+2D A-2b+c+2D
17 -6A+c+2D -2b+c+2D
18 -7A+c+2D -A-2b+c+2D
19 -8A+c+2D 2A+2D
20 A+2D A+2D
21 2D 2D
22 -A+2D 2A-B+2D
23 -3A+2D -B+2D
24 -4A+2D -2B+2a+2D
25 -6A+2D -2B+2D
26 -7A+2D B+2c+D

Figure 5. Proposed algorithm to sort the values of Table 4 from large to small

Proposing a new method for calculating DC sources in an extended … (Afzal Keivanlou Shahrestanaki)
198  ISSN: 1693-6930

By determining the 𝑏, 𝑐, 𝑑 coefficients, the ramaining 𝑉𝑂 s can be easily sorted. Due to the repetition
of some levels, among the 98 positive voltage levels listed in Table 4, 80 levels are unique. These levels can
also be created in negative polarity. Including the zero voltage level, a total of 161 voltage levels can be created
by the circuit of Figure 3.

3. VALIDATION BY MATLAB PROGRAM

In this section, the MATLAB program is used to confirm the correctness of the obtained results. For
this purpose, we wrote a MATLAB code, the flowchart of this code is presented in Figure 6, after entering the
relations mentioned in Table 4 shows us for what values of 𝑏, 𝑐, and 𝑑 as integer coefficients of 𝑎, the numbers
obtained from them will have the same intervals and how many levels can be created. For this, we must assign
a range to 𝑏, 𝑐, and 𝑑 in the “for” loop. After running the program, the bar chart will be executed as shown in
Figure 7. The red bars indicate that corresponding A, B, C, and D cannot form numbers with equal distances.
The blue bars mean that corresponding A, B, C, and D can form numbers with equal distances, which is our
preference. Corresponding A, B, C, and D are also shown the bars. After testing different amounts for B, C,
and D by the MATLAB program, we concluded that the best amounts for 𝑏, 𝑐, and 𝑑 are 3, 10, and 30 times
a, respectively. In this case, we will have the largest number of levels (161 level for both positive (+) and
negative (-) polarity and 0 (zero) level), while the distances between the levels are the same. This is the same
result obtained from equations 15, 16, and 13.

Figure 6. Proposed algorithm for MATLAB code

TELKOMNIKA Telecommun Comput El Control, Vol. 22, No. 1, February 2024: 190-201
TELKOMNIKA Telecommun Comput El Control  199

Figure 7. MATLAB code output

4. CONCLUSION
In this paper, a method for calculating the DC source amplitude in an extended multilevel converter
structure was presented. This method consists of a basic module that can be expanded to generate additional
voltage levels. In the past research, methods were introduced to calculate the DC source amplitude, but none
of them provided a reason for presenting these methods. First, all possible states for creating voltage at the
output were extracted. Then, according to the suggested algorithm, they were sorted from large values to small
values. Finally, the amplitudes of the DC sources are calculated to generate the maximum number of equally
spaced voltage levels, resulting in a lower THD and fewer parts. After we solved the problem through
calculation and analysis, a code was written in MATLAB with the aim that this time the code will tell us for
what values of DC sources we will have the largest number of levels, and as we expected, the output of the
MATLAB code confirmed the correctness of the calculations. This MATLAB code can be used for any other
topology in such a way that first, the voltages that can be generated in the output of the circuit are extracted
parametrically and fed to the MATLAB code. This code tells us for what amounts of the amplitude of DC
sources, the maximum number of levels can be created and whether the intervals between two consecutive
levels are the same throughout the output waveform. In this study, we used iteration-based methods to find
suitable values for DC sources. We did not obtain results from other methods except the iteration-based
method; for example, using graph theory for circuit analysis did not give results. Therefore, in future studies,
analytical methods can be used to find the best amounts for DC voltage sources. Additionally, presenting an
application with the aim of finding the best amounts for DC sources after feeding a proposed topology to it
would be an attractive topic.

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BIOGRAPHIES OF AUTHORS

Afzal Keivanlou Shahrestanaki was born in Sabzevar, Iran in May 1990. In

2013 he received his B.S. in Electrical Engineering from Birjand University. He is currently
studying for a master’s degree in Power Electronic and Electrical Machines at Hakim
Sabzevari University. His current research interests include multilevel inverters, electric
motor drives and solar inverter, maximum power point tracker, and battery chargers. He can
be contacted at email: [email protected].

Rahim Ildarabadi was born in Sabzevar, Iran in 1975. He received the Ph.D.
degree from Ferdowsi University of Mashhad in 2010. He is a full-time faculty member at
Sabzevar, Hakim Sabzevari University. His main area of interests is automation system,
electrical machine drive, renewable energy, instruments, and measurement. He is currently
an assistant professor of Electrical Engineering at Hakim Sabzevari University. He can be
contacted at email: [email protected].

Mahmoud Zadehbagheri was born in Yasouj, Iran, in October 1979. He

received a B.S. degree in Electrical Engineering from Kashan University, in 2003, an M.S.
degree in Electrical Engineering from Islamic Azad University, Najafabad Branch, in 2008,
and the joint Ph.D. degree in Electrical Engineering from Universiti Teknologi Malaysia
(UTM), Johor, Skudai, Malaysia, and Hakim Sabzvari University, Khorasan, Iran, in 2017.
He is with the Department of the Electrical Engineering, Islamic Azad University, Yasouj
Branch. He is currently collaborating as a reviewer and editorial board with the journals
applied energy, hydrogen energy, IJRER, micro machines, sensors, energies, EPCS, IJPEDS.
His research interests include the fields of power electronics, FACTS devices, optimization
methods, renewable energy, energy hub, and power quality. He can be contacted at email:
[email protected].

Tole Sutikno is a lecturer in Department of Electrical Engineering at the Ahmad

Dahlan (UAD) University, Yogyakarta, Indonesia. He received his B.Eng., M.Eng. and Ph.D.
degrees in Electrical Engineering from Diponegoro University, Universitas Gadjah Mada and
Universiti Teknologi Malaysia, in 1999, 2004, and 2016, respectively. Since July 2023, he has
been a full professor at Universitas Ahmad Dahlan in Yogyakarta, Indonesia, after previously
serving as an associate professor since June 2008. He is currently an editor-in-chief of the
TELKOMNIKA since 2005, and the head of the Embedded Systems and Power Electronics
Research Group since 2016. His research interests include the field of digital design, industrial
applications, industrial electronics, industrial informatics, power electronics, motor drives,
renewable energy, FPGA applications, embedded system, artificial intelligence, intelligent
control, and digital library. He can be contacted at email: [email protected].

Proposing a new method for calculating DC sources in an extended … (Afzal Keivanlou Shahrestanaki)