Lecture5 Arithmetic
Lecture5 Arithmetic
Lecture 5:
Arithmetic for Computers
169
Outline
Introduction
Multiplication
Division
Floating point
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Introduction
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Outline
Introductions
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Integer Addition
Example: 7 + 6
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Examples with overflow (I)
Example: (7)10 + (4)10 = ? using 5-bit representation
system.
(7)10 = (00111)2
(4)10 = (00100)2
00111 + 00100 = 01011 no overflow
Example: (9)10 + (7)10 = ? Using 5-bit representation
system
(9)10 = (01001)2
(7)10 = (00111)2
01001 + 00111 = 10000 overflow because the MSB bit = 1
Example: (14)10 - (9)10 = ? In 5-bit representation system
(14)10 = (01110)2
(9)10 = (01001)2
01110 – 01001 = 01110 + 10111 = 00101 (carry = 1) | carry is
discarded
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Examples with overflow (II)
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Dealing with Overflow
Exception:
Also called interrupt.
An unscheduled event that disrupts program
execution;
used to detect overflow.
interrupt
An exception that comes from outside of the
processor.
Some architectures use the term interrupt for
all exceptions.
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Outline
Introductions
Multiplication
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Binary multiplier
Usually there are more bits in the partial products and it
is necessary to use full adders to produce the sum of the
partial products.
And
13
4-bit by 3-bit binary
multiplier
Multiplicand B3B2B1B0
×
Multiplier A2A1A0
----------------------
Product C6C5C4C3C2C1C0
Length of product is
the sum of operand
lengths
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Multiplication Hardware
Initially 0
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An example
0101 × 0110
Iteration step Multiplier Multiplicand Product
0 Initialize values 0110 0000 0101 0000 0000
Multiplier0 = 0, so
1 (1) Multiplicand<<1 0011 0000 1010 0000 0000
(2) Multiplier >>1
Multiplier0 = 1, so
(1) Add mcand to
product
2 (2) Multiplicand<<1 0001 0001 0100 0000 1010
(3) Multiplier >>1
Multiplier0 = 1, so
(1) Add mcand to
3 product
(2) Multiplicand<<1
0000 0010 1000 0001 1110
(3) Multiplier >>1
Multiplier0 = 0, so
4 (1) Multiplicand<<1
0000 0101 0000 0001 1110
(2) Multiplier >>1
Multiplier0 = 0, so
5 (1) Multiplicand<<1 0000 1010 0000 0001 1110
(2) Multiplier >>1
Multiplier0 = 0, so
6 (1) Multiplicand<<1
(2) Multiplier >>1
0000 0100 0000 0001 1110
Multiplier0 = 0, so
7 (1) Multiplicand<<1 0000 1000 0000 0001 1110
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Multiplier0 = 0, so © by Hakem Beitollahi
8 (1) Multiplicand<<1 0000 0000 0000 0001 1110
(2) Multiplier >>1
Role of compilers
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Optimized Multiplier
Perform steps in parallel: add/shift
/multiplier
0010 × 0011
1
Multiplier0 = 1 (1) Prod=Prod + Mcand
0010 0010 0011
(2) Prod/Multiplier >>1
0001 0001
Multiplier0 = 1 (1) Prod=Prod + Mcand 0010 0011 0001
2 (2) Prod/Multiplier >>1
0001 1000
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Signed Multiplication
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Outline
Introductions
Multiplication
Division
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§3.4 Division
Division
Check for 0 divisor
Long division approach
quotient If divisor ≤ dividend bits
dividend • 1 bit in quotient, subtract
1001 Otherwise
1000 1001010 • 0 bit in quotient, bring down next
-1000 dividend bit
divisor
10 Restoring division
101 Do the subtract, and if remainder
1010 goes < 0, add divisor back
-1000 Signed division
10
remainder Divide using absolute values
Adjust sign of quotient and remainder
n-bit operands yield n-bit as required
quotient and remainder
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Division Hardware
Initially divisor
in left half
Initially dividend
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Divide example
Divide 7ten (0000 0111two) by 2ten (0010two)
Iteration step Quotient Divisor Reminder
0 Initialize values 0000 0010 0000 0000 0111
(1) Rem = Rem – div 0000 0010 0000 1110 0111
1 (2) Rem<0 +div, 1<<Q, Q0 = 0
(3) Diiv>>1 0000 0001 0000 0000 0111
(1) Rem = Rem – div 0000 0001 0000 1111 0111
2 (2) Rem<0 +div, 1<<Q, Q0 = 0
(3) Diiv>>1 0000 0000 1000 0000 0111
(1) Rem = Rem – div 0000 0000 1000 1111 1111
3 (2) Rem<0 +div, 1<<Q, Q0 = 0
0000
(3) Diiv>>1 0000 0100 0000 0111
(1) Rem = Rem – div 0000 0000 0011
(2) Rem>0 1<<Q, Q0 = 1 0000 0100
4 0001
(3) Diiv>>1 0000 0010 0000 0011
(1) Rem = Rem – div 0001 0000 0010 0000 0001
5 (2) Rem>0 1<<Q, Q0 = 1
(3) Diiv>>1 0011 0000 0001 0000 0001
Final 0011 0000 0001 0000 0001
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Optimized Divider
/Quotient
29
Divisions involving Negatives
30
MIPS Division
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Outline
Introductions
Multiplication
Division
Floating point
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Floating Point (I)
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Floating Point (II)
+987.02 × 109
In binary
±1.xxxxxxx2 × 2yyyy
Types float and double in C
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Floating Point Standard
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IEEE Floating-Point Format
single: 8 bits single: 23 bits
double: 11 bits double: 52 bits
S Exponent Fraction
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IEEE Floating-Point Format
(-1)1 × (1 + 0.1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000) × 2(1022-1023)
Fraction = 0.1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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Floating-Point
Example
Represent –0.75
–0.75 = (–1)1 × 1.12 × 2–1
S=1
Fraction = 1000…002
Exponent = –1 + Bias
• Single: –1 + 127 = 126 = 011111102
• Double: –1 + 1023 = 1022 = 011111111102
Single: 1011111101000…00
Double: 1011111111101000…00
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IEEE Floating-Point Format
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Single-Precision
Range
Exponents 00000000 and 11111111 reserved
Smallest value
Exponent: 00000001
actual exponent = 1 – 127 = –126
Fraction: 000…00 significand = 1.0
±1.0 × 2–126 ≈ ±1.2 × 10–38
Largest value
exponent: 11111110
actual exponent = 254 – 127 = +127
Fraction: 111…11 significand ≈ 2.0
±2.0 × 2+127 ≈ ±3.4 × 10+38
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Double-Precision
Range
Exponents 0000…00 and 1111…11 reserved
Smallest value
Exponent: 00000000001
actual exponent = 1 – 1023 = –1022
Fraction: 000…00 significand = 1.0
±1.0 × 2–1022 ≈ ±2.2 × 10–308
Largest value
Exponent: 11111111110
actual exponent = 2046 – 1023 = +1023
Fraction: 111…11 significand ≈ 2.0
±2.0 × 2+1023 ≈ ±1.8 × 10+308
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Floating Point
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Check Yourself
The revised IEEE 754-2008 standard added a 16-bit floating-
point format with five exponent bits. What do you think is the
likely range of numbers it could represent?
A) 1.000000 × 20 to 1.1111111111 × 231, 0
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Floating-Point Addition
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Floating-Point Addition
Consider a 4-digit decimal example
9.999 × 101 + 1.610 × 10–1
2. Add significands
1.0002 × 2–1 + –0.1112 × 2–1 = 0.0012 × 2–1
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FP Adder Hardware
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FP Adder Hardware
Step 1
Step 2
Step 3
Step 4
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Floating-Point Multiplication
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Floating-Point Multiplication
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FP Arithmetic
Hardware
FP multiplier is of similar complexity to FP
adder
But uses a multiplier for significands instead
of an adder
FP arithmetic hardware usually does
Addition, subtraction, multiplication, division,
square-root
FP integer conversion
Operations usually takes several cycles
Can be pipelined
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FP Multiply Flowchart
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FP Instructions in MIPS
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FP Instructions in
MIPS
FP hardware is coprocessor 1
Adjunct processor that extends the ISA
Separate FP registers
32 single-precision: $f0, $f1, … $f31
Paired for double-precision: $f0/$f1, $f2/$f3, …
• Release 2 of MIPs ISA supports 32 × 64-bit FP reg’s
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FP machine codes
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The history of coprocessor
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FP Example: °F to °C
C code:
float f2c (float fahr) {
return ((5.0/9.0)*(fahr - 32.0));
}
fahr in $f12, result in $f0, literals in global memory
space
Compiled MIPS code:
f2c: lwc1 $f16, const5($gp) #$f16=5.0
lwc2 $f18, const9($gp) #$f18=9.0
div.s $f16, $f16, $f18 #$f16=5.0/9.0
lwc1 $f18, const32($gp) #$f18=32.0
sub.s $f18, $f12, $f18 #$f18=fahr-32.0
mul.s $f0, $f16, $f18 #$f0=(5.0/9.0)*(fahr-32.0)
jr $ra #return
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Check yourself as an exam question
X = X + Y × Z
All 32 × 32 matrices, 64-bit double-precision elements
C code:
void mm (double x[][],
double y[][], double z[][]) {
int i, j, k;
for (i = 0; i! = 32; i = i + 1)
for (j = 0; j! = 32; j = j + 1)
for (k = 0; k! = 32; k = k + 1)
x[i][j] = x[i][j]
+ y[i][k] * z[k][j];
}
Addresses of x, y, z in $a0, $a1, $a2, and
i, j, k in $s0, $s1, $s2
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Fallacies (I)
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Fallacies (II)
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Pitfall
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