LOGO

Lecture 5:
Arithmetic for Computers

Dr. Hakem Beitollahi

Department of computer Engineering, Iran University of Science and

Technology

169
 Outline
Introduction

Addition and subtraction

Multiplication

Division

Floating point
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 Introduction

You already learned how to show

integer numbers.
What about fractions and other real
numbers?
What happens if an operation creates
a number bigger than can be
represented?
How does hardware really support
multiply and divide numbers?

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 Outline
Introductions

Addition and subtraction

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 Integer Addition
Example: 7 + 6

 Overflow if result out of range

 Adding +ve and –ve operands, no overflow
 Adding two +ve operands
 Overflow if result sign is 1
 Adding two –ve operands
 Overflow if result sign is 0
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 Integer Subtraction

Add negation (2’s complement) of second

operand
Example: 7 – 6 = 7 + (–6)
+7: 0000 0000 … 0000 0111
–6: 1111 1111 … 1111 1010
+1: 0000 0000 … 0000 0001
Overflow if result out of range
 Subtracting two +ve or two –ve operands, no overflow
 Subtracting +ve from –ve operand
• Overflow if result sign is 0
 Subtracting –ve from +ve operand
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• Overflow if result sign is 1 © by Hakem Beitollahi
 Overflow summary

Operation Operand A Operand B Result indicating

overflow
A+B ≥0 ≥0 <0
A+B <0 <0 ≥0
A-B ≥ <0 <0
A-B <0 ≥0 ≥0

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 Examples with overflow (I)
 Example: (7)10 + (4)10 = ? using 5-bit representation
system.
 (7)10 = (00111)2
 (4)10 = (00100)2
 00111 + 00100 = 01011  no overflow
 Example: (9)10 + (7)10 = ? Using 5-bit representation
system
 (9)10 = (01001)2
 (7)10 = (00111)2
 01001 + 00111 = 10000  overflow because the MSB bit = 1
 Example: (14)10 - (9)10 = ? In 5-bit representation system
 (14)10 = (01110)2
 (9)10 = (01001)2
 01110 – 01001 = 01110 + 10111 = 00101 (carry = 1) | carry is
discarded
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 Examples with overflow (II)

 Example: (9)10 - (14)10 = ? In 5-bit representation system

 01001 – 01110 = 01001 + 10010 = 11011 = (-5)
 Example: -(7)10 - (8)10 = ? In 5-bit representation system
 (7)10 = (00111)2
 (8)10 = (01000)2
 -(00111) – (01000) = 11001 + 11000 = 10001 (carry = 1) | carry
is discarded
 Example: -(12)10 - (5)10 = ? In 5-bit representation system
 (12)10 = (01100)2
 (5)10 = (00101)2
 -(01100)-(00101) = 10100 + 11011 = 01111 (carry = 1)
 Overflow is detected because the sign bit is 0

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 Dealing with Overflow

Some languages (e.g., C) ignore overflow

 Use MIPS addu, addui, subu instructions
Other languages (e.g., Ada, Fortran)
require raising an exception
 Use MIPS add, addi, sub instructions
 On overflow, invoke exception handler
• Save PC in exception program counter (EPC)
register
• Jump to predefined handler address
• mfc0 (move from coprocessor reg) instruction can
retrieve EPC value, to return after corrective action
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 Exception and Interrupt

Exception:
 Also called interrupt.
 An unscheduled event that disrupts program
execution;
 used to detect overflow.
interrupt
 An exception that comes from outside of the
processor.
 Some architectures use the term interrupt for
all exceptions.
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 Outline
Introductions

Addition and subtraction

Multiplication

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 Binary multiplier
 Usually there are more bits in the partial products and it
is necessary to use full adders to produce the sum of the
partial products.

And

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 4-bit by 3-bit binary
multiplier

Multiplicand B3B2B1B0
×
Multiplier A2A1A0
----------------------
Product C6C5C4C3C2C1C0

 For J multiplier bits and K

multiplicand bits we need
(J X K) AND gates and (J −
1) K-bit adders to produce
a product of J+K bits.

 K=4 and J=3, we need 12

AND gates and two 4-bit
adders. 14
 Multiplication
Start with long-multiplication
approach
multiplicand
1000
multiplier
× 1001
1000
0000
0000
1000
product 01001000

Length of product is
the sum of operand
lengths

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 Multiplication Hardware

Initially 0

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 An example
0101 × 0110
Iteration step Multiplier Multiplicand Product
0 Initialize values 0110 0000 0101 0000 0000
Multiplier0 = 0, so
1 (1) Multiplicand<<1 0011 0000 1010 0000 0000
(2) Multiplier >>1
Multiplier0 = 1, so
(1) Add mcand to
product
2 (2) Multiplicand<<1 0001 0001 0100 0000 1010
(3) Multiplier >>1

Multiplier0 = 1, so
(1) Add mcand to
3 product
(2) Multiplicand<<1
0000 0010 1000 0001 1110
(3) Multiplier >>1

Multiplier0 = 0, so
4 (1) Multiplicand<<1
0000 0101 0000 0001 1110
(2) Multiplier >>1

Multiplier0 = 0, so
5 (1) Multiplicand<<1 0000 1010 0000 0001 1110
(2) Multiplier >>1
Multiplier0 = 0, so
6 (1) Multiplicand<<1
(2) Multiplier >>1
0000 0100 0000 0001 1110
Multiplier0 = 0, so
7 (1) Multiplicand<<1 0000 1000 0000 0001 1110
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Multiplier0 = 0, so © by Hakem Beitollahi
8 (1) Multiplicand<<1 0000 0000 0000 0001 1110
(2) Multiplier >>1
 Role of compilers

 Replacing arithmetic by shifts can also occur

when multiplying by constants.
 Some compilers replace multiplies by short
constants with a series of shifts and adds.
 Because one bit to the left represents the same
effect as multiplying by a power of 2.
 Almost every compiler will perform the strength
reduction optimization of substituting a left shift
for a multiply by a power of 2
 E.g., x*7 = (4*x + 2*x + x)

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 Optimized Multiplier
Perform steps in parallel: add/shift

/multiplier

•32-bit ALU and multiplicand is untouched

• the sum keeps shifting right
• At every step, number of bits in product + multiplier
= 64, hence, they share a single 64-bit register
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 Example

0010 × 0011

Iteration step Multiplicand Product/Multiplier

0 Initialize values 0010 0000 0011

1
Multiplier0 = 1  (1) Prod=Prod + Mcand
0010 0010 0011
(2) Prod/Multiplier >>1
0001 0001
Multiplier0 = 1  (1) Prod=Prod + Mcand 0010 0011 0001
2 (2) Prod/Multiplier >>1
0001 1000

3 Multiplier0 = 0 (2) Prod/Multiplier >>1 0010 0000 1100

4 Multiplier0 = 0 (2) Prod/Multiplier >>1 0010 0000 0110

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 Signed Multiplication

How to multiply negative numbers?

 First convert the multiplier and multiplicand to
positive numbers
 Second, do multiplication using mentioned
algorithms
 Third, remember the origin signs.
 The algorithm should be run 31 iterations,
leaving the sign out of calculation.
 Remember: we need negate the product only
if the original signs disagree
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 MIPS Multiplication

Two 32-bit registers for product

 HI: most-significant 32 bits
 LO: least-significant 32-bits
Instructions
 mult rs, rt / multu rs, rt
• 64-bit product in HI/LO
 mfhi rd / mflo rd
• Move from HI/LO to rd
• Can test HI value to see if product overflows 32 bits
 mul rd, rs, rt
• Least-significant 32 bits of product –> rd
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 Fast Multiplier

Each adder produces a 32-bit sum and a

carry out

The least significant bit is a bit of the

product

The carry out and the upper 31 bits of the

sum are passed along to the next adder.

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 Outline
Introductions

Addition and subtraction

Multiplication

Division

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 §3.4 Division
Division
 Check for 0 divisor
 Long division approach
quotient  If divisor ≤ dividend bits
dividend • 1 bit in quotient, subtract
1001  Otherwise
1000 1001010 • 0 bit in quotient, bring down next
-1000 dividend bit
divisor
10  Restoring division
101  Do the subtract, and if remainder
1010 goes < 0, add divisor back
-1000  Signed division
10
remainder  Divide using absolute values
 Adjust sign of quotient and remainder
n-bit operands yield n-bit as required
quotient and remainder

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 Division Hardware

Initially divisor
in left half

Initially dividend

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 Divide example
Divide 7ten (0000 0111two) by 2ten (0010two)
Iteration step Quotient Divisor Reminder
0 Initialize values 0000 0010 0000 0000 0111
(1) Rem = Rem – div 0000 0010 0000 1110 0111
1 (2) Rem<0  +div, 1<<Q, Q0 = 0
(3) Diiv>>1 0000 0001 0000 0000 0111
(1) Rem = Rem – div 0000 0001 0000 1111 0111
2 (2) Rem<0  +div, 1<<Q, Q0 = 0
(3) Diiv>>1 0000 0000 1000 0000 0111
(1) Rem = Rem – div 0000 0000 1000 1111 1111
3 (2) Rem<0  +div, 1<<Q, Q0 = 0
0000
(3) Diiv>>1 0000 0100 0000 0111
(1) Rem = Rem – div 0000 0000 0011
(2) Rem>0  1<<Q, Q0 = 1 0000 0100
4 0001
(3) Diiv>>1 0000 0010 0000 0011
(1) Rem = Rem – div 0001 0000 0010 0000 0001
5 (2) Rem>0  1<<Q, Q0 = 1
(3) Diiv>>1 0011 0000 0001 0000 0001
Final 0011 0000 0001 0000 0001

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 Optimized Divider

/Quotient

 Multiplier circuit optimizations also work for

divider
 Shift Remainder left and do 32-bit subtractions
 Combine Quotient with right (unused) half of
Remainder Looks a lot like a multiplier!
28/69  Same hardware can be used for both
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Divisions involving Negatives

Simplest solution: convert to positive and adjust sign later

Note that multiple solutions exist for the equation:

Dividend = Quotient x Divisor + Remainder

+7 div +2 Quo = Rem =

-7 div +2 Quo = Rem =
+7 div -2 Quo = Rem =
-7 div -2 Quo = Rem =

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Divisions involving Negatives

Simplest solution: convert to positive and adjust sign later

Note that multiple solutions exist for the equation:

Dividend = Quotient x Divisor + Remainder

+7 div +2 Quo = +3 Rem = +1

-7 div +2 Quo = -3 Rem = -1
+7 div -2 Quo = -3 Rem = +1
-7 div -2 Quo = +3 Rem = -1

Convention: Dividend and remainder have the same sign

Quotient is negative if signs disagree
These rules fulfil the equation above

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 MIPS Division

Use HI/LO registers for result

 HI: 32-bit remainder
 LO: 32-bit quotient
Instructions
 div rs, rt / divu rs, rt
 No overflow or divide-by-0 checking
• Software must perform checks if required
 Use mfhi, mflo to access result

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 Outline
Introductions

Addition and subtraction

Multiplication

Division

Floating point
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 Floating Point (I)

 Going beyond signed and unsigned integers, programming

languages support numbers with fractions, which are called
reals in mathematics
 Some examples of reals:
 3.14159265… ten (pi)
 2.71828… ten (e)
 0.000000001ten or 1.0ten × 10−9 (seconds in a nanosecond)
 3,155,760,000ten or 3.15576ten × 109 (seconds in a typical century)
 Some numbers are bigger than we could represent with a
32-bit signed integer.
 The alternative notation for the last two numbers is called
scientific notation:
 A single digit to the left of the decimal point.

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 Floating Point (II)

Representation for non-integral

numbers
 Including very small and very large numbers
Like scientific notation
 –2.34 × 1056 normalized

 +0.002 × 10–4 not normalized

 +987.02 × 109
In binary
 ±1.xxxxxxx2 × 2yyyy
Types float and double in C
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 Floating Point Standard

 Defined by IEEE Std 754-1985

 Developed in response to divergence of
representations
 Portability issues for scientific code
 Now almost universally adopted
 Two representations
 Single precision (32-bit) # in programming it is called float
 Double precision (64-bit) # in programming it is called double

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 IEEE Floating-Point Format
single: 8 bits single: 23 bits
double: 11 bits double: 52 bits
S Exponent Fraction

x  ( 1)S  (1 Fraction)  2(Exponent Bias)

 S: sign bit (0  non-negative, 1  negative)
 Normalize significand: 1.0 ≤ |significand| < 2.0
 Always has a leading pre-binary-point 1 bit, so no need to
represent it explicitly (hidden bit)
 Significand is Fraction with the “1.” restored
 The fraction is also called the mantissa.
 Exponent: excess representation: actual
exponent + Bias
 Ensures exponent is unsigned
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 x  ( 1)S  (1 Fraction)  2(Exponent Bias)

where the bits of the fraction represent a

number between 0 and 1
If we number the bits of the fraction from
left to right s1, s2, s3, …, then the value is
Value = ( -1)S×(1 +(s1 ×2-1)+(s2 ×2-2)+(s3
×2-3)+(s4 ×2-4 )+ …) ×2(Exponent-Bias)

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 IEEE Floating-Point Format

 Example: show the IEEE-754 binary representation of the

number -0.75ten in single and double precision.
Solution:
-0.75ten = -0.11two
In the scientific notation, the value is:
-0.11 × 20
And in the normilized scientific notation, it is:
-1.1 × 2-1
The general representation for a single precision is
(-1)s × (1 + Fraction) × 2(Exponent – 127)
Fraction = 0.1000 0000 0000 0000 0000 000
Exponent = 126 because -1 = 126-127
So,
(-1) × (1.10000000000000000000000)×2(126-127)
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 IEEE Floating-Point Format

 Continue the example:

The double precision is (bias = 1023)

(-1)1 × (1 + 0.1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000) × 2(1022-1023)

Fraction = 0.1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

Exponent = 1022 because -1 = 1022 – 1023

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 Floating-Point
Example

Represent –0.75
 –0.75 = (–1)1 × 1.12 × 2–1
S=1
 Fraction = 1000…002
 Exponent = –1 + Bias
• Single: –1 + 127 = 126 = 011111102
• Double: –1 + 1023 = 1022 = 011111111102
Single: 1011111101000…00
Double: 1011111111101000…00
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 IEEE Floating-Point Format

Another example: What decimal number is

represented by this word?
11000000101000000000000000000000
Solution:
S= 1
Fraction: 0.01000000000000000000000
Exponent: 10000001
(-1)s × (1 + Fraction) × 2(exponent – bias)
(-1)1 × (1 + 0.25) × 2 (129-127)
-1× 1.25 × 22 = -1.25 × 4 = -5.0

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 Single-Precision
Range
 Exponents 00000000 and 11111111 reserved
 Smallest value
 Exponent: 00000001
 actual exponent = 1 – 127 = –126
 Fraction: 000…00  significand = 1.0
 ±1.0 × 2–126 ≈ ±1.2 × 10–38
 Largest value
 exponent: 11111110
 actual exponent = 254 – 127 = +127
 Fraction: 111…11  significand ≈ 2.0
 ±2.0 × 2+127 ≈ ±3.4 × 10+38
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 Double-Precision
Range
 Exponents 0000…00 and 1111…11 reserved
 Smallest value
 Exponent: 00000000001
 actual exponent = 1 – 1023 = –1022
 Fraction: 000…00  significand = 1.0
 ±1.0 × 2–1022 ≈ ±2.2 × 10–308
Largest value
 Exponent: 11111111110
 actual exponent = 2046 – 1023 = +1023
 Fraction: 111…11  significand ≈ 2.0
 ±2.0 × 2+1023 ≈ ±1.8 × 10+308
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 Floating Point

IEEE 754 encoding of floating-point numbers

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 Check Yourself
 The revised IEEE 754-2008 standard added a 16-bit floating-
point format with five exponent bits. What do you think is the
likely range of numbers it could represent?
 A) 1.000000 × 20 to 1.1111111111 × 231, 0

 B) ±1.000000000 × 2−14 to ± 1.111111111 × 215, ± 0, ± ∞, NaN

 C) ±1.0000000000 × 2−14 to ± 1.1111111111 × 215, ± 0, ± ∞, NaN

 D) ±1.0000000000 × 2−15 to ± 1.1111111111 × 214, ± 0, ± ∞, NaN

© by Hakem Beitollahi
 Floating-Point Addition

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 Floating-Point Addition
 Consider a 4-digit decimal example
 9.999 × 101 + 1.610 × 10–1

 1. Align decimal points

 Shift number with smaller exponent
 9.999 × 101 + 0.016 × 101

 2. Add significant parts

 9.999 × 101 + 0.016 × 101 = 10.015 × 101

 3. Normalize result & check for over/underflow

 1.0015 × 102

 4. Round and renormalize if necessary

 1.002 × 102
 Since we assumed that the significant could be only three digits long, we must round
the number
 Truncate the number, if the digit to the right of the desired point is between 0 and 4
and add 1 to the digit if the number to the right is between 5 and 9.
© by Hakem Beitollahi
 Floating-Point
Addition
 Now consider a 4-digit binary example
 1.0002 × 2–1 + –1.1102 × 2–2 (0.5 + –0.4375)

 1. Align binary points

 Shift number with smaller exponent
 1.0002 × 2–1 + –0.1112 × 2–1

 2. Add significands
 1.0002 × 2–1 + –0.1112 × 2–1 = 0.0012 × 2–1

 3. Normalize result & check for over/underflow

 1.0002 × 2–4, with no over/underflow

 4. Round and renormalize if necessary

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 1.0002 × 2–4 (no change) = 0.0625 © by Hakem Beitollahi
 Overflow vs. underflow

Overflow (floating-point): A situation in

which a positive exponent becomes too
large to fit in the exponent field.

underflow (floating-point): A situation

in which a negative exponent becomes too
large to fit in the exponent field.

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 FP Adder Hardware

Much more complex than integer

adder

Doing it in one clock cycle would take

too long
 Much longer than integer operations
 Slower clock would penalize all instructions

FP adder usually takes several cycles

 Can be pipelined
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 FP Addition Flowchart

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 FP Adder Hardware

Step 1

Step 2

Step 3

Step 4

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 Floating-Point Multiplication

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 Floating-Point Multiplication

 Consider a 4-digit decimal example

 1.110 × 1010 × 9.200 × 10–5
 1. Add exponents
 For biased exponents, subtract bias from sum
 New exponent = 10 + –5 = 5
 2. Multiply significands
 1.110 × 9.200 = 10.212  10.212 × 105
 3. Normalize result & check for over/underflow
 1.0212 × 106
 4. Round and renormalize if necessary
 1.021 × 106
 5. Determine sign of result from signs of
operands
 +1.021 × 106
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 Floating-Point Multiplication

 Now consider a 4-digit binary example

 1.0002 × 2–1 × –1.1102 × 2–2 (0.5 × –0.4375)
 1. Add exponents
 New exponent: –1 + –2 = –3
 2. Multiply significands
 1.0002 × 1.1102 = 1.1102  1.1102 × 2–3
 3. Normalize result & check for over/underflow
 1.1102 × 2–3 (no change) with no over/underflow
 4. Round and renormalize if necessary
 1.1102 × 2–3 (no change)
 5. Determine sign: +ve × –ve  –ve
 –1.1102 × 2–3 = –0.21875

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 FP Arithmetic
Hardware
FP multiplier is of similar complexity to FP
adder
 But uses a multiplier for significands instead
of an adder
FP arithmetic hardware usually does
 Addition, subtraction, multiplication, division,
square-root
 FP  integer conversion
Operations usually takes several cycles
 Can be pipelined
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 FP Multiply Flowchart

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 FP Instructions in MIPS

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 FP Instructions in
MIPS
 FP hardware is coprocessor 1
 Adjunct processor that extends the ISA

 Separate FP registers
 32 single-precision: $f0, $f1, … $f31
 Paired for double-precision: $f0/$f1, $f2/$f3, …
• Release 2 of MIPs ISA supports 32 × 64-bit FP reg’s

 FP instructions operate only on FP registers

 Programs generally don’t do integer ops on FP data, or vice
versa

 FP load and store instructions

 lwc1, swc1
• e.g., lwc1 $f8, 32($sp)
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 FP Instructions in MIPS
Single-precision arithmetic
 add.s, sub.s, mul.s, div.s
• e.g., add.s $f0, $f1, $f6
Double-precision arithmetic
 add.d, sub.d, mul.d, div.d
• e.g., mul.d $f4, $f4, $f6
Single- and double-precision comparison
 c.xx.s, c.xx.d (xx is eq, neq, lt, le, gt, ge)
 Sets or clears FP condition-code bit
• e.g. c.lt.s $f3, $f4
 Eq: equal, neq: not equal, lt: less than, le:
less than or equal, gt: greater than, ge:
greater of equal
Branch on FP condition code true or false
 bc1t, bc1f
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 FP instructions

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 FP machine codes

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 The history of coprocessor

 Microprocessors in the 1980s didn’t have enough

transistors to put the floating-point unit on the same
chip.
 The floating-point unit were available as a second
chip.
 Such optional accelerator chips are called
coprocessors,
 lwc1 means load word to coprocessor 1, the floating-
point unit
 Coprocessor 0 deals with virtual memory,
 Since the early 1990s, microprocessors have
integrated floating point on chip

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 FP Example: °F to °C
C code:
float f2c (float fahr) {
return ((5.0/9.0)*(fahr - 32.0));
}
 fahr in $f12, result in $f0, literals in global memory
space
Compiled MIPS code:
f2c: lwc1 $f16, const5($gp) #$f16=5.0
lwc2 $f18, const9($gp) #$f18=9.0
div.s $f16, $f16, $f18 #$f16=5.0/9.0
lwc1 $f18, const32($gp) #$f18=32.0
sub.s $f18, $f12, $f18 #$f18=fahr-32.0
mul.s $f0, $f16, $f18 #$f0=(5.0/9.0)*(fahr-32.0)
jr $ra #return
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 Check yourself as an exam question

X = X + Y × Z
 All 32 × 32 matrices, 64-bit double-precision elements
 C code:
void mm (double x[][],
double y[][], double z[][]) {
int i, j, k;
for (i = 0; i! = 32; i = i + 1)
for (j = 0; j! = 32; j = j + 1)
for (k = 0; k! = 32; k = k + 1)
x[i][j] = x[i][j]
+ y[i][k] * z[k][j];
}
 Addresses of x, y, z in $a0, $a1, $a2, and
i, j, k in $s0, $s1, $s2

See solution in your book

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 Fallacies and Pitfalls

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 Fallacies (I)

 Remember: Just as a left shift instruction can replace an integer

multiply by a power of 2, a right shift is the same as an integer
division by a power of 2.
 Note: This is true for unsigned integers
 The problem is with signed integers.
 For example, suppose we want to divide −5 by 4; the quotient
should be -1
 The two’s complement representation of −5 is
 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111011
 According to this fallacy, shifting right by two should divide by
4ten (22):
 00111111 11111111 11111111 11111111 11111111 11111111 11111111 11111110
 With a 0 in the sign bit, this result is clearly wrong
 The value created by the shift right is actually 1073741822
instead of −1

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 Fallacies (II)

A solution: Extend the sign bit instead of

shifting in 0s. A 2-bit arithmetic shift right
of −5 produces
 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111110

 The result is −2ten instead of −1ten; close, but no cigar.

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 Pitfall

 Pitfall: Floating-point addition is not associative.

 let’s see if c + (a + b) = (c + a) + b.
 Assume c = −1.5ten × 1038, a = 1.5ten × 1038,
and b = 1.0,
 C + (a+b) = −1.5ten × 1038 + (1.5ten × 1038+1.0)
= −1.5ten × 1038+ 1.5ten × 1038 = 0.0
 (c+a) + b =(−1.5ten × 1038+1.5ten × 1038) + 1.0
= 0.0 + 1.0 = 1.0
 Therefore, floating-point addition is not
associative.

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