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hpc part b

HIGH PERFORMANCE COMPUTING

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3 views5 pages

hpc part b

HIGH PERFORMANCE COMPUTING

Uploaded by

B.REENA HICET STAFF CSE
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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11.

Explain in detail the evolution of super-computing from vector processors


to modern scale computing. Discuss key milestones and their impact on
computational power.

1. Vector Processing Era (1970s–1980s)

The inception of supercomputing is closely tied to vector processing. The CDC 6600,
designed by Seymour Cray in 1964, is often considered the first supercomputer, introducing
the concept of parallel functional units and achieving performance of up to 3 megaFLOPS.
Wikipedia+1National Academies Press+1

The Cray-1, introduced in 1976, was a landmark in supercomputing. It utilized vector


registers to perform operations on entire arrays of data, significantly boosting performance
for scientific computations. The Cray-1's innovative architecture allowed it to achieve speeds
of 80 megaFLOPS. National Academies Press+1Wikipedia+1

Diagram: Vector Processor Architecture

2. Transition to Massively Parallel Processing (1990s)

As computational demands grew, the limitations of vector processors became evident,


leading to the adoption of Massively Parallel Processing (MPP). MPP systems consist of
numerous processors working simultaneously on different parts of a problem. The Intel
Paragon, introduced in the early 1990s, exemplified this shift, utilizing thousands of
processors connected via a high-speed network. Wikipedia

The Cray T3E, released in 1995, further advanced MPP by integrating over 2,000 processors
with a three-dimensional torus interconnect, enhancing scalability and performance.
Wikipedia

Diagram: Massively Parallel Processing Architecture


3. Petascale Computing (2000s)

The 2000s witnessed the advent of petascale computing, breaking the barrier of 10^15
FLOPS. IBM's Blue Gene/L, operational in 2004, achieved 280 teraFLOPS using over
65,000 processors. Its successor, Blue Gene/P, reached 1 petaFLOP in 2007. Wikipedia

These systems emphasized energy efficiency and scalability, setting the stage for future
supercomputers.

Diagram: Blue Gene Architecture

4. Exascale Computing and Beyond (2010s–Present)

The pursuit of exascale computing, achieving 10^18 FLOPS, has been a significant focus in
recent years. The Frontier supercomputer, developed by Hewlett Packard Enterprise and
operational at Oak Ridge National Laboratory since 2022, became the first to surpass the
exascale threshold, achieving 1.1 exaFLOPS. Wikipedia
Frontier utilizes a combination of AMD CPUs and GPUs, interconnected through a high-
speed network, to deliver unprecedented performance for complex simulations and AI
workloads.Wikipedia

Diagram: Exascale Supercomputer Architecture

Impact on Computational Power

Each evolutionary phase in supercomputing has exponentially increased computational


capabilities:

 Vector Processing: Enabled efficient handling of large datasets in scientific


computations.
 Massively Parallel Processing: Allowed for the division of complex problems into
smaller tasks, processed simultaneously.
 Petascale Computing: Facilitated high-resolution simulations in fields like climate
modeling and genomics.
 Exascale Computing: Supports advanced AI applications, real-time data analysis,
and intricate simulations, pushing the boundaries of research and innovation.

Conclusion

The evolution from vector processors to exascale computing reflects the relentless pursuit of
higher performance and efficiency in supercomputing. Each milestone has not only enhanced
computational power but also expanded the horizons of scientific discovery and technological
advancement.

12. With a neat diagram, explain the different levels of memory hierarchy and their impact on
data locality in HPC
In High-Performance Computing (HPC), the memory hierarchy plays a crucial role in determining the
performance of applications. As processor speeds have outpaced memory speeds, memory
hierarchy helps bridge the gap through layers of memory with different speeds, sizes, and costs.

Diagram: Memory Hierarchy


lua
CopyEdit
+---------------------+
| Registers | <- Fastest, smallest
+---------------------+
↓
+---------------------+
| L1 Cache |
+---------------------+
↓
+---------------------+
| L2 Cache |
+---------------------+
↓
+---------------------+
| L3 Cache |
+---------------------+
↓
+---------------------+
| Main Memory | (RAM)
+---------------------+
↓
+---------------------+
| Secondary Storage| (SSD/HDD)
+---------------------+

←-------------- Increasing Size & Latency --------------


--------------→ Increasing Speed & Cost per Byte →

Explanation of Memory Levels

1. Registers
o Located inside the CPU.
o Fastest memory, smallest in size.
o Holds operands for immediate processing.
2. L1, L2, L3 Caches
o L1 Cache: Closest to the CPU core, smallest (~32KB), fastest cache.
o L2 Cache: Larger (~256KB to 1MB), shared or private.
o L3 Cache: Shared among cores, bigger (~4MB–64MB), slower than L1/L2.
o These are hardware-managed caches, crucial for temporal locality.
3. Main Memory (RAM)
o Larger capacity (~GBs), slower than cache.
o Accessed when data is not found in the cache (cache miss).
o Affects spatial locality through prefetching.
4. Secondary Storage (Disk)
o Includes SSDs and HDDs.
o Much larger (TBs), but very high latency.
o Data is paged into main memory when needed.
o Not ideal for frequent data access in HPC.
Impact on Data Locality

1. Temporal Locality

 If a piece of data is accessed, it’s likely to be accessed again soon.


 Caches take advantage of this by keeping recently used data close to the CPU.

2. Spatial Locality

 If data at one memory location is accessed, nearby data is likely accessed soon.
 RAM and cache prefetching help load blocks of data to exploit spatial locality.

3. Importance in HPC

 Efficient use of memory hierarchy reduces memory latency.


 HPC applications often process large data arrays, so optimizing cache usage (through
blocking, loop unrolling, etc.) is vital.
 Poor data locality leads to cache misses, long memory access times, and underutilized CPU
cycles.

Conclusion

Understanding and optimizing for the memory hierarchy is essential in HPC to enhance performance.
By maximizing data locality, applications can reduce costly memory accesses, utilize faster memory
levels, and achieve better parallel efficiency.

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