UNIT-4
Q1- Explain the concept of paging. Also, explain paging hardware support using TLB
with suitable diagram.
Ans-Paging is a memory management scheme that eliminates the need for contiguous allocation
of physical memory, reducing fragmentation and improving efficiency.
In paging, the process's virtual address space is divided into fixed-sized pages, while the
physical memory is divided into frames of the same size. Each virtual page can be mapped to a
physical frame using a page table.
Basic Concepts of Paging
The logical memory (or virtual memory) is divided into fixed-size blocks called pages.
The physical memory is divided into blocks of the same size called frames.
When a process is to be executed, its pages are loaded into any available memory frames
from the backing store.
When a process accesses memory, the CPU translates the virtual address into a physical address
using this page table. This translation ensures that a process does not need contiguous physical
memory, leading to more efficient utilization of available space.
Address Translation in Paging
A logical address generated by the CPU is divided into:
Page number (p): Index into the page table.
Page offset (d): Specific location within the page.
The page table maps page numbers to corresponding frame numbers in physical memory.
Advantages of Paging
Easy to use memory management algorithm
No need for external fragmentation
Swapping is easy between equal-sized pages and page frames.
Disadvantages of Paging
This May cause Internal fragmentation in the last page.
Page tables consume additional memory.
Multi-level paging may lead to memory reference overhead.
Paging Hardware Support Using TLB
The Translation Lookaside Buffer (TLB) is a specialized hardware cache that speeds up the
page-table lookup process. Without a TLB, every memory reference would require multiple
memory accesses: first to fetch the page table entry, then to access the actual data. The TLB
stores frequently accessed page table entries, reducing lookup time.
Working of TLB in Paging:
1. CPU generates a virtual address.
2. TLB checks if the mapping (virtual-to-physical) is present:
o If found (TLB hit) → The physical address is directly retrieved.
o If not found (TLB miss) → The page table is accessed in memory.
3. If a TLB miss occurs, the page table provides the mapping, and the entry is loaded into
the TLB for future reference.
4. Physical memory is accessed, completing the request.
The use of TLB enhances performance significantly by reducing memory access time.
However, if a TLB miss happens frequently, system efficiency may degrade, requiring TLB
replacement strategies like LRU (Least Recently Used) or FIFO (First In First Out) to
manage entries effectively.
Q2- Explain segmentation memory management techniques with suitable diagram.
Ans- Segmentation is another memory management technique that gives the user's view of a
process. The user's view is mapped into the Physical Memory.
In Segmentation, a process is divided into multiple segments. The size of each segment is not
necessarily the same which is different from paging. In Paging, a process was divided into equal
partitions called pages. The module contained in a segment decides the size of the segment.
Need of Segmentation
In Paging, the process was divided into equal-sized pages irrespective of the fact that what is
inside the pages. It also divides some relative parts of a process into different pages which
should be loaded on the same page. It decreases the efficiency of the system and doesn't give
the user's view of a process.
In Segmentation, similar modules are loaded in the same segments. It gives the user's view of a
process and also increases the efficiency of the system as compared to Paging.
Segment Table
Segment Table stores the information about all the segments of a process.
It helps in the mapping of the two-dimensional logical addresses to the physical addresses.
It is stored in the main memory.
There are two entries in the Segment Table.
Base Address - It is the starting physical address of the particular segment inside the main
memory.
Limit - It denotes the size of a particular segment.
Translation of Logical Address into Physical Address
The CPU generates the logical address which consists of two parts:
Segment Number(s) - It is the number of bits required to represent a Segment. It is used as an
index in the Segment Table.
Segment Offset(d) - It is the number of bits required to represent the size of a Segment.
Segment Number from the Segment Table gives the base address of a Segment in the main
memory and Segment Offset gives the size of that Segment.
These two together give the Physical Address of a Segment in the memory.
If Offset(d)<Limit then the segment is fetched from the memory else there is an error.
Advantages of Segmentation
There is no Internal Fragmentation.
It gives the user's view of a process.
It helps in dividing a program into similar modules which are called segments.
Segment Table consumes less space than Page Table.
Disadvantages of Segmentation
When Process is removed from the memory, it breaks memory into small pieces which
leads to External Fragmentation.
